diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/ARM/Thumb2ITBlockPass.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/Hexagon/HexagonFrameLowering.cpp | 8 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsExpandPseudo.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsFrameLowering.cpp | 2 |
4 files changed, 9 insertions, 9 deletions
diff --git a/lib/Target/ARM/Thumb2ITBlockPass.cpp b/lib/Target/ARM/Thumb2ITBlockPass.cpp index 8feacab..def75dd 100644 --- a/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -76,7 +76,7 @@ static void TrackDefUses(MachineInstr *MI, for (unsigned i = 0, e = LocalUses.size(); i != e; ++i) { unsigned Reg = LocalUses[i]; Uses.insert(Reg); - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + for (const uint16_t *Subreg = TRI->getSubRegisters(Reg); *Subreg; ++Subreg) Uses.insert(*Subreg); } @@ -84,7 +84,7 @@ static void TrackDefUses(MachineInstr *MI, for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) { unsigned Reg = LocalDefs[i]; Defs.insert(Reg); - for (const unsigned *Subreg = TRI->getSubRegisters(Reg); + for (const uint16_t *Subreg = TRI->getSubRegisters(Reg); *Subreg; ++Subreg) Defs.insert(*Subreg); if (Reg == ARM::CPSR) diff --git a/lib/Target/Hexagon/HexagonFrameLowering.cpp b/lib/Target/Hexagon/HexagonFrameLowering.cpp index d66551f..49c6cdf 100644 --- a/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -235,7 +235,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters( // // Check if we can use a double-word store. // - const unsigned* SuperReg = TRI->getSuperRegisters(Reg); + const uint16_t* SuperReg = TRI->getSuperRegisters(Reg); // Assume that there is exactly one superreg. assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg"); @@ -243,7 +243,7 @@ HexagonFrameLowering::spillCalleeSavedRegisters( const TargetRegisterClass* SuperRegClass = 0; if (ContiguousRegs && (i < CSI.size()-1)) { - const unsigned* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); + const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); assert(SuperRegNext[0] && !SuperRegNext[1] && "Expected exactly one superreg"); SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]); @@ -295,14 +295,14 @@ bool HexagonFrameLowering::restoreCalleeSavedRegisters( // // Check if we can use a double-word load. // - const unsigned* SuperReg = TRI->getSuperRegisters(Reg); + const uint16_t* SuperReg = TRI->getSuperRegisters(Reg); const TargetRegisterClass* SuperRegClass = 0; // Assume that there is exactly one superreg. assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg"); bool CanUseDblLoad = false; if (ContiguousRegs && (i < CSI.size()-1)) { - const unsigned* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); + const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); assert(SuperRegNext[0] && !SuperRegNext[1] && "Expected exactly one superreg"); SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]); diff --git a/lib/Target/Mips/MipsExpandPseudo.cpp b/lib/Target/Mips/MipsExpandPseudo.cpp index 4068958..baeae97 100644 --- a/lib/Target/Mips/MipsExpandPseudo.cpp +++ b/lib/Target/Mips/MipsExpandPseudo.cpp @@ -95,7 +95,7 @@ void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB, unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); DebugLoc dl = I->getDebugLoc(); - const unsigned* SubReg = + const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(DstReg); // mtc1 Lo, $fp @@ -111,7 +111,7 @@ void MipsExpandPseudo::ExpandExtractElementF64(MachineBasicBlock& MBB, unsigned N = I->getOperand(2).getImm(); const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); DebugLoc dl = I->getDebugLoc(); - const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); + const uint16_t* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(*(SubReg + N)); } diff --git a/lib/Target/Mips/MipsFrameLowering.cpp b/lib/Target/Mips/MipsFrameLowering.cpp index c186b5d..e83c64e 100644 --- a/lib/Target/Mips/MipsFrameLowering.cpp +++ b/lib/Target/Mips/MipsFrameLowering.cpp @@ -216,7 +216,7 @@ void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { // If Reg is a double precision register, emit two cfa_offsets, // one for each of the paired single precision registers. if (Mips::AFGR64RegisterClass->contains(Reg)) { - const unsigned *SubRegs = RegInfo->getSubRegisters(Reg); + const uint16_t *SubRegs = RegInfo->getSubRegisters(Reg); MachineLocation DstML0(MachineLocation::VirtualFP, Offset); MachineLocation DstML1(MachineLocation::VirtualFP, Offset + 4); MachineLocation SrcML0(*SubRegs); |