diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/PowerPC/PPCCallingConv.td | 3 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 14 |
2 files changed, 15 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCCallingConv.td b/lib/Target/PowerPC/PPCCallingConv.td index 9e31b5a..0991d83 100644 --- a/lib/Target/PowerPC/PPCCallingConv.td +++ b/lib/Target/PowerPC/PPCCallingConv.td @@ -25,7 +25,8 @@ def RetCC_PPC : CallingConv<[ CCIfType<[i32], CCAssignToReg<[R3, R4]>>, CCIfType<[i64], CCAssignToReg<[X3, X4]>>, - CCIfType<[f32, f64], CCAssignToReg<[F1]>>, + CCIfType<[f32], CCAssignToReg<[F1]>>, + CCIfType<[f64], CCAssignToReg<[F1, F2]>>, // Vector types are always returned in V2. CCIfType<[v16i8, v8i16, v4i32, v4f32], CCAssignToReg<[V2]>> diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index cfebef1..ec1046f 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -1812,8 +1812,20 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG, NumResults = 1; NodeTys.push_back(MVT::i64); break; - case MVT::f32: case MVT::f64: + if (Op.Val->getValueType(1) == MVT::f64) { + Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1); + ResultVals[0] = Chain.getValue(0); + Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64, + Chain.getValue(2)).getValue(1); + ResultVals[1] = Chain.getValue(0); + NumResults = 2; + NodeTys.push_back(MVT::f64); + NodeTys.push_back(MVT::f64); + break; + } + // else fall through + case MVT::f32: Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0), InFlag).getValue(1); ResultVals[0] = Chain.getValue(0); |