diff options
Diffstat (limited to 'lib/Target')
58 files changed, 44 insertions, 199 deletions
diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp index 706d0b0..14daab3 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -29,7 +29,7 @@ #include <algorithm> -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "AArch64GenInstrInfo.inc" using namespace llvm; diff --git a/lib/Target/AArch64/AArch64Subtarget.cpp b/lib/Target/AArch64/AArch64Subtarget.cpp index 4da5294..eece389 100644 --- a/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/lib/Target/AArch64/AArch64Subtarget.cpp @@ -25,9 +25,6 @@ using namespace llvm; -// pin vtable to this file -void AArch64Subtarget::anchor() {} - AArch64Subtarget::AArch64Subtarget(StringRef TT, StringRef CPU, StringRef FS) : AArch64GenSubtargetInfo(TT, CPU, FS), HasFPARMv8(false), HasNEON(false), HasCrypto(false), TargetTriple(TT), CPUString(CPU) { diff --git a/lib/Target/AArch64/AArch64Subtarget.h b/lib/Target/AArch64/AArch64Subtarget.h index bbfd3bc..57eb187 100644 --- a/lib/Target/AArch64/AArch64Subtarget.h +++ b/lib/Target/AArch64/AArch64Subtarget.h @@ -27,7 +27,6 @@ class StringRef; class GlobalValue; class AArch64Subtarget : public AArch64GenSubtargetInfo { - virtual void anchor(); protected: bool HasFPARMv8; bool HasNEON; diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp index d001502..dd12e2c 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.cpp @@ -37,5 +37,3 @@ AArch64ELFMCAsmInfo::AArch64ELFMCAsmInfo() { // Exceptions handling ExceptionsType = ExceptionHandling::DwarfCFI; } - -void AArch64ELFMCAsmInfo::anchor() {} diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h b/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h index 67158c6..ae0a674 100644 --- a/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h +++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCAsmInfo.h @@ -18,12 +18,9 @@ namespace llvm { -struct AArch64ELFMCAsmInfo : public MCAsmInfoELF { - explicit AArch64ELFMCAsmInfo(); - -private: - virtual void anchor(); -}; + struct AArch64ELFMCAsmInfo : public MCAsmInfoELF { + explicit AArch64ELFMCAsmInfo(); + }; } // namespace llvm diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp index b2dd9d8..b76ef96 100644 --- a/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -37,7 +37,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "ARMGenInstrInfo.inc" using namespace llvm; diff --git a/lib/Target/Hexagon/CMakeLists.txt b/lib/Target/Hexagon/CMakeLists.txt index ae3c9eb..2b79791 100644 --- a/lib/Target/Hexagon/CMakeLists.txt +++ b/lib/Target/Hexagon/CMakeLists.txt @@ -17,7 +17,6 @@ add_llvm_target(HexagonCodeGen HexagonFrameLowering.cpp HexagonHardwareLoops.cpp HexagonFixupHwLoops.cpp - HexagonMachineFunctionInfo.cpp HexagonMachineScheduler.cpp HexagonMCInstLower.cpp HexagonInstrInfo.cpp diff --git a/lib/Target/Hexagon/HexagonInstrInfo.cpp b/lib/Target/Hexagon/HexagonInstrInfo.cpp index 7d5b284..5af645c 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -26,7 +26,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #define GET_INSTRMAP_INFO #include "HexagonGenInstrInfo.inc" #include "HexagonGenDFAPacketizer.inc" @@ -55,8 +55,6 @@ const int Hexagon_MEMH_AUTOINC_MIN = -16; const int Hexagon_MEMB_AUTOINC_MAX = 7; const int Hexagon_MEMB_AUTOINC_MIN = -8; -// pin vtable to this file -void HexagonInstrInfo::anchor() {} HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST) : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP), diff --git a/lib/Target/Hexagon/HexagonInstrInfo.h b/lib/Target/Hexagon/HexagonInstrInfo.h index 7679b5f..3c28df4 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.h +++ b/lib/Target/Hexagon/HexagonInstrInfo.h @@ -30,8 +30,6 @@ class HexagonInstrInfo : public HexagonGenInstrInfo { const HexagonSubtarget &Subtarget; typedef unsigned Opcode_t; - virtual void anchor(); - public: explicit HexagonInstrInfo(HexagonSubtarget &ST); diff --git a/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp b/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp deleted file mode 100644 index 9579c8b..0000000 --- a/lib/Target/Hexagon/HexagonMachineFunctionInfo.cpp +++ /dev/null @@ -1,16 +0,0 @@ -//= HexagonMachineFunctionInfo.cpp - Hexagon machine function info *- C++ -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "HexagonMachineFunctionInfo.h" - -using namespace llvm; - -// pin vtable to this file -void HexagonMachineFunctionInfo::anchor() {} - diff --git a/lib/Target/Hexagon/HexagonMachineFunctionInfo.h b/lib/Target/Hexagon/HexagonMachineFunctionInfo.h index c68416c..bd7b26a 100644 --- a/lib/Target/Hexagon/HexagonMachineFunctionInfo.h +++ b/lib/Target/Hexagon/HexagonMachineFunctionInfo.h @@ -1,4 +1,4 @@ -//=- HexagonMachineFunctionInfo.h - Hexagon machine function info -*- C++ -*-=// +//=- HexagonMachineFuctionInfo.h - Hexagon machine function info --*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -10,7 +10,6 @@ #ifndef HexagonMACHINEFUNCTIONINFO_H #define HexagonMACHINEFUNCTIONINFO_H -#include <map> #include "llvm/CodeGen/MachineFunction.h" namespace llvm { @@ -34,7 +33,6 @@ class HexagonMachineFunctionInfo : public MachineFunctionInfo { std::map<const MachineInstr*, unsigned> PacketInfo; - virtual void anchor(); public: HexagonMachineFunctionInfo() : SRetReturnReg(0), HasClobberLR(0), diff --git a/lib/Target/Hexagon/HexagonSubtarget.cpp b/lib/Target/Hexagon/HexagonSubtarget.cpp index a0a7c3d..07d5ce1 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -86,4 +86,3 @@ HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): ModeIEEERndNear = false; } -HexagonSubtarget::~HexagonSubtarget() {} diff --git a/lib/Target/Hexagon/HexagonSubtarget.h b/lib/Target/Hexagon/HexagonSubtarget.h index e871110..76a8fba 100644 --- a/lib/Target/Hexagon/HexagonSubtarget.h +++ b/lib/Target/Hexagon/HexagonSubtarget.h @@ -42,7 +42,6 @@ public: public: HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS); - virtual ~HexagonSubtarget(); /// getInstrItins - Return the instruction itineraies based on subtarget /// selection. diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index fa13008..b9fef0c 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -15,9 +15,6 @@ using namespace llvm; -// pin vtable to this file -void HexagonMCAsmInfo::anchor() {} - HexagonMCAsmInfo::HexagonMCAsmInfo(StringRef TT) { Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h index bd8cb76..b2c1d37 100644 --- a/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ b/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -19,7 +19,6 @@ namespace llvm { class HexagonMCAsmInfo : public MCAsmInfoELF { - virtual void anchor(); public: explicit HexagonMCAsmInfo(StringRef TT); }; diff --git a/lib/Target/MSP430/MSP430InstrInfo.cpp b/lib/Target/MSP430/MSP430InstrInfo.cpp index f0695a7..c850594 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -22,14 +22,11 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "MSP430GenInstrInfo.inc" using namespace llvm; -// pin vtable to this file -void MSP430InstrInfo::anchor() {} - MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm) : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), RI(tm) {} diff --git a/lib/Target/MSP430/MSP430InstrInfo.h b/lib/Target/MSP430/MSP430InstrInfo.h index ad2b8cc..d79f992 100644 --- a/lib/Target/MSP430/MSP430InstrInfo.h +++ b/lib/Target/MSP430/MSP430InstrInfo.h @@ -42,7 +42,6 @@ namespace MSP430II { class MSP430InstrInfo : public MSP430GenInstrInfo { const MSP430RegisterInfo RI; - virtual void anchor(); public: explicit MSP430InstrInfo(MSP430TargetMachine &TM); diff --git a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index 3d417a8..6c48053 100644 --- a/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -42,9 +42,6 @@ using namespace llvm; static cl::opt<bool> PrintHackDirectives("print-hack-directives", cl::init(false), cl::Hidden); -// pin vtable to this file -void MipsTargetStreamer::anchor() {} - static std::string ParseMipsTriple(StringRef TT, StringRef CPU) { std::string MipsArchFeature; size_t DashPosition = 0; diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp index a36dcc8..7b04a9a 100644 --- a/lib/Target/Mips/MipsInstrInfo.cpp +++ b/lib/Target/Mips/MipsInstrInfo.cpp @@ -22,14 +22,11 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "MipsGenInstrInfo.inc" using namespace llvm; -// pin vtable to this file -void MipsInstrInfo::anchor() {} - MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm, unsigned UncondBr) : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), TM(tm), UncondBrOpc(UncondBr) {} diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h index d9ac961..b6480ef 100644 --- a/lib/Target/Mips/MipsInstrInfo.h +++ b/lib/Target/Mips/MipsInstrInfo.h @@ -27,7 +27,6 @@ namespace llvm { class MipsInstrInfo : public MipsGenInstrInfo { - virtual void anchor(); protected: MipsTargetMachine &TM; unsigned UncondBrOpc; diff --git a/lib/Target/Mips/MipsTargetStreamer.h b/lib/Target/Mips/MipsTargetStreamer.h index 237017a..fb9f5ef 100644 --- a/lib/Target/Mips/MipsTargetStreamer.h +++ b/lib/Target/Mips/MipsTargetStreamer.h @@ -14,7 +14,6 @@ namespace llvm { class MipsTargetStreamer : public MCTargetStreamer { - virtual void anchor(); public: virtual void emitMipsHackELFFlags(unsigned Flags) = 0; virtual void emitMipsHackSTOCG(MCSymbol *Sym, unsigned Val) = 0; diff --git a/lib/Target/NVPTX/NVPTXISelLowering.cpp b/lib/Target/NVPTX/NVPTXISelLowering.cpp index 756b15e..7ff43bf 100644 --- a/lib/Target/NVPTX/NVPTXISelLowering.cpp +++ b/lib/Target/NVPTX/NVPTXISelLowering.cpp @@ -2288,29 +2288,3 @@ void NVPTXTargetLowering::ReplaceNodeResults( return; } } - -// pin NVPTXSection.h and NVPTXTargetObjectFile.h vtables to this file -void NVPTXSection::anchor() {} - -NVPTXTargetObjectFile::~NVPTXTargetObjectFile() { - delete TextSection; - delete DataSection; - delete BSSSection; - delete ReadOnlySection; - - delete StaticCtorSection; - delete StaticDtorSection; - delete LSDASection; - delete EHFrameSection; - delete DwarfAbbrevSection; - delete DwarfInfoSection; - delete DwarfLineSection; - delete DwarfFrameSection; - delete DwarfPubTypesSection; - delete DwarfDebugInlineSection; - delete DwarfStrSection; - delete DwarfLocSection; - delete DwarfARangesSection; - delete DwarfRangesSection; - delete DwarfMacroInfoSection; -} diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.cpp b/lib/Target/NVPTX/NVPTXInstrInfo.cpp index ce5b5d5..1f54d3e 100644 --- a/lib/Target/NVPTX/NVPTXInstrInfo.cpp +++ b/lib/Target/NVPTX/NVPTXInstrInfo.cpp @@ -14,7 +14,7 @@ #include "NVPTX.h" #include "NVPTXInstrInfo.h" #include "NVPTXTargetMachine.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "NVPTXGenInstrInfo.inc" #include "llvm/IR/Function.h" #include "llvm/ADT/STLExtras.h" @@ -24,9 +24,6 @@ using namespace llvm; -// pin vtable to this file -void NVPTXInstrInfo::anchor() {} - // FIXME: Add the subtarget support on this constructor. NVPTXInstrInfo::NVPTXInstrInfo(NVPTXTargetMachine &tm) : NVPTXGenInstrInfo(), TM(tm), RegInfo(*TM.getSubtargetImpl()) {} diff --git a/lib/Target/NVPTX/NVPTXInstrInfo.h b/lib/Target/NVPTX/NVPTXInstrInfo.h index 600fc5c..b1972e9 100644 --- a/lib/Target/NVPTX/NVPTXInstrInfo.h +++ b/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -26,7 +26,6 @@ namespace llvm { class NVPTXInstrInfo : public NVPTXGenInstrInfo { NVPTXTargetMachine &TM; const NVPTXRegisterInfo RegInfo; - virtual void anchor(); public: explicit NVPTXInstrInfo(NVPTXTargetMachine &TM); diff --git a/lib/Target/NVPTX/NVPTXSection.h b/lib/Target/NVPTX/NVPTXSection.h index f8a692e..e57ace9 100644 --- a/lib/Target/NVPTX/NVPTXSection.h +++ b/lib/Target/NVPTX/NVPTXSection.h @@ -24,10 +24,10 @@ namespace llvm { /// the ASMPrint interface. /// class NVPTXSection : public MCSection { - virtual void anchor(); + public: NVPTXSection(SectionVariant V, SectionKind K) : MCSection(V, K) {} - virtual ~NVPTXSection() {} + ~NVPTXSection() {} /// Override this as NVPTX has its own way of printing switching /// to a section. diff --git a/lib/Target/NVPTX/NVPTXSubtarget.cpp b/lib/Target/NVPTX/NVPTXSubtarget.cpp index 3e5bcf7..c4d0d6e 100644 --- a/lib/Target/NVPTX/NVPTXSubtarget.cpp +++ b/lib/Target/NVPTX/NVPTXSubtarget.cpp @@ -20,9 +20,6 @@ using namespace llvm; -// pin vtable to this file -void NVPTXSubtarget::anchor() {} - NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) : NVPTXGenSubtargetInfo(TT, CPU, FS), Is64Bit(is64Bit), PTXVersion(0), diff --git a/lib/Target/NVPTX/NVPTXSubtarget.h b/lib/Target/NVPTX/NVPTXSubtarget.h index a183920..670077d 100644 --- a/lib/Target/NVPTX/NVPTXSubtarget.h +++ b/lib/Target/NVPTX/NVPTXSubtarget.h @@ -36,8 +36,6 @@ class NVPTXSubtarget : public NVPTXGenSubtargetInfo { // SM version x.y is represented as 10*x+y, e.g. 3.1 == 31 unsigned int SmVersion; - virtual void anchor(); - public: /// This constructor initializes the data members to match that /// of the specified module. diff --git a/lib/Target/NVPTX/NVPTXTargetObjectFile.h b/lib/Target/NVPTX/NVPTXTargetObjectFile.h index 2a7394b..1449f52 100644 --- a/lib/Target/NVPTX/NVPTXTargetObjectFile.h +++ b/lib/Target/NVPTX/NVPTXTargetObjectFile.h @@ -44,7 +44,28 @@ public: DwarfMacroInfoSection = 0; } - virtual ~NVPTXTargetObjectFile(); + ~NVPTXTargetObjectFile() { + delete TextSection; + delete DataSection; + delete BSSSection; + delete ReadOnlySection; + + delete StaticCtorSection; + delete StaticDtorSection; + delete LSDASection; + delete EHFrameSection; + delete DwarfAbbrevSection; + delete DwarfInfoSection; + delete DwarfLineSection; + delete DwarfFrameSection; + delete DwarfPubTypesSection; + delete DwarfDebugInlineSection; + delete DwarfStrSection; + delete DwarfLocSection; + delete DwarfARangesSection; + delete DwarfRangesSection; + delete DwarfMacroInfoSection; + } virtual void Initialize(MCContext &ctx, const TargetMachine &TM) { TargetLoweringObjectFile::Initialize(ctx, TM); diff --git a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp index 8f4e224..5c08de1 100644 --- a/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp +++ b/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp @@ -37,9 +37,6 @@ using namespace llvm; -// pin vtable to this file -PPCTargetStreamer::~PPCTargetStreamer() {} - static MCInstrInfo *createPPCMCInstrInfo() { MCInstrInfo *X = new MCInstrInfo(); InitPPCMCInstrInfo(X); diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp index 1020571..375daee 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -33,7 +33,7 @@ #include "llvm/Support/raw_ostream.h" #define GET_INSTRMAP_INFO -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "PPCGenInstrInfo.inc" using namespace llvm; @@ -45,9 +45,6 @@ opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden, static cl::opt<bool> DisableCmpOpt("disable-ppc-cmp-opt", cl::desc("Disable compare instruction optimization"), cl::Hidden); -//pin vtable to this file -void PPCInstrInfo::anchor() {} - PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl()) {} diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h index f140c41..bd72a4d 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.h +++ b/lib/Target/PowerPC/PPCInstrInfo.h @@ -78,7 +78,6 @@ class PPCInstrInfo : public PPCGenInstrInfo { const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs, bool &NonRI, bool &SpillsVRS) const; - virtual void anchor(); public: explicit PPCInstrInfo(PPCTargetMachine &TM); diff --git a/lib/Target/PowerPC/PPCTargetStreamer.h b/lib/Target/PowerPC/PPCTargetStreamer.h index e876be1..3ecd8a8 100644 --- a/lib/Target/PowerPC/PPCTargetStreamer.h +++ b/lib/Target/PowerPC/PPCTargetStreamer.h @@ -15,7 +15,6 @@ namespace llvm { class PPCTargetStreamer : public MCTargetStreamer { public: - virtual ~PPCTargetStreamer(); virtual void emitTCEntry(const MCSymbol &S) = 0; }; } diff --git a/lib/Target/R600/AMDGPUInstrInfo.cpp b/lib/Target/R600/AMDGPUInstrInfo.cpp index 3a859cf..1b2e131 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.cpp +++ b/lib/Target/R600/AMDGPUInstrInfo.cpp @@ -20,17 +20,13 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_NAMED_OPS #define GET_INSTRMAP_INFO #include "AMDGPUGenInstrInfo.inc" using namespace llvm; - -// pin vtable to this file -void AMDGPUInstrInfo::anchor() {} - AMDGPUInstrInfo::AMDGPUInstrInfo(TargetMachine &tm) : AMDGPUGenInstrInfo(-1,-1), RI(tm), TM(tm) { } diff --git a/lib/Target/R600/AMDGPUInstrInfo.h b/lib/Target/R600/AMDGPUInstrInfo.h index ce5b58c..6378fdd 100644 --- a/lib/Target/R600/AMDGPUInstrInfo.h +++ b/lib/Target/R600/AMDGPUInstrInfo.h @@ -43,7 +43,6 @@ private: const AMDGPURegisterInfo RI; bool getNextBranchInstr(MachineBasicBlock::iterator &iter, MachineBasicBlock &MBB) const; - virtual void anchor(); protected: TargetMachine &TM; public: diff --git a/lib/Target/R600/AMDGPUMachineFunction.cpp b/lib/Target/R600/AMDGPUMachineFunction.cpp index d453101..f2342b0 100644 --- a/lib/Target/R600/AMDGPUMachineFunction.cpp +++ b/lib/Target/R600/AMDGPUMachineFunction.cpp @@ -6,9 +6,6 @@ using namespace llvm; static const char *const ShaderTypeAttribute = "ShaderType"; -// pin vtable to this file -void AMDGPUMachineFunction::anchor() {} - AMDGPUMachineFunction::AMDGPUMachineFunction(const MachineFunction &MF) : MachineFunctionInfo() { ShaderType = ShaderType::COMPUTE; diff --git a/lib/Target/R600/AMDGPUMachineFunction.h b/lib/Target/R600/AMDGPUMachineFunction.h index fea0b39..fe80ce3 100644 --- a/lib/Target/R600/AMDGPUMachineFunction.h +++ b/lib/Target/R600/AMDGPUMachineFunction.h @@ -19,7 +19,6 @@ namespace llvm { class AMDGPUMachineFunction : public MachineFunctionInfo { - virtual void anchor(); public: AMDGPUMachineFunction(const MachineFunction &MF); unsigned ShaderType; diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp deleted file mode 100644 index 521b3b3..0000000 --- a/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.cpp +++ /dev/null @@ -1,21 +0,0 @@ -//===-- AMDGPUCodeEmitter.cpp - AMDGPU Code Emitter interface -------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -/// \file -/// \brief CodeEmitter interface for R600 and SI codegen. -// -//===----------------------------------------------------------------------===// - -#include "AMDGPUMCCodeEmitter.h" - -using namespace llvm; - -// pin vtable to this file -void AMDGPUMCCodeEmitter::anchor() {} - diff --git a/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h b/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h index d8cf64a..cd3a7ce 100644 --- a/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h +++ b/lib/Target/R600/MCTargetDesc/AMDGPUMCCodeEmitter.h @@ -24,7 +24,6 @@ class MCInst; class MCOperand; class AMDGPUMCCodeEmitter : public MCCodeEmitter { - virtual void anchor(); public: uint64_t getBinaryCodeForInstr(const MCInst &MI, diff --git a/lib/Target/R600/MCTargetDesc/CMakeLists.txt b/lib/Target/R600/MCTargetDesc/CMakeLists.txt index 98f6925..3ccdf42 100644 --- a/lib/Target/R600/MCTargetDesc/CMakeLists.txt +++ b/lib/Target/R600/MCTargetDesc/CMakeLists.txt @@ -2,7 +2,6 @@ add_llvm_library(LLVMR600Desc AMDGPUAsmBackend.cpp AMDGPUELFObjectWriter.cpp - AMDGPUMCCodeEmitter.cpp AMDGPUMCTargetDesc.cpp AMDGPUMCAsmInfo.cpp R600MCCodeEmitter.cpp diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp index 1f47416..6381c38 100644 --- a/lib/Target/R600/R600InstrInfo.cpp +++ b/lib/Target/R600/R600InstrInfo.cpp @@ -23,7 +23,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "AMDGPUGenDFAPacketizer.inc" using namespace llvm; diff --git a/lib/Target/R600/R600MachineFunctionInfo.cpp b/lib/Target/R600/R600MachineFunctionInfo.cpp index d0d35cf..018b403 100644 --- a/lib/Target/R600/R600MachineFunctionInfo.cpp +++ b/lib/Target/R600/R600MachineFunctionInfo.cpp @@ -12,9 +12,7 @@ using namespace llvm; - -// pin vtable to this file -void R600MachineFunctionInfo::anchor() {} - R600MachineFunctionInfo::R600MachineFunctionInfo(const MachineFunction &MF) : AMDGPUMachineFunction(MF) { } + + diff --git a/lib/Target/R600/R600MachineFunctionInfo.h b/lib/Target/R600/R600MachineFunctionInfo.h index c1bec0a..f23d9b7 100644 --- a/lib/Target/R600/R600MachineFunctionInfo.h +++ b/lib/Target/R600/R600MachineFunctionInfo.h @@ -21,7 +21,6 @@ namespace llvm { class R600MachineFunctionInfo : public AMDGPUMachineFunction { - virtual void anchor(); public: R600MachineFunctionInfo(const MachineFunction &MF); SmallVector<unsigned, 4> LiveOuts; diff --git a/lib/Target/R600/SIMachineFunctionInfo.cpp b/lib/Target/R600/SIMachineFunctionInfo.cpp index 2f66360..ee0e307 100644 --- a/lib/Target/R600/SIMachineFunctionInfo.cpp +++ b/lib/Target/R600/SIMachineFunctionInfo.cpp @@ -13,10 +13,6 @@ using namespace llvm; - -// pin vtable to this file -void SIMachineFunctionInfo::anchor() {} - SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF) : AMDGPUMachineFunction(MF), PSInputAddr(0) { } diff --git a/lib/Target/R600/SIMachineFunctionInfo.h b/lib/Target/R600/SIMachineFunctionInfo.h index 2f1961c..6da9f7f 100644 --- a/lib/Target/R600/SIMachineFunctionInfo.h +++ b/lib/Target/R600/SIMachineFunctionInfo.h @@ -22,7 +22,6 @@ namespace llvm { /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which /// tells the hardware which interpolation parameters to load. class SIMachineFunctionInfo : public AMDGPUMachineFunction { - virtual void anchor(); public: SIMachineFunctionInfo(const MachineFunction &MF); unsigned PSInputAddr; diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp index 5e5e37a..93d7b56 100644 --- a/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/lib/Target/Sparc/SparcInstrInfo.cpp @@ -24,15 +24,11 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "SparcGenInstrInfo.inc" using namespace llvm; - -// pin vtable to this file -void SparcInstrInfo::anchor() {} - SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(ST), Subtarget(ST) { diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h index a86cbcb..d0b220b 100644 --- a/lib/Target/Sparc/SparcInstrInfo.h +++ b/lib/Target/Sparc/SparcInstrInfo.h @@ -37,7 +37,6 @@ namespace SPII { class SparcInstrInfo : public SparcGenInstrInfo { const SparcRegisterInfo RI; const SparcSubtarget& Subtarget; - virtual void anchor(); public: explicit SparcInstrInfo(SparcSubtarget &ST); diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt index d21c0a8..8a4eaa3 100644 --- a/lib/Target/SystemZ/CMakeLists.txt +++ b/lib/Target/SystemZ/CMakeLists.txt @@ -21,7 +21,6 @@ add_llvm_target(SystemZCodeGen SystemZISelLowering.cpp SystemZInstrInfo.cpp SystemZLongBranch.cpp - SystemZMachineFunctionInfo.cpp SystemZMCInstLower.cpp SystemZRegisterInfo.cpp SystemZSelectionDAGInfo.cpp diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 67aacf3..2ebbc0d 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -17,7 +17,7 @@ #include "llvm/CodeGen/LiveVariables.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #define GET_INSTRMAP_INFO #include "SystemZGenInstrInfo.inc" @@ -37,9 +37,6 @@ static bool isHighReg(unsigned int Reg) { return false; } -// pin vtable to this file -void SystemZInstrInfo::anchor() {} - SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP), RI(tm), TM(tm) { diff --git a/lib/Target/SystemZ/SystemZInstrInfo.h b/lib/Target/SystemZ/SystemZInstrInfo.h index be4c8fe..7978be4 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/lib/Target/SystemZ/SystemZInstrInfo.h @@ -127,7 +127,6 @@ class SystemZInstrInfo : public SystemZGenInstrInfo { void emitGRX32Move(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, DebugLoc DL, unsigned DestReg, unsigned SrcReg, unsigned LowLowOpcode, unsigned Size, bool KillSrc) const; - virtual void anchor(); public: explicit SystemZInstrInfo(SystemZTargetMachine &TM); diff --git a/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp b/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp deleted file mode 100644 index 00572d0..0000000 --- a/lib/Target/SystemZ/SystemZMachineFunctionInfo.cpp +++ /dev/null @@ -1,17 +0,0 @@ -//== SystemZMachineFuctionInfo.cpp - SystemZ machine function info-*- C++ -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#include "SystemZMachineFunctionInfo.h" - -using namespace llvm; - - -// pin vtable to this file -void SystemZMachineFunctionInfo::anchor() {} - diff --git a/lib/Target/SystemZ/SystemZMachineFunctionInfo.h b/lib/Target/SystemZ/SystemZMachineFunctionInfo.h index 509cef6..69c2691 100644 --- a/lib/Target/SystemZ/SystemZMachineFunctionInfo.h +++ b/lib/Target/SystemZ/SystemZMachineFunctionInfo.h @@ -23,8 +23,6 @@ class SystemZMachineFunctionInfo : public MachineFunctionInfo { unsigned RegSaveFrameIndex; bool ManipulatesSP; - virtual void anchor(); - public: explicit SystemZMachineFunctionInfo(MachineFunction &MF) : LowSavedGPR(0), HighSavedGPR(0), VarArgsFirstGPR(0), VarArgsFirstFPR(0), diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp index b9a9db2..4741920 100644 --- a/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -18,9 +18,6 @@ using namespace llvm; -// pin vtabel to this file -void SystemZSubtarget::anchor() {} - SystemZSubtarget::SystemZSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) diff --git a/lib/Target/SystemZ/SystemZSubtarget.h b/lib/Target/SystemZ/SystemZSubtarget.h index 5817491..74d3f90 100644 --- a/lib/Target/SystemZ/SystemZSubtarget.h +++ b/lib/Target/SystemZ/SystemZSubtarget.h @@ -26,7 +26,6 @@ class GlobalValue; class StringRef; class SystemZSubtarget : public SystemZGenSubtargetInfo { - virtual void anchor(); protected: bool HasDistinctOps; bool HasLoadStoreOnCond; diff --git a/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp b/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp index 6da4142..ed64a32 100644 --- a/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp +++ b/lib/Target/X86/MCTargetDesc/X86WinCOFFObjectWriter.cpp @@ -27,7 +27,7 @@ namespace { public: X86WinCOFFObjectWriter(bool Is64Bit_); - virtual ~X86WinCOFFObjectWriter(); + ~X86WinCOFFObjectWriter(); virtual unsigned getRelocType(const MCValue &Target, const MCFixup &Fixup, diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index b13fd33..63f699a 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -36,7 +36,7 @@ #include "llvm/Target/TargetOptions.h" #include <limits> -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "X86GenInstrInfo.inc" using namespace llvm; @@ -92,9 +92,6 @@ struct X86OpTblEntry { uint16_t Flags; }; -// pin vtable to this file -void X86InstrInfo::anchor() {} - X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit() ? X86::ADJCALLSTACKDOWN64 diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 600e392..532e780 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -152,8 +152,6 @@ class X86InstrInfo : public X86GenInstrInfo { MemOp2RegOpTableType &M2RTable, unsigned RegOp, unsigned MemOp, unsigned Flags); - virtual void anchor(); - public: explicit X86InstrInfo(X86TargetMachine &tm); diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp index 7193965..d6b8c2d 100644 --- a/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/lib/Target/XCore/XCoreInstrInfo.cpp @@ -22,7 +22,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/TargetRegistry.h" -#define GET_INSTRINFO_CTOR_DTOR +#define GET_INSTRINFO_CTOR #include "XCoreGenInstrInfo.inc" namespace llvm { @@ -39,10 +39,6 @@ namespace XCore { using namespace llvm; - -// pin vtable to this file -void XCoreInstrInfo::anchor() {} - XCoreInstrInfo::XCoreInstrInfo() : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), RI() { diff --git a/lib/Target/XCore/XCoreInstrInfo.h b/lib/Target/XCore/XCoreInstrInfo.h index 4429b07..51d66a1 100644 --- a/lib/Target/XCore/XCoreInstrInfo.h +++ b/lib/Target/XCore/XCoreInstrInfo.h @@ -24,7 +24,6 @@ namespace llvm { class XCoreInstrInfo : public XCoreGenInstrInfo { const XCoreRegisterInfo RI; - virtual void anchor(); public: XCoreInstrInfo(); |