diff options
Diffstat (limited to 'lib/Target')
78 files changed, 371 insertions, 72 deletions
diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp index 258c287..bac088a 100644 --- a/lib/Target/CBackend/CBackend.cpp +++ b/lib/Target/CBackend/CBackend.cpp @@ -31,6 +31,8 @@ #include <algorithm> #include <sstream> +namespace llvm { + namespace { class CWriter : public Pass, public InstVisitor<CWriter> { std::ostream &Out; @@ -161,7 +163,6 @@ namespace { void printIndexingExpression(Value *Ptr, User::op_iterator I, User::op_iterator E); }; -} // Pass the Type* and the variable name and this prints out the variable // declaration. @@ -339,7 +340,7 @@ void CWriter::printConstantArray(ConstantArray *CPA) { // compiler agreeing on the conversion process (which is pretty likely since we // only deal in IEEE FP). // -static bool isFPCSafeToPrint(const ConstantFP *CFP) { +bool isFPCSafeToPrint(const ConstantFP *CFP) { #if HAVE_PRINTF_A char Buffer[100]; sprintf(Buffer, "%a", CFP->getValue()); @@ -563,7 +564,7 @@ bool CWriter::nameAllUsedStructureTypes(Module &M) { // generateCompilerSpecificCode - This is where we add conditional compilation // directives to cater to specific compilers as need be. // -static void generateCompilerSpecificCode(std::ostream& Out) { +void generateCompilerSpecificCode(std::ostream& Out) { // Alloca is hard to get, and we don't want to include stdlib.h here... Out << "/* get a declaration for alloca */\n" << "#ifdef sun\n" @@ -1058,7 +1059,7 @@ void CWriter::visitUnwindInst(UnwindInst &I) { emittedInvoke = true; } -static bool isGotoCodeNecessary(BasicBlock *From, BasicBlock *To) { +bool isGotoCodeNecessary(BasicBlock *From, BasicBlock *To) { // If PHI nodes need copies, we need the copy code... if (isa<PHINode>(To->front()) || From->getNext() != To) // Not directly successor, need goto @@ -1195,10 +1196,10 @@ void CWriter::visitCastInst(CastInst &I) { void CWriter::visitCallInst(CallInst &I) { // Handle intrinsic function calls first... if (Function *F = I.getCalledFunction()) - if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) { + if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) { switch (ID) { default: assert(0 && "Unknown LLVM intrinsic!"); - case LLVMIntrinsic::va_start: + case Intrinsic::va_start: Out << "0; "; Out << "va_start(*(va_list*)&" << Mang->getValueName(&I) << ", "; @@ -1212,28 +1213,28 @@ void CWriter::visitCallInst(CallInst &I) { writeOperand(&I.getParent()->getParent()->aback()); Out << ")"; return; - case LLVMIntrinsic::va_end: + case Intrinsic::va_end: Out << "va_end(*(va_list*)&"; writeOperand(I.getOperand(1)); Out << ")"; return; - case LLVMIntrinsic::va_copy: + case Intrinsic::va_copy: Out << "0;"; Out << "va_copy(*(va_list*)&" << Mang->getValueName(&I) << ", "; Out << "*(va_list*)&"; writeOperand(I.getOperand(1)); Out << ")"; return; - case LLVMIntrinsic::setjmp: - case LLVMIntrinsic::sigsetjmp: + case Intrinsic::setjmp: + case Intrinsic::sigsetjmp: // This intrinsic should never exist in the program, but until we get // setjmp/longjmp transformations going on, we should codegen it to // something reasonable. This will allow code that never calls longjmp // to work. Out << "0"; return; - case LLVMIntrinsic::longjmp: - case LLVMIntrinsic::siglongjmp: + case Intrinsic::longjmp: + case Intrinsic::siglongjmp: // Longjmp is not implemented, and never will be. It would cause an // exception throw. Out << "abort()"; @@ -1385,9 +1386,12 @@ void CWriter::visitVAArgInst(VAArgInst &I) { Out << ");\n va_end(Tmp); }"; } +} //===----------------------------------------------------------------------===// // External Interface declaration //===----------------------------------------------------------------------===// Pass *createWriteToCPass(std::ostream &o) { return new CWriter(o); } + +} // End llvm namespace diff --git a/lib/Target/CBackend/Writer.cpp b/lib/Target/CBackend/Writer.cpp index 258c287..bac088a 100644 --- a/lib/Target/CBackend/Writer.cpp +++ b/lib/Target/CBackend/Writer.cpp @@ -31,6 +31,8 @@ #include <algorithm> #include <sstream> +namespace llvm { + namespace { class CWriter : public Pass, public InstVisitor<CWriter> { std::ostream &Out; @@ -161,7 +163,6 @@ namespace { void printIndexingExpression(Value *Ptr, User::op_iterator I, User::op_iterator E); }; -} // Pass the Type* and the variable name and this prints out the variable // declaration. @@ -339,7 +340,7 @@ void CWriter::printConstantArray(ConstantArray *CPA) { // compiler agreeing on the conversion process (which is pretty likely since we // only deal in IEEE FP). // -static bool isFPCSafeToPrint(const ConstantFP *CFP) { +bool isFPCSafeToPrint(const ConstantFP *CFP) { #if HAVE_PRINTF_A char Buffer[100]; sprintf(Buffer, "%a", CFP->getValue()); @@ -563,7 +564,7 @@ bool CWriter::nameAllUsedStructureTypes(Module &M) { // generateCompilerSpecificCode - This is where we add conditional compilation // directives to cater to specific compilers as need be. // -static void generateCompilerSpecificCode(std::ostream& Out) { +void generateCompilerSpecificCode(std::ostream& Out) { // Alloca is hard to get, and we don't want to include stdlib.h here... Out << "/* get a declaration for alloca */\n" << "#ifdef sun\n" @@ -1058,7 +1059,7 @@ void CWriter::visitUnwindInst(UnwindInst &I) { emittedInvoke = true; } -static bool isGotoCodeNecessary(BasicBlock *From, BasicBlock *To) { +bool isGotoCodeNecessary(BasicBlock *From, BasicBlock *To) { // If PHI nodes need copies, we need the copy code... if (isa<PHINode>(To->front()) || From->getNext() != To) // Not directly successor, need goto @@ -1195,10 +1196,10 @@ void CWriter::visitCastInst(CastInst &I) { void CWriter::visitCallInst(CallInst &I) { // Handle intrinsic function calls first... if (Function *F = I.getCalledFunction()) - if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) { + if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) { switch (ID) { default: assert(0 && "Unknown LLVM intrinsic!"); - case LLVMIntrinsic::va_start: + case Intrinsic::va_start: Out << "0; "; Out << "va_start(*(va_list*)&" << Mang->getValueName(&I) << ", "; @@ -1212,28 +1213,28 @@ void CWriter::visitCallInst(CallInst &I) { writeOperand(&I.getParent()->getParent()->aback()); Out << ")"; return; - case LLVMIntrinsic::va_end: + case Intrinsic::va_end: Out << "va_end(*(va_list*)&"; writeOperand(I.getOperand(1)); Out << ")"; return; - case LLVMIntrinsic::va_copy: + case Intrinsic::va_copy: Out << "0;"; Out << "va_copy(*(va_list*)&" << Mang->getValueName(&I) << ", "; Out << "*(va_list*)&"; writeOperand(I.getOperand(1)); Out << ")"; return; - case LLVMIntrinsic::setjmp: - case LLVMIntrinsic::sigsetjmp: + case Intrinsic::setjmp: + case Intrinsic::sigsetjmp: // This intrinsic should never exist in the program, but until we get // setjmp/longjmp transformations going on, we should codegen it to // something reasonable. This will allow code that never calls longjmp // to work. Out << "0"; return; - case LLVMIntrinsic::longjmp: - case LLVMIntrinsic::siglongjmp: + case Intrinsic::longjmp: + case Intrinsic::siglongjmp: // Longjmp is not implemented, and never will be. It would cause an // exception throw. Out << "abort()"; @@ -1385,9 +1386,12 @@ void CWriter::visitVAArgInst(VAArgInst &I) { Out << ");\n va_end(Tmp); }"; } +} //===----------------------------------------------------------------------===// // External Interface declaration //===----------------------------------------------------------------------===// Pass *createWriteToCPass(std::ostream &o) { return new CWriter(o); } + +} // End llvm namespace diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp index 6f35815..7c1028b 100644 --- a/lib/Target/MRegisterInfo.cpp +++ b/lib/Target/MRegisterInfo.cpp @@ -13,6 +13,8 @@ #include "llvm/Target/MRegisterInfo.h" +namespace llvm { + MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR, regclass_iterator RCB, regclass_iterator RCE, int CFSO, int CFDO) @@ -41,3 +43,5 @@ MRegisterInfo::MRegisterInfo(const MRegisterDesc *D, unsigned NR, MRegisterInfo::~MRegisterInfo() { delete[] PhysRegClasses; } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp b/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp index 2c45021..a603e94 100644 --- a/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp +++ b/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp @@ -18,6 +18,8 @@ #include "llvm/Bytecode/Writer.h" #include <iostream> +namespace llvm { + using std::ostream; namespace { @@ -113,3 +115,5 @@ namespace { Pass *UltraSparc::getBytecodeAsmPrinterPass(std::ostream &Out) { return new SparcBytecodeWriter(Out); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index a50439d..4e2bf47 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -22,6 +22,8 @@ #include "Support/CommandLine.h" #include <algorithm> +namespace llvm { + SchedDebugLevel_t SchedDebugLevel; static cl::opt<bool> EnableFillingDelaySlots("sched-fill-delay-slots", @@ -1518,3 +1520,6 @@ bool InstructionSchedulingWithSSA::runOnFunction(Function &F) FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) { return new InstructionSchedulingWithSSA(tgt); } + +} // End llvm namespace + diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index e7cd478..3a80880 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -23,6 +23,8 @@ #include "llvm/Target/TargetRegInfo.h" #include "Support/STLExtras.h" +namespace llvm { + //*********************** Internal Data Structures *************************/ // The following two types need to be classes, not typedefs, so we can use @@ -737,3 +739,5 @@ void SchedGraphNode::print(std::ostream &os) const { os << std::string(16, ' ') << *outEdges[i]; } } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.h b/lib/Target/SparcV9/InstrSched/SchedGraph.h index 50cc052..5aee9b2 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.h +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.h @@ -25,6 +25,8 @@ #include "Support/hash_map" #include "Support/GraphTraits.h" +namespace llvm { + class RegToRefVecMap; class ValueToDefVecMap; class RefVec; @@ -317,4 +319,6 @@ template <> struct GraphTraits<const SchedGraph*> { } }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp b/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp index b75e339..d96c201 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraphCommon.cpp @@ -15,6 +15,8 @@ #include "llvm/CodeGen/SchedGraphCommon.h" #include "Support/STLExtras.h" +namespace llvm { + class SchedGraphCommon; // @@ -175,3 +177,4 @@ void SchedGraphCommon::eraseIncidentEdges(SchedGraphNodeCommon* node, this->eraseOutgoingEdges(node, addDummyEdges); } +} // End llvm namespace diff --git a/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp b/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp index 1644d5e..7e05d14 100644 --- a/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedPriorities.cpp @@ -23,6 +23,8 @@ #include "llvm/Support/CFG.h" #include "Support/PostOrderIterator.h" +namespace llvm { + std::ostream &operator<<(std::ostream &os, const NodeDelayPair* nd) { return os << "Delay for node " << nd->node->getNodeId() << " = " << (long)nd->delay << "\n"; @@ -278,3 +280,4 @@ SchedPriorities::instructionHasLastUse(FunctionLiveVarInfo &LVI, return lastUseMap[MI] = hasLastUse; } +} // End llvm namespace diff --git a/lib/Target/SparcV9/InstrSched/SchedPriorities.h b/lib/Target/SparcV9/InstrSched/SchedPriorities.h index de321f9..7470467 100644 --- a/lib/Target/SparcV9/InstrSched/SchedPriorities.h +++ b/lib/Target/SparcV9/InstrSched/SchedPriorities.h @@ -26,6 +26,8 @@ #include "Support/hash_set" #include <list> +namespace llvm { + class Function; class MachineInstr; class SchedulingManager; @@ -214,4 +216,6 @@ inline void SchedPriorities::updateTime(cycles_t c) { std::ostream &operator<<(std::ostream &os, const NodeDelayPair* nd); +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/InstrSelection/InstrForest.cpp b/lib/Target/SparcV9/InstrSelection/InstrForest.cpp index 5496502..fd5056d2 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrForest.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrForest.cpp @@ -30,6 +30,8 @@ #include "Support/STLExtras.h" #include "Config/alloca.h" +namespace llvm { + //------------------------------------------------------------------------ // class InstrTreeNode //------------------------------------------------------------------------ @@ -330,3 +332,5 @@ InstructionNode* InstrForest::buildTreeForInstruction(Instruction *instr) { delete [] childArray; return treeNode; } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp index 0e3e2cd..7609765 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp @@ -28,6 +28,8 @@ #include "Support/LeakDetector.h" #include <vector> +namespace llvm { + std::vector<MachineInstr*> FixConstantOperandsForInstr(Instruction* vmInstr, MachineInstr* minstr, TargetMachine& target); @@ -82,6 +84,8 @@ namespace { }; } +namespace llvm { + TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi, Value *s1, Value *s2, const std::string &name) : Instruction(s1->getType(), Instruction::UserOp1, name) @@ -114,6 +118,7 @@ TmpInstruction::TmpInstruction(MachineCodeForInstruction& mcfi, LeakDetector::removeGarbageObject(this); } +} // End llvm namespace bool InstructionSelection::runOnFunction(Function &F) { @@ -375,7 +380,6 @@ InstructionSelection::PostprocessMachineCodeForTree(InstructionNode* instrNode, } - //===----------------------------------------------------------------------===// // createInstructionSelectionPass - Public entrypoint for instruction selection // and this file as a whole... @@ -383,3 +387,5 @@ InstructionSelection::PostprocessMachineCodeForTree(InstructionNode* instrNode, FunctionPass *createInstructionSelectionPass(TargetMachine &T) { return new InstructionSelection(T); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp index 93f7618..44a4359 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp @@ -25,6 +25,7 @@ #include "llvm/DerivedTypes.h" #include "../../Target/Sparc/SparcInstrSelectionSupport.h" // FIXME! +namespace llvm { // Generate code to load the constant into a TmpInstruction (virtual reg) and // returns the virtual register. @@ -257,3 +258,5 @@ FixConstantOperandsForInstr(Instruction* vmInstr, return MVec; } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp index 68eaebf..758f1b1 100644 --- a/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp +++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.cpp @@ -21,6 +21,7 @@ /// BROKEN: Should not include sparc stuff directly into here #include "../../Target/Sparc/SparcInternals.h" // Only for PHI defn +namespace llvm { BBLiveVar::BBLiveVar(const BasicBlock &bb, MachineBasicBlock &mbb, unsigned id) : BB(bb), MBB(mbb), POID(id) { @@ -229,6 +230,4 @@ void BBLiveVar::printInOutSets() const { std::cerr << " Out: "; printSet(OutSet); std::cerr << "\n"; } - - - +} // End llvm namespace diff --git a/lib/Target/SparcV9/LiveVar/BBLiveVar.h b/lib/Target/SparcV9/LiveVar/BBLiveVar.h index 33a4faf..781143a 100644 --- a/lib/Target/SparcV9/LiveVar/BBLiveVar.h +++ b/lib/Target/SparcV9/LiveVar/BBLiveVar.h @@ -17,6 +17,9 @@ #include "llvm/CodeGen/ValueSet.h" #include "Support/hash_map" + +namespace llvm { + class BasicBlock; class Value; class MachineBasicBlock; @@ -82,4 +85,6 @@ public: void printInOutSets() const; // for printing In/Out sets }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp index 588ec64..8f0e318 100644 --- a/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp +++ b/lib/Target/SparcV9/LiveVar/FunctionLiveVarInfo.cpp @@ -23,6 +23,8 @@ #include "Support/CommandLine.h" #include "BBLiveVar.h" +namespace llvm { + static RegisterAnalysis<FunctionLiveVarInfo> X("livevar", "Live Variable Analysis"); @@ -318,3 +320,5 @@ void FunctionLiveVarInfo::calcLiveVarSetsForBB(const BasicBlock *BB) { SetAI = NewSet; } } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/LiveVar/ValueSet.cpp b/lib/Target/SparcV9/LiveVar/ValueSet.cpp index ba944cb..fd82896 100644 --- a/lib/Target/SparcV9/LiveVar/ValueSet.cpp +++ b/lib/Target/SparcV9/LiveVar/ValueSet.cpp @@ -11,6 +11,8 @@ #include "llvm/Value.h" #include <iostream> +namespace llvm { + std::ostream &operator<<(std::ostream &O, RAV V) { // func to print a Value const Value &v = V.V; if (v.hasName()) @@ -26,3 +28,4 @@ void printSet(const ValueSet &S) { std::cerr << RAV(*I); } +} // End llvm namespace diff --git a/lib/Target/SparcV9/MachineCodeForInstruction.h b/lib/Target/SparcV9/MachineCodeForInstruction.h index d421f3e..9a08de7 100644 --- a/lib/Target/SparcV9/MachineCodeForInstruction.h +++ b/lib/Target/SparcV9/MachineCodeForInstruction.h @@ -28,6 +28,8 @@ #include "Support/Annotation.h" #include <vector> +namespace llvm { + class MachineInstr; class Instruction; class Value; @@ -96,4 +98,6 @@ public: CallArgsDescriptor* getCallArgsDescriptor() const { return callArgsDesc; } }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/MachineFunctionInfo.h b/lib/Target/SparcV9/MachineFunctionInfo.h index db73322..fdf135b 100644 --- a/lib/Target/SparcV9/MachineFunctionInfo.h +++ b/lib/Target/SparcV9/MachineFunctionInfo.h @@ -17,6 +17,9 @@ #include "Support/HashExtras.h" #include "Support/hash_set" + +namespace llvm { + class MachineFunction; class Value; class Constant; @@ -112,4 +115,6 @@ private: int allocateOptionalArg(const Type* type); }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/MachineInstrAnnot.h b/lib/Target/SparcV9/MachineInstrAnnot.h index 98dde59..19d93ab 100644 --- a/lib/Target/SparcV9/MachineInstrAnnot.h +++ b/lib/Target/SparcV9/MachineInstrAnnot.h @@ -17,6 +17,8 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/Target/TargetRegInfo.h" +namespace llvm { + class Value; class TmpInstruction; class CallInst; @@ -88,5 +90,6 @@ public: static CallArgsDescriptor *get(const MachineInstr* MI); }; +} // End llvm namespace #endif diff --git a/lib/Target/SparcV9/MappingInfo.cpp b/lib/Target/SparcV9/MappingInfo.cpp index db03f13..2afde6b 100644 --- a/lib/Target/SparcV9/MappingInfo.cpp +++ b/lib/Target/SparcV9/MappingInfo.cpp @@ -49,6 +49,8 @@ #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "Support/StringExtras.h" +namespace llvm { + namespace { class MappingInfoAsmPrinter : public FunctionPass { std::ostream &Out; @@ -293,3 +295,5 @@ bool MappingInfoAsmPrinter::doFinalization (Module &M) { return false; } +} // End llvm namespace + diff --git a/lib/Target/SparcV9/MappingInfo.h b/lib/Target/SparcV9/MappingInfo.h index f86e2b4..6af116a 100644 --- a/lib/Target/SparcV9/MappingInfo.h +++ b/lib/Target/SparcV9/MappingInfo.h @@ -18,6 +18,9 @@ #include <iosfwd> #include <vector> #include <string> + +namespace llvm { + class Pass; Pass *getMappingInfoAsmPrinterPass(std::ostream &out); @@ -41,4 +44,6 @@ public: } }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/ModuloScheduling/ModuloSchedGraph.cpp b/lib/Target/SparcV9/ModuloScheduling/ModuloSchedGraph.cpp index 6318c5a..8aaaa2b 100644 --- a/lib/Target/SparcV9/ModuloScheduling/ModuloSchedGraph.cpp +++ b/lib/Target/SparcV9/ModuloScheduling/ModuloSchedGraph.cpp @@ -13,6 +13,8 @@ #include "ModuloSchedGraph.h" #include "llvm/Type.h" +namespace llvm { + ModuloSchedGraphNode::ModuloSchedGraphNode(unsigned id, int index, const Instruction *inst, const TargetMachine &targ) @@ -135,3 +137,4 @@ ModuloSchedGraphSet::~ModuloSchedGraphSet(){ //delete all the graphs } +} // End llvm namespace diff --git a/lib/Target/SparcV9/ModuloScheduling/ModuloSchedGraph.h b/lib/Target/SparcV9/ModuloScheduling/ModuloSchedGraph.h index 214e24c..552d699 100644 --- a/lib/Target/SparcV9/ModuloScheduling/ModuloSchedGraph.h +++ b/lib/Target/SparcV9/ModuloScheduling/ModuloSchedGraph.h @@ -22,6 +22,7 @@ #include "Support/hash_map" #include <vector> +namespace llvm { class ModuloSchedGraphNode : public SchedGraphNodeCommon { @@ -106,4 +107,6 @@ public: }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp b/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp index 91ec6c2..219d892 100644 --- a/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp +++ b/lib/Target/SparcV9/ModuloScheduling/ModuloScheduling.cpp @@ -16,6 +16,8 @@ #include "llvm/Function.h" #include "llvm/Pass.h" +namespace llvm { + namespace { class ModuloScheduling : public FunctionPass { @@ -40,3 +42,5 @@ bool ModuloScheduling::runOnFunction(Function &F) { bool Changed = false; return Changed; } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/RegAlloc/AllocInfo.h b/lib/Target/SparcV9/RegAlloc/AllocInfo.h index f83f210..67f58a7 100644 --- a/lib/Target/SparcV9/RegAlloc/AllocInfo.h +++ b/lib/Target/SparcV9/RegAlloc/AllocInfo.h @@ -19,6 +19,8 @@ #include "llvm/DerivedTypes.h" #include "llvm/Constants.h" +namespace llvm { + /// AllocInfo - Structure representing one instruction's operand's-worth of /// register allocation state. We create tables made out of these data /// structures to generate mapping information for this register allocator. @@ -77,4 +79,6 @@ struct AllocInfo { } }; +} // End llvm namespace + #endif // ALLOCINFO_H diff --git a/lib/Target/SparcV9/RegAlloc/IGNode.cpp b/lib/Target/SparcV9/RegAlloc/IGNode.cpp index f883fb1..a76fdea 100644 --- a/lib/Target/SparcV9/RegAlloc/IGNode.cpp +++ b/lib/Target/SparcV9/RegAlloc/IGNode.cpp @@ -16,6 +16,8 @@ #include <algorithm> #include <iostream> +namespace llvm { + //----------------------------------------------------------------------------- // Sets this IGNode on stack and reduce the degree of neighbors //----------------------------------------------------------------------------- @@ -56,3 +58,5 @@ IGNode::getCombinedDegree(const IGNode* otherNode) const { std::vector<IGNode*>::iterator new_end = unique(nbrs.begin(), nbrs.end()); return new_end - nbrs.begin(); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/RegAlloc/IGNode.h b/lib/Target/SparcV9/RegAlloc/IGNode.h index 82f07e0..9fdc7a6 100644 --- a/lib/Target/SparcV9/RegAlloc/IGNode.h +++ b/lib/Target/SparcV9/RegAlloc/IGNode.h @@ -32,6 +32,9 @@ #include "LiveRange.h" #include <vector> + +namespace llvm { + class RegClass; //---------------------------------------------------------------------------- @@ -115,4 +118,6 @@ public: inline LiveRange *getParentLR() const { return ParentLR; } }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp index 392a96c..3cef19e 100644 --- a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp +++ b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp @@ -17,6 +17,8 @@ #include "Support/STLExtras.h" #include <algorithm> +namespace llvm { + // for asserting this IG node is infact in the IGNodeList of this class inline static void assertIGNode(const InterferenceGraph *IG, const IGNode *Node) { @@ -246,3 +248,5 @@ void InterferenceGraph::printIGNodeList() const { } } } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h index 6b8cf3c..79850c1 100644 --- a/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h +++ b/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h @@ -30,6 +30,9 @@ #define INTERFERENCEGRAPH_H #include <vector> + +namespace llvm { + class LiveRange; class RegClass; class IGNode; @@ -67,4 +70,6 @@ class InterferenceGraph { void printIGNodeList() const; }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/RegAlloc/LiveRange.h b/lib/Target/SparcV9/RegAlloc/LiveRange.h index aa409c6..d6e2cf6 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRange.h +++ b/lib/Target/SparcV9/RegAlloc/LiveRange.h @@ -21,6 +21,8 @@ #include "llvm/Value.h" #include "llvm/CodeGen/ValueSet.h" +namespace llvm { + class RegClass; class IGNode; @@ -177,4 +179,6 @@ public: } }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp index b9fcda7..9fd04d2 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp +++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp @@ -23,6 +23,8 @@ #include "llvm/Target/TargetRegInfo.h" #include "Support/SetOperations.h" +namespace llvm { + unsigned LiveRange::getRegClassID() const { return getRegClass()->getID(); } LiveRangeInfo::LiveRangeInfo(const Function *F, const TargetMachine &tm, @@ -411,3 +413,5 @@ void LiveRangeInfo::printLiveRanges() { } } } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h index 5c5244b..a8d0e71 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h +++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h @@ -29,6 +29,8 @@ #include "llvm/CodeGen/ValueSet.h" #include "Support/hash_map" +namespace llvm { + class LiveRange; class MachineInstr; class RegClass; @@ -121,4 +123,6 @@ public: void printLiveRanges(); }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp index 99917cd..332ae95 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp @@ -47,6 +47,8 @@ #include "Support/STLExtras.h" #include <cmath> +namespace llvm { + RegAllocDebugLevel_t DEBUG_RA; /// The reoptimizer wants to be able to grovel through the register @@ -1392,3 +1394,5 @@ bool PhyRegAlloc::runOnFunction (Function &F) { if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n"; return false; // Function was not modified } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h index c524f9f..4ec083c 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h @@ -31,6 +31,8 @@ #include "llvm/Target/TargetRegInfo.h" #include <map> +namespace llvm { + class MachineFunction; class FunctionLiveVarInfo; class MachineInstr; @@ -179,4 +181,6 @@ private: void addInterf4PseudoInstr(const MachineInstr *MI); }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h b/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h index 97d102a..7dd86b2 100644 --- a/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h +++ b/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h @@ -14,6 +14,8 @@ #ifndef REGALLOCCOMMON_H #define REGALLOCCOMMON_H +namespace llvm { + enum RegAllocDebugLevel_t { RA_DEBUG_None = 0, RA_DEBUG_Results = 1, @@ -25,4 +27,6 @@ enum RegAllocDebugLevel_t { extern RegAllocDebugLevel_t DEBUG_RA; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.cpp b/lib/Target/SparcV9/RegAlloc/RegClass.cpp index 9c8603b..9af87ba 100644 --- a/lib/Target/SparcV9/RegAlloc/RegClass.cpp +++ b/lib/Target/SparcV9/RegAlloc/RegClass.cpp @@ -16,6 +16,8 @@ #include "RegClass.h" #include "llvm/Target/TargetRegInfo.h" +namespace llvm { + //---------------------------------------------------------------------------- // This constructor inits IG. The actual matrix is created by a call to // createInterferenceGraph() above. @@ -245,4 +247,4 @@ void RegClass::printIG() { IG.printIG(); } - +} // End llvm namespace diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.h b/lib/Target/SparcV9/RegAlloc/RegClass.h index c861fba..0071f7c 100644 --- a/lib/Target/SparcV9/RegAlloc/RegClass.h +++ b/lib/Target/SparcV9/RegAlloc/RegClass.h @@ -20,6 +20,9 @@ #include "llvm/Target/TargetRegInfo.h" #include "InterferenceGraph.h" #include <stack> + +namespace llvm { + class TargetRegClassInfo; @@ -139,4 +142,6 @@ class RegClass { void printIG(); }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/SparcV9.burg.in b/lib/Target/SparcV9/SparcV9.burg.in index a5bc98f..38dc243 100644 --- a/lib/Target/SparcV9/SparcV9.burg.in +++ b/lib/Target/SparcV9/SparcV9.burg.in @@ -11,7 +11,7 @@ Xinclude <cstdio> Xinclude <llvm/CodeGen/InstrForest.h> -typedef InstrTreeNode* NODEPTR_TYPE; +typedef llvm::InstrTreeNode* NODEPTR_TYPE; Xdefine OP_LABEL(p) ((p)->opLabel) Xdefine LEFT_CHILD(p) ((p)->LeftChild) Xdefine RIGHT_CHILD(p) ((p)->RightChild) diff --git a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp index 2503417..6af9836 100644 --- a/lib/Target/SparcV9/SparcV9AsmPrinter.cpp +++ b/lib/Target/SparcV9/SparcV9AsmPrinter.cpp @@ -33,6 +33,8 @@ #include "SparcInternals.h" #include <string> +namespace llvm { + namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); @@ -877,12 +879,13 @@ SparcFunctionAsmPrinter::emitFunction(const Function &F) } // End anonymous namespace +namespace llvm { + Pass *UltraSparc::getFunctionAsmPrinterPass(std::ostream &Out) { return new SparcFunctionAsmPrinter(Out, *this); } - - +} // End llvm namespace //===----------------------------------------------------------------------===// @@ -954,3 +957,5 @@ void SparcModuleAsmPrinter::emitGlobals(const Module &M) { Pass *UltraSparc::getModuleAsmPrinterPass(std::ostream &Out) { return new SparcModuleAsmPrinter(Out, *this); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp index d60d915..c50dca5 100644 --- a/lib/Target/SparcV9/SparcV9CodeEmitter.cpp +++ b/lib/Target/SparcV9/SparcV9CodeEmitter.cpp @@ -38,6 +38,8 @@ #include "SparcV9CodeEmitter.h" #include "Config/alloca.h" +namespace llvm { + namespace { Statistic<> OverwrittenCalls("call-ovwr", "Number of over-written calls"); Statistic<> UnmodifiedCalls("call-skip", "Number of unmodified calls"); @@ -443,7 +445,6 @@ uint64_t JITResolver::emitStubForFunction(Function *F) { return (intptr_t)MCE.finishFunctionStub(*F)+4; /* 1 instr past the restore */ } - SparcV9CodeEmitter::SparcV9CodeEmitter(TargetMachine &tm, MachineCodeEmitter &M): TM(tm), MCE(M) { @@ -809,4 +810,6 @@ void* SparcV9CodeEmitter::getGlobalAddress(GlobalValue *V, MachineInstr &MI, } } +} // End llvm namespace + #include "SparcV9CodeEmitter.inc" diff --git a/lib/Target/SparcV9/SparcV9CodeEmitter.h b/lib/Target/SparcV9/SparcV9CodeEmitter.h index 7e19c44..d21345e 100644 --- a/lib/Target/SparcV9/SparcV9CodeEmitter.h +++ b/lib/Target/SparcV9/SparcV9CodeEmitter.h @@ -19,6 +19,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/Target/TargetMachine.h" +namespace llvm { + class GlobalValue; class MachineInstr; class MachineOperand; @@ -81,4 +83,6 @@ private: }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/SparcV9InstrInfo.cpp b/lib/Target/SparcV9/SparcV9InstrInfo.cpp index d92e3be..11b0c7b 100644 --- a/lib/Target/SparcV9/SparcV9InstrInfo.cpp +++ b/lib/Target/SparcV9/SparcV9InstrInfo.cpp @@ -23,6 +23,8 @@ #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +namespace llvm { + static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*) static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR @@ -792,3 +794,5 @@ UltraSparcInstrInfo::CreateZeroExtensionInstructions( CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal, destVal, numLowBits, mvec, mcfi); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/SparcV9InstrSelection.cpp b/lib/Target/SparcV9/SparcV9InstrSelection.cpp index b377658..21e884b 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelection.cpp +++ b/lib/Target/SparcV9/SparcV9InstrSelection.cpp @@ -32,6 +32,8 @@ #include <algorithm> #include <cmath> +namespace llvm { + static inline void Add3OperandInstr(unsigned Opcode, InstructionNode* Node, std::vector<MachineInstr*>& mvec) { mvec.push_back(BuildMI(Opcode, 3).addReg(Node->leftChild()->getValue()) @@ -1390,12 +1392,12 @@ AllUsesAreBranches(const Instruction* setccI) // instead of a regular call. If not that kind of intrinsic, do nothing. // Returns true if code was generated, otherwise false. // -bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr, +bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr, TargetMachine &target, std::vector<MachineInstr*>& mvec) { switch (iid) { - case LLVMIntrinsic::va_start: { + case Intrinsic::va_start: { // Get the address of the first incoming vararg argument on the stack bool ignore; Function* func = cast<Function>(callInstr.getParent()->getParent()); @@ -1409,10 +1411,10 @@ bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr, return true; } - case LLVMIntrinsic::va_end: + case Intrinsic::va_end: return true; // no-op on Sparc - case LLVMIntrinsic::va_copy: + case Intrinsic::va_copy: // Simple copy of current va_list (arg1) to new va_list (result) mvec.push_back(BuildMI(V9::ORr, 3). addMReg(target.getRegInfo().getZeroRegNum()). @@ -1420,8 +1422,8 @@ bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr, addRegDef(&callInstr)); return true; - case LLVMIntrinsic::sigsetjmp: - case LLVMIntrinsic::setjmp: { + case Intrinsic::sigsetjmp: + case Intrinsic::setjmp: { // act as if we return 0 unsigned g0 = target.getRegInfo().getZeroRegNum(); mvec.push_back(BuildMI(V9::ORr,3).addMReg(g0).addMReg(g0) @@ -1429,8 +1431,8 @@ bool CodeGenIntrinsic(LLVMIntrinsic::ID iid, CallInst &callInstr, return true; } - case LLVMIntrinsic::siglongjmp: - case LLVMIntrinsic::longjmp: { + case Intrinsic::siglongjmp: + case Intrinsic::longjmp: { // call abort() Module* M = callInstr.getParent()->getParent()->getParent(); const FunctionType *voidvoidFuncTy = @@ -2474,8 +2476,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, // sequence (e.g., va_start). Indirect calls cannot be special. // bool specialIntrinsic = false; - LLVMIntrinsic::ID iid; - if (calledFunc && (iid=(LLVMIntrinsic::ID)calledFunc->getIntrinsicID())) + Intrinsic::ID iid; + if (calledFunc && (iid=(Intrinsic::ID)calledFunc->getIntrinsicID())) specialIntrinsic = CodeGenIntrinsic(iid, *callInstr, target, mvec); // If not, generate the normal call sequence for the function. @@ -2929,3 +2931,5 @@ GetInstructionsByRule(InstructionNode* subtreeRoot, } } } + +} diff --git a/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h b/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h index d49863c..b69c5c2 100644 --- a/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h +++ b/lib/Target/SparcV9/SparcV9InstrSelectionSupport.h @@ -17,6 +17,8 @@ #include "llvm/DerivedTypes.h" #include "SparcInternals.h" +namespace llvm { + // Choose load instruction opcode based on type of value inline MachineOpCode ChooseLoadInstruction(const Type *DestTy) @@ -220,4 +222,6 @@ convertOpcodeFromRegToImm(unsigned Opcode) { } } +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h index 4d0a48e..5e5f155 100644 --- a/lib/Target/SparcV9/SparcV9Internals.h +++ b/lib/Target/SparcV9/SparcV9Internals.h @@ -25,6 +25,8 @@ #include "SparcRegClassInfo.h" #include "Config/sys/types.h" +namespace llvm { + class LiveRange; class UltraSparc; class Pass; @@ -693,4 +695,6 @@ public: Pass* getBytecodeAsmPrinterPass(std::ostream &Out); }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp index 83081b7..9713a02 100644 --- a/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp +++ b/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp @@ -20,6 +20,8 @@ #include "llvm/BasicBlock.h" #include "llvm/Pass.h" +namespace llvm { + //************************* Internal Functions *****************************/ static inline void @@ -163,3 +165,5 @@ bool PeepholeOpts::runOnBasicBlock(BasicBlock &BB) { FunctionPass* createPeepholeOptsPass(const TargetMachine &TM) { return new PeepholeOpts(TM); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/SparcV9PreSelection.cpp b/lib/Target/SparcV9/SparcV9PreSelection.cpp index 9078dc1..205ecd3 100644 --- a/lib/Target/SparcV9/SparcV9PreSelection.cpp +++ b/lib/Target/SparcV9/SparcV9PreSelection.cpp @@ -29,6 +29,8 @@ #include "llvm/Transforms/Scalar.h" #include <algorithm> +namespace llvm { + namespace { //===--------------------------------------------------------------------===// @@ -71,6 +73,7 @@ namespace { "Specialize LLVM code for a target machine" createPreselectionPass); #endif + } // end anonymous namespace @@ -236,7 +239,6 @@ void PreSelection::visitCallInst(CallInst &I) { visitOperands(I, (/*firstOp=*/ I.getCalledFunction()? 1 : 0)); } - //===----------------------------------------------------------------------===// // createPreSelectionPass - Public entrypoint for pre-selection pass // and this file as a whole... @@ -244,3 +246,5 @@ void PreSelection::visitCallInst(CallInst &I) { FunctionPass* createPreSelectionPass(const TargetMachine &TM) { return new PreSelection(TM); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp index ff7bd7d..555b6b1 100644 --- a/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp +++ b/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp @@ -27,6 +27,8 @@ #include "llvm/DerivedTypes.h" #include "llvm/Intrinsics.h" +namespace llvm { + namespace { struct InsertPrologEpilogCode : public MachineFunctionPass { const char *getPassName() const { return "Sparc Prolog/Epilog Inserter"; } @@ -177,3 +179,5 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF) FunctionPass *UltraSparc::getPrologEpilogInsertionPass() { return new InsertPrologEpilogCode(); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp index d6de5f9..564e59c 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.cpp @@ -17,6 +17,8 @@ #include "../../CodeGen/RegAlloc/RegAllocCommon.h" // FIXME! #include "../../CodeGen/RegAlloc/IGNode.h" // FIXME! +namespace llvm { + //----------------------------------------------------------------------------- // Int Register Class - method for coloring a node in the interference graph. // @@ -390,3 +392,5 @@ int SparcFloatRegClass::findFloatColor(const LiveRange *LR, return -1; } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.h b/lib/Target/SparcV9/SparcV9RegClassInfo.h index 321ce60..cc492e7 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.h +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.h @@ -16,6 +16,8 @@ #include "llvm/Target/TargetRegInfo.h" +namespace llvm { + //----------------------------------------------------------------------------- // Integer Register Class //----------------------------------------------------------------------------- @@ -217,4 +219,6 @@ struct SparcSpecialRegClass : public TargetRegClassInfo { const char * const getRegName(unsigned reg) const; }; +} // End llvm namespace + #endif diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index 84dc92e..5edbbe0 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -27,6 +27,8 @@ #include "llvm/Function.h" #include "llvm/DerivedTypes.h" +namespace llvm { + enum { BadRegClass = ~0 }; @@ -967,3 +969,5 @@ void UltraSparcRegInfo::printReg(const LiveRange *LR) const { std::cerr << "+" << getUnifiedRegName(uRegName+1); std::cerr << "]\n"; } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/SparcV9SchedInfo.cpp b/lib/Target/SparcV9/SparcV9SchedInfo.cpp index fd03ad6..7d8ea05 100644 --- a/lib/Target/SparcV9/SparcV9SchedInfo.cpp +++ b/lib/Target/SparcV9/SparcV9SchedInfo.cpp @@ -13,6 +13,8 @@ #include "SparcInternals.h" +using namespace llvm; + /*--------------------------------------------------------------------------- Scheduling guidelines for SPARC IIi: diff --git a/lib/Target/SparcV9/SparcV9StackSlots.cpp b/lib/Target/SparcV9/SparcV9StackSlots.cpp index 551dd92..5fd0ba1 100644 --- a/lib/Target/SparcV9/SparcV9StackSlots.cpp +++ b/lib/Target/SparcV9/SparcV9StackSlots.cpp @@ -20,6 +20,8 @@ #include "llvm/CodeGen/MachineFunctionInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" +namespace llvm { + namespace { class StackSlots : public MachineFunctionPass { const TargetMachine &Target; @@ -48,3 +50,5 @@ namespace { Pass *createStackSlotsPass(const TargetMachine &Target) { return new StackSlots(Target); } + +} // End llvm namespace diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp index d20fc75..73f2fd8 100644 --- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp +++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp @@ -27,6 +27,8 @@ #include "llvm/Target/TargetMachineImpls.h" #include "Support/CommandLine.h" +namespace llvm { + static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */ // Build the MachineInstruction Description Array... const TargetInstrDescriptor SparcMachineInstrDesc[] = { @@ -267,3 +269,5 @@ bool UltraSparc::addPassesToJITCompile(FunctionPassManager &PM) { return false; // success! } + +} // End llvm namespace diff --git a/lib/Target/TargetData.cpp b/lib/Target/TargetData.cpp index a377fd0..ed6936d 100644 --- a/lib/Target/TargetData.cpp +++ b/lib/Target/TargetData.cpp @@ -22,13 +22,14 @@ #include "llvm/DerivedTypes.h" #include "llvm/Constants.h" +namespace llvm { + // Handle the Pass registration stuff necessary to use TargetData's. namespace { // Register the default SparcV9 implementation... RegisterPass<TargetData> X("targetdata", "Target Data Layout"); } - static inline void getTypeInfo(const Type *Ty, const TargetData *TD, uint64_t &Size, unsigned char &Alignment); @@ -221,3 +222,5 @@ uint64_t TargetData::getIndexedOffset(const Type *ptrTy, return Result; } + +} // End llvm namespace diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp index f377d67..0f9015f 100644 --- a/lib/Target/TargetInstrInfo.cpp +++ b/lib/Target/TargetInstrInfo.cpp @@ -15,6 +15,8 @@ #include "llvm/Constant.h" #include "llvm/DerivedTypes.h" +namespace llvm { + // External object describing the machine instructions // Initialized only when the TargetMachine class is created // and reset when that class is destroyed. @@ -59,3 +61,5 @@ bool TargetInstrInfo::ConstantTypeMustBeLoaded(const Constant* CV) const { assert(CV->getType()->isPrimitiveType() || isa<PointerType>(CV->getType())); return !(CV->getType()->isIntegral() || isa<PointerType>(CV->getType())); } + +} // End llvm namespace diff --git a/lib/Target/TargetMachine.cpp b/lib/Target/TargetMachine.cpp index b7c1b34..e7630b4 100644 --- a/lib/Target/TargetMachine.cpp +++ b/lib/Target/TargetMachine.cpp @@ -16,6 +16,8 @@ #include "llvm/Target/TargetCacheInfo.h" #include "llvm/Type.h" +namespace llvm { + //--------------------------------------------------------------------------- // class TargetMachine // @@ -49,3 +51,5 @@ void TargetCacheInfo::Initialize() { cacheSizes.push_back(1 << 15); cacheSizes.push_back(1 << 20); cacheAssoc.push_back(1); cacheAssoc.push_back(4); } + +} // End llvm namespace diff --git a/lib/Target/TargetSchedInfo.cpp b/lib/Target/TargetSchedInfo.cpp index 0dbde45..f33223c 100644 --- a/lib/Target/TargetSchedInfo.cpp +++ b/lib/Target/TargetSchedInfo.cpp @@ -15,6 +15,8 @@ #include "llvm/Target/TargetSchedInfo.h" #include "llvm/Target/TargetMachine.h" +namespace llvm { + resourceId_t MachineResource::nextId = 0; // Check if fromRVec and toRVec have *any* common entries. @@ -249,3 +251,5 @@ void InstrRUsage::addUsageDelta(const InstrRUsageDelta &delta) { assert(r >= 0 && "Resource to remove was unused in cycle c!"); } } + +} // End llvm namespace diff --git a/lib/Target/X86/FloatingPoint.cpp b/lib/Target/X86/FloatingPoint.cpp index 07e58ba..5c6e6eb 100644 --- a/lib/Target/X86/FloatingPoint.cpp +++ b/lib/Target/X86/FloatingPoint.cpp @@ -25,6 +25,8 @@ #include <algorithm> #include <iostream> +namespace llvm { + namespace { Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted"); Statistic<> NumFP ("x86-codegen", "Number of floating point instructions"); @@ -70,7 +72,7 @@ namespace { // getSTReg - Return the X86::ST(i) register which contains the specified // FP<RegNo> register unsigned getSTReg(unsigned RegNo) const { - return StackTop - 1 - getSlot(RegNo) + X86::ST0; + return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; } // pushReg - Push the specifiex FP<n> register onto the stack @@ -598,3 +600,5 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { I = MBB->erase(I)-1; // Remove the pseudo instruction } + +} // End llvm namespace diff --git a/lib/Target/X86/InstSelectPattern.cpp b/lib/Target/X86/InstSelectPattern.cpp index 434ceee..e518294 100644 --- a/lib/Target/X86/InstSelectPattern.cpp +++ b/lib/Target/X86/InstSelectPattern.cpp @@ -28,6 +28,8 @@ // Include the generated instruction selector... #include "X86GenInstrSelector.inc" +namespace llvm { + namespace { struct ISel : public FunctionPass, SelectionDAGTargetBuilder { TargetMachine &TM; @@ -114,7 +116,6 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) { assert(0 && "ISel::expandCall not implemented!"); } - /// createX86PatternInstructionSelector - This pass converts an LLVM function /// into a machine code representation using pattern matching and a machine /// description file. @@ -122,3 +123,5 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) { FunctionPass *createX86PatternInstructionSelector(TargetMachine &TM) { return new ISel(TM); } + +} // End llvm namespace diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index 1242545..de341c4 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -29,6 +29,8 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Support/InstVisitor.h" +namespace llvm { + /// BMI - A special BuildMI variant that takes an iterator to insert the /// instruction at as well as a basic block. This is the version for when you /// have a destination register in mind. @@ -138,7 +140,7 @@ namespace { void doCall(const ValueRecord &Ret, MachineInstr *CallMI, const std::vector<ValueRecord> &Args); void visitCallInst(CallInst &I); - void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I); + void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I); // Arithmetic operators void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass); @@ -1045,7 +1047,7 @@ void ISel::visitCallInst(CallInst &CI) { MachineInstr *TheCall; if (Function *F = CI.getCalledFunction()) { // Is it an intrinsic function call? - if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) { + if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) { visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here return; } @@ -1066,29 +1068,29 @@ void ISel::visitCallInst(CallInst &CI) { } -void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) { +void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) { unsigned TmpReg1, TmpReg2; switch (ID) { - case LLVMIntrinsic::va_start: + case Intrinsic::va_start: // Get the address of the first vararg value... TmpReg1 = getReg(CI); addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex); return; - case LLVMIntrinsic::va_copy: + case Intrinsic::va_copy: TmpReg1 = getReg(CI); TmpReg2 = getReg(CI.getOperand(1)); BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2); return; - case LLVMIntrinsic::va_end: return; // Noop on X86 + case Intrinsic::va_end: return; // Noop on X86 - case LLVMIntrinsic::longjmp: - case LLVMIntrinsic::siglongjmp: + case Intrinsic::longjmp: + case Intrinsic::siglongjmp: BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true); return; - case LLVMIntrinsic::setjmp: - case LLVMIntrinsic::sigsetjmp: + case Intrinsic::setjmp: + case Intrinsic::sigsetjmp: // Setjmp always returns zero... BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0); return; @@ -2127,7 +2129,6 @@ void ISel::visitFreeInst(FreeInst &I) { doCall(ValueRecord(0, Type::VoidTy), TheCall, Args); } - /// createX86SimpleInstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The /// generated code sucks but the implementation is nice and simple. @@ -2135,3 +2136,5 @@ void ISel::visitFreeInst(FreeInst &I) { FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) { return new ISel(TM); } + +} // End llvm namespace diff --git a/lib/Target/X86/PeepholeOptimizer.cpp b/lib/Target/X86/PeepholeOptimizer.cpp index fbc84f7..2f3280a 100644 --- a/lib/Target/X86/PeepholeOptimizer.cpp +++ b/lib/Target/X86/PeepholeOptimizer.cpp @@ -15,6 +15,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +namespace llvm { + namespace { struct PH : public MachineFunctionPass { virtual bool runOnMachineFunction(MachineFunction &MF); @@ -131,3 +133,5 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, return false; } } + +} // End llvm namespace diff --git a/lib/Target/X86/Printer.cpp b/lib/Target/X86/Printer.cpp index 3d073f7..292a465 100644 --- a/lib/Target/X86/Printer.cpp +++ b/lib/Target/X86/Printer.cpp @@ -29,6 +29,8 @@ #include "Support/StringExtras.h" #include "Support/CommandLine.h" +namespace llvm { + namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); @@ -960,3 +962,5 @@ bool Printer::doFinalization(Module &M) { delete Mang; return false; // success } + +} // End llvm namespace diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h index 01041f8..5cf897f 100644 --- a/lib/Target/X86/X86.h +++ b/lib/Target/X86/X86.h @@ -16,6 +16,9 @@ #define TARGET_X86_H #include <iosfwd> + +namespace llvm { + class TargetMachine; class FunctionPass; @@ -58,6 +61,8 @@ FunctionPass *createEmitX86CodeToMemory(); // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. // +} // End llvm namespace + #include "X86GenRegisterNames.inc" // Defines symbolic names for the X86 instructions. diff --git a/lib/Target/X86/X86AsmPrinter.cpp b/lib/Target/X86/X86AsmPrinter.cpp index 3d073f7..292a465 100644 --- a/lib/Target/X86/X86AsmPrinter.cpp +++ b/lib/Target/X86/X86AsmPrinter.cpp @@ -29,6 +29,8 @@ #include "Support/StringExtras.h" #include "Support/CommandLine.h" +namespace llvm { + namespace { Statistic<> EmittedInsts("asm-printer", "Number of machine instrs printed"); @@ -960,3 +962,5 @@ bool Printer::doFinalization(Module &M) { delete Mang; return false; // success } + +} // End llvm namespace diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index f49fde5..e24e290 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -24,6 +24,8 @@ #include "Support/Statistic.h" #include "Config/alloca.h" +namespace llvm { + namespace { Statistic<> NumEmitted("x86-emitter", "Number of machine instructions emitted"); @@ -589,3 +591,5 @@ void Emitter::emitInstruction(MachineInstr &MI) { break; } } + +} // End llvm namespace diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp index 07e58ba..5c6e6eb 100644 --- a/lib/Target/X86/X86FloatingPoint.cpp +++ b/lib/Target/X86/X86FloatingPoint.cpp @@ -25,6 +25,8 @@ #include <algorithm> #include <iostream> +namespace llvm { + namespace { Statistic<> NumFXCH("x86-codegen", "Number of fxch instructions inserted"); Statistic<> NumFP ("x86-codegen", "Number of floating point instructions"); @@ -70,7 +72,7 @@ namespace { // getSTReg - Return the X86::ST(i) register which contains the specified // FP<RegNo> register unsigned getSTReg(unsigned RegNo) const { - return StackTop - 1 - getSlot(RegNo) + X86::ST0; + return StackTop - 1 - getSlot(RegNo) + llvm::X86::ST0; } // pushReg - Push the specifiex FP<n> register onto the stack @@ -598,3 +600,5 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &I) { I = MBB->erase(I)-1; // Remove the pseudo instruction } + +} // End llvm namespace diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index 434ceee..e518294 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -28,6 +28,8 @@ // Include the generated instruction selector... #include "X86GenInstrSelector.inc" +namespace llvm { + namespace { struct ISel : public FunctionPass, SelectionDAGTargetBuilder { TargetMachine &TM; @@ -114,7 +116,6 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) { assert(0 && "ISel::expandCall not implemented!"); } - /// createX86PatternInstructionSelector - This pass converts an LLVM function /// into a machine code representation using pattern matching and a machine /// description file. @@ -122,3 +123,5 @@ void ISel::expandCall(SelectionDAG &SD, CallInst &CI) { FunctionPass *createX86PatternInstructionSelector(TargetMachine &TM) { return new ISel(TM); } + +} // End llvm namespace diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index 1242545..de341c4 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -29,6 +29,8 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Support/InstVisitor.h" +namespace llvm { + /// BMI - A special BuildMI variant that takes an iterator to insert the /// instruction at as well as a basic block. This is the version for when you /// have a destination register in mind. @@ -138,7 +140,7 @@ namespace { void doCall(const ValueRecord &Ret, MachineInstr *CallMI, const std::vector<ValueRecord> &Args); void visitCallInst(CallInst &I); - void visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &I); + void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I); // Arithmetic operators void visitSimpleBinary(BinaryOperator &B, unsigned OpcodeClass); @@ -1045,7 +1047,7 @@ void ISel::visitCallInst(CallInst &CI) { MachineInstr *TheCall; if (Function *F = CI.getCalledFunction()) { // Is it an intrinsic function call? - if (LLVMIntrinsic::ID ID = (LLVMIntrinsic::ID)F->getIntrinsicID()) { + if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) { visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here return; } @@ -1066,29 +1068,29 @@ void ISel::visitCallInst(CallInst &CI) { } -void ISel::visitIntrinsicCall(LLVMIntrinsic::ID ID, CallInst &CI) { +void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) { unsigned TmpReg1, TmpReg2; switch (ID) { - case LLVMIntrinsic::va_start: + case Intrinsic::va_start: // Get the address of the first vararg value... TmpReg1 = getReg(CI); addFrameReference(BuildMI(BB, X86::LEAr32, 5, TmpReg1), VarArgsFrameIndex); return; - case LLVMIntrinsic::va_copy: + case Intrinsic::va_copy: TmpReg1 = getReg(CI); TmpReg2 = getReg(CI.getOperand(1)); BuildMI(BB, X86::MOVrr32, 1, TmpReg1).addReg(TmpReg2); return; - case LLVMIntrinsic::va_end: return; // Noop on X86 + case Intrinsic::va_end: return; // Noop on X86 - case LLVMIntrinsic::longjmp: - case LLVMIntrinsic::siglongjmp: + case Intrinsic::longjmp: + case Intrinsic::siglongjmp: BuildMI(BB, X86::CALLpcrel32, 1).addExternalSymbol("abort", true); return; - case LLVMIntrinsic::setjmp: - case LLVMIntrinsic::sigsetjmp: + case Intrinsic::setjmp: + case Intrinsic::sigsetjmp: // Setjmp always returns zero... BuildMI(BB, X86::MOVir32, 1, getReg(CI)).addZImm(0); return; @@ -2127,7 +2129,6 @@ void ISel::visitFreeInst(FreeInst &I) { doCall(ValueRecord(0, Type::VoidTy), TheCall, Args); } - /// createX86SimpleInstructionSelector - This pass converts an LLVM function /// into a machine code representation is a very simple peep-hole fashion. The /// generated code sucks but the implementation is nice and simple. @@ -2135,3 +2136,5 @@ void ISel::visitFreeInst(FreeInst &I) { FunctionPass *createX86SimpleInstructionSelector(TargetMachine &TM) { return new ISel(TM); } + +} // End llvm namespace diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h index a6d65d4..a5643bd 100644 --- a/lib/Target/X86/X86InstrBuilder.h +++ b/lib/Target/X86/X86InstrBuilder.h @@ -26,6 +26,8 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" +namespace llvm { + /// addDirectMem - This function is used to add a direct memory reference to the /// current instruction -- that is, a dereference of an address in a register, /// with no scale, index or displacement. An example is: DWORD PTR [EAX]. @@ -69,4 +71,6 @@ addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI, return MIB.addConstantPoolIndex(CPI).addZImm(1).addReg(0).addSImm(Offset); } +} // End llvm namespace + #endif diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 012cead..681bf02 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -17,6 +17,8 @@ #include "X86GenInstrInfo.inc" +using namespace llvm; + X86InstrInfo::X86InstrInfo() : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0]), 0) { } diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index 26b2618..2bf82d1 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -17,6 +17,8 @@ #include "llvm/Target/TargetInstrInfo.h" #include "X86RegisterInfo.h" +namespace llvm { + /// X86II - This namespace holds all of the target specific flags that /// instruction info tracks. /// @@ -181,4 +183,6 @@ public: } }; +} // End llvm namespace + #endif diff --git a/lib/Target/X86/X86PeepholeOpt.cpp b/lib/Target/X86/X86PeepholeOpt.cpp index fbc84f7..2f3280a 100644 --- a/lib/Target/X86/X86PeepholeOpt.cpp +++ b/lib/Target/X86/X86PeepholeOpt.cpp @@ -15,6 +15,8 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" +namespace llvm { + namespace { struct PH : public MachineFunctionPass { virtual bool runOnMachineFunction(MachineFunction &MF); @@ -131,3 +133,5 @@ bool PH::PeepholeOptimize(MachineBasicBlock &MBB, return false; } } + +} // End llvm namespace diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index fd8a615..0e8b889 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -25,6 +25,8 @@ #include "llvm/Target/TargetFrameInfo.h" #include "Support/CommandLine.h" +namespace llvm { + namespace { cl::opt<bool> NoFPElim("disable-fp-elim", @@ -253,8 +255,12 @@ int X86RegisterInfo::emitEpilogue(MachineFunction &MF, return MBB.size() - oldSize; } +} // End llvm namespace + #include "X86GenRegisterInfo.inc" +namespace llvm { + const TargetRegisterClass* X86RegisterInfo::getRegClassForType(const Type* Ty) const { switch (Ty->getPrimitiveID()) { @@ -274,3 +280,5 @@ X86RegisterInfo::getRegClassForType(const Type* Ty) const { case Type::DoubleTyID: return &RFPInstance; } } + +} // End llvm namespace diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index 0db8e18..77a8a1a 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -16,10 +16,12 @@ #include "llvm/Target/MRegisterInfo.h" -class Type; +class llvm::Type; #include "X86GenRegisterInfo.h.inc" +namespace llvm { + struct X86RegisterInfo : public X86GenRegisterInfo { X86RegisterInfo(); const TargetRegisterClass* getRegClassForType(const Type* Ty) const; @@ -52,4 +54,6 @@ struct X86RegisterInfo : public X86GenRegisterInfo { int emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; }; +} // End llvm namespace + #endif diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 954d4f4..31eb4bd 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -22,6 +22,8 @@ #include "Support/CommandLine.h" #include "Support/Statistic.h" +namespace llvm { + namespace { cl::opt<bool> PrintCode("print-machineinstrs", cl::desc("Print generated machine code")); @@ -153,3 +155,5 @@ void X86TargetMachine::replaceMachineCodeForFunction (void *Old, void *New) { int32_t OldAddr = (intptr_t) OldWord; *OldWord = NewAddr - OldAddr - 4; // Emit PC-relative addr of New code. } + +} // End llvm namespace diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 5581da4..12f5c0e6 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -19,6 +19,8 @@ #include "llvm/PassManager.h" #include "X86InstrInfo.h" +namespace llvm { + class X86TargetMachine : public TargetMachine { X86InstrInfo InstrInfo; TargetFrameInfo FrameInfo; @@ -55,4 +57,6 @@ public: virtual void replaceMachineCodeForFunction (void *Old, void *New); }; +} // End llvm namespace + #endif |