diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 16 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 4 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.h | 4 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 6 |
5 files changed, 18 insertions, 18 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 327a8fe..a0f8697 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2500,8 +2500,8 @@ static SDOperand getMemcpyLoadsAndStores(SelectionDAG &DAG, SDOperand Src, uint64_t Size, unsigned Align, bool AlwaysInline, - Value *DstSV, uint64_t DstOff, - Value *SrcSV, uint64_t SrcOff) { + const Value *DstSV, uint64_t DstOff, + const Value *SrcSV, uint64_t SrcOff) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); // Expand memcpy to a series of store ops if the size operand falls below @@ -2573,7 +2573,7 @@ static SDOperand getMemsetStores(SelectionDAG &DAG, SDOperand Chain, SDOperand Dst, SDOperand Src, uint64_t Size, unsigned Align, - Value *DstSV, uint64_t DstOff) { + const Value *DstSV, uint64_t DstOff) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); // Expand memset to a series of load/store ops if the size operand @@ -2604,8 +2604,8 @@ static SDOperand getMemsetStores(SelectionDAG &DAG, SDOperand SelectionDAG::getMemcpy(SDOperand Chain, SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, bool AlwaysInline, - Value *DstSV, uint64_t DstOff, - Value *SrcSV, uint64_t SrcOff) { + const Value *DstSV, uint64_t DstOff, + const Value *SrcSV, uint64_t SrcOff) { // Check to see if we should lower the memcpy to loads and stores first. // For cases within the target-specified limits, this is the best choice. @@ -2658,8 +2658,8 @@ SDOperand SelectionDAG::getMemcpy(SDOperand Chain, SDOperand Dst, SDOperand SelectionDAG::getMemmove(SDOperand Chain, SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, - Value *DstSV, uint64_t DstOff, - Value *SrcSV, uint64_t SrcOff) { + const Value *DstSV, uint64_t DstOff, + const Value *SrcSV, uint64_t SrcOff) { // TODO: Optimize small memmove cases with simple loads and stores, // ensuring that all loads precede all stores. This can cause severe @@ -2691,7 +2691,7 @@ SDOperand SelectionDAG::getMemmove(SDOperand Chain, SDOperand Dst, SDOperand SelectionDAG::getMemset(SDOperand Chain, SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, - Value *DstSV, uint64_t DstOff) { + const Value *DstSV, uint64_t DstOff) { // Check to see if we should lower the memset to stores first. // For cases within the target-specified limits, this is the best choice. diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 0095352..6a581f7 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1247,8 +1247,8 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, bool AlwaysInline, - Value *DstSV, uint64_t DstOff, - Value *SrcSV, uint64_t SrcOff){ + const Value *DstSV, uint64_t DstOff, + const Value *SrcSV, uint64_t SrcOff){ // Do repeated 4-byte loads and stores. To be improved. // This requires 4-byte alignment. if ((Align & 3) != 0) diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 58d8d8c..13f5c08 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -149,8 +149,8 @@ namespace llvm { SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, bool AlwaysInline, - Value *DstSV, uint64_t DstOff, - Value *SrcSV, uint64_t SrcOff); + const Value *DstSV, uint64_t DstOff, + const Value *SrcSV, uint64_t SrcOff); }; } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index ac58ab4..38e6342 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -4664,7 +4664,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, SDOperand Chain, SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, - Value *DstSV, uint64_t DstOff) { + const Value *DstSV, uint64_t DstOff) { ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size); /// If not DWORD aligned or size is more than the threshold, call the library. @@ -4804,8 +4804,8 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, bool AlwaysInline, - Value *DstSV, uint64_t DstOff, - Value *SrcSV, uint64_t SrcOff){ + const Value *DstSV, uint64_t DstOff, + const Value *SrcSV, uint64_t SrcOff){ // This requires the copy size to be a constant, preferrably // within a subtarget-specific limit. diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index fea2d2b..e3000db 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -550,14 +550,14 @@ namespace llvm { SDOperand Chain, SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, - Value *DstSV, uint64_t DstOff); + const Value *DstSV, uint64_t DstOff); SDOperand EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDOperand Chain, SDOperand Dst, SDOperand Src, SDOperand Size, unsigned Align, bool AlwaysInline, - Value *DstSV, uint64_t DstOff, - Value *SrcSV, uint64_t SrcOff); + const Value *DstSV, uint64_t DstOff, + const Value *SrcSV, uint64_t SrcOff); }; } |