diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/BranchFolding.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/Alpha/AlphaInstrInfo.td | 8 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCHazardRecognizers.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 4 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 2 |
6 files changed, 15 insertions, 5 deletions
diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index aedd7c9..727f0a5 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -414,7 +414,7 @@ static unsigned EstimateRuntime(MachineBasicBlock::iterator I, const TargetInstrDesc &TID = I->getDesc(); if (TID.isCall()) Time += 10; - else if (TID.isSimpleLoad() || TID.mayStore()) + else if (TID.mayLoad() || TID.mayStore()) Time += 2; else ++Time; diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp index b85daa1..cd5f321 100644 --- a/lib/Target/ARM/ARMRegisterInfo.cpp +++ b/lib/Target/ARM/ARMRegisterInfo.cpp @@ -834,7 +834,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, assert(Offset && "This code isn't needed if offset already handled!"); if (isThumb) { - if (Desc.isSimpleLoad()) { + if (Desc.mayLoad()) { // Use the destination register to materialize sp + offset. unsigned TmpReg = MI.getOperand(0).getReg(); bool UseRR = false; diff --git a/lib/Target/Alpha/AlphaInstrInfo.td b/lib/Target/Alpha/AlphaInstrInfo.td index c4e6edc..531b7fa 100644 --- a/lib/Target/Alpha/AlphaInstrInfo.td +++ b/lib/Target/Alpha/AlphaInstrInfo.td @@ -570,7 +570,9 @@ def : Pat<(truncstorei8 GPRC:$DATA, GPRC:$addr), //load address, rellocated gpdist form -let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM) in { +let OutOperandList = (ops GPRC:$RA), + InOperandList = (ops s16imm:$DISP, GPRC:$RB, s16imm:$NUM), + mayLoad = 1 in { def LDAg : MForm<0x08, 1, "lda $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address def LDAHg : MForm<0x09, 1, "ldah $RA,0($RB)\t\t!gpdisp!$NUM", [], s_lda>; //Load address } @@ -589,7 +591,9 @@ let OutOperandList = (outs GPRC:$RR), def STQ_C : MForm<0x2F, 0, "stq_l $RA,$DISP($RB)", [], s_ist>; def STL_C : MForm<0x2E, 0, "stl_l $RA,$DISP($RB)", [], s_ist>; } -let OutOperandList = (ops GPRC:$RA), InOperandList = (ops s64imm:$DISP, GPRC:$RB) in { +let OutOperandList = (ops GPRC:$RA), + InOperandList = (ops s64imm:$DISP, GPRC:$RB), + mayLoad = 1 in { def LDQ_L : MForm<0x2B, 1, "ldq_l $RA,$DISP($RB)", [], s_ild>; def LDL_L : MForm<0x2A, 1, "ldl_l $RA,$DISP($RB)", [], s_ild>; } diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index b9b7496..14745e6 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -72,7 +72,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode, const TargetInstrDesc &TID = TII.get(Opcode); - isLoad = TID.isSimpleLoad(); + isLoad = TID.mayLoad(); isStore = TID.mayStore(); unsigned TSFlags = TID.TSFlags; diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 6867cd7..a2f1834 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -487,6 +487,7 @@ def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), PPC970_DGroup_Cracked; // Update forms. +let mayLoad = 1 in def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, ptr_rc:$rA), "lhau $rD, $disp($rA)", LdStGeneral, @@ -520,6 +521,7 @@ def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), // Update forms. +let mayLoad = 1 in { def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), "lbzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, @@ -533,6 +535,7 @@ def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; } +} // Full 8-byte loads. @@ -544,6 +547,7 @@ def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), "ldx $rD, $src", LdStLD, [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; +let mayLoad = 1 in def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), "ldu $rD, $addr", LdStLD, []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 0cb7c85..4106c45 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -683,6 +683,7 @@ def LFD : DForm_1<50, (outs F8RC:$rD), (ins memri:$src), // Unindexed (r+i) Loads with Update (preinc). +let mayLoad = 1 in { def LBZU : DForm_1<35, (outs GPRC:$rD, ptr_rc:$ea_result), (ins memri:$addr), "lbzu $rD, $addr", LdStGeneral, []>, RegConstraint<"$addr.reg = $ea_result">, @@ -713,6 +714,7 @@ def LFDU : DForm_1<51, (outs F8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), []>, RegConstraint<"$addr.reg = $ea_result">, NoEncode<"$ea_result">; } +} // Indexed (r+r) Loads. // |