diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/R600/AMDGPUInstructions.td | 2 | ||||
| -rw-r--r-- | lib/Target/R600/R600ISelLowering.cpp | 6 | ||||
| -rw-r--r-- | lib/Target/R600/SIInstrInfo.cpp | 10 |
3 files changed, 9 insertions, 9 deletions
diff --git a/lib/Target/R600/AMDGPUInstructions.td b/lib/Target/R600/AMDGPUInstructions.td index 5778a8c..0c81a6b 100644 --- a/lib/Target/R600/AMDGPUInstructions.td +++ b/lib/Target/R600/AMDGPUInstructions.td @@ -231,7 +231,7 @@ class Constants { int TWO_PI = 0x40c90fdb; int PI = 0x40490fdb; int TWO_PI_INV = 0x3e22f983; -int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding +int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding } def CONST : Constants; diff --git a/lib/Target/R600/R600ISelLowering.cpp b/lib/Target/R600/R600ISelLowering.cpp index 26041ed..dfcfeed 100644 --- a/lib/Target/R600/R600ISelLowering.cpp +++ b/lib/Target/R600/R600ISelLowering.cpp @@ -1834,7 +1834,7 @@ SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, std::vector<SDValue> Ops; for(SDNode::op_iterator I = Node->op_begin(), E = Node->op_end(); I != E; ++I) - Ops.push_back(*I); + Ops.push_back(*I); if (Opcode == AMDGPU::DOT_4) { int OperandIdx[] = { @@ -1846,7 +1846,7 @@ SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Y), TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_Z), TII->getOperandIdx(Opcode, AMDGPU::OpName::src1_W) - }; + }; int NegIdx[] = { TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_X), TII->getOperandIdx(Opcode, AMDGPU::OpName::src0_neg_Y), @@ -1899,7 +1899,7 @@ SDNode *R600TargetLowering::PostISelFolding(MachineSDNode *Node, std::vector<SDValue> Ops; unsigned NumOp = Src.getNumOperands(); for(unsigned i = 0; i < NumOp; ++i) - Ops.push_back(Src.getOperand(i)); + Ops.push_back(Src.getOperand(i)); Ops[ClampIdx - 1] = DAG.getTargetConstant(1, MVT::i32); return DAG.getMachineNode(Src.getMachineOpcode(), SDLoc(Node), Node->getVTList(), Ops); diff --git a/lib/Target/R600/SIInstrInfo.cpp b/lib/Target/R600/SIInstrInfo.cpp index e45baa5..c635229 100644 --- a/lib/Target/R600/SIInstrInfo.cpp +++ b/lib/Target/R600/SIInstrInfo.cpp @@ -118,14 +118,14 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) { assert(AMDGPU::VReg_32RegClass.contains(SrcReg) || - AMDGPU::SReg_32RegClass.contains(SrcReg)); + AMDGPU::SReg_32RegClass.contains(SrcReg)); BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); return; } else if (AMDGPU::VReg_64RegClass.contains(DestReg)) { assert(AMDGPU::VReg_64RegClass.contains(SrcReg) || - AMDGPU::SReg_64RegClass.contains(SrcReg)); + AMDGPU::SReg_64RegClass.contains(SrcReg)); Opcode = AMDGPU::V_MOV_B32_e32; SubIndices = Sub0_1; @@ -136,19 +136,19 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, } else if (AMDGPU::VReg_128RegClass.contains(DestReg)) { assert(AMDGPU::VReg_128RegClass.contains(SrcReg) || - AMDGPU::SReg_128RegClass.contains(SrcReg)); + AMDGPU::SReg_128RegClass.contains(SrcReg)); Opcode = AMDGPU::V_MOV_B32_e32; SubIndices = Sub0_3; } else if (AMDGPU::VReg_256RegClass.contains(DestReg)) { assert(AMDGPU::VReg_256RegClass.contains(SrcReg) || - AMDGPU::SReg_256RegClass.contains(SrcReg)); + AMDGPU::SReg_256RegClass.contains(SrcReg)); Opcode = AMDGPU::V_MOV_B32_e32; SubIndices = Sub0_7; } else if (AMDGPU::VReg_512RegClass.contains(DestReg)) { assert(AMDGPU::VReg_512RegClass.contains(SrcReg) || - AMDGPU::SReg_512RegClass.contains(SrcReg)); + AMDGPU::SReg_512RegClass.contains(SrcReg)); Opcode = AMDGPU::V_MOV_B32_e32; SubIndices = Sub0_15; |