3 files changed, 5 insertions, 3 deletions
diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp
index 5395a81..6306269 100644
--- a/lib/CodeGen/InstrSched/InstrScheduling.cpp
+++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp
@@ -648,7 +648,8 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
   
   // Remove all except the dummy PHI instructions from MBB, and
   // pre-allocate create space for the ones we will put back in.
-  while (I != MBB.end()) MBB.remove(I);
+  while (I != MBB.end())
+    MBB.remove(I++);
   
   InstrSchedule::const_iterator NIend = S.isched.end();
   for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
index 5395a81..6306269 100644
--- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
+++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp
@@ -648,7 +648,8 @@ RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
   
   // Remove all except the dummy PHI instructions from MBB, and
   // pre-allocate create space for the ones we will put back in.
-  while (I != MBB.end()) MBB.remove(I);
+  while (I != MBB.end())
+    MBB.remove(I++);
   
   InstrSchedule::const_iterator NIend = S.isched.end();
   for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 51a6f8b..28fc75a 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -542,7 +542,7 @@ void PhyRegAlloc::updateMachineCode()
               }
 
               // move instruction before branch
-              MBB.insert(MII, MBB.remove(DelaySlotMI));
+              MBB.insert(MII, MBB.remove(DelaySlotMI++));
 
               // On cond1 we are done (we already moved the
               // instruction out of the delay slot). On cond2 we need