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-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp3
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp7
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp40
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp6
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp7
5 files changed, 51 insertions, 12 deletions
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 14efb44..aff3869 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -5011,7 +5011,8 @@ SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
} else {
unsigned NewIdx =
cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
- MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
+ MappedOps.push_back(DAG.getConstant(NewIdx,
+ ShufMask.getOperand(i).getValueType()));
}
}
ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4b02c54..b49fa9b 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -186,7 +186,7 @@ private:
/// scalar (e.g. f32) value.
SDOperand ScalarizeVectorOp(SDOperand O);
- /// isShuffleLegal - Return true if a vector shuffle is legal with the
+ /// isShuffleLegal - Return non-null if a vector shuffle is legal with the
/// specified mask and type. Targets can specify exactly which masks they
/// support and the code generator is tasked with not creating illegal masks.
///
@@ -241,6 +241,7 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
// If this is promoted to a different type, convert the shuffle mask and
// ask if it is legal in the promoted type!
MVT NVT = TLI.getTypeToPromoteTo(ISD::VECTOR_SHUFFLE, VT);
+ MVT EltVT = NVT.getVectorElementType();
// If we changed # elements, change the shuffle mask.
unsigned NumEltsGrowth =
@@ -253,10 +254,10 @@ SDNode *SelectionDAGLegalize::isShuffleLegal(MVT VT, SDOperand Mask) const {
SDOperand InOp = Mask.getOperand(i);
for (unsigned j = 0; j != NumEltsGrowth; ++j) {
if (InOp.getOpcode() == ISD::UNDEF)
- Ops.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+ Ops.push_back(DAG.getNode(ISD::UNDEF, EltVT));
else {
unsigned InEltNo = cast<ConstantSDNode>(InOp)->getValue();
- Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, MVT::i32));
+ Ops.push_back(DAG.getConstant(InEltNo*NumEltsGrowth+j, EltVT));
}
}
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index e757133..882985f 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -740,6 +740,25 @@ SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
return CSEMap.FindNodeOrInsertPos(ID, InsertPos);
}
+/// VerifyNode - Sanity check the given node. Aborts if it is invalid.
+void SelectionDAG::VerifyNode(SDNode *N) {
+ switch (N->getOpcode()) {
+ default:
+ break;
+ case ISD::BUILD_VECTOR: {
+ assert(N->getNumValues() == 1 && "Too many results for BUILD_VECTOR!");
+ assert(N->getValueType(0).isVector() && "Wrong BUILD_VECTOR return type!");
+ assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
+ "Wrong number of BUILD_VECTOR operands!");
+ MVT EltVT = N->getValueType(0).getVectorElementType();
+ for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
+ assert(I->getSDOperand().getValueType() == EltVT &&
+ "Wrong BUILD_VECTOR operand type!");
+ break;
+ }
+ }
+}
+
/// getMVTAlignment - Compute the default alignment value for the
/// given type.
///
@@ -1965,6 +1984,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT) {
CSEMap.InsertNode(N, IP);
AllNodes.push_back(N);
+#ifndef NDEBUG
+ VerifyNode(N);
+#endif
return SDOperand(N, 0);
}
@@ -2161,12 +2183,14 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT, SDOperand Operand) {
N = getAllocator().Allocate<UnarySDNode>();
new (N) UnarySDNode(Opcode, VTs, Operand);
}
+
AllNodes.push_back(N);
+#ifndef NDEBUG
+ VerifyNode(N);
+#endif
return SDOperand(N, 0);
}
-
-
SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
SDOperand N1, SDOperand N2) {
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
@@ -2515,6 +2539,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
}
AllNodes.push_back(N);
+#ifndef NDEBUG
+ VerifyNode(N);
+#endif
return SDOperand(N, 0);
}
@@ -2580,6 +2607,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
new (N) TernarySDNode(Opcode, VTs, N1, N2, N3);
}
AllNodes.push_back(N);
+#ifndef NDEBUG
+ VerifyNode(N);
+#endif
return SDOperand(N, 0);
}
@@ -3394,6 +3424,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT VT,
new (N) SDNode(Opcode, VTs, Ops, NumOps);
}
AllNodes.push_back(N);
+#ifndef NDEBUG
+ VerifyNode(N);
+#endif
return SDOperand(N, 0);
}
@@ -3478,6 +3511,9 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, SDVTList VTList,
}
}
AllNodes.push_back(N);
+#ifndef NDEBUG
+ VerifyNode(N);
+#endif
return SDOperand(N, 0);
}
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index ad16baa..2ea48cf 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3281,10 +3281,10 @@ static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
// Force LHS/RHS to be the right type.
LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
-
+
SDOperand Ops[16];
for (unsigned i = 0; i != 16; ++i)
- Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
+ Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
return DAG.getNode(ISD::BIT_CONVERT, VT, T);
@@ -3529,7 +3529,7 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
}
SDOperand Ops[16];
for (unsigned i = 0; i != 16; ++i)
- Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
+ Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 85788ef..e5c8cb8 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -3569,6 +3569,7 @@ SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
unsigned NumElems = PermMask.getNumOperands();
unsigned NewWidth = (NumElems == 4) ? 2 : 4;
MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth);
+ MVT MaskEltVT = MaskVT.getVectorElementType();
MVT NewVT = MaskVT;
switch (VT.getSimpleVT()) {
default: assert(false && "Unexpected!");
@@ -3599,9 +3600,9 @@ SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
return SDOperand();
}
if (StartIdx == ~0U)
- MaskVec.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
+ MaskVec.push_back(DAG.getNode(ISD::UNDEF, MaskEltVT));
else
- MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MVT::i32));
+ MaskVec.push_back(DAG.getConstant(StartIdx / Scale, MaskEltVT));
}
V1 = DAG.getNode(ISD::BIT_CONVERT, NewVT, V1);
@@ -4054,7 +4055,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
// UNPCKHPD the element to the lowest double word, then movsd.
// Note if the lower 64 bits of the result of the UNPCKHPD is then stored
// to a f64mem, the whole operation is folded into a single MOVHPDmr.
- MVT MaskVT = MVT::getIntVectorWithNumElements(4);
+ MVT MaskVT = MVT::getIntVectorWithNumElements(2);
SmallVector<SDOperand, 8> IdxVec;
IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
IdxVec.
generated by cgit v1.1 at 2025-03-09 14:39:26 +0000