diff options
Diffstat (limited to 'test/CodeGen/AArch64/arm64-register-offset-addressing.ll')
| -rw-r--r-- | test/CodeGen/AArch64/arm64-register-offset-addressing.ll | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/test/CodeGen/AArch64/arm64-register-offset-addressing.ll b/test/CodeGen/AArch64/arm64-register-offset-addressing.ll index 045712b..7078ffc 100644 --- a/test/CodeGen/AArch64/arm64-register-offset-addressing.ll +++ b/test/CodeGen/AArch64/arm64-register-offset-addressing.ll @@ -5,8 +5,8 @@ define i8 @test_64bit_add(i16* %a, i64 %b) { ; CHECK: lsl [[REG:x[0-9]+]], x1, #1 ; CHECK: ldrb w0, [x0, [[REG]]] ; CHECK: ret - %tmp1 = getelementptr inbounds i16* %a, i64 %b - %tmp2 = load i16* %tmp1 + %tmp1 = getelementptr inbounds i16, i16* %a, i64 %b + %tmp2 = load i16, i16* %tmp1 %tmp3 = trunc i16 %tmp2 to i8 ret i8 %tmp3 } @@ -18,8 +18,8 @@ define void @ldst_8bit(i8* %base, i64 %offset) minsize { %off32.sext.tmp = shl i64 %offset, 32 %off32.sext = ashr i64 %off32.sext.tmp, 32 - %addr8_sxtw = getelementptr i8* %base, i64 %off32.sext - %val8_sxtw = load volatile i8* %addr8_sxtw + %addr8_sxtw = getelementptr i8, i8* %base, i64 %off32.sext + %val8_sxtw = load volatile i8, i8* %addr8_sxtw %val32_signed = sext i8 %val8_sxtw to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] @@ -28,7 +28,7 @@ define void @ldst_8bit(i8* %base, i64 %offset) minsize { %offset_uxtw = and i64 %offset, 4294967295 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i8* - %val8_uxtw = load volatile i8* %addr_uxtw + %val8_uxtw = load volatile i8, i8* %addr_uxtw %newval8 = add i8 %val8_uxtw, 1 store volatile i8 %newval8, i8* @var_8bit ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] @@ -44,7 +44,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize { %offset_uxtw = and i64 %offset, 4294967295 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i16* - %val8_uxtw = load volatile i16* %addr_uxtw + %val8_uxtw = load volatile i16, i16* %addr_uxtw %newval8 = add i16 %val8_uxtw, 1 store volatile i16 %newval8, i16* @var_16bit ; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] @@ -54,7 +54,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize { %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i16* - %val16_sxtw = load volatile i16* %addr_sxtw + %val16_sxtw = load volatile i16, i16* %addr_sxtw %val64_signed = sext i16 %val16_sxtw to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] @@ -65,7 +65,7 @@ define void @ldst_16bit(i16* %base, i64 %offset) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 1 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i16* - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit %val16_trunc32 = trunc i32 %val32 to i16 store volatile i16 %val16_trunc32, i16* %addr_uxtwN ; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #1] @@ -79,7 +79,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize { %offset_uxtw = and i64 %offset, 4294967295 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i32* - %val32_uxtw = load volatile i32* %addr_uxtw + %val32_uxtw = load volatile i32, i32* %addr_uxtw %newval32 = add i32 %val32_uxtw, 1 store volatile i32 %newval32, i32* @var_32bit ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] @@ -89,7 +89,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize { %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i32* - %val32_sxtw = load volatile i32* %addr_sxtw + %val32_sxtw = load volatile i32, i32* %addr_sxtw %val64_signed = sext i32 %val32_sxtw to i64 store volatile i64 %val64_signed, i64* @var_64bit ; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] @@ -100,7 +100,7 @@ define void @ldst_32bit(i32* %base, i64 %offset) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 2 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i32* - %val32 = load volatile i32* @var_32bit + %val32 = load volatile i32, i32* @var_32bit store volatile i32 %val32, i32* %addr_uxtwN ; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #2] ret void @@ -113,7 +113,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize { %offset_uxtw = and i64 %offset, 4294967295 %addrint1_uxtw = add i64 %addrint_uxtw, %offset_uxtw %addr_uxtw = inttoptr i64 %addrint1_uxtw to i64* - %val64_uxtw = load volatile i64* %addr_uxtw + %val64_uxtw = load volatile i64, i64* %addr_uxtw %newval8 = add i64 %val64_uxtw, 1 store volatile i64 %newval8, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw] @@ -123,7 +123,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize { %offset_sxtw = ashr i64 %offset_sxtw.tmp, 32 %addrint_sxtw = add i64 %base_sxtw, %offset_sxtw %addr_sxtw = inttoptr i64 %addrint_sxtw to i64* - %val64_sxtw = load volatile i64* %addr_sxtw + %val64_sxtw = load volatile i64, i64* %addr_sxtw store volatile i64 %val64_sxtw, i64* @var_64bit ; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, sxtw] @@ -133,7 +133,7 @@ define void @ldst_64bit(i64* %base, i64 %offset) minsize { %offset2_uxtwN = shl i64 %offset_uxtwN, 3 %addrint_uxtwN = add i64 %base_uxtwN, %offset2_uxtwN %addr_uxtwN = inttoptr i64 %addrint_uxtwN to i64* - %val64 = load volatile i64* @var_64bit + %val64 = load volatile i64, i64* @var_64bit store volatile i64 %val64, i64* %addr_uxtwN ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{w[0-9]+}}, uxtw #3] ret void |