diff options
Diffstat (limited to 'test/CodeGen/AArch64/arm64-scvt.ll')
| -rw-r--r-- | test/CodeGen/AArch64/arm64-scvt.ll | 176 |
1 files changed, 88 insertions, 88 deletions
diff --git a/test/CodeGen/AArch64/arm64-scvt.ll b/test/CodeGen/AArch64/arm64-scvt.ll index 8baaf22..fc64d7b 100644 --- a/test/CodeGen/AArch64/arm64-scvt.ll +++ b/test/CodeGen/AArch64/arm64-scvt.ll @@ -7,7 +7,7 @@ entry: ; CHECK-LABEL: t1: ; CHECK: ldr s0, [x0] ; CHECK: scvtf s0, s0 - %tmp1 = load i32* %src, align 4 + %tmp1 = load i32, i32* %src, align 4 %tmp2 = sitofp i32 %tmp1 to float ret float %tmp2 } @@ -17,7 +17,7 @@ entry: ; CHECK-LABEL: t2: ; CHECK: ldr s0, [x0] ; CHECK: ucvtf s0, s0 - %tmp1 = load i32* %src, align 4 + %tmp1 = load i32, i32* %src, align 4 %tmp2 = uitofp i32 %tmp1 to float ret float %tmp2 } @@ -27,7 +27,7 @@ entry: ; CHECK-LABEL: t3: ; CHECK: ldr d0, [x0] ; CHECK: scvtf d0, d0 - %tmp1 = load i64* %src, align 4 + %tmp1 = load i64, i64* %src, align 4 %tmp2 = sitofp i64 %tmp1 to double ret double %tmp2 } @@ -37,7 +37,7 @@ entry: ; CHECK-LABEL: t4: ; CHECK: ldr d0, [x0] ; CHECK: ucvtf d0, d0 - %tmp1 = load i64* %src, align 4 + %tmp1 = load i64, i64* %src, align 4 %tmp2 = uitofp i64 %tmp1 to double ret double %tmp2 } @@ -48,7 +48,7 @@ entry: ; CHECK-LABEL: t5: ; CHECK: ldr [[REG:w[0-9]+]], [x0] ; CHECK: scvtf d0, [[REG]] - %tmp1 = load i32* %src, align 4 + %tmp1 = load i32, i32* %src, align 4 %tmp2 = sitofp i32 %tmp1 to double ret double %tmp2 } @@ -75,8 +75,8 @@ define float @fct1(i8* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -88,8 +88,8 @@ define float @fct2(i16* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -101,8 +101,8 @@ define float @fct3(i32* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -115,8 +115,8 @@ define float @fct4(i64* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -129,8 +129,8 @@ define float @fct5(i8* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -142,8 +142,8 @@ define float @fct6(i16* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -155,8 +155,8 @@ define float @fct7(i32* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], s[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -169,8 +169,8 @@ define float @fct8(i64* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:s[0-9]+]], x[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -184,8 +184,8 @@ define double @fct9(i8* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -197,8 +197,8 @@ define double @fct10(i16* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -210,8 +210,8 @@ define double @fct11(i32* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -223,8 +223,8 @@ define double @fct12(i64* nocapture %sp0) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -237,8 +237,8 @@ define double @fct13(i8* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -250,8 +250,8 @@ define double @fct14(i16* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -263,8 +263,8 @@ define double @fct15(i32* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -276,8 +276,8 @@ define double @fct16(i64* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: ucvtf [[REG:d[0-9]+]], d[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -293,7 +293,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -307,7 +307,7 @@ define float @fct18(i16* nocapture %sp0) { %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* - %pix_sp0.0.copyload = load i16* %addr, align 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -321,7 +321,7 @@ define float @fct19(i32* nocapture %sp0) { %bitcast = ptrtoint i32* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i32* - %pix_sp0.0.copyload = load i32* %addr, align 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -336,7 +336,7 @@ define float @fct20(i64* nocapture %sp0) { %bitcast = ptrtoint i64* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i64* - %pix_sp0.0.copyload = load i64* %addr, align 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -353,7 +353,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = uitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -367,7 +367,7 @@ define double @fct22(i16* nocapture %sp0) { %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* - %pix_sp0.0.copyload = load i16* %addr, align 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = uitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -381,7 +381,7 @@ define double @fct23(i32* nocapture %sp0) { %bitcast = ptrtoint i32* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i32* - %pix_sp0.0.copyload = load i32* %addr, align 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = uitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -395,7 +395,7 @@ define double @fct24(i64* nocapture %sp0) { %bitcast = ptrtoint i64* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i64* - %pix_sp0.0.copyload = load i64* %addr, align 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = uitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -415,8 +415,8 @@ define float @sfct1(i8* nocapture %sp0) { ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -429,8 +429,8 @@ define float @sfct2(i16* nocapture %sp0) { ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -442,8 +442,8 @@ define float @sfct3(i32* nocapture %sp0) { ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -456,8 +456,8 @@ define float @sfct4(i64* nocapture %sp0) { ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -476,8 +476,8 @@ define float @sfct5(i8* nocapture %sp0, i64 %offset) { ; CHECK-A57-NEXT: scvtf [[REG:s[0-9]+]], w[[REGNUM]] ; CHECK-A57-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -490,8 +490,8 @@ define float @sfct6(i16* nocapture %sp0, i64 %offset) { ; CHECK: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -503,8 +503,8 @@ define float @sfct7(i32* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], s[[SEXTREG]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -517,8 +517,8 @@ define float @sfct8(i64* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: scvtf [[REG:s[0-9]+]], x[[REGNUM]] ; CHECK-NEXT: fmul s0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -531,8 +531,8 @@ define double @sfct9(i8* nocapture %sp0) { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 1 - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -550,8 +550,8 @@ define double @sfct10(i16* nocapture %sp0) { ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 1 - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -564,8 +564,8 @@ define double @sfct11(i32* nocapture %sp0) { ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -577,8 +577,8 @@ define double @sfct12(i64* nocapture %sp0) { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 1 - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -591,8 +591,8 @@ define double @sfct13(i8* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i8* %sp0, i64 %offset - %pix_sp0.0.copyload = load i8* %addr, align 1 + %addr = getelementptr i8, i8* %sp0, i64 %offset + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -610,8 +610,8 @@ define double @sfct14(i16* nocapture %sp0, i64 %offset) { ; CHECK-A57-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-A57-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i16* %sp0, i64 %offset - %pix_sp0.0.copyload = load i16* %addr, align 1 + %addr = getelementptr i16, i16* %sp0, i64 %offset + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -624,8 +624,8 @@ define double @sfct15(i32* nocapture %sp0, i64 %offset) { ; CHECK: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 %offset - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 %offset + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -637,8 +637,8 @@ define double @sfct16(i64* nocapture %sp0, i64 %offset) { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], d[[SEXTREG]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i64* %sp0, i64 %offset - %pix_sp0.0.copyload = load i64* %addr, align 1 + %addr = getelementptr i64, i64* %sp0, i64 %offset + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -660,7 +660,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -675,7 +675,7 @@ define float @sfct18(i16* nocapture %sp0) { %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* - %pix_sp0.0.copyload = load i16* %addr, align 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -689,7 +689,7 @@ define float @sfct19(i32* nocapture %sp0) { %bitcast = ptrtoint i32* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i32* - %pix_sp0.0.copyload = load i32* %addr, align 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -704,7 +704,7 @@ define float @sfct20(i64* nocapture %sp0) { %bitcast = ptrtoint i64* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i64* - %pix_sp0.0.copyload = load i64* %addr, align 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -721,7 +721,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -741,7 +741,7 @@ define double @sfct22(i16* nocapture %sp0) { %bitcast = ptrtoint i16* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i16* - %pix_sp0.0.copyload = load i16* %addr, align 1 + %pix_sp0.0.copyload = load i16, i16* %addr, align 1 %val = sitofp i16 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -756,7 +756,7 @@ define double @sfct23(i32* nocapture %sp0) { %bitcast = ptrtoint i32* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i32* - %pix_sp0.0.copyload = load i32* %addr, align 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -770,7 +770,7 @@ define double @sfct24(i64* nocapture %sp0) { %bitcast = ptrtoint i64* %sp0 to i64 %add = add i64 %bitcast, 1 %addr = inttoptr i64 %add to i64* - %pix_sp0.0.copyload = load i64* %addr, align 1 + %pix_sp0.0.copyload = load i64, i64* %addr, align 1 %val = sitofp i64 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i @@ -787,7 +787,7 @@ entry: %bitcast = ptrtoint i8* %sp0 to i64 %add = add i64 %bitcast, -1 %addr = inttoptr i64 %add to i8* - %pix_sp0.0.copyload = load i8* %addr, align 1 + %pix_sp0.0.copyload = load i8, i8* %addr, align 1 %val = sitofp i8 %pix_sp0.0.copyload to float %vmull.i = fmul float %val, %val ret float %vmull.i @@ -799,8 +799,8 @@ define double @codesize_sfct11(i32* nocapture %sp0) minsize { ; CHECK-NEXT: scvtf [[REG:d[0-9]+]], w[[REGNUM]] ; CHECK-NEXT: fmul d0, [[REG]], [[REG]] entry: - %addr = getelementptr i32* %sp0, i64 1 - %pix_sp0.0.copyload = load i32* %addr, align 1 + %addr = getelementptr i32, i32* %sp0, i64 1 + %pix_sp0.0.copyload = load i32, i32* %addr, align 1 %val = sitofp i32 %pix_sp0.0.copyload to double %vmull.i = fmul double %val, %val ret double %vmull.i |