diff options
Diffstat (limited to 'test/CodeGen/AArch64/ldst-unsignedimm.ll')
| -rw-r--r-- | test/CodeGen/AArch64/ldst-unsignedimm.ll | 62 |
1 files changed, 31 insertions, 31 deletions
diff --git a/test/CodeGen/AArch64/ldst-unsignedimm.ll b/test/CodeGen/AArch64/ldst-unsignedimm.ll index 44c1586..e171d22 100644 --- a/test/CodeGen/AArch64/ldst-unsignedimm.ll +++ b/test/CodeGen/AArch64/ldst-unsignedimm.ll @@ -1,4 +1,4 @@ -; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s +; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu | FileCheck %s ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s @var_8bit = global i8 0 @@ -20,25 +20,25 @@ define void @ldst_8bit() { %val32_signed = sext i8 %val8_sext32 to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: adrp {{x[0-9]+}}, var_8bit -; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] +; CHECK: ldrsb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; match a zero-extending load volatile 8-bit -> 32-bit %val8_zext32 = load volatile i8* @var_8bit %val32_unsigned = zext i8 %val8_zext32 to i32 store volatile i32 %val32_unsigned, i32* @var_32bit -; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; match an any-extending load volatile 8-bit -> 32-bit %val8_anyext = load volatile i8* @var_8bit %newval8 = add i8 %val8_anyext, 1 store volatile i8 %newval8, i8* @var_8bit -; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; match a sign-extending load volatile 8-bit -> 64-bit %val8_sext64 = load volatile i8* @var_8bit %val64_signed = sext i8 %val8_sext64 to i64 store volatile i64 %val64_signed, i64* @var_64bit -; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] +; CHECK: ldrsb {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; match a zero-extending load volatile 8-bit -> 64-bit. ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits @@ -46,19 +46,19 @@ define void @ldst_8bit() { %val8_zext64 = load volatile i8* @var_8bit %val64_unsigned = zext i8 %val8_zext64 to i64 store volatile i64 %val64_unsigned, i64* @var_64bit -; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] +; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; truncating store volatile 32-bits to 8-bits %val32 = load volatile i32* @var_32bit %val8_trunc32 = trunc i32 %val32 to i8 store volatile i8 %val8_trunc32, i8* @var_8bit -; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] +; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ; truncating store volatile 64-bits to 8-bits %val64 = load volatile i64* @var_64bit %val8_trunc64 = trunc i64 %val64 to i8 store volatile i8 %val8_trunc64, i8* @var_8bit -; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_8bit] +; CHECK: strb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_8bit] ret void } @@ -74,25 +74,25 @@ define void @ldst_16bit() { %val32_signed = sext i16 %val16_sext32 to i32 store volatile i32 %val32_signed, i32* @var_32bit ; CHECK: adrp {{x[0-9]+}}, var_16bit -; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] +; CHECK: ldrsh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; match a zero-extending load volatile 16-bit -> 32-bit %val16_zext32 = load volatile i16* @var_16bit %val32_unsigned = zext i16 %val16_zext32 to i32 store volatile i32 %val32_unsigned, i32* @var_32bit -; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; match an any-extending load volatile 16-bit -> 32-bit %val16_anyext = load volatile i16* @var_16bit %newval16 = add i16 %val16_anyext, 1 store volatile i16 %newval16, i16* @var_16bit -; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; match a sign-extending load volatile 16-bit -> 64-bit %val16_sext64 = load volatile i16* @var_16bit %val64_signed = sext i16 %val16_sext64 to i64 store volatile i64 %val64_signed, i64* @var_64bit -; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] +; CHECK: ldrsh {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; match a zero-extending load volatile 16-bit -> 64-bit. ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits @@ -100,19 +100,19 @@ define void @ldst_16bit() { %val16_zext64 = load volatile i16* @var_16bit %val64_unsigned = zext i16 %val16_zext64 to i64 store volatile i64 %val64_unsigned, i64* @var_64bit -; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] +; CHECK: ldrh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; truncating store volatile 32-bits to 16-bits %val32 = load volatile i32* @var_32bit %val16_trunc32 = trunc i32 %val32 to i16 store volatile i16 %val16_trunc32, i16* @var_16bit -; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] +; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ; truncating store volatile 64-bits to 16-bits %val64 = load volatile i64* @var_64bit %val16_trunc64 = trunc i64 %val64 to i16 store volatile i16 %val16_trunc64, i16* @var_16bit -; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_16bit] +; CHECK: strh {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_16bit] ret void } @@ -124,29 +124,29 @@ define void @ldst_32bit() { %val32_noext = load volatile i32* @var_32bit store volatile i32 %val32_noext, i32* @var_32bit ; CHECK: adrp {{x[0-9]+}}, var_32bit -; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] -; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] +; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] ; Zero-extension to 64-bits %val32_zext = load volatile i32* @var_32bit %val64_unsigned = zext i32 %val32_zext to i64 store volatile i64 %val64_unsigned, i64* @var_64bit -; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] -; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit] +; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] +; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] ; Sign-extension to 64-bits %val32_sext = load volatile i32* @var_32bit %val64_signed = sext i32 %val32_sext to i64 store volatile i64 %val64_signed, i64* @var_64bit -; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] -; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit] +; CHECK: ldrsw {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] +; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] ; Truncation from 64-bits %val64_trunc = load volatile i64* @var_64bit %val32_trunc = trunc i64 %val64_trunc to i32 store volatile i32 %val32_trunc, i32* @var_32bit -; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_64bit] -; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_32bit] +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit] +; CHECK: str {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_32bit] ret void } @@ -165,7 +165,7 @@ define void @ldst_complex_offsets() { ; CHECK: ldst_complex_offsets %arr8_addr = load volatile i8** @arr8 ; CHECK: adrp {{x[0-9]+}}, arr8 -; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:arr8] +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr8] %arr8_sub1_addr = getelementptr i8* %arr8_addr, i64 1 %arr8_sub1 = load volatile i8* %arr8_sub1_addr @@ -180,7 +180,7 @@ define void @ldst_complex_offsets() { %arr16_addr = load volatile i16** @arr16 ; CHECK: adrp {{x[0-9]+}}, arr16 -; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:arr16] +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr16] %arr16_sub1_addr = getelementptr i16* %arr16_addr, i64 1 %arr16_sub1 = load volatile i16* %arr16_sub1_addr @@ -195,7 +195,7 @@ define void @ldst_complex_offsets() { %arr32_addr = load volatile i32** @arr32 ; CHECK: adrp {{x[0-9]+}}, arr32 -; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:arr32] +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr32] %arr32_sub1_addr = getelementptr i32* %arr32_addr, i64 1 %arr32_sub1 = load volatile i32* %arr32_sub1_addr @@ -210,7 +210,7 @@ define void @ldst_complex_offsets() { %arr64_addr = load volatile i64** @arr64 ; CHECK: adrp {{x[0-9]+}}, arr64 -; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, #:lo12:arr64] +; CHECK: ldr {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:arr64] %arr64_sub1_addr = getelementptr i64* %arr64_addr, i64 1 %arr64_sub1 = load volatile i64* %arr64_sub1_addr @@ -230,11 +230,11 @@ define void @ldst_float() { %valfp = load volatile float* @var_float ; CHECK: adrp {{x[0-9]+}}, var_float -; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_float] +; CHECK: ldr {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_float] ; CHECK-NOFP-NOT: ldr {{s[0-9]+}}, store volatile float %valfp, float* @var_float -; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_float] +; CHECK: str {{s[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_float] ; CHECK-NOFP-NOT: str {{s[0-9]+}}, ret void @@ -245,11 +245,11 @@ define void @ldst_double() { %valfp = load volatile double* @var_double ; CHECK: adrp {{x[0-9]+}}, var_double -; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_double] +; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_double] ; CHECK-NOFP-NOT: ldr {{d[0-9]+}}, store volatile double %valfp, double* @var_double -; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, #:lo12:var_double] +; CHECK: str {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_double] ; CHECK-NOFP-NOT: str {{d[0-9]+}}, ret void |