diff options
Diffstat (limited to 'test/CodeGen/AArch64/neon-compare-instructions.ll')
-rw-r--r-- | test/CodeGen/AArch64/neon-compare-instructions.ll | 168 |
1 files changed, 56 insertions, 112 deletions
diff --git a/test/CodeGen/AArch64/neon-compare-instructions.ll b/test/CodeGen/AArch64/neon-compare-instructions.ll index 0848f9b..68f0342 100644 --- a/test/CodeGen/AArch64/neon-compare-instructions.ll +++ b/test/CodeGen/AArch64/neon-compare-instructions.ll @@ -51,8 +51,7 @@ define <2 x i64> @cmeq2xi64(<2 x i64> %A, <2 x i64> %B) { define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) { ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <8 x i8> %A, %B; %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -60,8 +59,7 @@ define <8 x i8> @cmne8xi8(<8 x i8> %A, <8 x i8> %B) { define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) { ;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <16 x i8> %A, %B; %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -69,8 +67,7 @@ define <16 x i8> @cmne16xi8(<16 x i8> %A, <16 x i8> %B) { define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) { ;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <4 x i16> %A, %B; %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -78,8 +75,7 @@ define <4 x i16> @cmne4xi16(<4 x i16> %A, <4 x i16> %B) { define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) { ;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <8 x i16> %A, %B; %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -87,8 +83,7 @@ define <8 x i16> @cmne8xi16(<8 x i16> %A, <8 x i16> %B) { define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) { ;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <2 x i32> %A, %B; %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -96,8 +91,7 @@ define <2 x i32> @cmne2xi32(<2 x i32> %A, <2 x i32> %B) { define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) { ;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <4 x i32> %A, %B; %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -105,8 +99,7 @@ define <4 x i32> @cmne4xi32(<4 x i32> %A, <4 x i32> %B) { define <2 x i64> @cmne2xi64(<2 x i64> %A, <2 x i64> %B) { ;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <2 x i64> %A, %B; %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -867,8 +860,7 @@ define <2 x i64> @cmltz2xi64(<2 x i64> %A) { define <8 x i8> @cmneqz8xi8(<8 x i8> %A) { ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <8 x i8> %A, zeroinitializer; %tmp4 = sext <8 x i1> %tmp3 to <8 x i8> ret <8 x i8> %tmp4 @@ -876,8 +868,7 @@ define <8 x i8> @cmneqz8xi8(<8 x i8> %A) { define <16 x i8> @cmneqz16xi8(<16 x i8> %A) { ;CHECK: cmeq {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <16 x i8> %A, zeroinitializer; %tmp4 = sext <16 x i1> %tmp3 to <16 x i8> ret <16 x i8> %tmp4 @@ -885,8 +876,7 @@ define <16 x i8> @cmneqz16xi8(<16 x i8> %A) { define <4 x i16> @cmneqz4xi16(<4 x i16> %A) { ;CHECK: cmeq {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <4 x i16> %A, zeroinitializer; %tmp4 = sext <4 x i1> %tmp3 to <4 x i16> ret <4 x i16> %tmp4 @@ -894,8 +884,7 @@ define <4 x i16> @cmneqz4xi16(<4 x i16> %A) { define <8 x i16> @cmneqz8xi16(<8 x i16> %A) { ;CHECK: cmeq {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <8 x i16> %A, zeroinitializer; %tmp4 = sext <8 x i1> %tmp3 to <8 x i16> ret <8 x i16> %tmp4 @@ -903,8 +892,7 @@ define <8 x i16> @cmneqz8xi16(<8 x i16> %A) { define <2 x i32> @cmneqz2xi32(<2 x i32> %A) { ;CHECK: cmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = icmp ne <2 x i32> %A, zeroinitializer; %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -912,8 +900,7 @@ define <2 x i32> @cmneqz2xi32(<2 x i32> %A) { define <4 x i32> @cmneqz4xi32(<4 x i32> %A) { ;CHECK: cmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <4 x i32> %A, zeroinitializer; %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -921,8 +908,7 @@ define <4 x i32> @cmneqz4xi32(<4 x i32> %A) { define <2 x i64> @cmneqz2xi64(<2 x i64> %A) { ;CHECK: cmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0x0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = icmp ne <2 x i64> %A, zeroinitializer; %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1369,8 +1355,7 @@ define <2 x i32> @fcmuno2xfloat(<2 x float> %A, <2 x float> %B) { ;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s ;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s ;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp uno <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1382,8 +1367,7 @@ define <4 x i32> @fcmuno4xfloat(<4 x float> %A, <4 x float> %B) { ;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s ;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uno <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1395,8 +1379,7 @@ define <2 x i64> @fcmuno2xdouble(<2 x double> %A, <2 x double> %B) { ;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d ;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uno <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1408,8 +1391,7 @@ define <2 x i32> @fcmueq2xfloat(<2 x float> %A, <2 x float> %B) { ;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s ;CHECK-NEXT: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s ;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ueq <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1421,8 +1403,7 @@ define <4 x i32> @fcmueq4xfloat(<4 x float> %A, <4 x float> %B) { ;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s ;CHECK-NEXT: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ueq <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1434,8 +1415,7 @@ define <2 x i64> @fcmueq2xdouble(<2 x double> %A, <2 x double> %B) { ;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d ;CHECK-NEXT: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ueq <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1445,8 +1425,7 @@ define <2 x i32> @fcmuge2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGE = ULE with swapped operands, ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.2s, v1.2s, v0.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp uge <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1456,8 +1435,7 @@ define <4 x i32> @fcmuge4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGE = ULE with swapped operands, ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.4s, v1.4s, v0.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uge <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1467,8 +1445,7 @@ define <2 x i64> @fcmuge2xdouble(<2 x double> %A, <2 x double> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGE = ULE with swapped operands, ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.2d, v1.2d, v0.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uge <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1478,8 +1455,7 @@ define <2 x i32> @fcmugt2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGT = ULT with swapped operands, ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.2s, v1.2s, v0.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ugt <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1489,16 +1465,14 @@ define <4 x i32> @fcmugt4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UGT = ULT with swapped operands, ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.4s, v1.4s, v0.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ugt <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 } define <2 x i64> @fcmugt2xdouble(<2 x double> %A, <2 x double> %B) { ;CHECK: fcmge {{v[0-9]+}}.2d, v1.2d, v0.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ugt <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1508,8 +1482,7 @@ define <2 x i32> @fcmule2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.2s, v0.2s, v1.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ule <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1519,8 +1492,7 @@ define <4 x i32> @fcmule4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.4s, v0.4s, v1.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ule <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1529,8 +1501,7 @@ define <2 x i64> @fcmule2xdouble(<2 x double> %A, <2 x double> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULE implemented as !OGT. ;CHECK: fcmgt {{v[0-9]+}}.2d, v0.2d, v1.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ule <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1540,8 +1511,7 @@ define <2 x i32> @fcmult2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.2s, v0.2s, v1.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ult <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1551,8 +1521,7 @@ define <4 x i32> @fcmult4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.4s, v0.4s, v1.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ult <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1561,8 +1530,7 @@ define <2 x i64> @fcmult2xdouble(<2 x double> %A, <2 x double> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; ULT implemented as !OGE. ;CHECK: fcmge {{v[0-9]+}}.2d, v0.2d, v1.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ult <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1572,8 +1540,7 @@ define <2 x i32> @fcmune2xfloat(<2 x float> %A, <2 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UNE = !OEQ. ;CHECK: fcmeq {{v[0-9]+}}.2s, v0.2s, v1.2s -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp une <2 x float> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1583,8 +1550,7 @@ define <4 x i32> @fcmune4xfloat(<4 x float> %A, <4 x float> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UNE = !OEQ. ;CHECK: fcmeq {{v[0-9]+}}.4s, v0.4s, v1.4s -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp une <4 x float> %A, %B %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1593,8 +1559,7 @@ define <2 x i64> @fcmune2xdouble(<2 x double> %A, <2 x double> %B) { ; Using registers other than v0, v1 are possible, but would be odd. ; UNE = !OEQ. ;CHECK: fcmeq {{v[0-9]+}}.2d, v0.2d, v1.2d -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp une <2 x double> %A, %B %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1766,8 +1731,7 @@ define <2 x i32> @fcmueqz2xfloat(<2 x float> %A) { ;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ueq <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1778,8 +1742,7 @@ define <4 x i32> @fcmueqz4xfloat(<4 x float> %A) { ;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ueq <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1790,8 +1753,7 @@ define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) { ;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ueq <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1800,8 +1762,7 @@ define <2 x i64> @fcmueqz2xdouble(<2 x double> %A) { define <2 x i32> @fcmugez2xfloat(<2 x float> %A) { ; UGE with zero = !OLT ;CHECK: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp uge <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1810,8 +1771,7 @@ define <2 x i32> @fcmugez2xfloat(<2 x float> %A) { define <4 x i32> @fcmugez4xfloat(<4 x float> %A) { ; UGE with zero = !OLT ;CHECK: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uge <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1819,8 +1779,7 @@ define <4 x i32> @fcmugez4xfloat(<4 x float> %A) { define <2 x i64> @fcmugez2xdouble(<2 x double> %A) { ; UGE with zero = !OLT ;CHECK: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uge <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1829,8 +1788,7 @@ define <2 x i64> @fcmugez2xdouble(<2 x double> %A) { define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) { ; UGT with zero = !OLE ;CHECK: fcmle {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ugt <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1839,8 +1797,7 @@ define <2 x i32> @fcmugtz2xfloat(<2 x float> %A) { define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) { ; UGT with zero = !OLE ;CHECK: fcmle {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ugt <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1848,8 +1805,7 @@ define <4 x i32> @fcmugtz4xfloat(<4 x float> %A) { define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) { ; UGT with zero = !OLE ;CHECK: fcmle {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ugt <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1858,8 +1814,7 @@ define <2 x i64> @fcmugtz2xdouble(<2 x double> %A) { define <2 x i32> @fcmultz2xfloat(<2 x float> %A) { ; ULT with zero = !OGE ;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ult <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1867,8 +1822,7 @@ define <2 x i32> @fcmultz2xfloat(<2 x float> %A) { define <4 x i32> @fcmultz4xfloat(<4 x float> %A) { ;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ult <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1876,8 +1830,7 @@ define <4 x i32> @fcmultz4xfloat(<4 x float> %A) { define <2 x i64> @fcmultz2xdouble(<2 x double> %A) { ;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ult <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1887,8 +1840,7 @@ define <2 x i64> @fcmultz2xdouble(<2 x double> %A) { define <2 x i32> @fcmulez2xfloat(<2 x float> %A) { ; ULE with zero = !OGT ;CHECK: fcmgt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp ule <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1897,8 +1849,7 @@ define <2 x i32> @fcmulez2xfloat(<2 x float> %A) { define <4 x i32> @fcmulez4xfloat(<4 x float> %A) { ; ULE with zero = !OGT ;CHECK: fcmgt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ule <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1907,8 +1858,7 @@ define <4 x i32> @fcmulez4xfloat(<4 x float> %A) { define <2 x i64> @fcmulez2xdouble(<2 x double> %A) { ; ULE with zero = !OGT ;CHECK: fcmgt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp ule <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1917,8 +1867,7 @@ define <2 x i64> @fcmulez2xdouble(<2 x double> %A) { define <2 x i32> @fcmunez2xfloat(<2 x float> %A) { ; UNE with zero = !OEQ with zero ;CHECK: fcmeq {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp une <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1927,8 +1876,7 @@ define <2 x i32> @fcmunez2xfloat(<2 x float> %A) { define <4 x i32> @fcmunez4xfloat(<4 x float> %A) { ; UNE with zero = !OEQ with zero ;CHECK: fcmeq {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp une <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1936,8 +1884,7 @@ define <4 x i32> @fcmunez4xfloat(<4 x float> %A) { define <2 x i64> @fcmunez2xdouble(<2 x double> %A) { ; UNE with zero = !OEQ with zero ;CHECK: fcmeq {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp une <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 @@ -1949,8 +1896,7 @@ define <2 x i32> @fcmunoz2xfloat(<2 x float> %A) { ;CHECK: fcmge {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -;CHECK-NEXT: movi {{v[0-9]+}}.8b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b +;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b %tmp3 = fcmp uno <2 x float> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i32> ret <2 x i32> %tmp4 @@ -1961,8 +1907,7 @@ define <4 x i32> @fcmunoz4xfloat(<4 x float> %A) { ;CHECK: fcmge {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uno <4 x float> %A, zeroinitializer %tmp4 = sext <4 x i1> %tmp3 to <4 x i32> ret <4 x i32> %tmp4 @@ -1973,8 +1918,7 @@ define <2 x i64> @fcmunoz2xdouble(<2 x double> %A) { ;CHECK: fcmge {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 ;CHECK-NEXT: fcmlt {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #0.0 ;CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b -;CHECK-NEXT: movi {{v[0-9]+}}.16b, #0xff -;CHECK-NEXT: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +;CHECK-NEXT: not {{v[0-9]+}}.16b, {{v[0-9]+}}.16b %tmp3 = fcmp uno <2 x double> %A, zeroinitializer %tmp4 = sext <2 x i1> %tmp3 to <2 x i64> ret <2 x i64> %tmp4 |