diff options
Diffstat (limited to 'test/CodeGen/AArch64/neon-perm.ll')
| -rw-r--r-- | test/CodeGen/AArch64/neon-perm.ll | 838 |
1 files changed, 416 insertions, 422 deletions
diff --git a/test/CodeGen/AArch64/neon-perm.ll b/test/CodeGen/AArch64/neon-perm.ll index a0b17e1..4f8571d 100644 --- a/test/CodeGen/AArch64/neon-perm.ll +++ b/test/CodeGen/AArch64/neon-perm.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK %struct.int8x8x2_t = type { [2 x <8 x i8>] } %struct.int16x4x2_t = type { [2 x <4 x i16>] } @@ -20,7 +20,7 @@ %struct.poly16x8x2_t = type { [2 x <8 x i16>] } define <8 x i8> @test_vuzp1_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp1_s8: +; CHECK-LABEL: test_vuzp1_s8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -28,7 +28,7 @@ entry: } define <16 x i8> @test_vuzp1q_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzp1q_s8: +; CHECK-LABEL: test_vuzp1q_s8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -36,7 +36,7 @@ entry: } define <4 x i16> @test_vuzp1_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp1_s16: +; CHECK-LABEL: test_vuzp1_s16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -44,7 +44,7 @@ entry: } define <8 x i16> @test_vuzp1q_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzp1q_s16: +; CHECK-LABEL: test_vuzp1q_s16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -52,15 +52,15 @@ entry: } define <2 x i32> @test_vuzp1_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vuzp1_s32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vuzp1_s32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vuzp1q_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vuzp1q_s32: +; CHECK-LABEL: test_vuzp1q_s32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -68,15 +68,15 @@ entry: } define <2 x i64> @test_vuzp1q_s64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vuzp1q_s64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vuzp1q_s64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2> ret <2 x i64> %shuffle.i } define <8 x i8> @test_vuzp1_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp1_u8: +; CHECK-LABEL: test_vuzp1_u8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -84,7 +84,7 @@ entry: } define <16 x i8> @test_vuzp1q_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzp1q_u8: +; CHECK-LABEL: test_vuzp1q_u8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -92,7 +92,7 @@ entry: } define <4 x i16> @test_vuzp1_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp1_u16: +; CHECK-LABEL: test_vuzp1_u16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -100,7 +100,7 @@ entry: } define <8 x i16> @test_vuzp1q_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzp1q_u16: +; CHECK-LABEL: test_vuzp1q_u16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -108,15 +108,15 @@ entry: } define <2 x i32> @test_vuzp1_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vuzp1_u32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vuzp1_u32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vuzp1q_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vuzp1q_u32: +; CHECK-LABEL: test_vuzp1q_u32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -124,23 +124,23 @@ entry: } define <2 x i64> @test_vuzp1q_u64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vuzp1q_u64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vuzp1q_u64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2> ret <2 x i64> %shuffle.i } define <2 x float> @test_vuzp1_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vuzp1_f32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vuzp1_f32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 0, i32 2> ret <2 x float> %shuffle.i } define <4 x float> @test_vuzp1q_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vuzp1q_f32: +; CHECK-LABEL: test_vuzp1q_f32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -148,15 +148,15 @@ entry: } define <2 x double> @test_vuzp1q_f64(<2 x double> %a, <2 x double> %b) { -; CHECK: test_vuzp1q_f64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vuzp1q_f64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2> ret <2 x double> %shuffle.i } define <8 x i8> @test_vuzp1_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp1_p8: +; CHECK-LABEL: test_vuzp1_p8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -164,7 +164,7 @@ entry: } define <16 x i8> @test_vuzp1q_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzp1q_p8: +; CHECK-LABEL: test_vuzp1q_p8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -172,7 +172,7 @@ entry: } define <4 x i16> @test_vuzp1_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp1_p16: +; CHECK-LABEL: test_vuzp1_p16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -180,7 +180,7 @@ entry: } define <8 x i16> @test_vuzp1q_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzp1q_p16: +; CHECK-LABEL: test_vuzp1q_p16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -188,7 +188,7 @@ entry: } define <8 x i8> @test_vuzp2_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp2_s8: +; CHECK-LABEL: test_vuzp2_s8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -196,7 +196,7 @@ entry: } define <16 x i8> @test_vuzp2q_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzp2q_s8: +; CHECK-LABEL: test_vuzp2q_s8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -204,7 +204,7 @@ entry: } define <4 x i16> @test_vuzp2_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp2_s16: +; CHECK-LABEL: test_vuzp2_s16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -212,7 +212,7 @@ entry: } define <8 x i16> @test_vuzp2q_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzp2q_s16: +; CHECK-LABEL: test_vuzp2q_s16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -220,15 +220,15 @@ entry: } define <2 x i32> @test_vuzp2_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vuzp2_s32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vuzp2_s32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vuzp2q_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vuzp2q_s32: +; CHECK-LABEL: test_vuzp2q_s32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -236,16 +236,15 @@ entry: } define <2 x i64> @test_vuzp2q_s64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vuzp2q_s64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] -; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK-LABEL: test_vuzp2q_s64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> ret <2 x i64> %shuffle.i } define <8 x i8> @test_vuzp2_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp2_u8: +; CHECK-LABEL: test_vuzp2_u8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -253,7 +252,7 @@ entry: } define <16 x i8> @test_vuzp2q_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzp2q_u8: +; CHECK-LABEL: test_vuzp2q_u8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -261,7 +260,7 @@ entry: } define <4 x i16> @test_vuzp2_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp2_u16: +; CHECK-LABEL: test_vuzp2_u16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -269,7 +268,7 @@ entry: } define <8 x i16> @test_vuzp2q_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzp2q_u16: +; CHECK-LABEL: test_vuzp2q_u16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -277,15 +276,15 @@ entry: } define <2 x i32> @test_vuzp2_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vuzp2_u32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vuzp2_u32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vuzp2q_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vuzp2q_u32: +; CHECK-LABEL: test_vuzp2q_u32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -293,24 +292,23 @@ entry: } define <2 x i64> @test_vuzp2q_u64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vuzp2q_u64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] -; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK-LABEL: test_vuzp2q_u64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> ret <2 x i64> %shuffle.i } define <2 x float> @test_vuzp2_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vuzp2_f32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vuzp2_f32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 3> ret <2 x float> %shuffle.i } define <4 x float> @test_vuzp2q_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vuzp2q_f32: +; CHECK-LABEL: test_vuzp2q_f32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -318,16 +316,15 @@ entry: } define <2 x double> @test_vuzp2q_f64(<2 x double> %a, <2 x double> %b) { -; CHECK: test_vuzp2q_f64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] -; CHECK-NEXT: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b +; CHECK-LABEL: test_vuzp2q_f64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3> ret <2 x double> %shuffle.i } define <8 x i8> @test_vuzp2_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp2_p8: +; CHECK-LABEL: test_vuzp2_p8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -335,7 +332,7 @@ entry: } define <16 x i8> @test_vuzp2q_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzp2q_p8: +; CHECK-LABEL: test_vuzp2q_p8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -343,7 +340,7 @@ entry: } define <4 x i16> @test_vuzp2_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp2_p16: +; CHECK-LABEL: test_vuzp2_p16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -351,7 +348,7 @@ entry: } define <8 x i16> @test_vuzp2q_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzp2q_p16: +; CHECK-LABEL: test_vuzp2q_p16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -359,7 +356,7 @@ entry: } define <8 x i8> @test_vzip1_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip1_s8: +; CHECK-LABEL: test_vzip1_s8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -367,7 +364,7 @@ entry: } define <16 x i8> @test_vzip1q_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzip1q_s8: +; CHECK-LABEL: test_vzip1q_s8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -375,7 +372,7 @@ entry: } define <4 x i16> @test_vzip1_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip1_s16: +; CHECK-LABEL: test_vzip1_s16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -383,7 +380,7 @@ entry: } define <8 x i16> @test_vzip1q_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzip1q_s16: +; CHECK-LABEL: test_vzip1q_s16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -391,15 +388,15 @@ entry: } define <2 x i32> @test_vzip1_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vzip1_s32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vzip1_s32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vzip1q_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vzip1q_s32: +; CHECK-LABEL: test_vzip1q_s32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -407,15 +404,15 @@ entry: } define <2 x i64> @test_vzip1q_s64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vzip1q_s64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vzip1q_s64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2> ret <2 x i64> %shuffle.i } define <8 x i8> @test_vzip1_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip1_u8: +; CHECK-LABEL: test_vzip1_u8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -423,7 +420,7 @@ entry: } define <16 x i8> @test_vzip1q_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzip1q_u8: +; CHECK-LABEL: test_vzip1q_u8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -431,7 +428,7 @@ entry: } define <4 x i16> @test_vzip1_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip1_u16: +; CHECK-LABEL: test_vzip1_u16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -439,7 +436,7 @@ entry: } define <8 x i16> @test_vzip1q_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzip1q_u16: +; CHECK-LABEL: test_vzip1q_u16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -447,15 +444,15 @@ entry: } define <2 x i32> @test_vzip1_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vzip1_u32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vzip1_u32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vzip1q_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vzip1q_u32: +; CHECK-LABEL: test_vzip1q_u32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -463,23 +460,23 @@ entry: } define <2 x i64> @test_vzip1q_u64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vzip1q_u64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vzip1q_u64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2> ret <2 x i64> %shuffle.i } define <2 x float> @test_vzip1_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vzip1_f32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vzip1_f32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 0, i32 2> ret <2 x float> %shuffle.i } define <4 x float> @test_vzip1q_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vzip1q_f32: +; CHECK-LABEL: test_vzip1q_f32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -487,15 +484,15 @@ entry: } define <2 x double> @test_vzip1q_f64(<2 x double> %a, <2 x double> %b) { -; CHECK: test_vzip1q_f64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vzip1q_f64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2> ret <2 x double> %shuffle.i } define <8 x i8> @test_vzip1_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip1_p8: +; CHECK-LABEL: test_vzip1_p8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -503,7 +500,7 @@ entry: } define <16 x i8> @test_vzip1q_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzip1q_p8: +; CHECK-LABEL: test_vzip1q_p8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -511,7 +508,7 @@ entry: } define <4 x i16> @test_vzip1_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip1_p16: +; CHECK-LABEL: test_vzip1_p16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -519,7 +516,7 @@ entry: } define <8 x i16> @test_vzip1q_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzip1q_p16: +; CHECK-LABEL: test_vzip1q_p16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -527,7 +524,7 @@ entry: } define <8 x i8> @test_vzip2_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip2_s8: +; CHECK-LABEL: test_vzip2_s8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -535,7 +532,7 @@ entry: } define <16 x i8> @test_vzip2q_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzip2q_s8: +; CHECK-LABEL: test_vzip2q_s8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -543,7 +540,7 @@ entry: } define <4 x i16> @test_vzip2_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip2_s16: +; CHECK-LABEL: test_vzip2_s16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -551,7 +548,7 @@ entry: } define <8 x i16> @test_vzip2q_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzip2q_s16: +; CHECK-LABEL: test_vzip2q_s16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -559,15 +556,15 @@ entry: } define <2 x i32> @test_vzip2_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vzip2_s32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vzip2_s32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vzip2q_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vzip2q_s32: +; CHECK-LABEL: test_vzip2q_s32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -575,15 +572,15 @@ entry: } define <2 x i64> @test_vzip2q_s64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vzip2q_s64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] +; CHECK-LABEL: test_vzip2q_s64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> ret <2 x i64> %shuffle.i } define <8 x i8> @test_vzip2_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip2_u8: +; CHECK-LABEL: test_vzip2_u8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -591,7 +588,7 @@ entry: } define <16 x i8> @test_vzip2q_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzip2q_u8: +; CHECK-LABEL: test_vzip2q_u8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -599,7 +596,7 @@ entry: } define <4 x i16> @test_vzip2_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip2_u16: +; CHECK-LABEL: test_vzip2_u16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -607,7 +604,7 @@ entry: } define <8 x i16> @test_vzip2q_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzip2q_u16: +; CHECK-LABEL: test_vzip2q_u16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -615,15 +612,15 @@ entry: } define <2 x i32> @test_vzip2_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vzip2_u32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vzip2_u32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vzip2q_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vzip2q_u32: +; CHECK-LABEL: test_vzip2q_u32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -631,23 +628,23 @@ entry: } define <2 x i64> @test_vzip2q_u64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vzip2q_u64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] +; CHECK-LABEL: test_vzip2q_u64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> ret <2 x i64> %shuffle.i } define <2 x float> @test_vzip2_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vzip2_f32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vzip2_f32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 3> ret <2 x float> %shuffle.i } define <4 x float> @test_vzip2q_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vzip2q_f32: +; CHECK-LABEL: test_vzip2q_f32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -655,15 +652,15 @@ entry: } define <2 x double> @test_vzip2q_f64(<2 x double> %a, <2 x double> %b) { -; CHECK: test_vzip2q_f64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] +; CHECK-LABEL: test_vzip2q_f64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3> ret <2 x double> %shuffle.i } define <8 x i8> @test_vzip2_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip2_p8: +; CHECK-LABEL: test_vzip2_p8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -671,7 +668,7 @@ entry: } define <16 x i8> @test_vzip2q_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzip2q_p8: +; CHECK-LABEL: test_vzip2q_p8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -679,7 +676,7 @@ entry: } define <4 x i16> @test_vzip2_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip2_p16: +; CHECK-LABEL: test_vzip2_p16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -687,7 +684,7 @@ entry: } define <8 x i16> @test_vzip2q_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzip2q_p16: +; CHECK-LABEL: test_vzip2q_p16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -695,7 +692,7 @@ entry: } define <8 x i8> @test_vtrn1_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn1_s8: +; CHECK-LABEL: test_vtrn1_s8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -703,7 +700,7 @@ entry: } define <16 x i8> @test_vtrn1q_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrn1q_s8: +; CHECK-LABEL: test_vtrn1q_s8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -711,7 +708,7 @@ entry: } define <4 x i16> @test_vtrn1_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn1_s16: +; CHECK-LABEL: test_vtrn1_s16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -719,7 +716,7 @@ entry: } define <8 x i16> @test_vtrn1q_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrn1q_s16: +; CHECK-LABEL: test_vtrn1q_s16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -727,15 +724,15 @@ entry: } define <2 x i32> @test_vtrn1_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vtrn1_s32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vtrn1_s32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vtrn1q_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vtrn1q_s32: +; CHECK-LABEL: test_vtrn1q_s32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -743,15 +740,15 @@ entry: } define <2 x i64> @test_vtrn1q_s64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vtrn1q_s64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vtrn1q_s64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2> ret <2 x i64> %shuffle.i } define <8 x i8> @test_vtrn1_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn1_u8: +; CHECK-LABEL: test_vtrn1_u8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -759,7 +756,7 @@ entry: } define <16 x i8> @test_vtrn1q_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrn1q_u8: +; CHECK-LABEL: test_vtrn1q_u8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -767,7 +764,7 @@ entry: } define <4 x i16> @test_vtrn1_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn1_u16: +; CHECK-LABEL: test_vtrn1_u16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -775,7 +772,7 @@ entry: } define <8 x i16> @test_vtrn1q_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrn1q_u16: +; CHECK-LABEL: test_vtrn1q_u16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -783,15 +780,15 @@ entry: } define <2 x i32> @test_vtrn1_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vtrn1_u32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vtrn1_u32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vtrn1q_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vtrn1q_u32: +; CHECK-LABEL: test_vtrn1q_u32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -799,23 +796,23 @@ entry: } define <2 x i64> @test_vtrn1q_u64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vtrn1q_u64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vtrn1q_u64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 0, i32 2> ret <2 x i64> %shuffle.i } define <2 x float> @test_vtrn1_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vtrn1_f32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] +; CHECK-LABEL: test_vtrn1_f32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 0, i32 2> ret <2 x float> %shuffle.i } define <4 x float> @test_vtrn1q_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vtrn1q_f32: +; CHECK-LABEL: test_vtrn1q_f32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -823,15 +820,15 @@ entry: } define <2 x double> @test_vtrn1q_f64(<2 x double> %a, <2 x double> %b) { -; CHECK: test_vtrn1q_f64: -; CHECK: ins {{v[0-9]+}}.d[1], {{v[0-9]+}}.d[0] +; CHECK-LABEL: test_vtrn1q_f64: +; CHECK: zip1 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 0, i32 2> ret <2 x double> %shuffle.i } define <8 x i8> @test_vtrn1_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn1_p8: +; CHECK-LABEL: test_vtrn1_p8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -839,7 +836,7 @@ entry: } define <16 x i8> @test_vtrn1q_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrn1q_p8: +; CHECK-LABEL: test_vtrn1q_p8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -847,7 +844,7 @@ entry: } define <4 x i16> @test_vtrn1_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn1_p16: +; CHECK-LABEL: test_vtrn1_p16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -855,7 +852,7 @@ entry: } define <8 x i16> @test_vtrn1q_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrn1q_p16: +; CHECK-LABEL: test_vtrn1q_p16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -863,7 +860,7 @@ entry: } define <8 x i8> @test_vtrn2_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn2_s8: +; CHECK-LABEL: test_vtrn2_s8: ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -871,7 +868,7 @@ entry: } define <16 x i8> @test_vtrn2q_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrn2q_s8: +; CHECK-LABEL: test_vtrn2q_s8: ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -879,7 +876,7 @@ entry: } define <4 x i16> @test_vtrn2_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn2_s16: +; CHECK-LABEL: test_vtrn2_s16: ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -887,7 +884,7 @@ entry: } define <8 x i16> @test_vtrn2q_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrn2q_s16: +; CHECK-LABEL: test_vtrn2q_s16: ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -895,15 +892,15 @@ entry: } define <2 x i32> @test_vtrn2_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vtrn2_s32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vtrn2_s32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vtrn2q_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vtrn2q_s32: +; CHECK-LABEL: test_vtrn2q_s32: ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -911,15 +908,15 @@ entry: } define <2 x i64> @test_vtrn2q_s64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vtrn2q_s64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] +; CHECK-LABEL: test_vtrn2q_s64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> ret <2 x i64> %shuffle.i } define <8 x i8> @test_vtrn2_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn2_u8: +; CHECK-LABEL: test_vtrn2_u8: ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -927,7 +924,7 @@ entry: } define <16 x i8> @test_vtrn2q_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrn2q_u8: +; CHECK-LABEL: test_vtrn2q_u8: ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -935,7 +932,7 @@ entry: } define <4 x i16> @test_vtrn2_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn2_u16: +; CHECK-LABEL: test_vtrn2_u16: ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -943,7 +940,7 @@ entry: } define <8 x i16> @test_vtrn2q_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrn2q_u16: +; CHECK-LABEL: test_vtrn2q_u16: ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -951,15 +948,15 @@ entry: } define <2 x i32> @test_vtrn2_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vtrn2_u32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vtrn2_u32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> ret <2 x i32> %shuffle.i } define <4 x i32> @test_vtrn2q_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vtrn2q_u32: +; CHECK-LABEL: test_vtrn2q_u32: ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -967,23 +964,23 @@ entry: } define <2 x i64> @test_vtrn2q_u64(<2 x i64> %a, <2 x i64> %b) { -; CHECK: test_vtrn2q_u64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] +; CHECK-LABEL: test_vtrn2q_u64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x i64> %a, <2 x i64> %b, <2 x i32> <i32 1, i32 3> ret <2 x i64> %shuffle.i } define <2 x float> @test_vtrn2_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vtrn2_f32: -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vtrn2_f32: +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %shuffle.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 3> ret <2 x float> %shuffle.i } define <4 x float> @test_vtrn2q_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vtrn2q_f32: +; CHECK-LABEL: test_vtrn2q_f32: ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -991,15 +988,15 @@ entry: } define <2 x double> @test_vtrn2q_f64(<2 x double> %a, <2 x double> %b) { -; CHECK: test_vtrn2q_f64: -; CHECK: ins {{v[0-9]+}}.d[0], {{v[0-9]+}}.d[1] +; CHECK-LABEL: test_vtrn2q_f64: +; CHECK: zip2 {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d entry: %shuffle.i = shufflevector <2 x double> %a, <2 x double> %b, <2 x i32> <i32 1, i32 3> ret <2 x double> %shuffle.i } define <8 x i8> @test_vtrn2_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn2_p8: +; CHECK-LABEL: test_vtrn2_p8: ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -1007,7 +1004,7 @@ entry: } define <16 x i8> @test_vtrn2q_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrn2q_p8: +; CHECK-LABEL: test_vtrn2q_p8: ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -1015,7 +1012,7 @@ entry: } define <4 x i16> @test_vtrn2_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn2_p16: +; CHECK-LABEL: test_vtrn2_p16: ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %b, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -1023,7 +1020,7 @@ entry: } define <8 x i16> @test_vtrn2q_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrn2q_p16: +; CHECK-LABEL: test_vtrn2q_p16: ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -1031,7 +1028,7 @@ entry: } define <8 x i8> @test_same_vuzp1_s8(<8 x i8> %a) { -; CHECK: test_same_vuzp1_s8: +; CHECK-LABEL: test_same_vuzp1_s8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1039,7 +1036,7 @@ entry: } define <16 x i8> @test_same_vuzp1q_s8(<16 x i8> %a) { -; CHECK: test_same_vuzp1q_s8: +; CHECK-LABEL: test_same_vuzp1q_s8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -1047,7 +1044,7 @@ entry: } define <4 x i16> @test_same_vuzp1_s16(<4 x i16> %a) { -; CHECK: test_same_vuzp1_s16: +; CHECK-LABEL: test_same_vuzp1_s16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1055,7 +1052,7 @@ entry: } define <8 x i16> @test_same_vuzp1q_s16(<8 x i16> %a) { -; CHECK: test_same_vuzp1q_s16: +; CHECK-LABEL: test_same_vuzp1q_s16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1063,7 +1060,7 @@ entry: } define <4 x i32> @test_same_vuzp1q_s32(<4 x i32> %a) { -; CHECK: test_same_vuzp1q_s32: +; CHECK-LABEL: test_same_vuzp1q_s32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1071,7 +1068,7 @@ entry: } define <8 x i8> @test_same_vuzp1_u8(<8 x i8> %a) { -; CHECK: test_same_vuzp1_u8: +; CHECK-LABEL: test_same_vuzp1_u8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1079,7 +1076,7 @@ entry: } define <16 x i8> @test_same_vuzp1q_u8(<16 x i8> %a) { -; CHECK: test_same_vuzp1q_u8: +; CHECK-LABEL: test_same_vuzp1q_u8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -1087,7 +1084,7 @@ entry: } define <4 x i16> @test_same_vuzp1_u16(<4 x i16> %a) { -; CHECK: test_same_vuzp1_u16: +; CHECK-LABEL: test_same_vuzp1_u16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1095,7 +1092,7 @@ entry: } define <8 x i16> @test_same_vuzp1q_u16(<8 x i16> %a) { -; CHECK: test_same_vuzp1q_u16: +; CHECK-LABEL: test_same_vuzp1q_u16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1103,7 +1100,7 @@ entry: } define <4 x i32> @test_same_vuzp1q_u32(<4 x i32> %a) { -; CHECK: test_same_vuzp1q_u32: +; CHECK-LABEL: test_same_vuzp1q_u32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1111,7 +1108,7 @@ entry: } define <4 x float> @test_same_vuzp1q_f32(<4 x float> %a) { -; CHECK: test_same_vuzp1q_f32: +; CHECK-LABEL: test_same_vuzp1q_f32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1119,7 +1116,7 @@ entry: } define <8 x i8> @test_same_vuzp1_p8(<8 x i8> %a) { -; CHECK: test_same_vuzp1_p8: +; CHECK-LABEL: test_same_vuzp1_p8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1127,7 +1124,7 @@ entry: } define <16 x i8> @test_same_vuzp1q_p8(<16 x i8> %a) { -; CHECK: test_same_vuzp1q_p8: +; CHECK-LABEL: test_same_vuzp1q_p8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -1135,7 +1132,7 @@ entry: } define <4 x i16> @test_same_vuzp1_p16(<4 x i16> %a) { -; CHECK: test_same_vuzp1_p16: +; CHECK-LABEL: test_same_vuzp1_p16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1143,7 +1140,7 @@ entry: } define <8 x i16> @test_same_vuzp1q_p16(<8 x i16> %a) { -; CHECK: test_same_vuzp1q_p16: +; CHECK-LABEL: test_same_vuzp1q_p16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1151,7 +1148,7 @@ entry: } define <8 x i8> @test_same_vuzp2_s8(<8 x i8> %a) { -; CHECK: test_same_vuzp2_s8: +; CHECK-LABEL: test_same_vuzp2_s8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1159,7 +1156,7 @@ entry: } define <16 x i8> @test_same_vuzp2q_s8(<16 x i8> %a) { -; CHECK: test_same_vuzp2q_s8: +; CHECK-LABEL: test_same_vuzp2q_s8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -1167,7 +1164,7 @@ entry: } define <4 x i16> @test_same_vuzp2_s16(<4 x i16> %a) { -; CHECK: test_same_vuzp2_s16: +; CHECK-LABEL: test_same_vuzp2_s16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1175,7 +1172,7 @@ entry: } define <8 x i16> @test_same_vuzp2q_s16(<8 x i16> %a) { -; CHECK: test_same_vuzp2q_s16: +; CHECK-LABEL: test_same_vuzp2q_s16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1183,7 +1180,7 @@ entry: } define <4 x i32> @test_same_vuzp2q_s32(<4 x i32> %a) { -; CHECK: test_same_vuzp2q_s32: +; CHECK-LABEL: test_same_vuzp2q_s32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1191,7 +1188,7 @@ entry: } define <8 x i8> @test_same_vuzp2_u8(<8 x i8> %a) { -; CHECK: test_same_vuzp2_u8: +; CHECK-LABEL: test_same_vuzp2_u8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1199,7 +1196,7 @@ entry: } define <16 x i8> @test_same_vuzp2q_u8(<16 x i8> %a) { -; CHECK: test_same_vuzp2q_u8: +; CHECK-LABEL: test_same_vuzp2q_u8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -1207,7 +1204,7 @@ entry: } define <4 x i16> @test_same_vuzp2_u16(<4 x i16> %a) { -; CHECK: test_same_vuzp2_u16: +; CHECK-LABEL: test_same_vuzp2_u16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1215,7 +1212,7 @@ entry: } define <8 x i16> @test_same_vuzp2q_u16(<8 x i16> %a) { -; CHECK: test_same_vuzp2q_u16: +; CHECK-LABEL: test_same_vuzp2q_u16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1223,7 +1220,7 @@ entry: } define <4 x i32> @test_same_vuzp2q_u32(<4 x i32> %a) { -; CHECK: test_same_vuzp2q_u32: +; CHECK-LABEL: test_same_vuzp2q_u32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1231,7 +1228,7 @@ entry: } define <4 x float> @test_same_vuzp2q_f32(<4 x float> %a) { -; CHECK: test_same_vuzp2q_f32: +; CHECK-LABEL: test_same_vuzp2q_f32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1239,7 +1236,7 @@ entry: } define <8 x i8> @test_same_vuzp2_p8(<8 x i8> %a) { -; CHECK: test_same_vuzp2_p8: +; CHECK-LABEL: test_same_vuzp2_p8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1247,7 +1244,7 @@ entry: } define <16 x i8> @test_same_vuzp2q_p8(<16 x i8> %a) { -; CHECK: test_same_vuzp2q_p8: +; CHECK-LABEL: test_same_vuzp2q_p8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -1255,7 +1252,7 @@ entry: } define <4 x i16> @test_same_vuzp2_p16(<4 x i16> %a) { -; CHECK: test_same_vuzp2_p16: +; CHECK-LABEL: test_same_vuzp2_p16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1263,7 +1260,7 @@ entry: } define <8 x i16> @test_same_vuzp2q_p16(<8 x i16> %a) { -; CHECK: test_same_vuzp2q_p16: +; CHECK-LABEL: test_same_vuzp2q_p16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1271,7 +1268,7 @@ entry: } define <8 x i8> @test_same_vzip1_s8(<8 x i8> %a) { -; CHECK: test_same_vzip1_s8: +; CHECK-LABEL: test_same_vzip1_s8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -1279,7 +1276,7 @@ entry: } define <16 x i8> @test_same_vzip1q_s8(<16 x i8> %a) { -; CHECK: test_same_vzip1q_s8: +; CHECK-LABEL: test_same_vzip1q_s8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -1287,7 +1284,7 @@ entry: } define <4 x i16> @test_same_vzip1_s16(<4 x i16> %a) { -; CHECK: test_same_vzip1_s16: +; CHECK-LABEL: test_same_vzip1_s16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -1295,7 +1292,7 @@ entry: } define <8 x i16> @test_same_vzip1q_s16(<8 x i16> %a) { -; CHECK: test_same_vzip1q_s16: +; CHECK-LABEL: test_same_vzip1q_s16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -1303,7 +1300,7 @@ entry: } define <4 x i32> @test_same_vzip1q_s32(<4 x i32> %a) { -; CHECK: test_same_vzip1q_s32: +; CHECK-LABEL: test_same_vzip1q_s32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -1311,7 +1308,7 @@ entry: } define <8 x i8> @test_same_vzip1_u8(<8 x i8> %a) { -; CHECK: test_same_vzip1_u8: +; CHECK-LABEL: test_same_vzip1_u8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -1319,7 +1316,7 @@ entry: } define <16 x i8> @test_same_vzip1q_u8(<16 x i8> %a) { -; CHECK: test_same_vzip1q_u8: +; CHECK-LABEL: test_same_vzip1q_u8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -1327,7 +1324,7 @@ entry: } define <4 x i16> @test_same_vzip1_u16(<4 x i16> %a) { -; CHECK: test_same_vzip1_u16: +; CHECK-LABEL: test_same_vzip1_u16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -1335,7 +1332,7 @@ entry: } define <8 x i16> @test_same_vzip1q_u16(<8 x i16> %a) { -; CHECK: test_same_vzip1q_u16: +; CHECK-LABEL: test_same_vzip1q_u16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -1343,7 +1340,7 @@ entry: } define <4 x i32> @test_same_vzip1q_u32(<4 x i32> %a) { -; CHECK: test_same_vzip1q_u32: +; CHECK-LABEL: test_same_vzip1q_u32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -1351,7 +1348,7 @@ entry: } define <4 x float> @test_same_vzip1q_f32(<4 x float> %a) { -; CHECK: test_same_vzip1q_f32: +; CHECK-LABEL: test_same_vzip1q_f32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -1359,7 +1356,7 @@ entry: } define <8 x i8> @test_same_vzip1_p8(<8 x i8> %a) { -; CHECK: test_same_vzip1_p8: +; CHECK-LABEL: test_same_vzip1_p8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -1367,7 +1364,7 @@ entry: } define <16 x i8> @test_same_vzip1q_p8(<16 x i8> %a) { -; CHECK: test_same_vzip1q_p8: +; CHECK-LABEL: test_same_vzip1q_p8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -1375,7 +1372,7 @@ entry: } define <4 x i16> @test_same_vzip1_p16(<4 x i16> %a) { -; CHECK: test_same_vzip1_p16: +; CHECK-LABEL: test_same_vzip1_p16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -1383,7 +1380,7 @@ entry: } define <8 x i16> @test_same_vzip1q_p16(<8 x i16> %a) { -; CHECK: test_same_vzip1q_p16: +; CHECK-LABEL: test_same_vzip1q_p16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -1391,7 +1388,7 @@ entry: } define <8 x i8> @test_same_vzip2_s8(<8 x i8> %a) { -; CHECK: test_same_vzip2_s8: +; CHECK-LABEL: test_same_vzip2_s8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -1399,7 +1396,7 @@ entry: } define <16 x i8> @test_same_vzip2q_s8(<16 x i8> %a) { -; CHECK: test_same_vzip2q_s8: +; CHECK-LABEL: test_same_vzip2q_s8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -1407,7 +1404,7 @@ entry: } define <4 x i16> @test_same_vzip2_s16(<4 x i16> %a) { -; CHECK: test_same_vzip2_s16: +; CHECK-LABEL: test_same_vzip2_s16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -1415,7 +1412,7 @@ entry: } define <8 x i16> @test_same_vzip2q_s16(<8 x i16> %a) { -; CHECK: test_same_vzip2q_s16: +; CHECK-LABEL: test_same_vzip2q_s16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -1423,7 +1420,7 @@ entry: } define <4 x i32> @test_same_vzip2q_s32(<4 x i32> %a) { -; CHECK: test_same_vzip2q_s32: +; CHECK-LABEL: test_same_vzip2q_s32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -1431,7 +1428,7 @@ entry: } define <8 x i8> @test_same_vzip2_u8(<8 x i8> %a) { -; CHECK: test_same_vzip2_u8: +; CHECK-LABEL: test_same_vzip2_u8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -1439,7 +1436,7 @@ entry: } define <16 x i8> @test_same_vzip2q_u8(<16 x i8> %a) { -; CHECK: test_same_vzip2q_u8: +; CHECK-LABEL: test_same_vzip2q_u8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -1447,7 +1444,7 @@ entry: } define <4 x i16> @test_same_vzip2_u16(<4 x i16> %a) { -; CHECK: test_same_vzip2_u16: +; CHECK-LABEL: test_same_vzip2_u16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -1455,7 +1452,7 @@ entry: } define <8 x i16> @test_same_vzip2q_u16(<8 x i16> %a) { -; CHECK: test_same_vzip2q_u16: +; CHECK-LABEL: test_same_vzip2q_u16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -1463,7 +1460,7 @@ entry: } define <4 x i32> @test_same_vzip2q_u32(<4 x i32> %a) { -; CHECK: test_same_vzip2q_u32: +; CHECK-LABEL: test_same_vzip2q_u32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -1471,7 +1468,7 @@ entry: } define <4 x float> @test_same_vzip2q_f32(<4 x float> %a) { -; CHECK: test_same_vzip2q_f32: +; CHECK-LABEL: test_same_vzip2q_f32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -1479,7 +1476,7 @@ entry: } define <8 x i8> @test_same_vzip2_p8(<8 x i8> %a) { -; CHECK: test_same_vzip2_p8: +; CHECK-LABEL: test_same_vzip2_p8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -1487,7 +1484,7 @@ entry: } define <16 x i8> @test_same_vzip2q_p8(<16 x i8> %a) { -; CHECK: test_same_vzip2q_p8: +; CHECK-LABEL: test_same_vzip2q_p8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -1495,7 +1492,7 @@ entry: } define <4 x i16> @test_same_vzip2_p16(<4 x i16> %a) { -; CHECK: test_same_vzip2_p16: +; CHECK-LABEL: test_same_vzip2_p16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -1503,7 +1500,7 @@ entry: } define <8 x i16> @test_same_vzip2q_p16(<8 x i16> %a) { -; CHECK: test_same_vzip2q_p16: +; CHECK-LABEL: test_same_vzip2q_p16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -1511,7 +1508,7 @@ entry: } define <8 x i8> @test_same_vtrn1_s8(<8 x i8> %a) { -; CHECK: test_same_vtrn1_s8: +; CHECK-LABEL: test_same_vtrn1_s8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -1519,7 +1516,7 @@ entry: } define <16 x i8> @test_same_vtrn1q_s8(<16 x i8> %a) { -; CHECK: test_same_vtrn1q_s8: +; CHECK-LABEL: test_same_vtrn1q_s8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -1527,7 +1524,7 @@ entry: } define <4 x i16> @test_same_vtrn1_s16(<4 x i16> %a) { -; CHECK: test_same_vtrn1_s16: +; CHECK-LABEL: test_same_vtrn1_s16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -1535,7 +1532,7 @@ entry: } define <8 x i16> @test_same_vtrn1q_s16(<8 x i16> %a) { -; CHECK: test_same_vtrn1q_s16: +; CHECK-LABEL: test_same_vtrn1q_s16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -1543,7 +1540,7 @@ entry: } define <4 x i32> @test_same_vtrn1q_s32(<4 x i32> %a) { -; CHECK: test_same_vtrn1q_s32: +; CHECK-LABEL: test_same_vtrn1q_s32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -1551,7 +1548,7 @@ entry: } define <8 x i8> @test_same_vtrn1_u8(<8 x i8> %a) { -; CHECK: test_same_vtrn1_u8: +; CHECK-LABEL: test_same_vtrn1_u8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -1559,7 +1556,7 @@ entry: } define <16 x i8> @test_same_vtrn1q_u8(<16 x i8> %a) { -; CHECK: test_same_vtrn1q_u8: +; CHECK-LABEL: test_same_vtrn1q_u8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -1567,7 +1564,7 @@ entry: } define <4 x i16> @test_same_vtrn1_u16(<4 x i16> %a) { -; CHECK: test_same_vtrn1_u16: +; CHECK-LABEL: test_same_vtrn1_u16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -1575,7 +1572,7 @@ entry: } define <8 x i16> @test_same_vtrn1q_u16(<8 x i16> %a) { -; CHECK: test_same_vtrn1q_u16: +; CHECK-LABEL: test_same_vtrn1q_u16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -1583,7 +1580,7 @@ entry: } define <4 x i32> @test_same_vtrn1q_u32(<4 x i32> %a) { -; CHECK: test_same_vtrn1q_u32: +; CHECK-LABEL: test_same_vtrn1q_u32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -1591,7 +1588,7 @@ entry: } define <4 x float> @test_same_vtrn1q_f32(<4 x float> %a) { -; CHECK: test_same_vtrn1q_f32: +; CHECK-LABEL: test_same_vtrn1q_f32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -1599,7 +1596,7 @@ entry: } define <8 x i8> @test_same_vtrn1_p8(<8 x i8> %a) { -; CHECK: test_same_vtrn1_p8: +; CHECK-LABEL: test_same_vtrn1_p8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -1607,7 +1604,7 @@ entry: } define <16 x i8> @test_same_vtrn1q_p8(<16 x i8> %a) { -; CHECK: test_same_vtrn1q_p8: +; CHECK-LABEL: test_same_vtrn1q_p8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -1615,7 +1612,7 @@ entry: } define <4 x i16> @test_same_vtrn1_p16(<4 x i16> %a) { -; CHECK: test_same_vtrn1_p16: +; CHECK-LABEL: test_same_vtrn1_p16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -1623,7 +1620,7 @@ entry: } define <8 x i16> @test_same_vtrn1q_p16(<8 x i16> %a) { -; CHECK: test_same_vtrn1q_p16: +; CHECK-LABEL: test_same_vtrn1q_p16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -1631,7 +1628,7 @@ entry: } define <8 x i8> @test_same_vtrn2_s8(<8 x i8> %a) { -; CHECK: test_same_vtrn2_s8: +; CHECK-LABEL: test_same_vtrn2_s8: ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -1639,7 +1636,7 @@ entry: } define <16 x i8> @test_same_vtrn2q_s8(<16 x i8> %a) { -; CHECK: test_same_vtrn2q_s8: +; CHECK-LABEL: test_same_vtrn2q_s8: ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -1647,7 +1644,7 @@ entry: } define <4 x i16> @test_same_vtrn2_s16(<4 x i16> %a) { -; CHECK: test_same_vtrn2_s16: +; CHECK-LABEL: test_same_vtrn2_s16: ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -1655,7 +1652,7 @@ entry: } define <8 x i16> @test_same_vtrn2q_s16(<8 x i16> %a) { -; CHECK: test_same_vtrn2q_s16: +; CHECK-LABEL: test_same_vtrn2q_s16: ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -1663,7 +1660,7 @@ entry: } define <4 x i32> @test_same_vtrn2q_s32(<4 x i32> %a) { -; CHECK: test_same_vtrn2q_s32: +; CHECK-LABEL: test_same_vtrn2q_s32: ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -1671,7 +1668,7 @@ entry: } define <8 x i8> @test_same_vtrn2_u8(<8 x i8> %a) { -; CHECK: test_same_vtrn2_u8: +; CHECK-LABEL: test_same_vtrn2_u8: ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -1679,7 +1676,7 @@ entry: } define <16 x i8> @test_same_vtrn2q_u8(<16 x i8> %a) { -; CHECK: test_same_vtrn2q_u8: +; CHECK-LABEL: test_same_vtrn2q_u8: ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -1687,7 +1684,7 @@ entry: } define <4 x i16> @test_same_vtrn2_u16(<4 x i16> %a) { -; CHECK: test_same_vtrn2_u16: +; CHECK-LABEL: test_same_vtrn2_u16: ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -1695,7 +1692,7 @@ entry: } define <8 x i16> @test_same_vtrn2q_u16(<8 x i16> %a) { -; CHECK: test_same_vtrn2q_u16: +; CHECK-LABEL: test_same_vtrn2q_u16: ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -1703,7 +1700,7 @@ entry: } define <4 x i32> @test_same_vtrn2q_u32(<4 x i32> %a) { -; CHECK: test_same_vtrn2q_u32: +; CHECK-LABEL: test_same_vtrn2q_u32: ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> %a, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -1711,7 +1708,7 @@ entry: } define <4 x float> @test_same_vtrn2q_f32(<4 x float> %a) { -; CHECK: test_same_vtrn2q_f32: +; CHECK-LABEL: test_same_vtrn2q_f32: ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> %a, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -1719,7 +1716,7 @@ entry: } define <8 x i8> @test_same_vtrn2_p8(<8 x i8> %a) { -; CHECK: test_same_vtrn2_p8: +; CHECK-LABEL: test_same_vtrn2_p8: ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> %a, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -1727,7 +1724,7 @@ entry: } define <16 x i8> @test_same_vtrn2q_p8(<16 x i8> %a) { -; CHECK: test_same_vtrn2q_p8: +; CHECK-LABEL: test_same_vtrn2q_p8: ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> %a, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -1735,7 +1732,7 @@ entry: } define <4 x i16> @test_same_vtrn2_p16(<4 x i16> %a) { -; CHECK: test_same_vtrn2_p16: +; CHECK-LABEL: test_same_vtrn2_p16: ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> %a, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -1743,7 +1740,7 @@ entry: } define <8 x i16> @test_same_vtrn2q_p16(<8 x i16> %a) { -; CHECK: test_same_vtrn2q_p16: +; CHECK-LABEL: test_same_vtrn2q_p16: ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> %a, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -1752,7 +1749,7 @@ entry: define <8 x i8> @test_undef_vuzp1_s8(<8 x i8> %a) { -; CHECK: test_undef_vuzp1_s8: +; CHECK-LABEL: test_undef_vuzp1_s8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1760,7 +1757,7 @@ entry: } define <16 x i8> @test_undef_vuzp1q_s8(<16 x i8> %a) { -; CHECK: test_undef_vuzp1q_s8: +; CHECK-LABEL: test_undef_vuzp1q_s8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -1768,7 +1765,7 @@ entry: } define <4 x i16> @test_undef_vuzp1_s16(<4 x i16> %a) { -; CHECK: test_undef_vuzp1_s16: +; CHECK-LABEL: test_undef_vuzp1_s16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1776,7 +1773,7 @@ entry: } define <8 x i16> @test_undef_vuzp1q_s16(<8 x i16> %a) { -; CHECK: test_undef_vuzp1q_s16: +; CHECK-LABEL: test_undef_vuzp1q_s16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1784,7 +1781,7 @@ entry: } define <4 x i32> @test_undef_vuzp1q_s32(<4 x i32> %a) { -; CHECK: test_undef_vuzp1q_s32: +; CHECK-LABEL: test_undef_vuzp1q_s32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1792,7 +1789,7 @@ entry: } define <8 x i8> @test_undef_vuzp1_u8(<8 x i8> %a) { -; CHECK: test_undef_vuzp1_u8: +; CHECK-LABEL: test_undef_vuzp1_u8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1800,7 +1797,7 @@ entry: } define <16 x i8> @test_undef_vuzp1q_u8(<16 x i8> %a) { -; CHECK: test_undef_vuzp1q_u8: +; CHECK-LABEL: test_undef_vuzp1q_u8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -1808,7 +1805,7 @@ entry: } define <4 x i16> @test_undef_vuzp1_u16(<4 x i16> %a) { -; CHECK: test_undef_vuzp1_u16: +; CHECK-LABEL: test_undef_vuzp1_u16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1816,7 +1813,7 @@ entry: } define <8 x i16> @test_undef_vuzp1q_u16(<8 x i16> %a) { -; CHECK: test_undef_vuzp1q_u16: +; CHECK-LABEL: test_undef_vuzp1q_u16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1824,7 +1821,7 @@ entry: } define <4 x i32> @test_undef_vuzp1q_u32(<4 x i32> %a) { -; CHECK: test_undef_vuzp1q_u32: +; CHECK-LABEL: test_undef_vuzp1q_u32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1832,7 +1829,7 @@ entry: } define <4 x float> @test_undef_vuzp1q_f32(<4 x float> %a) { -; CHECK: test_undef_vuzp1q_f32: +; CHECK-LABEL: test_undef_vuzp1q_f32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1840,7 +1837,7 @@ entry: } define <8 x i8> @test_undef_vuzp1_p8(<8 x i8> %a) { -; CHECK: test_undef_vuzp1_p8: +; CHECK-LABEL: test_undef_vuzp1_p8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1848,7 +1845,7 @@ entry: } define <16 x i8> @test_undef_vuzp1q_p8(<16 x i8> %a) { -; CHECK: test_undef_vuzp1q_p8: +; CHECK-LABEL: test_undef_vuzp1q_p8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> @@ -1856,7 +1853,7 @@ entry: } define <4 x i16> @test_undef_vuzp1_p16(<4 x i16> %a) { -; CHECK: test_undef_vuzp1_p16: +; CHECK-LABEL: test_undef_vuzp1_p16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 2, i32 4, i32 6> @@ -1864,7 +1861,7 @@ entry: } define <8 x i16> @test_undef_vuzp1q_p16(<8 x i16> %a) { -; CHECK: test_undef_vuzp1q_p16: +; CHECK-LABEL: test_undef_vuzp1q_p16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> @@ -1872,7 +1869,7 @@ entry: } define <8 x i8> @test_undef_vuzp2_s8(<8 x i8> %a) { -; CHECK: test_undef_vuzp2_s8: +; CHECK-LABEL: test_undef_vuzp2_s8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1880,7 +1877,7 @@ entry: } define <16 x i8> @test_undef_vuzp2q_s8(<16 x i8> %a) { -; CHECK: test_undef_vuzp2q_s8: +; CHECK-LABEL: test_undef_vuzp2q_s8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -1888,7 +1885,7 @@ entry: } define <4 x i16> @test_undef_vuzp2_s16(<4 x i16> %a) { -; CHECK: test_undef_vuzp2_s16: +; CHECK-LABEL: test_undef_vuzp2_s16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1896,7 +1893,7 @@ entry: } define <8 x i16> @test_undef_vuzp2q_s16(<8 x i16> %a) { -; CHECK: test_undef_vuzp2q_s16: +; CHECK-LABEL: test_undef_vuzp2q_s16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1904,7 +1901,7 @@ entry: } define <4 x i32> @test_undef_vuzp2q_s32(<4 x i32> %a) { -; CHECK: test_undef_vuzp2q_s32: +; CHECK-LABEL: test_undef_vuzp2q_s32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1912,7 +1909,7 @@ entry: } define <8 x i8> @test_undef_vuzp2_u8(<8 x i8> %a) { -; CHECK: test_undef_vuzp2_u8: +; CHECK-LABEL: test_undef_vuzp2_u8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1920,7 +1917,7 @@ entry: } define <16 x i8> @test_undef_vuzp2q_u8(<16 x i8> %a) { -; CHECK: test_undef_vuzp2q_u8: +; CHECK-LABEL: test_undef_vuzp2q_u8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -1928,7 +1925,7 @@ entry: } define <4 x i16> @test_undef_vuzp2_u16(<4 x i16> %a) { -; CHECK: test_undef_vuzp2_u16: +; CHECK-LABEL: test_undef_vuzp2_u16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1936,7 +1933,7 @@ entry: } define <8 x i16> @test_undef_vuzp2q_u16(<8 x i16> %a) { -; CHECK: test_undef_vuzp2q_u16: +; CHECK-LABEL: test_undef_vuzp2q_u16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1944,7 +1941,7 @@ entry: } define <4 x i32> @test_undef_vuzp2q_u32(<4 x i32> %a) { -; CHECK: test_undef_vuzp2q_u32: +; CHECK-LABEL: test_undef_vuzp2q_u32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1952,7 +1949,7 @@ entry: } define <4 x float> @test_undef_vuzp2q_f32(<4 x float> %a) { -; CHECK: test_undef_vuzp2q_f32: +; CHECK-LABEL: test_undef_vuzp2q_f32: ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1960,7 +1957,7 @@ entry: } define <8 x i8> @test_undef_vuzp2_p8(<8 x i8> %a) { -; CHECK: test_undef_vuzp2_p8: +; CHECK-LABEL: test_undef_vuzp2_p8: ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1968,7 +1965,7 @@ entry: } define <16 x i8> @test_undef_vuzp2q_p8(<16 x i8> %a) { -; CHECK: test_undef_vuzp2q_p8: +; CHECK-LABEL: test_undef_vuzp2q_p8: ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31> @@ -1976,7 +1973,7 @@ entry: } define <4 x i16> @test_undef_vuzp2_p16(<4 x i16> %a) { -; CHECK: test_undef_vuzp2_p16: +; CHECK-LABEL: test_undef_vuzp2_p16: ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7> @@ -1984,7 +1981,7 @@ entry: } define <8 x i16> @test_undef_vuzp2q_p16(<8 x i16> %a) { -; CHECK: test_undef_vuzp2q_p16: +; CHECK-LABEL: test_undef_vuzp2q_p16: ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -1992,7 +1989,7 @@ entry: } define <8 x i8> @test_undef_vzip1_s8(<8 x i8> %a) { -; CHECK: test_undef_vzip1_s8: +; CHECK-LABEL: test_undef_vzip1_s8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -2000,7 +1997,7 @@ entry: } define <16 x i8> @test_undef_vzip1q_s8(<16 x i8> %a) { -; CHECK: test_undef_vzip1q_s8: +; CHECK-LABEL: test_undef_vzip1q_s8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -2008,7 +2005,7 @@ entry: } define <4 x i16> @test_undef_vzip1_s16(<4 x i16> %a) { -; CHECK: test_undef_vzip1_s16: +; CHECK-LABEL: test_undef_vzip1_s16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -2016,7 +2013,7 @@ entry: } define <8 x i16> @test_undef_vzip1q_s16(<8 x i16> %a) { -; CHECK: test_undef_vzip1q_s16: +; CHECK-LABEL: test_undef_vzip1q_s16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -2024,7 +2021,7 @@ entry: } define <4 x i32> @test_undef_vzip1q_s32(<4 x i32> %a) { -; CHECK: test_undef_vzip1q_s32: +; CHECK-LABEL: test_undef_vzip1q_s32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -2032,7 +2029,7 @@ entry: } define <8 x i8> @test_undef_vzip1_u8(<8 x i8> %a) { -; CHECK: test_undef_vzip1_u8: +; CHECK-LABEL: test_undef_vzip1_u8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -2040,7 +2037,7 @@ entry: } define <16 x i8> @test_undef_vzip1q_u8(<16 x i8> %a) { -; CHECK: test_undef_vzip1q_u8: +; CHECK-LABEL: test_undef_vzip1q_u8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -2048,7 +2045,7 @@ entry: } define <4 x i16> @test_undef_vzip1_u16(<4 x i16> %a) { -; CHECK: test_undef_vzip1_u16: +; CHECK-LABEL: test_undef_vzip1_u16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -2056,7 +2053,7 @@ entry: } define <8 x i16> @test_undef_vzip1q_u16(<8 x i16> %a) { -; CHECK: test_undef_vzip1q_u16: +; CHECK-LABEL: test_undef_vzip1q_u16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -2064,7 +2061,7 @@ entry: } define <4 x i32> @test_undef_vzip1q_u32(<4 x i32> %a) { -; CHECK: test_undef_vzip1q_u32: +; CHECK-LABEL: test_undef_vzip1q_u32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -2072,7 +2069,7 @@ entry: } define <4 x float> @test_undef_vzip1q_f32(<4 x float> %a) { -; CHECK: test_undef_vzip1q_f32: +; CHECK-LABEL: test_undef_vzip1q_f32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -2080,7 +2077,7 @@ entry: } define <8 x i8> @test_undef_vzip1_p8(<8 x i8> %a) { -; CHECK: test_undef_vzip1_p8: +; CHECK-LABEL: test_undef_vzip1_p8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -2088,7 +2085,7 @@ entry: } define <16 x i8> @test_undef_vzip1q_p8(<16 x i8> %a) { -; CHECK: test_undef_vzip1q_p8: +; CHECK-LABEL: test_undef_vzip1q_p8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> @@ -2096,7 +2093,7 @@ entry: } define <4 x i16> @test_undef_vzip1_p16(<4 x i16> %a) { -; CHECK: test_undef_vzip1_p16: +; CHECK-LABEL: test_undef_vzip1_p16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 4, i32 1, i32 5> @@ -2104,7 +2101,7 @@ entry: } define <8 x i16> @test_undef_vzip1q_p16(<8 x i16> %a) { -; CHECK: test_undef_vzip1q_p16: +; CHECK-LABEL: test_undef_vzip1q_p16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11> @@ -2112,7 +2109,7 @@ entry: } define <8 x i8> @test_undef_vzip2_s8(<8 x i8> %a) { -; CHECK: test_undef_vzip2_s8: +; CHECK-LABEL: test_undef_vzip2_s8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -2120,7 +2117,7 @@ entry: } define <16 x i8> @test_undef_vzip2q_s8(<16 x i8> %a) { -; CHECK: test_undef_vzip2q_s8: +; CHECK-LABEL: test_undef_vzip2q_s8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -2128,7 +2125,7 @@ entry: } define <4 x i16> @test_undef_vzip2_s16(<4 x i16> %a) { -; CHECK: test_undef_vzip2_s16: +; CHECK-LABEL: test_undef_vzip2_s16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -2136,7 +2133,7 @@ entry: } define <8 x i16> @test_undef_vzip2q_s16(<8 x i16> %a) { -; CHECK: test_undef_vzip2q_s16: +; CHECK-LABEL: test_undef_vzip2q_s16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -2144,7 +2141,7 @@ entry: } define <4 x i32> @test_undef_vzip2q_s32(<4 x i32> %a) { -; CHECK: test_undef_vzip2q_s32: +; CHECK-LABEL: test_undef_vzip2q_s32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -2152,7 +2149,7 @@ entry: } define <8 x i8> @test_undef_vzip2_u8(<8 x i8> %a) { -; CHECK: test_undef_vzip2_u8: +; CHECK-LABEL: test_undef_vzip2_u8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -2160,7 +2157,7 @@ entry: } define <16 x i8> @test_undef_vzip2q_u8(<16 x i8> %a) { -; CHECK: test_undef_vzip2q_u8: +; CHECK-LABEL: test_undef_vzip2q_u8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -2168,7 +2165,7 @@ entry: } define <4 x i16> @test_undef_vzip2_u16(<4 x i16> %a) { -; CHECK: test_undef_vzip2_u16: +; CHECK-LABEL: test_undef_vzip2_u16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -2176,7 +2173,7 @@ entry: } define <8 x i16> @test_undef_vzip2q_u16(<8 x i16> %a) { -; CHECK: test_undef_vzip2q_u16: +; CHECK-LABEL: test_undef_vzip2q_u16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -2184,7 +2181,7 @@ entry: } define <4 x i32> @test_undef_vzip2q_u32(<4 x i32> %a) { -; CHECK: test_undef_vzip2q_u32: +; CHECK-LABEL: test_undef_vzip2q_u32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -2192,7 +2189,7 @@ entry: } define <4 x float> @test_undef_vzip2q_f32(<4 x float> %a) { -; CHECK: test_undef_vzip2q_f32: +; CHECK-LABEL: test_undef_vzip2q_f32: ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -2200,7 +2197,7 @@ entry: } define <8 x i8> @test_undef_vzip2_p8(<8 x i8> %a) { -; CHECK: test_undef_vzip2_p8: +; CHECK-LABEL: test_undef_vzip2_p8: ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -2208,7 +2205,7 @@ entry: } define <16 x i8> @test_undef_vzip2q_p8(<16 x i8> %a) { -; CHECK: test_undef_vzip2q_p8: +; CHECK-LABEL: test_undef_vzip2q_p8: ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> @@ -2216,7 +2213,7 @@ entry: } define <4 x i16> @test_undef_vzip2_p16(<4 x i16> %a) { -; CHECK: test_undef_vzip2_p16: +; CHECK-LABEL: test_undef_vzip2_p16: ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 2, i32 6, i32 3, i32 7> @@ -2224,7 +2221,7 @@ entry: } define <8 x i16> @test_undef_vzip2q_p16(<8 x i16> %a) { -; CHECK: test_undef_vzip2q_p16: +; CHECK-LABEL: test_undef_vzip2q_p16: ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> @@ -2232,7 +2229,7 @@ entry: } define <8 x i8> @test_undef_vtrn1_s8(<8 x i8> %a) { -; CHECK: test_undef_vtrn1_s8: +; CHECK-LABEL: test_undef_vtrn1_s8: ; CHECK: ret entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -2240,7 +2237,7 @@ entry: } define <16 x i8> @test_undef_vtrn1q_s8(<16 x i8> %a) { -; CHECK: test_undef_vtrn1q_s8: +; CHECK-LABEL: test_undef_vtrn1q_s8: ; CHECK: ret entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -2248,7 +2245,7 @@ entry: } define <4 x i16> @test_undef_vtrn1_s16(<4 x i16> %a) { -; CHECK: test_undef_vtrn1_s16: +; CHECK-LABEL: test_undef_vtrn1_s16: ; CHECK: ret entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -2256,7 +2253,7 @@ entry: } define <8 x i16> @test_undef_vtrn1q_s16(<8 x i16> %a) { -; CHECK: test_undef_vtrn1q_s16: +; CHECK-LABEL: test_undef_vtrn1q_s16: ; CHECK: ret entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -2264,7 +2261,7 @@ entry: } define <4 x i32> @test_undef_vtrn1q_s32(<4 x i32> %a) { -; CHECK: test_undef_vtrn1q_s32: +; CHECK-LABEL: test_undef_vtrn1q_s32: ; CHECK: ret entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -2272,7 +2269,7 @@ entry: } define <8 x i8> @test_undef_vtrn1_u8(<8 x i8> %a) { -; CHECK: test_undef_vtrn1_u8: +; CHECK-LABEL: test_undef_vtrn1_u8: ; CHECK: ret entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -2280,7 +2277,7 @@ entry: } define <16 x i8> @test_undef_vtrn1q_u8(<16 x i8> %a) { -; CHECK: test_undef_vtrn1q_u8: +; CHECK-LABEL: test_undef_vtrn1q_u8: ; CHECK: ret entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -2288,7 +2285,7 @@ entry: } define <4 x i16> @test_undef_vtrn1_u16(<4 x i16> %a) { -; CHECK: test_undef_vtrn1_u16: +; CHECK-LABEL: test_undef_vtrn1_u16: ; CHECK: ret entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -2296,7 +2293,7 @@ entry: } define <8 x i16> @test_undef_vtrn1q_u16(<8 x i16> %a) { -; CHECK: test_undef_vtrn1q_u16: +; CHECK-LABEL: test_undef_vtrn1q_u16: ; CHECK: ret entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -2304,7 +2301,7 @@ entry: } define <4 x i32> @test_undef_vtrn1q_u32(<4 x i32> %a) { -; CHECK: test_undef_vtrn1q_u32: +; CHECK-LABEL: test_undef_vtrn1q_u32: ; CHECK: ret entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -2312,7 +2309,7 @@ entry: } define <4 x float> @test_undef_vtrn1q_f32(<4 x float> %a) { -; CHECK: test_undef_vtrn1q_f32: +; CHECK-LABEL: test_undef_vtrn1q_f32: ; CHECK: ret entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -2320,7 +2317,7 @@ entry: } define <8 x i8> @test_undef_vtrn1_p8(<8 x i8> %a) { -; CHECK: test_undef_vtrn1_p8: +; CHECK-LABEL: test_undef_vtrn1_p8: ; CHECK: ret entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -2328,7 +2325,7 @@ entry: } define <16 x i8> @test_undef_vtrn1q_p8(<16 x i8> %a) { -; CHECK: test_undef_vtrn1q_p8: +; CHECK-LABEL: test_undef_vtrn1q_p8: ; CHECK: ret entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> @@ -2336,7 +2333,7 @@ entry: } define <4 x i16> @test_undef_vtrn1_p16(<4 x i16> %a) { -; CHECK: test_undef_vtrn1_p16: +; CHECK-LABEL: test_undef_vtrn1_p16: ; CHECK: ret entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 0, i32 4, i32 2, i32 6> @@ -2344,7 +2341,7 @@ entry: } define <8 x i16> @test_undef_vtrn1q_p16(<8 x i16> %a) { -; CHECK: test_undef_vtrn1q_p16: +; CHECK-LABEL: test_undef_vtrn1q_p16: ; CHECK: ret entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 0, i32 8, i32 2, i32 10, i32 4, i32 12, i32 6, i32 14> @@ -2352,7 +2349,7 @@ entry: } define <8 x i8> @test_undef_vtrn2_s8(<8 x i8> %a) { -; CHECK: test_undef_vtrn2_s8: +; CHECK-LABEL: test_undef_vtrn2_s8: ; CHECK: rev16 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -2360,7 +2357,7 @@ entry: } define <16 x i8> @test_undef_vtrn2q_s8(<16 x i8> %a) { -; CHECK: test_undef_vtrn2q_s8: +; CHECK-LABEL: test_undef_vtrn2q_s8: ; CHECK: rev16 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -2368,7 +2365,7 @@ entry: } define <4 x i16> @test_undef_vtrn2_s16(<4 x i16> %a) { -; CHECK: test_undef_vtrn2_s16: +; CHECK-LABEL: test_undef_vtrn2_s16: ; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -2376,7 +2373,7 @@ entry: } define <8 x i16> @test_undef_vtrn2q_s16(<8 x i16> %a) { -; CHECK: test_undef_vtrn2q_s16: +; CHECK-LABEL: test_undef_vtrn2q_s16: ; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -2384,7 +2381,7 @@ entry: } define <4 x i32> @test_undef_vtrn2q_s32(<4 x i32> %a) { -; CHECK: test_undef_vtrn2q_s32: +; CHECK-LABEL: test_undef_vtrn2q_s32: ; CHECK: rev64 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -2392,7 +2389,7 @@ entry: } define <8 x i8> @test_undef_vtrn2_u8(<8 x i8> %a) { -; CHECK: test_undef_vtrn2_u8: +; CHECK-LABEL: test_undef_vtrn2_u8: ; CHECK: rev16 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -2400,7 +2397,7 @@ entry: } define <16 x i8> @test_undef_vtrn2q_u8(<16 x i8> %a) { -; CHECK: test_undef_vtrn2q_u8: +; CHECK-LABEL: test_undef_vtrn2q_u8: ; CHECK: rev16 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -2408,7 +2405,7 @@ entry: } define <4 x i16> @test_undef_vtrn2_u16(<4 x i16> %a) { -; CHECK: test_undef_vtrn2_u16: +; CHECK-LABEL: test_undef_vtrn2_u16: ; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -2416,7 +2413,7 @@ entry: } define <8 x i16> @test_undef_vtrn2q_u16(<8 x i16> %a) { -; CHECK: test_undef_vtrn2q_u16: +; CHECK-LABEL: test_undef_vtrn2q_u16: ; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -2424,7 +2421,7 @@ entry: } define <4 x i32> @test_undef_vtrn2q_u32(<4 x i32> %a) { -; CHECK: test_undef_vtrn2q_u32: +; CHECK-LABEL: test_undef_vtrn2q_u32: ; CHECK: rev64 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -2432,7 +2429,7 @@ entry: } define <4 x float> @test_undef_vtrn2q_f32(<4 x float> %a) { -; CHECK: test_undef_vtrn2q_f32: +; CHECK-LABEL: test_undef_vtrn2q_f32: ; CHECK: rev64 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: %shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -2440,7 +2437,7 @@ entry: } define <8 x i8> @test_undef_vtrn2_p8(<8 x i8> %a) { -; CHECK: test_undef_vtrn2_p8: +; CHECK-LABEL: test_undef_vtrn2_p8: ; CHECK: rev16 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: %shuffle.i = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -2448,7 +2445,7 @@ entry: } define <16 x i8> @test_undef_vtrn2q_p8(<16 x i8> %a) { -; CHECK: test_undef_vtrn2q_p8: +; CHECK-LABEL: test_undef_vtrn2q_p8: ; CHECK: rev16 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: %shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 1, i32 17, i32 3, i32 19, i32 5, i32 21, i32 7, i32 23, i32 9, i32 25, i32 11, i32 27, i32 13, i32 29, i32 15, i32 31> @@ -2456,7 +2453,7 @@ entry: } define <4 x i16> @test_undef_vtrn2_p16(<4 x i16> %a) { -; CHECK: test_undef_vtrn2_p16: +; CHECK-LABEL: test_undef_vtrn2_p16: ; CHECK: rev32 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: %shuffle.i = shufflevector <4 x i16> %a, <4 x i16> undef, <4 x i32> <i32 1, i32 5, i32 3, i32 7> @@ -2464,7 +2461,7 @@ entry: } define <8 x i16> @test_undef_vtrn2q_p16(<8 x i16> %a) { -; CHECK: test_undef_vtrn2q_p16: +; CHECK-LABEL: test_undef_vtrn2q_p16: ; CHECK: rev32 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: %shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <8 x i32> <i32 1, i32 9, i32 3, i32 11, i32 5, i32 13, i32 7, i32 15> @@ -2472,7 +2469,7 @@ entry: } define %struct.int8x8x2_t @test_vuzp_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp_s8: +; CHECK-LABEL: test_vuzp_s8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -2484,7 +2481,7 @@ entry: } define %struct.int16x4x2_t @test_vuzp_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp_s16: +; CHECK-LABEL: test_vuzp_s16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -2496,9 +2493,9 @@ entry: } define %struct.int32x2x2_t @test_vuzp_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vuzp_s32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vuzp_s32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vuzp.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> %vuzp1.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> @@ -2508,7 +2505,7 @@ entry: } define %struct.uint8x8x2_t @test_vuzp_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp_u8: +; CHECK-LABEL: test_vuzp_u8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -2520,7 +2517,7 @@ entry: } define %struct.uint16x4x2_t @test_vuzp_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp_u16: +; CHECK-LABEL: test_vuzp_u16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -2532,9 +2529,9 @@ entry: } define %struct.uint32x2x2_t @test_vuzp_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vuzp_u32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vuzp_u32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vuzp.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> %vuzp1.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> @@ -2544,9 +2541,9 @@ entry: } define %struct.float32x2x2_t @test_vuzp_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vuzp_f32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vuzp_f32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vuzp.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 0, i32 2> %vuzp1.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 3> @@ -2556,7 +2553,7 @@ entry: } define %struct.poly8x8x2_t @test_vuzp_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vuzp_p8: +; CHECK-LABEL: test_vuzp_p8: ; CHECK: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -2568,7 +2565,7 @@ entry: } define %struct.poly16x4x2_t @test_vuzp_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vuzp_p16: +; CHECK-LABEL: test_vuzp_p16: ; CHECK: uzp1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: uzp2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -2580,7 +2577,7 @@ entry: } define %struct.int8x16x2_t @test_vuzpq_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzpq_s8: +; CHECK-LABEL: test_vuzpq_s8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -2592,7 +2589,7 @@ entry: } define %struct.int16x8x2_t @test_vuzpq_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzpq_s16: +; CHECK-LABEL: test_vuzpq_s16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -2604,7 +2601,7 @@ entry: } define %struct.int32x4x2_t @test_vuzpq_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vuzpq_s32: +; CHECK-LABEL: test_vuzpq_s32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -2616,7 +2613,7 @@ entry: } define %struct.uint8x16x2_t @test_vuzpq_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzpq_u8: +; CHECK-LABEL: test_vuzpq_u8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -2628,7 +2625,7 @@ entry: } define %struct.uint16x8x2_t @test_vuzpq_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzpq_u16: +; CHECK-LABEL: test_vuzpq_u16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -2640,7 +2637,7 @@ entry: } define %struct.uint32x4x2_t @test_vuzpq_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vuzpq_u32: +; CHECK-LABEL: test_vuzpq_u32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -2652,7 +2649,7 @@ entry: } define %struct.float32x4x2_t @test_vuzpq_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vuzpq_f32: +; CHECK-LABEL: test_vuzpq_f32: ; CHECK: uzp1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: uzp2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -2664,7 +2661,7 @@ entry: } define %struct.poly8x16x2_t @test_vuzpq_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vuzpq_p8: +; CHECK-LABEL: test_vuzpq_p8: ; CHECK: uzp1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: uzp2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -2676,7 +2673,7 @@ entry: } define %struct.poly16x8x2_t @test_vuzpq_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vuzpq_p16: +; CHECK-LABEL: test_vuzpq_p16: ; CHECK: uzp1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: uzp2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -2688,7 +2685,7 @@ entry: } define %struct.int8x8x2_t @test_vzip_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip_s8: +; CHECK-LABEL: test_vzip_s8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -2700,7 +2697,7 @@ entry: } define %struct.int16x4x2_t @test_vzip_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip_s16: +; CHECK-LABEL: test_vzip_s16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -2712,9 +2709,9 @@ entry: } define %struct.int32x2x2_t @test_vzip_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vzip_s32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vzip_s32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vzip.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> %vzip1.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> @@ -2724,7 +2721,7 @@ entry: } define %struct.uint8x8x2_t @test_vzip_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip_u8: +; CHECK-LABEL: test_vzip_u8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -2736,7 +2733,7 @@ entry: } define %struct.uint16x4x2_t @test_vzip_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip_u16: +; CHECK-LABEL: test_vzip_u16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -2748,9 +2745,9 @@ entry: } define %struct.uint32x2x2_t @test_vzip_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vzip_u32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vzip_u32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vzip.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> %vzip1.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> @@ -2760,9 +2757,9 @@ entry: } define %struct.float32x2x2_t @test_vzip_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vzip_f32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vzip_f32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vzip.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 0, i32 2> %vzip1.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 3> @@ -2772,7 +2769,7 @@ entry: } define %struct.poly8x8x2_t @test_vzip_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vzip_p8: +; CHECK-LABEL: test_vzip_p8: ; CHECK: zip1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: zip2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -2784,7 +2781,7 @@ entry: } define %struct.poly16x4x2_t @test_vzip_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vzip_p16: +; CHECK-LABEL: test_vzip_p16: ; CHECK: zip1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: zip2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -2796,7 +2793,7 @@ entry: } define %struct.int8x16x2_t @test_vzipq_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzipq_s8: +; CHECK-LABEL: test_vzipq_s8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -2808,7 +2805,7 @@ entry: } define %struct.int16x8x2_t @test_vzipq_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzipq_s16: +; CHECK-LABEL: test_vzipq_s16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -2820,7 +2817,7 @@ entry: } define %struct.int32x4x2_t @test_vzipq_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vzipq_s32: +; CHECK-LABEL: test_vzipq_s32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -2832,7 +2829,7 @@ entry: } define %struct.uint8x16x2_t @test_vzipq_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzipq_u8: +; CHECK-LABEL: test_vzipq_u8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -2844,7 +2841,7 @@ entry: } define %struct.uint16x8x2_t @test_vzipq_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzipq_u16: +; CHECK-LABEL: test_vzipq_u16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -2856,7 +2853,7 @@ entry: } define %struct.uint32x4x2_t @test_vzipq_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vzipq_u32: +; CHECK-LABEL: test_vzipq_u32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -2868,7 +2865,7 @@ entry: } define %struct.float32x4x2_t @test_vzipq_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vzipq_f32: +; CHECK-LABEL: test_vzipq_f32: ; CHECK: zip1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: zip2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -2880,7 +2877,7 @@ entry: } define %struct.poly8x16x2_t @test_vzipq_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vzipq_p8: +; CHECK-LABEL: test_vzipq_p8: ; CHECK: zip1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: zip2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -2892,7 +2889,7 @@ entry: } define %struct.poly16x8x2_t @test_vzipq_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vzipq_p16: +; CHECK-LABEL: test_vzipq_p16: ; CHECK: zip1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: zip2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -2904,7 +2901,7 @@ entry: } define %struct.int8x8x2_t @test_vtrn_s8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn_s8: +; CHECK-LABEL: test_vtrn_s8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -2916,7 +2913,7 @@ entry: } define %struct.int16x4x2_t @test_vtrn_s16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn_s16: +; CHECK-LABEL: test_vtrn_s16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -2928,9 +2925,9 @@ entry: } define %struct.int32x2x2_t @test_vtrn_s32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vtrn_s32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vtrn_s32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vtrn.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> %vtrn1.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> @@ -2940,7 +2937,7 @@ entry: } define %struct.uint8x8x2_t @test_vtrn_u8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn_u8: +; CHECK-LABEL: test_vtrn_u8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -2952,7 +2949,7 @@ entry: } define %struct.uint16x4x2_t @test_vtrn_u16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn_u16: +; CHECK-LABEL: test_vtrn_u16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -2964,9 +2961,9 @@ entry: } define %struct.uint32x2x2_t @test_vtrn_u32(<2 x i32> %a, <2 x i32> %b) { -; CHECK: test_vtrn_u32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vtrn_u32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vtrn.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 0, i32 2> %vtrn1.i = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3> @@ -2976,9 +2973,9 @@ entry: } define %struct.float32x2x2_t @test_vtrn_f32(<2 x float> %a, <2 x float> %b) { -; CHECK: test_vtrn_f32: -; CHECK: ins {{v[0-9]+}}.s[1], {{v[0-9]+}}.s[0] -; CHECK: ins {{v[0-9]+}}.s[0], {{v[0-9]+}}.s[1] +; CHECK-LABEL: test_vtrn_f32: +; CHECK: zip1 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s +; CHECK: zip2 {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s entry: %vtrn.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 0, i32 2> %vtrn1.i = shufflevector <2 x float> %a, <2 x float> %b, <2 x i32> <i32 1, i32 3> @@ -2988,7 +2985,7 @@ entry: } define %struct.poly8x8x2_t @test_vtrn_p8(<8 x i8> %a, <8 x i8> %b) { -; CHECK: test_vtrn_p8: +; CHECK-LABEL: test_vtrn_p8: ; CHECK: trn1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b ; CHECK: trn2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b entry: @@ -3000,7 +2997,7 @@ entry: } define %struct.poly16x4x2_t @test_vtrn_p16(<4 x i16> %a, <4 x i16> %b) { -; CHECK: test_vtrn_p16: +; CHECK-LABEL: test_vtrn_p16: ; CHECK: trn1 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h ; CHECK: trn2 {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h entry: @@ -3012,7 +3009,7 @@ entry: } define %struct.int8x16x2_t @test_vtrnq_s8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrnq_s8: +; CHECK-LABEL: test_vtrnq_s8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -3024,7 +3021,7 @@ entry: } define %struct.int16x8x2_t @test_vtrnq_s16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrnq_s16: +; CHECK-LABEL: test_vtrnq_s16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -3036,7 +3033,7 @@ entry: } define %struct.int32x4x2_t @test_vtrnq_s32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vtrnq_s32: +; CHECK-LABEL: test_vtrnq_s32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -3048,7 +3045,7 @@ entry: } define %struct.uint8x16x2_t @test_vtrnq_u8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrnq_u8: +; CHECK-LABEL: test_vtrnq_u8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -3060,7 +3057,7 @@ entry: } define %struct.uint16x8x2_t @test_vtrnq_u16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrnq_u16: +; CHECK-LABEL: test_vtrnq_u16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -3072,7 +3069,7 @@ entry: } define %struct.uint32x4x2_t @test_vtrnq_u32(<4 x i32> %a, <4 x i32> %b) { -; CHECK: test_vtrnq_u32: +; CHECK-LABEL: test_vtrnq_u32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -3084,7 +3081,7 @@ entry: } define %struct.float32x4x2_t @test_vtrnq_f32(<4 x float> %a, <4 x float> %b) { -; CHECK: test_vtrnq_f32: +; CHECK-LABEL: test_vtrnq_f32: ; CHECK: trn1 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s ; CHECK: trn2 {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s entry: @@ -3096,7 +3093,7 @@ entry: } define %struct.poly8x16x2_t @test_vtrnq_p8(<16 x i8> %a, <16 x i8> %b) { -; CHECK: test_vtrnq_p8: +; CHECK-LABEL: test_vtrnq_p8: ; CHECK: trn1 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b ; CHECK: trn2 {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b entry: @@ -3108,7 +3105,7 @@ entry: } define %struct.poly16x8x2_t @test_vtrnq_p16(<8 x i16> %a, <8 x i16> %b) { -; CHECK: test_vtrnq_p16: +; CHECK-LABEL: test_vtrnq_p16: ; CHECK: trn1 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h ; CHECK: trn2 {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h entry: @@ -3120,7 +3117,7 @@ entry: } define %struct.uint8x8x2_t @test_uzp(<16 x i8> %y) { -; CHECK: test_uzp: +; CHECK-LABEL: test_uzp: %vuzp.i = shufflevector <16 x i8> %y, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> %vuzp1.i = shufflevector <16 x i8> %y, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> @@ -3128,7 +3125,4 @@ define %struct.uint8x8x2_t @test_uzp(<16 x i8> %y) { %.fca.0.1.insert = insertvalue %struct.uint8x8x2_t %.fca.0.0.insert, <8 x i8> %vuzp1.i, 0, 1 ret %struct.uint8x8x2_t %.fca.0.1.insert -; CHECK: dup {{d[0-9]+}}, {{v[0-9]+}}.d[1] -; CHECK-NEXT: uzp1 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b -; CHECK-NEXT: uzp2 {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b } |