diff options
Diffstat (limited to 'test/CodeGen/AArch64/neon-scalar-compare.ll')
-rw-r--r-- | test/CodeGen/AArch64/neon-scalar-compare.ll | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/test/CodeGen/AArch64/neon-scalar-compare.ll b/test/CodeGen/AArch64/neon-scalar-compare.ll index 5f10cbb..e1f3964 100644 --- a/test/CodeGen/AArch64/neon-scalar-compare.ll +++ b/test/CodeGen/AArch64/neon-scalar-compare.ll @@ -122,28 +122,28 @@ entry: define <1 x i64> @test_vcage_f64(<1 x double> %a, <1 x double> %b) #0 { ; CHECK: test_vcage_f64 ; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}} - %vcage2.i = tail call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %a, <1 x double> %b) #2 + %vcage2.i = tail call <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double> %a, <1 x double> %b) #2 ret <1 x i64> %vcage2.i } define <1 x i64> @test_vcagt_f64(<1 x double> %a, <1 x double> %b) #0 { ; CHECK: test_vcagt_f64 ; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}} - %vcagt2.i = tail call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %a, <1 x double> %b) #2 + %vcagt2.i = tail call <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double> %a, <1 x double> %b) #2 ret <1 x i64> %vcagt2.i } define <1 x i64> @test_vcale_f64(<1 x double> %a, <1 x double> %b) #0 { ; CHECK: test_vcale_f64 ; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}} - %vcage2.i = tail call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %b, <1 x double> %a) #2 + %vcage2.i = tail call <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double> %b, <1 x double> %a) #2 ret <1 x i64> %vcage2.i } define <1 x i64> @test_vcalt_f64(<1 x double> %a, <1 x double> %b) #0 { ; CHECK: test_vcalt_f64 ; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}} - %vcagt2.i = tail call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %b, <1 x double> %a) #2 + %vcagt2.i = tail call <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double> %b, <1 x double> %a) #2 ret <1 x i64> %vcagt2.i } @@ -271,7 +271,7 @@ define <1 x i64> @test_vceqz_s64(<1 x i64> %a) #0 { ; CHECK: test_vceqz_s64 ; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0 %1 = icmp eq <1 x i64> %a, zeroinitializer - %vceqz.i = zext <1 x i1> %1 to <1 x i64> + %vceqz.i = sext <1 x i1> %1 to <1 x i64> ret <1 x i64> %vceqz.i } @@ -279,7 +279,7 @@ define <1 x i64> @test_vceqz_u64(<1 x i64> %a) #0 { ; CHECK: test_vceqz_u64 ; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0 %1 = icmp eq <1 x i64> %a, zeroinitializer - %vceqz.i = zext <1 x i1> %1 to <1 x i64> + %vceqz.i = sext <1 x i1> %1 to <1 x i64> ret <1 x i64> %vceqz.i } @@ -287,7 +287,7 @@ define <1 x i64> @test_vceqz_p64(<1 x i64> %a) #0 { ; CHECK: test_vceqz_p64 ; CHECK: cmeq {{d[0-9]}}, {{d[0-9]}}, #0x0 %1 = icmp eq <1 x i64> %a, zeroinitializer - %vceqz.i = zext <1 x i1> %1 to <1 x i64> + %vceqz.i = sext <1 x i1> %1 to <1 x i64> ret <1 x i64> %vceqz.i } @@ -295,7 +295,7 @@ define <2 x i64> @test_vceqzq_p64(<2 x i64> %a) #0 { ; CHECK: test_vceqzq_p64 ; CHECK: cmeq {{v[0-9]}}.2d, {{v[0-9]}}.2d, #0 %1 = icmp eq <2 x i64> %a, zeroinitializer - %vceqz.i = zext <2 x i1> %1 to <2 x i64> + %vceqz.i = sext <2 x i1> %1 to <2 x i64> ret <2 x i64> %vceqz.i } @@ -303,7 +303,7 @@ define <1 x i64> @test_vcgez_s64(<1 x i64> %a) #0 { ; CHECK: test_vcgez_s64 ; CHECK: cmge {{d[0-9]}}, {{d[0-9]}}, #0x0 %1 = icmp sge <1 x i64> %a, zeroinitializer - %vcgez.i = zext <1 x i1> %1 to <1 x i64> + %vcgez.i = sext <1 x i1> %1 to <1 x i64> ret <1 x i64> %vcgez.i } @@ -311,7 +311,7 @@ define <1 x i64> @test_vclez_s64(<1 x i64> %a) #0 { ; CHECK: test_vclez_s64 ; CHECK: cmle {{d[0-9]}}, {{d[0-9]}}, #0x0 %1 = icmp sle <1 x i64> %a, zeroinitializer - %vclez.i = zext <1 x i1> %1 to <1 x i64> + %vclez.i = sext <1 x i1> %1 to <1 x i64> ret <1 x i64> %vclez.i } @@ -319,7 +319,7 @@ define <1 x i64> @test_vcgtz_s64(<1 x i64> %a) #0 { ; CHECK: test_vcgtz_s64 ; CHECK: cmgt {{d[0-9]}}, {{d[0-9]}}, #0x0 %1 = icmp sgt <1 x i64> %a, zeroinitializer - %vcgtz.i = zext <1 x i1> %1 to <1 x i64> + %vcgtz.i = sext <1 x i1> %1 to <1 x i64> ret <1 x i64> %vcgtz.i } @@ -327,12 +327,12 @@ define <1 x i64> @test_vcltz_s64(<1 x i64> %a) #0 { ; CHECK: test_vcltz_s64 ; CHECK: cmlt {{d[0-9]}}, {{d[0-9]}}, #0 %1 = icmp slt <1 x i64> %a, zeroinitializer - %vcltz.i = zext <1 x i1> %1 to <1 x i64> + %vcltz.i = sext <1 x i1> %1 to <1 x i64> ret <1 x i64> %vcltz.i } -declare <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>) -declare <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double>, <1 x double>) +declare <1 x i64> @llvm.arm.neon.vacgt.v1i64.v1f64(<1 x double>, <1 x double>) +declare <1 x i64> @llvm.arm.neon.vacge.v1i64.v1f64(<1 x double>, <1 x double>) declare <1 x i64> @llvm.aarch64.neon.vtstd.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>) declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>) declare <1 x i64> @llvm.aarch64.neon.vchs.v1i64.v1i64.v1i64(<1 x i64>, <1 x i64>) |