diff options
Diffstat (limited to 'test/CodeGen/ARM/machine-licm.ll')
| -rw-r--r-- | test/CodeGen/ARM/machine-licm.ll | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/test/CodeGen/ARM/machine-licm.ll b/test/CodeGen/ARM/machine-licm.ll index fc9b226..ca65501 100644 --- a/test/CodeGen/ARM/machine-licm.ll +++ b/test/CodeGen/ARM/machine-licm.ll @@ -5,20 +5,12 @@ ; rdar://7354376 ; rdar://8887598 -; The generated code is no where near ideal. It's not recognizing the two -; constantpool entries being loaded can be merged into one. - @GV = external global i32 ; <i32*> [#uses=2] define void @t(i32* nocapture %vals, i32 %c) nounwind { entry: ; ARM-LABEL: t: ; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0 -; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool. -; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy -; to add the pseudo instructions to make sure they are CSE'ed at the same -; time as the "ldr cp". -; ARM: ldr r{{[0-9]+}}, LCPI0_1 ; ARM: LPC0_0: ; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]] ; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}] @@ -36,7 +28,7 @@ entry: bb.nph: ; preds = %entry ; ARM: LCPI0_0: -; ARM: LCPI0_1: +; ARM-NOT: LCPI0_1: ; ARM: .section ; THUMB: BB#1 |