diff options
Diffstat (limited to 'test/CodeGen/ARM/vcnt.ll')
| -rw-r--r-- | test/CodeGen/ARM/vcnt.ll | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll index 390559b..de251c5 100644 --- a/test/CodeGen/ARM/vcnt.ll +++ b/test/CodeGen/ARM/vcnt.ll @@ -4,7 +4,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vcnt8: ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -12,7 +12,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vcntQ8: ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -23,7 +23,7 @@ declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclz8: ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0) ret <8 x i8> %tmp2 } @@ -31,7 +31,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vclz16: ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0) ret <4 x i16> %tmp2 } @@ -39,7 +39,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vclz32: ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}} - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0) ret <2 x i32> %tmp2 } @@ -47,7 +47,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vclzQ8: ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0) ret <16 x i8> %tmp2 } @@ -55,7 +55,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vclzQ16: ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0) ret <8 x i16> %tmp2 } @@ -63,7 +63,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vclzQ32: ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}} - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0) ret <4 x i32> %tmp2 } @@ -79,7 +79,7 @@ declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { ;CHECK-LABEL: vclss8: ;CHECK: vcls.s8 - %tmp1 = load <8 x i8>* %A + %tmp1 = load <8 x i8>, <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1) ret <8 x i8> %tmp2 } @@ -87,7 +87,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { ;CHECK-LABEL: vclss16: ;CHECK: vcls.s16 - %tmp1 = load <4 x i16>* %A + %tmp1 = load <4 x i16>, <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1) ret <4 x i16> %tmp2 } @@ -95,7 +95,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { ;CHECK-LABEL: vclss32: ;CHECK: vcls.s32 - %tmp1 = load <2 x i32>* %A + %tmp1 = load <2 x i32>, <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1) ret <2 x i32> %tmp2 } @@ -103,7 +103,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { ;CHECK-LABEL: vclsQs8: ;CHECK: vcls.s8 - %tmp1 = load <16 x i8>* %A + %tmp1 = load <16 x i8>, <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1) ret <16 x i8> %tmp2 } @@ -111,7 +111,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { ;CHECK-LABEL: vclsQs16: ;CHECK: vcls.s16 - %tmp1 = load <8 x i16>* %A + %tmp1 = load <8 x i16>, <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1) ret <8 x i16> %tmp2 } @@ -119,7 +119,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind { ;CHECK-LABEL: vclsQs32: ;CHECK: vcls.s32 - %tmp1 = load <4 x i32>* %A + %tmp1 = load <4 x i32>, <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1) ret <4 x i32> %tmp2 } |