aboutsummaryrefslogtreecommitdiffstats
path: root/test/CodeGen/ARM
diff options
context:
space:
mode:
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r--test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll12
-rw-r--r--test/CodeGen/ARM/arm-modifier.ll6
-rw-r--r--test/CodeGen/ARM/carry.ll1
-rw-r--r--test/CodeGen/ARM/inlineasm3.ll42
-rw-r--r--test/CodeGen/ARM/vcvt_combine.ll99
-rw-r--r--test/CodeGen/ARM/vdiv_combine.ll102
6 files changed, 257 insertions, 5 deletions
diff --git a/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
new file mode 100644
index 0000000..1b5b8a9
--- /dev/null
+++ b/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll
@@ -0,0 +1,12 @@
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s
+; CHECK: .zerofill __DATA,__bss,__MergedGlobals,16,2
+
+%struct.config = type { i16, i16, i16, i16 }
+
+@prev = external global [0 x i16]
+@max_lazy_match = internal unnamed_addr global i32 0, align 4
+@read_buf = external global i32 (i8*, i32)*
+@window = external global [0 x i8]
+@lookahead = internal unnamed_addr global i32 0, align 4
+@eofile.b = internal unnamed_addr global i1 false
+@ins_h = internal unnamed_addr global i32 0, align 4
diff --git a/test/CodeGen/ARM/arm-modifier.ll b/test/CodeGen/ARM/arm-modifier.ll
index 0a7bb6c..396de37 100644
--- a/test/CodeGen/ARM/arm-modifier.ll
+++ b/test/CodeGen/ARM/arm-modifier.ll
@@ -46,9 +46,9 @@ ret void
define void @f3() nounwind {
entry:
; CHECK: f3
-; CHECK: stm r{{[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
-; CHECK: adds lr, [[REG1]]
-; CHECK: ldm r{{[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
+; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}}
+; CHECK: adds {{lr|r[0-9]+}}, [[REG1]]
+; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}}
%tmp = load i64* @f3_var, align 4
%tmp1 = load i64* @f3_var2, align 4
%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind
diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll
index 9b90408..06b459e 100644
--- a/test/CodeGen/ARM/carry.ll
+++ b/test/CodeGen/ARM/carry.ll
@@ -24,7 +24,6 @@ entry:
define i64 @f3(i32 %al, i32 %bl) {
; CHECK: f3:
; CHECK: adds r
-; CHECK: adcs r
; CHECK: adc r
entry:
; unsigned wide add
diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll
index 58687b9..853585d 100644
--- a/test/CodeGen/ARM/inlineasm3.ll
+++ b/test/CodeGen/ARM/inlineasm3.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon,+v6t2 | FileCheck %s
; Radar 7449043
%struct.int32x4_t = type { <4 x i32> }
@@ -58,3 +58,43 @@ entry:
call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
ret i32 0
}
+
+; Radar 9307836 & 9119939
+
+define float @t6(float %y) nounwind {
+entry:
+; CHECK: t6
+; CHECK: flds s15, s0
+ %0 = tail call float asm "flds s15, $0", "=x"() nounwind
+ ret float %0
+}
+
+; Radar 9307836 & 9119939
+
+define double @t7(double %y) nounwind {
+entry:
+; CHECK: t7
+; CHECK: flds s15, d0
+ %0 = tail call double asm "flds s15, $0", "=x"() nounwind
+ ret double %0
+}
+
+; Radar 9307836 & 9119939
+
+define float @t8(float %y) nounwind {
+entry:
+; CHECK: t8
+; CHECK: flds s15, s0
+ %0 = tail call float asm "flds s15, $0", "=t"() nounwind
+ ret float %0
+}
+
+; Radar 9307836 & 9119939
+
+define i32 @t9(i32 %r0) nounwind {
+entry:
+; CHECK: t9
+; CHECK: movw r0, #27182
+ %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
+ ret i32 %0
+}
diff --git a/test/CodeGen/ARM/vcvt_combine.ll b/test/CodeGen/ARM/vcvt_combine.ll
new file mode 100644
index 0000000..3009e50
--- /dev/null
+++ b/test/CodeGen/ARM/vcvt_combine.ll
@@ -0,0 +1,99 @@
+; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
+
+@in = global float 0x400921FA00000000, align 4
+
+; Test signed conversion.
+; CHECK: t0
+; CHECK-NOT: vmul
+define void @t0() nounwind {
+entry:
+ %tmp = load float* @in, align 4, !tbaa !0
+ %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+ %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+ %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00>
+ %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
+ tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
+ ret void
+}
+
+declare void @foo_int32x2_t(<2 x i32>)
+
+; Test unsigned conversion.
+; CHECK: t1
+; CHECK-NOT: vmul
+define void @t1() nounwind {
+entry:
+ %tmp = load float* @in, align 4, !tbaa !0
+ %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+ %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+ %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00>
+ %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
+ tail call void @foo_uint32x2_t(<2 x i32> %vcvt.i) nounwind
+ ret void
+}
+
+declare void @foo_uint32x2_t(<2 x i32>)
+
+; Test which should not fold due to non-power of 2.
+; CHECK: t2
+; CHECK: vmul
+define void @t2() nounwind {
+entry:
+ %tmp = load float* @in, align 4, !tbaa !0
+ %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+ %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+ %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000>
+ %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
+ tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
+ ret void
+}
+
+; Test which should not fold due to power of 2 out of range.
+; CHECK: t3
+; CHECK: vmul
+define void @t3() nounwind {
+entry:
+ %tmp = load float* @in, align 4, !tbaa !0
+ %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+ %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+ %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000>
+ %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
+ tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
+ ret void
+}
+
+; Test which case where const is max power of 2 (i.e., 2^32).
+; CHECK: t4
+; CHECK-NOT: vmul
+define void @t4() nounwind {
+entry:
+ %tmp = load float* @in, align 4, !tbaa !0
+ %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+ %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+ %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000>
+ %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
+ tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
+ ret void
+}
+
+; Test quadword.
+; CHECK: t5
+; CHECK-NOT: vmul
+define void @t5() nounwind {
+entry:
+ %tmp = load float* @in, align 4, !tbaa !0
+ %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0
+ %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1
+ %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2
+ %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %tmp, i32 3
+ %mul.i = fmul <4 x float> %vecinit6.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
+ %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
+ tail call void @foo_int32x4_t(<4 x i32> %vcvt.i) nounwind
+ ret void
+}
+
+declare void @foo_int32x4_t(<4 x i32>)
+
+!0 = metadata !{metadata !"float", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll
new file mode 100644
index 0000000..1387393
--- /dev/null
+++ b/test/CodeGen/ARM/vdiv_combine.ll
@@ -0,0 +1,102 @@
+; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
+
+@in = global float 0x400921FA00000000, align 4
+@iin = global i32 -1023, align 4
+@uin = global i32 1023, align 4
+
+declare void @foo_int32x4_t(<4 x i32>)
+
+; Test signed conversion.
+; CHECK: t1
+; CHECK-NOT: vdiv
+define void @t1() nounwind {
+entry:
+ %tmp = load i32* @iin, align 4, !tbaa !3
+ %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+ %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+ %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
+ %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
+ tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+ ret void
+}
+
+declare void @foo_float32x2_t(<2 x float>)
+
+; Test unsigned conversion.
+; CHECK: t2
+; CHECK-NOT: vdiv
+define void @t2() nounwind {
+entry:
+ %tmp = load i32* @uin, align 4, !tbaa !3
+ %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+ %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+ %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>
+ %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
+ tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+ ret void
+}
+
+; Test which should not fold due to non-power of 2.
+; CHECK: t3
+; CHECK: vdiv
+define void @t3() nounwind {
+entry:
+ %tmp = load i32* @iin, align 4, !tbaa !3
+ %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+ %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+ %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
+ %div.i = fdiv <2 x float> %vcvt.i, <float 0x401B333340000000, float 0x401B333340000000>
+ tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+ ret void
+}
+
+; Test which should not fold due to power of 2 out of range.
+; CHECK: t4
+; CHECK: vdiv
+define void @t4() nounwind {
+entry:
+ %tmp = load i32* @iin, align 4, !tbaa !3
+ %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+ %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+ %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
+ %div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
+ tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+ ret void
+}
+
+; Test case where const is max power of 2 (i.e., 2^32).
+; CHECK: t5
+; CHECK-NOT: vdiv
+define void @t5() nounwind {
+entry:
+ %tmp = load i32* @iin, align 4, !tbaa !3
+ %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+ %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+ %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
+ %div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>
+ tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+ ret void
+}
+
+; Test quadword.
+; CHECK: t6
+; CHECK-NOT: vdiv
+define void @t6() nounwind {
+entry:
+ %tmp = load i32* @iin, align 4, !tbaa !3
+ %vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0
+ %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1
+ %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2
+ %vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %tmp, i32 3
+ %vcvt.i = sitofp <4 x i32> %vecinit6.i to <4 x float>
+ %div.i = fdiv <4 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
+ tail call void @foo_float32x4_t(<4 x float> %div.i) nounwind
+ ret void
+}
+
+declare void @foo_float32x4_t(<4 x float>)
+
+!0 = metadata !{metadata !"float", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
+!3 = metadata !{metadata !"int", metadata !1}
generated by cgit v1.1 at 2025-08-17 08:45:35 +0000