diff options
Diffstat (limited to 'test/CodeGen/ARM')
100 files changed, 5284 insertions, 499 deletions
diff --git a/test/CodeGen/ARM/2009-10-16-Scope.ll b/test/CodeGen/ARM/2009-10-16-Scope.ll index dd08b56..570fcf9 100644 --- a/test/CodeGen/ARM/2009-10-16-Scope.ll +++ b/test/CodeGen/ARM/2009-10-16-Scope.ll @@ -24,8 +24,7 @@ declare i32 @foo(i32) ssp !0 = metadata !{i32 5, i32 2, metadata !1, null} !1 = metadata !{i32 458763, null, metadata !2, i32 1, i32 1, i32 0}; [DW_TAG_lexical_block ] -!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", i32 4, null, i1 false, i1 true, - i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0}; [DW_TAG_subprogram ] +!2 = metadata !{i32 458798, i32 0, metadata !3, metadata !"bar", metadata !"bar", metadata !"bar", i32 4, null, i1 false, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0}; [DW_TAG_subprogram ] !3 = metadata !{i32 458769, metadata !8, i32 12, metadata !"clang 1.1", i1 true, metadata !"", i32 0, null, metadata !9, null, null, null, metadata !""}; [DW_TAG_compile_unit ] !4 = metadata !{i32 459008, metadata !5, metadata !"count_", metadata !3, i32 5, metadata !6}; [ DW_TAG_auto_variable ] !5 = metadata !{i32 458763, null, metadata !1, i32 1, i32 1, i32 0}; [DW_TAG_lexical_block ] diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index 89f468a..35739d7 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -13,12 +13,13 @@ entry: declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!3} +!llvm.module.flags = !{!15} !0 = metadata !{i32 524545, metadata !1, metadata !"b", metadata !2, i32 93, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] !1 = metadata !{i32 524334, metadata !12, null, metadata !"__addvsi3", metadata !"__addvsi3", metadata !"__addvsi3", i32 94, metadata !4, i1 false, i1 true, i32 0, i32 0, null, i32 0, i32 0, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ] !2 = metadata !{i32 524329, metadata !12} ; [ DW_TAG_file_type ] !12 = metadata !{metadata !"libgcc2.c", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc"} !3 = metadata !{i32 524305, metadata !12, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 00)", i1 true, metadata !"", i32 0, metadata !13, metadata !13, metadata !14, null, null, metadata !""} ; [ DW_TAG_compile_unit ] -!4 = metadata !{i32 524309, metadata !12, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{i32 524309, metadata !12, metadata !2, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !5, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !5 = metadata !{metadata !6, metadata !6, metadata !6} !6 = metadata !{i32 524310, metadata !12, null, metadata !"SItype", i32 152, i64 0, i64 0, i64 0, i32 0, metadata !8} ; [ DW_TAG_typedef ] !7 = metadata !{i32 524329, metadata !"libgcc2.h", metadata !"/Users/bwilson/local/nightly/test-2010-04-14/build/llvmgcc.roots/llvmgcc~obj/src/gcc", metadata !3} ; [ DW_TAG_file_type ] @@ -28,3 +29,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !11 = metadata !{i32 100, i32 0, metadata !10, null} !13 = metadata !{i32 0} !14 = metadata !{metadata !1} +!15 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index f4ad4bc..7aacd1a 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -75,9 +75,10 @@ return: ; preds = %entry declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!3} +!llvm.module.flags = !{!49} !0 = metadata !{i32 786478, metadata !48, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"", i32 11, metadata !14, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 786451, metadata !48, null, metadata !"SVal", i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_structure_type ] +!1 = metadata !{i32 786451, metadata !48, null, metadata !"SVal", i32 1, i64 128, i64 64, i64 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [SVal] [line 1, size 128, align 64, offset 0] [def] [from ] !2 = metadata !{i32 786473, metadata !48} ; [ DW_TAG_file_type ] !3 = metadata !{i32 786449, metadata !48, i32 4, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build)", i1 false, metadata !"", i32 0, metadata !47, metadata !47, metadata !46, metadata !47, metadata !47, metadata !""} ; [ DW_TAG_compile_unit ] !4 = metadata !{metadata !5, metadata !7, metadata !0, metadata !9} @@ -86,18 +87,18 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !7 = metadata !{i32 786445, metadata !48, metadata !1, metadata !"Kind", i32 8, i64 32, i64 32, i64 64, i32 0, metadata !8} ; [ DW_TAG_member ] !8 = metadata !{i32 786468, metadata !48, null, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] !9 = metadata !{i32 786478, metadata !48, metadata !1, metadata !"~SVal", metadata !"~SVal", metadata !"", i32 12, metadata !10, i1 false, i1 false, i32 0, i32 0, null, i1 false, i1 false, null, null, null, null, i32 0} ; [ DW_TAG_subprogram ] -!10 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null} ; [ DW_TAG_subroutine_type ] +!10 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !11, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !11 = metadata !{null, metadata !12, metadata !13} !12 = metadata !{i32 786447, metadata !48, null, metadata !"", i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] !13 = metadata !{i32 786468, metadata !48, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null} ; [ DW_TAG_subroutine_type ] +!14 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !15, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !15 = metadata !{null, metadata !12} !16 = metadata !{i32 786478, metadata !48, metadata !1, metadata !"SVal", metadata !"SVal", metadata !"_ZN4SValC1Ev", i32 11, metadata !14, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, void (%struct.SVal*)* @_ZN4SValC1Ev, null, null, null, i32 0} ; [ DW_TAG_subprogram ] !17 = metadata !{i32 786478, metadata !48, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3fooi4SVal", i32 16, metadata !18, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32, %struct.SVal*)* @_Z3fooi4SVal, null, null, null, i32 0} ; [ DW_TAG_subprogram ] -!18 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null} ; [ DW_TAG_subroutine_type ] +!18 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !19, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !19 = metadata !{metadata !13, metadata !13, metadata !1} !20 = metadata !{i32 786478, metadata !48, metadata !2, metadata !"main", metadata !"main", metadata !"main", i32 23, metadata !21, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @main, null, null, null, i32 0} ; [ DW_TAG_subprogram ] -!21 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null} ; [ DW_TAG_subroutine_type ] +!21 = metadata !{i32 786453, metadata !48, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !22, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !22 = metadata !{metadata !13} !23 = metadata !{i32 786689, metadata !17, metadata !"i", metadata !2, i32 16, metadata !13, i32 0, i32 0} ; [ DW_TAG_arg_variable ] !24 = metadata !{i32 16, i32 0, metadata !17, null} @@ -125,3 +126,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !46 = metadata !{metadata !0, metadata !9, metadata !16, metadata !17, metadata !20} !47 = metadata !{i32 0} !48 = metadata !{metadata !"small.cc", metadata !"/Users/manav/R8248330"} +!49 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll index e6d1518..3053694 100644 --- a/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll +++ b/test/CodeGen/ARM/2010-09-29-mc-asm-header-test.ll @@ -1,10 +1,79 @@ +; This tests that MC/asm header conversion is smooth and that the +; build attributes are correct + +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s --check-prefix=V6 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi | FileCheck %s --check-prefix=V6M +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s | FileCheck %s --check-prefix=ARM1156T2F-S +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M ; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8 ; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8 -; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+v8fp | FileCheck %s --check-prefix=V8-V8FP -; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=+neon | FileCheck %s --check-prefix=V8-NEON -; This tests that MC/asm header conversion is smooth -; +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-neon,-crypto | FileCheck %s --check-prefix=V8-FPARMv8 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON +; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9-mp | FileCheck %s --check-prefix=CORTEX-A9-MP +; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15 +; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0 +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT +; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD +; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53 +; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57 + +; V6: .eabi_attribute 6, 6 +; V6: .eabi_attribute 8, 1 +; V6: .eabi_attribute 24, 1 +; V6: .eabi_attribute 25, 1 +; V6-NOT: .eabi_attribute 27 +; V6-NOT: .eabi_attribute 28 +; V6-NOT: .eabi_attribute 36 +; V6-NOT: .eabi_attribute 42 +; V6-NOT: .eabi_attribute 68 + +; V6M: .eabi_attribute 6, 12 +; V6M: .eabi_attribute 7, 77 +; V6M: .eabi_attribute 8, 0 +; V6M: .eabi_attribute 9, 1 +; V6M: .eabi_attribute 24, 1 +; V6M: .eabi_attribute 25, 1 +; V6M-NOT: .eabi_attribute 27 +; V6M-NOT: .eabi_attribute 28 +; V6M-NOT: .eabi_attribute 36 +; V6M-NOT: .eabi_attribute 42 +; V6M-NOT: .eabi_attribute 68 + +; ARM1156T2F-S: .cpu arm1156t2f-s +; ARM1156T2F-S: .eabi_attribute 6, 8 +; ARM1156T2F-S: .eabi_attribute 8, 1 +; ARM1156T2F-S: .eabi_attribute 9, 2 +; ARM1156T2F-S: .fpu vfpv2 +; ARM1156T2F-S: .eabi_attribute 20, 1 +; ARM1156T2F-S: .eabi_attribute 21, 1 +; ARM1156T2F-S: .eabi_attribute 23, 3 +; ARM1156T2F-S: .eabi_attribute 24, 1 +; ARM1156T2F-S: .eabi_attribute 25, 1 +; ARM1156T2F-S-NOT: .eabi_attribute 27 +; ARM1156T2F-S-NOT: .eabi_attribute 28 +; ARM1156T2F-S-NOT: .eabi_attribute 36 +; ARM1156T2F-S-NOT: .eabi_attribute 42 +; ARM1156T2F-S-NOT: .eabi_attribute 68 + +; V7M: .eabi_attribute 6, 10 +; V7M: .eabi_attribute 7, 77 +; V7M: .eabi_attribute 8, 0 +; V7M: .eabi_attribute 9, 2 +; V7M: .eabi_attribute 24, 1 +; V7M: .eabi_attribute 25, 1 +; V7M-NOT: .eabi_attribute 27 +; V7M-NOT: .eabi_attribute 28 +; V7M-NOT: .eabi_attribute 36 +; V7M-NOT: .eabi_attribute 42 +; V7M: .eabi_attribute 44, 0 +; V7M-NOT: .eabi_attribute 68 + ; V7: .syntax unified ; V7: .eabi_attribute 6, 10 ; V7: .eabi_attribute 20, 1 @@ -12,6 +81,11 @@ ; V7: .eabi_attribute 23, 3 ; V7: .eabi_attribute 24, 1 ; V7: .eabi_attribute 25, 1 +; V7-NOT: .eabi_attribute 27 +; V7-NOT: .eabi_attribute 28 +; V7-NOT: .eabi_attribute 36 +; V7-NOT: .eabi_attribute 42 +; V7-NOT: .eabi_attribute 68 ; V8: .syntax unified ; V8: .eabi_attribute 6, 14 @@ -19,14 +93,193 @@ ; Vt8: .syntax unified ; Vt8: .eabi_attribute 6, 14 -; V8-V8FP: .syntax unified -; V8-V8FP: .eabi_attribute 6, 14 -; V8-V8FP: .eabi_attribute 10, 7 +; V8-FPARMv8: .syntax unified +; V8-FPARMv8: .eabi_attribute 6, 14 +; V8-FPARMv8: .fpu fp-armv8 ; V8-NEON: .syntax unified ; V8-NEON: .eabi_attribute 6, 14 +; V8-NEON: .fpu neon ; V8-NEON: .eabi_attribute 12, 3 +; V8-FPARMv8-NEON: .syntax unified +; V8-FPARMv8-NEON: .eabi_attribute 6, 14 +; V8-FPARMv8-NEON: .fpu neon-fp-armv8 +; V8-FPARMv8-NEON: .eabi_attribute 12, 3 + +; V8-FPARMv8-NEON-CRYPTO: .syntax unified +; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 6, 14 +; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8 +; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3 + +; CORTEX-A9-SOFT: .cpu cortex-a9 +; CORTEX-A9-SOFT: .eabi_attribute 6, 10 +; CORTEX-A9-SOFT: .eabi_attribute 7, 65 +; CORTEX-A9-SOFT: .eabi_attribute 8, 1 +; CORTEX-A9-SOFT: .eabi_attribute 9, 2 +; CORTEX-A9-SOFT: .fpu neon +; CORTEX-A9-SOFT: .eabi_attribute 20, 1 +; CORTEX-A9-SOFT: .eabi_attribute 21, 1 +; CORTEX-A9-SOFT: .eabi_attribute 23, 3 +; CORTEX-A9-SOFT: .eabi_attribute 24, 1 +; CORTEX-A9-SOFT: .eabi_attribute 25, 1 +; CORTEX-A9-SOFT-NOT: .eabi_attribute 27 +; CORTEX-A9-SOFT-NOT: .eabi_attribute 28 +; CORTEX-A9-SOFT: .eabi_attribute 36, 1 +; CORTEX-A9-SOFT-NOT: .eabi_attribute 42 +; CORTEX-A9-SOFT: .eabi_attribute 68, 1 + +; CORTEX-A9-HARD: .cpu cortex-a9 +; CORTEX-A9-HARD: .eabi_attribute 6, 10 +; CORTEX-A9-HARD: .eabi_attribute 7, 65 +; CORTEX-A9-HARD: .eabi_attribute 8, 1 +; CORTEX-A9-HARD: .eabi_attribute 9, 2 +; CORTEX-A9-HARD: .fpu neon +; CORTEX-A9-HARD: .eabi_attribute 20, 1 +; CORTEX-A9-HARD: .eabi_attribute 21, 1 +; CORTEX-A9-HARD: .eabi_attribute 23, 3 +; CORTEX-A9-HARD: .eabi_attribute 24, 1 +; CORTEX-A9-HARD: .eabi_attribute 25, 1 +; CORTEX-A9-HARD-NOT: .eabi_attribute 27 +; CORTEX-A9-HARD: .eabi_attribute 28, 1 +; CORTEX-A9-HARD: .eabi_attribute 36, 1 +; CORTEX-A9-HARD-NOT: .eabi_attribute 42 +; CORTEX-A9-HARD: .eabi_attribute 68, 1 + +; CORTEX-A9-MP: .cpu cortex-a9-mp +; CORTEX-A9-MP: .eabi_attribute 6, 10 +; CORTEX-A9-MP: .eabi_attribute 7, 65 +; CORTEX-A9-MP: .eabi_attribute 8, 1 +; CORTEX-A9-MP: .eabi_attribute 9, 2 +; CORTEX-A9-MP: .fpu neon +; CORTEX-A9-MP: .eabi_attribute 20, 1 +; CORTEX-A9-MP: .eabi_attribute 21, 1 +; CORTEX-A9-MP: .eabi_attribute 23, 3 +; CORTEX-A9-MP: .eabi_attribute 24, 1 +; CORTEX-A9-MP: .eabi_attribute 25, 1 +; CORTEX-A9-NOT: .eabi_attribute 27 +; CORTEX-A9-NOT: .eabi_attribute 28 +; CORTEX-A9-MP: .eabi_attribute 36, 1 +; CORTEX-A9-MP: .eabi_attribute 42, 1 +; CORTEX-A9-MP: .eabi_attribute 68, 1 + +; CORTEX-A15: .cpu cortex-a15 +; CORTEX-A15: .eabi_attribute 6, 10 +; CORTEX-A15: .eabi_attribute 7, 65 +; CORTEX-A15: .eabi_attribute 8, 1 +; CORTEX-A15: .eabi_attribute 9, 2 +; CORTEX-A15: .fpu neon-vfpv4 +; CORTEX-A15: .eabi_attribute 20, 1 +; CORTEX-A15: .eabi_attribute 21, 1 +; CORTEX-A15: .eabi_attribute 23, 3 +; CORTEX-A15: .eabi_attribute 24, 1 +; CORTEX-A15: .eabi_attribute 25, 1 +; CORTEX-A15-NOT: .eabi_attribute 27 +; CORTEX-A15-NOT: .eabi_attribute 28 +; CORTEX-A15: .eabi_attribute 36, 1 +; CORTEX-A15: .eabi_attribute 42, 1 +; CORTEX-A15: .eabi_attribute 44, 2 +; CORTEX-A15: .eabi_attribute 68, 3 + +; CORTEX-M0: .cpu cortex-m0 +; CORTEX-M0: .eabi_attribute 6, 12 +; CORTEX-M0: .eabi_attribute 7, 77 +; CORTEX-M0: .eabi_attribute 8, 0 +; CORTEX-M0: .eabi_attribute 9, 1 +; CORTEX-M0: .eabi_attribute 24, 1 +; CORTEX-M0: .eabi_attribute 25, 1 +; CORTEX-M0-NOT: .eabi_attribute 27 +; CORTEX-M0-NOT: .eabi_attribute 28 +; CORTEX-M0-NOT: .eabi_attribute 36 +; CORTEX-M0-NOT: .eabi_attribute 42 +; CORTEX-M0-NOT: .eabi_attribute 68 + +; CORTEX-M4-SOFT: .cpu cortex-m4 +; CORTEX-M4-SOFT: .eabi_attribute 6, 13 +; CORTEX-M4-SOFT: .eabi_attribute 7, 77 +; CORTEX-M4-SOFT: .eabi_attribute 8, 0 +; CORTEX-M4-SOFT: .eabi_attribute 9, 2 +; CORTEX-M4-SOFT: .fpu vfpv4-d16 +; CORTEX-M4-SOFT: .eabi_attribute 20, 1 +; CORTEX-M4-SOFT: .eabi_attribute 21, 1 +; CORTEX-M4-SOFT: .eabi_attribute 23, 3 +; CORTEX-M4-SOFT: .eabi_attribute 24, 1 +; CORTEX-M4-SOFT: .eabi_attribute 25, 1 +; CORTEX-M4-SOFT: .eabi_attribute 27, 1 +; CORTEX-M4-SOFT-NOT: .eabi_attribute 28 +; CORTEX-M4-SOFT: .eabi_attribute 36, 1 +; CORTEX-M4-SOFT-NOT: .eabi_attribute 42 +; CORTEX-M4-SOFT: .eabi_attribute 44, 0 +; CORTEX-M4-SOFT-NOT: .eabi_attribute 68 + +; CORTEX-M4-HARD: .cpu cortex-m4 +; CORTEX-M4-HARD: .eabi_attribute 6, 13 +; CORTEX-M4-HARD: .eabi_attribute 7, 77 +; CORTEX-M4-HARD: .eabi_attribute 8, 0 +; CORTEX-M4-HARD: .eabi_attribute 9, 2 +; CORTEX-M4-HARD: .fpu vfpv4-d16 +; CORTEX-M4-HARD: .eabi_attribute 20, 1 +; CORTEX-M4-HARD: .eabi_attribute 21, 1 +; CORTEX-M4-HARD: .eabi_attribute 23, 3 +; CORTEX-M4-HARD: .eabi_attribute 24, 1 +; CORTEX-M4-HARD: .eabi_attribute 25, 1 +; CORTEX-M4-HARD: .eabi_attribute 27, 1 +; CORTEX-M4-HARD: .eabi_attribute 28, 1 +; CORTEX-M4-HARD: .eabi_attribute 36, 1 +; CORTEX-M4-HARD-NOT: .eabi_attribute 42 +; CORTEX-M4-HARD: .eabi_attribute 44, 0 +; CORTEX-M4-HRAD-NOT: .eabi_attribute 68 + +; CORTEX-R5: .cpu cortex-r5 +; CORTEX-R5: .eabi_attribute 6, 10 +; CORTEX-R5: .eabi_attribute 7, 82 +; CORTEX-R5: .eabi_attribute 8, 1 +; CORTEX-R5: .eabi_attribute 9, 2 +; CORTEX-R5: .fpu vfpv3-d16 +; CORTEX-R5: .eabi_attribute 20, 1 +; CORTEX-R5: .eabi_attribute 21, 1 +; CORTEX-R5: .eabi_attribute 23, 3 +; CORTEX-R5: .eabi_attribute 24, 1 +; CORTEX-R5: .eabi_attribute 25, 1 +; CORTEX-R5: .eabi_attribute 27, 1 +; CORTEX-R5-NOT: .eabi_attribute 28 +; CORTEX-R5-NOT: .eabi_attribute 36 +; CORTEX-R5-NOT: .eabi_attribute 42 +; CORTEX-R5: .eabi_attribute 44, 2 +; CORTEX-R5-NOT: .eabi_attribute 68 + +; CORTEX-A53: .cpu cortex-a53 +; CORTEX-A53: .eabi_attribute 6, 14 +; CORTEX-A53: .eabi_attribute 7, 65 +; CORTEX-A53: .eabi_attribute 8, 1 +; CORTEX-A53: .eabi_attribute 9, 2 +; CORTEX-A53: .fpu crypto-neon-fp-armv8 +; CORTEX-A53: .eabi_attribute 12, 3 +; CORTEX-A53: .eabi_attribute 24, 1 +; CORTEX-A53: .eabi_attribute 25, 1 +; CORTEX-A53-NOT: .eabi_attribute 27 +; CORTEX-A53-NOT: .eabi_attribute 28 +; CORTEX-A53: .eabi_attribute 36, 1 +; CORTEX-A53: .eabi_attribute 42, 1 +; CORTEX-A53: .eabi_attribute 44, 2 +; CORTEX-A53: .eabi_attribute 68, 3 + +; CORTEX-A57: .cpu cortex-a57 +; CORTEX-A57: .eabi_attribute 6, 14 +; CORTEX-A57: .eabi_attribute 7, 65 +; CORTEX-A57: .eabi_attribute 8, 1 +; CORTEX-A57: .eabi_attribute 9, 2 +; CORTEX-A57: .fpu crypto-neon-fp-armv8 +; CORTEX-A57: .eabi_attribute 12, 3 +; CORTEX-A57: .eabi_attribute 24, 1 +; CORTEX-A57: .eabi_attribute 25, 1 +; CORTEX-A57-NOT: .eabi_attribute 27 +; CORTEX-A57-NOT: .eabi_attribute 28 +; CORTEX-A57: .eabi_attribute 36, 1 +; CORTEX-A57: .eabi_attribute 42, 1 +; CORTEX-A57: .eabi_attribute 44, 2 +; CORTEX-A57: .eabi_attribute 68, 3 + define i32 @f(i64 %z) { ret i32 0 } diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll deleted file mode 100644 index d19adcc..0000000 --- a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll +++ /dev/null @@ -1,47 +0,0 @@ -; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ -; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=BASIC %s -; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \ -; RUN: -mattr=-neon,-vfp3,+vfp2 \ -; RUN: -arm-reserve-r9 -filetype=obj -o - | \ -; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=CORTEXA8 %s - - -; This tests that the extpected ARM attributes are emitted. -; -; BASIC: Section { -; BASIC: Name: .ARM.attributes -; BASIC-NEXT: Type: SHT_ARM_ATTRIBUTES -; BASIC-NEXT: Flags [ (0x0) -; BASIC-NEXT: ] -; BASIC-NEXT: Address: 0x0 -; BASIC-NEXT: Offset: 0x3C -; BASIC-NEXT: Size: 28 -; BASIC-NEXT: Link: 0 -; BASIC-NEXT: Info: 0 -; BASIC-NEXT: AddressAlignment: 1 -; BASIC-NEXT: EntrySize: 0 -; BASIC-NEXT: SectionData ( -; BASIC-NEXT: 0000: 411B0000 00616561 62690001 11000000 -; BASIC-NEXT: 0010: 06011401 15011703 18011901 -; BASIC-NEXT: ) - -; CORTEXA8: Name: .ARM.attributes -; CORTEXA8-NEXT: Type: SHT_ARM_ATTRIBUTES -; CORTEXA8-NEXT: Flags [ (0x0) -; CORTEXA8-NEXT: ] -; CORTEXA8-NEXT: Address: 0x0 -; CORTEXA8-NEXT: Offset: 0x3C -; CORTEXA8-NEXT: Size: 47 -; CORTEXA8-NEXT: Link: 0 -; CORTEXA8-NEXT: Info: 0 -; CORTEXA8-NEXT: AddressAlignment: 1 -; CORTEXA8-NEXT: EntrySize: 0 -; CORTEXA8-NEXT: SectionData ( -; CORTEXA8-NEXT: 0000: 412E0000 00616561 62690001 24000000 -; CORTEXA8-NEXT: 0010: 05434F52 5445582D 41380006 0A074108 -; CORTEXA8-NEXT: 0020: 0109020A 02140115 01170318 011901 -; CORTEXA8-NEXT: ) - -define i32 @f(i64 %z) { - ret i32 0 -} diff --git a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll b/test/CodeGen/ARM/2010-11-30-reloc-movt.ll deleted file mode 100644 index 6bea7b8..0000000 --- a/test/CodeGen/ARM/2010-11-30-reloc-movt.ll +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: llc %s -mtriple=armv7-linux-gnueabi -filetype=obj -o - | \ -; RUN: llvm-readobj -s -sr -sd | FileCheck -check-prefix=OBJ %s - -target triple = "armv7-none-linux-gnueabi" - -@a = external global i8 - -define arm_aapcs_vfpcc i32 @barf() nounwind { -entry: - %0 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind - ret i32 %0 -; OBJ: Section { -; OBJ: Name: .text -; OBJ: SectionData ( -; OBJ-NEXT: 0000: 00482DE9 000000E3 000040E3 FEFFFFEB -; OBJ-NEXT: 0010: 0088BDE8 -; OBJ-NEXT: ) -; OBJ: Relocations [ -; OBJ-NEXT: 0x4 R_ARM_MOVW_ABS_NC a -; OBJ-NEXT: 0x8 R_ARM_MOVT_ABS -; OBJ-NEXT: 0xC R_ARM_CALL foo -; OBJ-NEXT: ] - -} - -declare arm_aapcs_vfpcc i32 @foo(i8*) - diff --git a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll index 626d121..f57411b 100644 --- a/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll @@ -76,11 +76,12 @@ entry: } !llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!49} !0 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"get1", metadata !"get1", metadata !"get1", i32 4, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get1, null, null, metadata !42, i32 4} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] !2 = metadata !{i32 786449, metadata !47, i32 1, metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2369.8)", i1 true, metadata !"", i32 0, metadata !48, metadata !48, metadata !40, metadata !41, metadata !41, metadata !""} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !47, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!3 = metadata !{i32 786453, metadata !47, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !4 = metadata !{metadata !5, metadata !5} !5 = metadata !{i32 786468, metadata !47, metadata !1, metadata !"_Bool", i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] !6 = metadata !{i32 786478, metadata !47, metadata !1, metadata !"get2", metadata !"get2", metadata !"get2", i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i8 (i8)* @get2, null, null, metadata !43, i32 7} ; [ DW_TAG_subprogram ] @@ -126,3 +127,4 @@ entry: !46 = metadata !{metadata !27, metadata !28} !47 = metadata !{metadata !"foo.c", metadata !"/tmp/"} !48 = metadata !{i32 0} +!49 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll index f689d49..bc72e12 100644 --- a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll +++ b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll @@ -21,8 +21,8 @@ for.body: ; preds = %_Z14printIsNotZeroi %x = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 0 %y = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %i.022, i32 1 %inc = add i32 %i.022, 1 - %tmp8 = load i32* %x, align 4, !tbaa !0 - %tmp11 = load i32* %y, align 4, !tbaa !0 + %tmp8 = load i32* %x, align 4 + %tmp11 = load i32* %y, align 4 %mul = mul nsw i32 %tmp11, %tmp8 %tobool.i14 = icmp eq i32 %mul, 0 br i1 %tobool.i14, label %_Z14printIsNotZeroi.exit17, label %if.then.i16 @@ -35,15 +35,10 @@ _Z14printIsNotZeroi.exit17: ; preds = %_Z14printIsNotZeroi _Z14printIsNotZeroi.exit17.for.body_crit_edge: ; preds = %_Z14printIsNotZeroi.exit17 %b.phi.trans.insert = getelementptr %struct.Outer* @oStruct, i32 0, i32 1, i32 %inc, i32 3 - %tmp3.pre = load i8* %b.phi.trans.insert, align 1, !tbaa !3 + %tmp3.pre = load i8* %b.phi.trans.insert, align 1 %phitmp27 = icmp eq i8 undef, 0 br label %for.body for.end: ; preds = %_Z14printIsNotZeroi.exit17 ret void } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} -!3 = metadata !{metadata !"bool", metadata !1} diff --git a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll index 348ec9f..e30c9c6 100644 --- a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll +++ b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll @@ -15,15 +15,14 @@ for.cond: for.body: ; CHECK: %for. -; CHECK: movs r{{[0-9]+}}, #{{[01]}} +; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}} +; CHECK: mov{{.*}} r{{[0-9]+}}, #{{[01]}} +; CHECK-NOT: mov r{{[0-9]+}}, #{{[01]}} %arrayidx = getelementptr i32* %A, i32 %0 %tmp4 = load i32* %arrayidx, align 4 %cmp6 = icmp eq i32 %tmp4, %value br i1 %cmp6, label %return, label %for.inc -; CHECK: %for. -; CHECK: movs r{{[0-9]+}}, #{{[01]}} - for.inc: %inc = add i32 %0, 1 br label %for.cond diff --git a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll index 33826f8..bb78707 100644 --- a/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll +++ b/test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll @@ -73,17 +73,18 @@ define i32 @get5(i32 %a) nounwind optsize ssp { declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!49} !0 = metadata !{i32 786449, metadata !47, i32 12, metadata !"clang", i1 true, metadata !"", i32 0, metadata !48, metadata !48, metadata !40, metadata !41, metadata !41, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get1", metadata !"get1", metadata !"", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get1", metadata !"get1", metadata !"", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32)* @get1, null, null, metadata !42, i32 5} ; [ DW_TAG_subprogram ] [line 5] [def] [get1] !2 = metadata !{i32 786473, metadata !47} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786453, metadata !47, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!3 = metadata !{i32 786453, metadata !47, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get2", metadata !"get2", metadata !"", i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get2, null, null, metadata !43, i32 8} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get3", metadata !"get3", metadata !"", i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get3, null, null, metadata !44, i32 11} ; [ DW_TAG_subprogram ] -!8 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get4", metadata !"get4", metadata !"", i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get4, null, null, metadata !45, i32 14} ; [ DW_TAG_subprogram ] -!9 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get5", metadata !"get5", metadata !"", i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32)* @get5, null, null, metadata !46, i32 17} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get2", metadata !"get2", metadata !"", i32 8, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32)* @get2, null, null, metadata !43, i32 8} ; [ DW_TAG_subprogram ] [line 8] [def] [get2] +!7 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get3", metadata !"get3", metadata !"", i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32)* @get3, null, null, metadata !44, i32 11} ; [ DW_TAG_subprogram ] [line 11] [def] [get3] +!8 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get4", metadata !"get4", metadata !"", i32 14, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32)* @get4, null, null, metadata !45, i32 14} ; [ DW_TAG_subprogram ] [line 14] [def] [get4] +!9 = metadata !{i32 786478, metadata !47, metadata !2, metadata !"get5", metadata !"get5", metadata !"", i32 17, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32)* @get5, null, null, metadata !46, i32 17} ; [ DW_TAG_subprogram ] [line 17] [def] [get5] !10 = metadata !{i32 786689, metadata !1, metadata !"a", metadata !2, i32 16777221, metadata !5, i32 0, null} ; [ DW_TAG_arg_variable ] !11 = metadata !{i32 786688, metadata !12, metadata !"b", metadata !2, i32 5, metadata !5, i32 0, null} ; [ DW_TAG_auto_variable ] !12 = metadata !{i32 786443, metadata !47, metadata !1, i32 5, i32 19, i32 0} ; [ DW_TAG_lexical_block ] @@ -123,3 +124,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !46 = metadata !{metadata !27, metadata !28} !47 = metadata !{metadata !"ss3.c", metadata !"/private/tmp"} !48 = metadata !{i32 0} +!49 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll index 91de08a..9163166 100644 --- a/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll +++ b/test/CodeGen/ARM/2011-08-25-ldmia_ret.ll @@ -42,7 +42,7 @@ if.then: ; preds = %land.lhs.true ; If-convert the return ; CHECK: it ne ; Fold the CSR+return into a pop -; CHECK: pop {r4, r5, r6, r7, pc} +; CHECK: pop {r4, r5, r7, pc} sw.bb18: %call20 = tail call i32 @bar(i32 %in2) nounwind switch i32 %call20, label %sw.default56 [ diff --git a/test/CodeGen/ARM/2011-10-26-memset-inline.ll b/test/CodeGen/ARM/2011-10-26-memset-inline.ll index ff049c8..03614ed 100644 --- a/test/CodeGen/ARM/2011-10-26-memset-inline.ll +++ b/test/CodeGen/ARM/2011-10-26-memset-inline.ll @@ -10,8 +10,8 @@ target triple = "thumbv7-apple-ios5.0.0" ; CHECK-GENERIT-NEXT: strb ; CHECK-GENERIT-NEXT: strb ; CHECK-GENERIT-NEXT: strb -; CHECK-UNALIGNED: strb -; CHECK-UNALIGNED-NEXT: str +; CHECK-UNALIGNED: strb +; CHECK-UNALIGNED: str define void @foo(i8* nocapture %c) nounwind optsize { entry: call void @llvm.memset.p0i8.i64(i8* %c, i8 -1, i64 5, i32 1, i1 false) diff --git a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll index f563eee..850c511 100644 --- a/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll +++ b/test/CodeGen/ARM/2011-10-26-memset-with-neon.ll @@ -1,8 +1,8 @@ ; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s ; Trigger multiple NEON stores. -; CHECK: vst1.64 -; CHECK-NEXT: vst1.64 +; CHECK: vst1.64 +; CHECK: vst1.64 define void @f_0_40(i8* nocapture %c) nounwind optsize { entry: call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 40, i32 16, i1 false) diff --git a/test/CodeGen/ARM/2012-08-30-select.ll b/test/CodeGen/ARM/2012-08-30-select.ll index 2fd8df4..e78bbde 100644 --- a/test/CodeGen/ARM/2012-08-30-select.ll +++ b/test/CodeGen/ARM/2012-08-30-select.ll @@ -5,14 +5,11 @@ ;CHECK: it ne ;CHECK-NEXT: vmovne.i32 ;CHECK: bx -define <16 x i8> @select_s_v_v(i32 %avail, i8* %bar) { +define <16 x i8> @select_s_v_v(<16 x i8> %vec, i32 %avail) { entry: - %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1) %and = and i32 %avail, 1 %tobool = icmp eq i32 %and, 0 - %vld1. = select i1 %tobool, <16 x i8> %vld1, <16 x i8> zeroinitializer - ret <16 x i8> %vld1. + %ret = select i1 %tobool, <16 x i8> %vec, <16 x i8> zeroinitializer + ret <16 x i8> %ret } -declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* , i32 ) - diff --git a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll index 135b144..f812118 100644 --- a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll +++ b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s -; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4 +; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=CHECK-VFP4 define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind { ; CHECK-LABEL: muladd: diff --git a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll index 2eeebac..c4f5f54 100644 --- a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll +++ b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll @@ -1,4 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=CHECK-V8 %s +; RUN: llc < %s -mtriple=thumbv7 -arm-restrict-it | FileCheck -check-prefix=CHECK-V8 %s ; rdar://13782395 define i32 @t1(i32 %a, i32 %b, i8** %retaddr) { @@ -81,7 +83,7 @@ KBBlockZero.exit: ; preds = %bb2.i ; <rdar://problem/14379453> ; Hard-coded registers comes from the ABI. -; CHECK: wrapDistance: +; CHECK-LABEL: wrapDistance: ; CHECK: cmp r1, #59 ; CHECK-NEXT: itt le ; CHECK-NEXT: suble r0, r2, #1 @@ -100,6 +102,27 @@ KBBlockZero.exit: ; preds = %bb2.i ; CHECK: [[LABEL]]: ; CHECK-NEXT: subs r0, r1, r0 ; CHECK-NEXT: bx lr + +; CHECK-V8-LABEL: wrapDistance: +; CHECK-V8: cmp r1, #59 +; CHECK-V8-NEXT: bgt +; CHECK-V8-NEXT: %if.then +; CHECK-V8-NEXT: subs r0, r2, #1 +; CHECK-V8-NEXT: bx lr +; CHECK-V8-NEXT: %if.else +; CHECK-V8-NEXT: subs [[REG:r[0-9]+]], #120 +; CHECK-V8-NEXT: cmp [[REG]], r1 +; CHECK-V8-NEXT: bge +; CHECK-V8-NEXT: %if.else +; CHECK-V8-NEXT: cmp r0, #119 +; CHECK-V8-NEXT: bgt +; CHECK-V8-NEXT: %if.then4 +; CHECK-V8-NEXT: adds r0, r1, #1 +; CHECK-V8-NEXT: bx lr +; CHECK-V8-NEXT: %if.end5 +; CHECK-V8-NEXT: subs r0, r1, r0 +; CHECK-V8-NEXT: bx lr + define i32 @wrapDistance(i32 %tx, i32 %sx, i32 %w) { entry: %cmp = icmp slt i32 %sx, 60 diff --git a/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll b/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll new file mode 100644 index 0000000..defb946 --- /dev/null +++ b/test/CodeGen/ARM/2013-05-07-ByteLoadSameAddress.ll @@ -0,0 +1,64 @@ +; RUN: llc < %s -march=thumb -mattr=+v7,+thumb2 | FileCheck %s + +define i8 @f1(i8* %call1, i8* %call3, i32 %h, i32 %w, i32 %Width) { +; CHECK: f1: +entry: + %mul17 = mul nsw i32 %Width, %h + %add = add nsw i32 %mul17, %w + %sub19 = sub i32 %add, %Width + %sub20 = add i32 %sub19, -1 + %arrayidx21 = getelementptr inbounds i8* %call1, i32 %sub20 + %0 = load i8* %arrayidx21, align 1 + %conv22 = zext i8 %0 to i32 + %arrayidx25 = getelementptr inbounds i8* %call1, i32 %sub19 + %1 = load i8* %arrayidx25, align 1 + %conv26 = zext i8 %1 to i32 + %mul23189 = add i32 %conv26, %conv22 + %add30 = add i32 %sub19, 1 + %arrayidx31 = getelementptr inbounds i8* %call1, i32 %add30 + %2 = load i8* %arrayidx31, align 1 + %conv32 = zext i8 %2 to i32 +; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] +; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1] + %add28190 = add i32 %mul23189, %conv32 + %sub35 = add i32 %add, -1 + %arrayidx36 = getelementptr inbounds i8* %call1, i32 %sub35 + %3 = load i8* %arrayidx36, align 1 + %conv37 = zext i8 %3 to i32 + %add34191 = add i32 %add28190, %conv37 + %arrayidx40 = getelementptr inbounds i8* %call1, i32 %add + %4 = load i8* %arrayidx40, align 1 + %conv41 = zext i8 %4 to i32 + %mul42 = mul nsw i32 %conv41, 255 + %add44 = add i32 %add, 1 + %arrayidx45 = getelementptr inbounds i8* %call1, i32 %add44 + %5 = load i8* %arrayidx45, align 1 + %conv46 = zext i8 %5 to i32 +; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] +; CHECK-NEXT: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #1] + %add49 = add i32 %add, %Width + %sub50 = add i32 %add49, -1 + %arrayidx51 = getelementptr inbounds i8* %call1, i32 %sub50 + %6 = load i8* %arrayidx51, align 1 + %conv52 = zext i8 %6 to i32 + %arrayidx56 = getelementptr inbounds i8* %call1, i32 %add49 + %7 = load i8* %arrayidx56, align 1 + %conv57 = zext i8 %7 to i32 + %add61 = add i32 %add49, 1 + %arrayidx62 = getelementptr inbounds i8* %call1, i32 %add61 + %8 = load i8* %arrayidx62, align 1 + %conv63 = zext i8 %8 to i32 +; CHECK: ldrb r{{[0-9]*}}, [r{{[0-9]*}}, #-1] +; CHECK-NEXT: ldrb{{[.w]*}} r{{[0-9]*}}, [r{{[0-9]*}}, #1] + %tmp = add i32 %add34191, %conv46 + %tmp193 = add i32 %tmp, %conv52 + %tmp194 = add i32 %tmp193, %conv57 + %tmp195 = add i32 %tmp194, %conv63 + %tmp196 = mul i32 %tmp195, -28 + %add65 = add i32 %tmp196, %mul42 + %9 = lshr i32 %add65, 8 + %conv68 = trunc i32 %9 to i8 + %arrayidx69 = getelementptr inbounds i8* %call3, i32 %add + store i8 %conv68, i8* %arrayidx69, align 1 + ret i8 %conv68 +} diff --git a/test/CodeGen/ARM/2013-10-11-select-stalls.ll b/test/CodeGen/ARM/2013-10-11-select-stalls.ll new file mode 100644 index 0000000..33c0587 --- /dev/null +++ b/test/CodeGen/ARM/2013-10-11-select-stalls.ll @@ -0,0 +1,16 @@ +; REQUIRES: asserts +; RUN: llc < %s -mtriple=thumbv7-apple-ios -stats 2>&1 | not grep "Number of pipeline stalls" +; Evaluate the two vld1.8 instructions in separate MBB's, +; instead of stalling on one and conditionally overwriting its result. + +define <16 x i8> @multiselect(i32 %avail, i8* %foo, i8* %bar) { +entry: + %vld1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %foo, i32 1) + %vld2 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %bar, i32 1) + %and = and i32 %avail, 1 + %tobool = icmp eq i32 %and, 0 + %retv = select i1 %tobool, <16 x i8> %vld1, <16 x i8> %vld2 + ret <16 x i8> %retv +} + +declare <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* , i32 ) diff --git a/test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll b/test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll new file mode 100644 index 0000000..5a86477 --- /dev/null +++ b/test/CodeGen/ARM/2013-11-08-inline-asm-neon-array.ll @@ -0,0 +1,16 @@ +;RUN: not llc -mtriple=arm-linux-gnueabihf < %s 2>&1 | FileCheck %s + +; ModuleID = 'bug.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64" +target triple = "armv7--" + +%struct.uint8x8x4_t = type { [4 x <8 x i8>] } + +define void @foo() #0 { + %vsrc = alloca %struct.uint8x8x4_t, align 8 + %ptr = alloca i8; + %1 = call i8* asm sideeffect "vld4.u8 ${0:h}, [$1], $2", "=*w,=r,r,1"(%struct.uint8x8x4_t* %vsrc, i32 0, i8* %ptr) + ret void +} + +; CHECK: error: couldn't allocate output register for constraint 'w' diff --git a/test/CodeGen/ARM/a15-SD-dep.ll b/test/CodeGen/ARM/a15-SD-dep.ll index df921e0..019ff61 100644 --- a/test/CodeGen/ARM/a15-SD-dep.ll +++ b/test/CodeGen/ARM/a15-SD-dep.ll @@ -1,5 +1,5 @@ -; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=DISABLED %s -; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s +; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-DISABLED %s +; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=CHECK-ENABLED %s ; CHECK-ENABLED-LABEL: t1: ; CHECK-DISABLED-LABEL: t1: diff --git a/test/CodeGen/ARM/addrspacecast.ll b/test/CodeGen/ARM/addrspacecast.ll new file mode 100644 index 0000000..2e98ba5 --- /dev/null +++ b/test/CodeGen/ARM/addrspacecast.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -march=arm + +; Check that codegen for an addrspace cast succeeds without error. +define <4 x i32 addrspace(1)*> @f (<4 x i32*> %x) { + %1 = addrspacecast <4 x i32*> %x to <4 x i32 addrspace(1)*> + ret <4 x i32 addrspace(1)*> %1 +} diff --git a/test/CodeGen/ARM/aliases.ll b/test/CodeGen/ARM/aliases.ll index d668334..f55ae10 100644 --- a/test/CodeGen/ARM/aliases.ll +++ b/test/CodeGen/ARM/aliases.ll @@ -1,15 +1,30 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi -o %t -; RUN: grep " = " %t | count 5 -; RUN: grep globl %t | count 4 -; RUN: grep weak %t | count 1 +; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -@bar = external global i32 +; CHECK: .globl test + +; CHECK: .globl foo1 +; CHECK: foo1 = bar + +; CHECK: .globl foo2 +; CHECK: foo2 = bar + +; CHECK: .weak bar_f +; CHECK: bar_f = foo_f + +; CHECK: bar_i = bar + +; CHECK: .globl A +; CHECK: A = bar + +@bar = global i32 42 @foo1 = alias i32* @bar @foo2 = alias i32* @bar %FunTy = type i32() -declare i32 @foo_f() +define i32 @foo_f() { + ret i32 0 +} @bar_f = alias weak %FunTy* @foo_f @bar_i = alias internal i32* @bar diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll index 0762070..88d797e 100644 --- a/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck -check-prefix=ARM %s ; RUN: llc < %s -march=thumb | FileCheck -check-prefix=THUMB %s ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck -check-prefix=T2 %s +; RUN: llc < %s -mtriple=thumbv8 | FileCheck -check-prefix=V8 %s ; FIXME: The -march=thumb test doesn't change if -disable-peephole is specified. @@ -39,6 +40,17 @@ tailrecurse: ; preds = %sw.bb, %entry br i1 %tst, label %sw.bb, label %tailrecurse.switch tailrecurse.switch: ; preds = %tailrecurse +; V8-LABEL: %tailrecurse.switch +; V8: cmp +; V8-NEXT: beq +; V8-NEXT: %tailrecurse.switch +; V8: cmp +; V8-NEXT: beq +; V8-NEXT: %tailrecurse.switch +; V8: cmp +; V8-NEXT: beq +; V8-NEXT: b +; The trailing space in the last line checks that the branch is unconditional switch i32 %and, label %sw.epilog [ i32 1, label %sw.bb i32 3, label %sw.bb6 @@ -73,6 +85,7 @@ sw.epilog: ; preds = %tailrecurse.switch ; ARM: bar ; THUMB: bar ; T2: bar +; V8-LABEL: bar: define internal zeroext i8 @bar(%struct.S* %x, %struct.S* nocapture %y) nounwind readonly { entry: %0 = getelementptr inbounds %struct.S* %x, i32 0, i32 1, i32 0 @@ -81,22 +94,32 @@ entry: ; ARM: ands ; THUMB: ands ; T2: ands +; V8: ands +; V8-NEXT: beq %3 = and i32 %2, 112 %4 = icmp eq i32 %3, 0 br i1 %4, label %return, label %bb bb: ; preds = %entry +; V8-NEXT: %bb %5 = getelementptr inbounds %struct.S* %y, i32 0, i32 1, i32 0 %6 = load i8* %5, align 1 %7 = zext i8 %6 to i32 ; ARM: andsne ; THUMB: ands ; T2: andsne +; V8: ands +; V8-NEXT: beq %8 = and i32 %7, 112 %9 = icmp eq i32 %8, 0 br i1 %9, label %return, label %bb2 bb2: ; preds = %bb +; V8-NEXT: %bb2 +; V8-NEXT: cmp +; V8-NEXT: it ne +; V8-NEXT: cmpne +; V8-NEXT: bne %10 = icmp eq i32 %3, 16 %11 = icmp eq i32 %8, 16 %or.cond = or i1 %10, %11 diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index 8ec829c..0477d4f 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s -; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB +; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-THUMB define i64 @test1(i64* %ptr, i64 %val) { ; CHECK-LABEL: test1: @@ -175,28 +175,14 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { ret i64 %r } -; Compiles down to cmpxchg -; FIXME: Should compile to a single ldrexd +; Compiles down to a single ldrexd define i64 @test8(i64* %ptr) { ; CHECK-LABEL: test8: ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] -; CHECK: cmp [[REG1]] -; CHECK: cmpeq [[REG2]] -; CHECK: bne -; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} -; CHECK: cmp -; CHECK: bne ; CHECK: dmb {{ish$}} ; CHECK-THUMB-LABEL: test8: ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] -; CHECK-THUMB: cmp [[REG1]] -; CHECK-THUMB: it eq -; CHECK-THUMB: cmpeq [[REG2]] -; CHECK-THUMB: bne -; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}} -; CHECK-THUMB: cmp -; CHECK-THUMB: bne ; CHECK-THUMB: dmb {{ish$}} %r = load atomic i64* %ptr seq_cst, align 8 diff --git a/test/CodeGen/ARM/atomic-load-store.ll b/test/CodeGen/ARM/atomic-load-store.ll index 476b3dd..53c7184 100644 --- a/test/CodeGen/ARM/atomic-load-store.ll +++ b/test/CodeGen/ARM/atomic-load-store.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=thumbv7-apple-ios | FileCheck %s -check-prefix=THUMBTWO +; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s -check-prefix=THUMBTWO ; RUN: llc < %s -mtriple=thumbv6-apple-ios | FileCheck %s -check-prefix=THUMBONE ; RUN llc < %s -mtriple=armv4-apple-ios | FileCheck %s -check-prefix=ARMV4 diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll index 6e6b363..9a79c9f 100644 --- a/test/CodeGen/ARM/atomic-op.ll +++ b/test/CodeGen/ARM/atomic-op.ll @@ -1,5 +1,7 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1 +; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-T1 define void @func(i32 %argc, i8** %argv) nounwind { entry: @@ -24,78 +26,93 @@ entry: ; CHECK: ldrex ; CHECK: add ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_add_4 %0 = atomicrmw add i32* %val1, i32 %tmp monotonic store i32 %0, i32* %old ; CHECK: ldrex ; CHECK: sub ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_sub_4 %1 = atomicrmw sub i32* %val2, i32 30 monotonic store i32 %1, i32* %old ; CHECK: ldrex ; CHECK: add ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_add_4 %2 = atomicrmw add i32* %val2, i32 1 monotonic store i32 %2, i32* %old ; CHECK: ldrex ; CHECK: sub ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_sub_4 %3 = atomicrmw sub i32* %val2, i32 1 monotonic store i32 %3, i32* %old ; CHECK: ldrex ; CHECK: and ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_and_4 %4 = atomicrmw and i32* %andt, i32 4080 monotonic store i32 %4, i32* %old ; CHECK: ldrex ; CHECK: or ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_or_4 %5 = atomicrmw or i32* %ort, i32 4080 monotonic store i32 %5, i32* %old ; CHECK: ldrex ; CHECK: eor ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_xor_4 %6 = atomicrmw xor i32* %xort, i32 4080 monotonic store i32 %6, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_min_4 %7 = atomicrmw min i32* %val2, i32 16 monotonic store i32 %7, i32* %old %neg = sub i32 0, 1 ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_min_4 %8 = atomicrmw min i32* %val2, i32 %neg monotonic store i32 %8, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_max_4 %9 = atomicrmw max i32* %val2, i32 1 monotonic store i32 %9, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_max_4 %10 = atomicrmw max i32* %val2, i32 0 monotonic store i32 %10, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umin_4 %11 = atomicrmw umin i32* %val2, i32 16 monotonic store i32 %11, i32* %old %uneg = sub i32 0, 1 ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umin_4 %12 = atomicrmw umin i32* %val2, i32 %uneg monotonic store i32 %12, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umax_4 %13 = atomicrmw umax i32* %val2, i32 1 monotonic store i32 %13, i32* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umax_4 %14 = atomicrmw umax i32* %val2, i32 0 monotonic store i32 %14, i32* %old @@ -110,22 +127,26 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umin_2 %0 = atomicrmw umin i16* %val, i16 16 monotonic store i16 %0, i16* %old %uneg = sub i16 0, 1 ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umin_2 %1 = atomicrmw umin i16* %val, i16 %uneg monotonic store i16 %1, i16* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umax_2 %2 = atomicrmw umax i16* %val, i16 1 monotonic store i16 %2, i16* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umax_2 %3 = atomicrmw umax i16* %val, i16 0 monotonic store i16 %3, i16* %old ret void @@ -139,22 +160,26 @@ entry: ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umin_1 %0 = atomicrmw umin i8* %val, i8 16 monotonic store i8 %0, i8* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umin_1 %uneg = sub i8 0, 1 %1 = atomicrmw umin i8* %val, i8 %uneg monotonic store i8 %1, i8* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umax_1 %2 = atomicrmw umax i8* %val, i8 1 monotonic store i8 %2, i8* %old ; CHECK: ldrex ; CHECK: cmp ; CHECK: strex + ; CHECK-T1: blx ___sync_fetch_and_umax_1 %3 = atomicrmw umax i8* %val, i8 0 monotonic store i8 %3, i8* %old ret void diff --git a/test/CodeGen/ARM/atomic-ops-v8.ll b/test/CodeGen/ARM/atomic-ops-v8.ll new file mode 100644 index 0000000..3f93929 --- /dev/null +++ b/test/CodeGen/ARM/atomic-ops-v8.ll @@ -0,0 +1,1344 @@ +; RUN: llc -mtriple=armv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=thumbv8-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s + +@var8 = global i8 0 +@var16 = global i16 0 +@var32 = global i32 0 +@var64 = global i64 0 + +define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_add_i8: + %old = atomicrmw add i8* @var8, i8 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_add_i16: + %old = atomicrmw add i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_add_i32: + %old = atomicrmw add i32* @var32, i32 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: add{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_add_i64: + %old = atomicrmw add i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: adds [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: adc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 +; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_sub_i8: + %old = atomicrmw sub i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_sub_i16: + %old = atomicrmw sub i16* @var16, i16 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_sub_i32: + %old = atomicrmw sub i32* @var32, i32 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: sub{{s?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: strex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_sub_i64: + %old = atomicrmw sub i64* @var64, i64 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: subs [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: sbc{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 +; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_and_i8: + %old = atomicrmw and i8* @var8, i8 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_and_i16: + %old = atomicrmw and i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_and_i32: + %old = atomicrmw and i32* @var32, i32 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: and{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_and_i64: + %old = atomicrmw and i64* @var64, i64 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: and{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: and{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 +; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_or_i8: + %old = atomicrmw or i8* @var8, i8 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_or_i16: + %old = atomicrmw or i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_or_i32: + %old = atomicrmw or i32* @var32, i32 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: orr{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: strex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_or_i64: + %old = atomicrmw or i64* @var64, i64 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: orr{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: orr{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 +; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_xor_i8: + %old = atomicrmw xor i8* @var8, i8 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_xor_i16: + %old = atomicrmw xor i16* @var16, i16 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_xor_i32: + %old = atomicrmw xor i32* @var32, i32 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: eor{{(\.w)?}} [[NEW:r[0-9]+]], r[[OLD]], r0 +; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], [[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_xor_i64: + %old = atomicrmw xor i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: eor{{(\.w)?}} [[NEW1:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: eor{{(\.w)?}} [[NEW2:r[0-9]+]], r[[OLD2]], r1 +; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], [[NEW1]], [[NEW2]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_xchg_i8: + %old = atomicrmw xchg i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r0, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_xchg_i16: + %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r0, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_xchg_i32: + %old = atomicrmw xchg i32* @var32, i32 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r0, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_xchg_i64: + %old = atomicrmw xchg i64* @var64, i64 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_min_i8: + %old = atomicrmw min i8* @var8, i8 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK-NEXT: sxtb r[[OLDX:[0-9]+]], r[[OLD]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp r[[OLDX]], r0 +; Thumb mode: it ge +; CHECK: movge r[[OLDX]], r0 +; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_min_i16: + %old = atomicrmw min i16* @var16, i16 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp r[[OLDX]], r0 +; Thumb mode: it ge +; CHECK: movge r[[OLDX]], r0 +; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_min_i32: + %old = atomicrmw min i32* @var32, i32 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 +; CHECK-NEXT: cmp r[[OLD]], r0 +; Thumb mode: it lt +; CHECK: movlt r[[NEW]], r[[OLD]] +; CHECK-NEXT: strex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_min_i64: + %old = atomicrmw min i64* @var64, i64 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: subs [[NEW:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: sbcs{{(\.w)?}} [[NEW]], r[[OLD2]], r1 +; CHECK-NEXT: blt .LBB{{[0-9]+}}_3 +; CHECK-NEXT: BB#2: +; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_max_i8: + %old = atomicrmw max i8* @var8, i8 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK-NEXT: sxtb r[[OLDX:[0-9]+]], r[[OLD]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp r[[OLDX]], r0 +; Thumb mode: it le +; CHECK: movle r[[OLDX]], r0 +; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_max_i16: + %old = atomicrmw max i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] +; CHECK-NEXT: sxth r[[OLDX:[0-9]+]], r[[OLD]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp r[[OLDX]], r0 +; Thumb mode: it le +; CHECK: movle r[[OLDX]], r0 +; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[OLDX]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_max_i32: + %old = atomicrmw max i32* @var32, i32 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 +; CHECK-NEXT: cmp r[[OLD]], r0 +; Thumb mode: it gt +; CHECK: movgt r[[NEW]], r[[OLD]] +; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_max_i64: + %old = atomicrmw max i64* @var64, i64 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: subs [[NEW:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: sbcs{{(\.w)?}} [[NEW]], r[[OLD2]], r1 +; CHECK-NEXT: bge .LBB{{[0-9]+}}_3 +; CHECK-NEXT: BB#2: +; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_umin_i8: + %old = atomicrmw umin i8* @var8, i8 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 +; CHECK-NEXT: cmp r[[OLD]], r0 +; Thumb mode: it lo +; CHECK: movlo r[[NEW]], r[[OLD]] +; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_umin_i16: + %old = atomicrmw umin i16* @var16, i16 %offset acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 +; CHECK-NEXT: cmp r[[OLD]], r0 +; Thumb mode: it lo +; CHECK: movlo r[[NEW]], r[[OLD]] +; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_umin_i32: + %old = atomicrmw umin i32* @var32, i32 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 +; CHECK-NEXT: cmp r[[OLD]], r0 +; Thumb mode: it lo +; CHECK: movlo r[[NEW]], r[[OLD]] +; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_umin_i64: + %old = atomicrmw umin i64* @var64, i64 %offset acq_rel +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: subs [[NEW:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: sbcs{{(\.w)?}} [[NEW]], r[[OLD2]], r1 +; CHECK-NEXT: blo .LBB{{[0-9]+}}_3 +; CHECK-NEXT: BB#2: +; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_umax_i8: + %old = atomicrmw umax i8* @var8, i8 %offset acq_rel +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 +; CHECK-NEXT: cmp r[[OLD]], r0 +; Thumb mode: it hi +; CHECK: movhi r[[NEW]], r[[OLD]] +; CHECK-NEXT: stlexb [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_umax_i16: + %old = atomicrmw umax i16* @var16, i16 %offset monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 +; CHECK-NEXT: cmp r[[OLD]], r0 +; Thumb mode: it hi +; CHECK: movhi r[[NEW]], r[[OLD]] +; CHECK-NEXT: strexh [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_umax_i32: + %old = atomicrmw umax i32* @var32, i32 %offset seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: mov r[[NEW:[0-9]+]], r0 +; CHECK-NEXT: cmp r[[OLD]], r0 +; Thumb mode: it hi +; CHECK: movhi r[[NEW]], r[[OLD]] +; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r[[NEW]], [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { +; CHECK-LABEL: test_atomic_load_umax_i64: + %old = atomicrmw umax i64* @var64, i64 %offset release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexd r[[OLD1:[0-9]+]], r[[OLD2:[0-9]+]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: subs [[NEW:r[0-9]+]], r[[OLD1]], r0 +; CHECK-NEXT: sbcs{{(\.w)?}} [[NEW]], r[[OLD2]], r1 +; CHECK-NEXT: bhs .LBB{{[0-9]+}}_3 +; CHECK-NEXT: BB#2: +; CHECK-NEXT: stlexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD1]] +; CHECK-NEXT: mov r1, r[[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { +; CHECK-LABEL: test_atomic_cmpxchg_i8: + %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexb r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 +; CHECK-NEXT: BB#2: + ; As above, r1 is a reasonable guess. +; CHECK-NEXT: strexb [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i8 %old +} + +define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { +; CHECK-LABEL: test_atomic_cmpxchg_i16: + %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK: movt r[[ADDR]], :upper16:var16 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldaexh r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 +; CHECK-NEXT: BB#2: + ; As above, r1 is a reasonable guess. +; CHECK-NEXT: stlexh [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i16 %old +} + +define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { +; CHECK-LABEL: test_atomic_cmpxchg_i32: + %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var32 +; CHECK: movt r[[ADDR]], :upper16:var32 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrex r[[OLD:[0-9]+]], [r[[ADDR]]] + ; r0 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp r[[OLD]], r0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 +; CHECK-NEXT: BB#2: + ; As above, r1 is a reasonable guess. +; CHECK-NEXT: stlex [[STATUS:r[0-9]+]], r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, r[[OLD]] + ret i32 %old +} + +define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { +; CHECK-LABEL: test_atomic_cmpxchg_i64: + %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: +; CHECK-NEXT: ldrexd [[OLD1:r[0-9]+|lr]], [[OLD2:r[0-9]+|lr]], [r[[ADDR]]] + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK-NEXT: cmp [[OLD1]], r0 +; Thumb mode: it eq +; CHECK: cmpeq [[OLD2]], r1 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_3 +; CHECK-NEXT: BB#2: + ; As above, r2, r3 is a reasonable guess. +; CHECK-NEXT: strexd [[STATUS:r[0-9]+]], r2, r3, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + +; CHECK: mov r0, [[OLD1]] +; CHECK-NEXT: mov r1, [[OLD2]] + ret i64 %old +} + +define i8 @test_atomic_load_monotonic_i8() nounwind { +; CHECK-LABEL: test_atomic_load_monotonic_i8: + %val = load atomic i8* @var8 monotonic, align 1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK: ldrb r0, [r[[ADDR]]] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + + ret i8 %val +} + +define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { +; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8: + %addr_int = add i64 %base, %off + %addr = inttoptr i64 %addr_int to i8* + + %val = load atomic i8* %addr monotonic, align 1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: ldrb r0, [r0, r2] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + + ret i8 %val +} + +define i8 @test_atomic_load_acquire_i8() nounwind { +; CHECK-LABEL: test_atomic_load_acquire_i8: + %val = load atomic i8* @var8 acquire, align 1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: ldab r0, [r[[ADDR]]] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + ret i8 %val +} + +define i8 @test_atomic_load_seq_cst_i8() nounwind { +; CHECK-LABEL: test_atomic_load_seq_cst_i8: + %val = load atomic i8* @var8 seq_cst, align 1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: ldab r0, [r[[ADDR]]] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + ret i8 %val +} + +define i16 @test_atomic_load_monotonic_i16() nounwind { +; CHECK-LABEL: test_atomic_load_monotonic_i16: + %val = load atomic i16* @var16 monotonic, align 2 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movt r[[ADDR]], :upper16:var16 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: ldrh r0, [r[[ADDR]]] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + + ret i16 %val +} + +define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind { +; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32: + %addr_int = add i64 %base, %off + %addr = inttoptr i64 %addr_int to i32* + + %val = load atomic i32* %addr monotonic, align 4 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: ldr r0, [r0, r2] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + + ret i32 %val +} + +define i64 @test_atomic_load_seq_cst_i64() nounwind { +; CHECK-LABEL: test_atomic_load_seq_cst_i64: + %val = load atomic i64* @var64 seq_cst, align 8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movt r[[ADDR]], :upper16:var64 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: ldaexd r0, r1, [r[[ADDR]]] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + ret i64 %val +} + +define void @test_atomic_store_monotonic_i8(i8 %val) nounwind { +; CHECK-LABEL: test_atomic_store_monotonic_i8: + store atomic i8 %val, i8* @var8 monotonic, align 1 +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK: strb r0, [r[[ADDR]]] + + ret void +} + +define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind { +; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8: + + %addr_int = add i64 %base, %off + %addr = inttoptr i64 %addr_int to i8* + + store atomic i8 %val, i8* %addr monotonic, align 1 +; CHECK: ldrb{{(\.w)?}} [[VAL:r[0-9]+]], [sp] +; CHECK: strb [[VAL]], [r0, r2] + + ret void +} + +define void @test_atomic_store_release_i8(i8 %val) nounwind { +; CHECK-LABEL: test_atomic_store_release_i8: + store atomic i8 %val, i8* @var8 release, align 1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: stlb r0, [r[[ADDR]]] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + ret void +} + +define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { +; CHECK-LABEL: test_atomic_store_seq_cst_i8: + store atomic i8 %val, i8* @var8 seq_cst, align 1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movt r[[ADDR]], :upper16:var8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: stlb r0, [r[[ADDR]]] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + ret void +} + +define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { +; CHECK-LABEL: test_atomic_store_monotonic_i16: + store atomic i16 %val, i16* @var16 monotonic, align 2 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movt r[[ADDR]], :upper16:var16 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: strh r0, [r[[ADDR]]] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + ret void +} + +define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind { +; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32: + + %addr_int = add i64 %base, %off + %addr = inttoptr i64 %addr_int to i32* + + store atomic i32 %val, i32* %addr monotonic, align 4 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: ldr [[VAL:r[0-9]+]], [sp] +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: str [[VAL]], [r0, r2] +; CHECK-NOT: dmb +; CHECK-NOT: mcr + + ret void +} + +define void @test_atomic_store_release_i64(i64 %val) nounwind { +; CHECK-LABEL: test_atomic_store_release_i64: + store atomic i64 %val, i64* @var64 release, align 8 +; CHECK-NOT: dmb +; CHECK-NOT: mcr +; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var64 +; CHECK: movt r[[ADDR]], :upper16:var64 + +; CHECK: .LBB{{[0-9]+}}_1: + ; r0, r1 below is a reasonable guess but could change: it certainly comes into the + ; function there. +; CHECK: stlexd [[STATUS:r[0-9]+]], r0, r1, [r[[ADDR]]] +; CHECK-NEXT: cmp [[STATUS]], #0 +; CHECK-NEXT: bne .LBB{{[0-9]+}}_1 +; CHECK-NOT: dmb +; CHECK-NOT: mcr + + ret void +} + +define i32 @not.barriers(i32* %var, i1 %cond) { +; CHECK-LABEL: not.barriers: + br i1 %cond, label %atomic_ver, label %simple_ver +simple_ver: + %oldval = load i32* %var + %newval = add nsw i32 %oldval, -1 + store i32 %newval, i32* %var + br label %somewhere +atomic_ver: + fence seq_cst + %val = atomicrmw add i32* %var, i32 -1 monotonic + fence seq_cst + br label %somewhere +; CHECK: dmb +; CHECK: ldrex +; CHECK: dmb + ; The key point here is that the second dmb isn't immediately followed by the + ; simple_ver basic block, which LLVM attempted to do when DMB had been marked + ; with isBarrier. For now, look for something that looks like "somewhere". +; CHECK-NEXT: mov +somewhere: + %combined = phi i32 [ %val, %atomic_ver ], [ %newval, %simple_ver] + ret i32 %combined +} diff --git a/test/CodeGen/ARM/build-attributes-encoding.s b/test/CodeGen/ARM/build-attributes-encoding.s new file mode 100644 index 0000000..5ad51b2 --- /dev/null +++ b/test/CodeGen/ARM/build-attributes-encoding.s @@ -0,0 +1,85 @@ +// This tests that ARM attributes are properly encoded. + +// RUN: llvm-mc < %s -triple=arm-linux-gnueabi -filetype=obj -o - \ +// RUN: | llvm-readobj -s -sd | FileCheck %s + +// Tag_CPU_name (=5) +.cpu Cortex-A8 + +// Tag_CPU_arch (=6) +.eabi_attribute 6, 10 + +// Tag_arch_profile (=7) +.eabi_attribute 7, 'A' + +// Tag_ARM_ISA_use (=8) +.eabi_attribute 8, 1 + +// Tag_THUMB_ISA_use (=9) +.eabi_attribute 9, 2 + +// Tag_FP_arch (=10) +.fpu vfpv3 + +// Tag_Advanced_SIMD_arch (=12) +.eabi_attribute 12, 2 + +// Tag_ABI_FP_denormal (=20) +.eabi_attribute 20, 1 + +// Tag_ABI_FP_exceptions (=21) +.eabi_attribute 21, 1 + +// Tag_ABI_FP_number_model (=23) +.eabi_attribute 23, 1 + +// Tag_ABI_align_needed (=24) +.eabi_attribute 24, 1 + +// Tag_ABI_align_preserved (=25) +.eabi_attribute 25, 1 + +// Tag_ABI_HardFP_use (=27) +.eabi_attribute 27, 0 + +// Tag_ABI_VFP_args (=28) +.eabi_attribute 28, 1 + +// Tag_FP_HP_extension (=36) +.eabi_attribute 36, 1 + +// Tag_MPextension_use (=42) +.eabi_attribute 42, 1 + +// Tag_DIV_use (=44) +.eabi_attribute 44, 2 + +// Tag_Virtualization_use (=68) +.eabi_attribute 68, 3 + +// Check that values > 128 are encoded properly +.eabi_attribute 110, 160 + +// Check that tags > 128 are encoded properly +.eabi_attribute 129, 1 +.eabi_attribute 250, 1 + +// CHECK: Section { +// CHECK: Name: .ARM.attributes +// CHECK-NEXT: Type: SHT_ARM_ATTRIBUTES +// CHECK-NEXT: Flags [ (0x0) +// CHECK-NEXT: ] +// CHECK-NEXT: Address: 0x0 +// CHECK-NEXT: Offset: 0x34 +// CHECK-NEXT: Size: 70 +// CHECK-NEXT: Link: 0 +// CHECK-NEXT: Info: 0 +// CHECK-NEXT: AddressAlignment: 1 +// CHECK-NEXT: EntrySize: 0 +// CHECK-NEXT: SectionData ( +// CHECK-NEXT: 0000: 41450000 00616561 62690001 3B000000 +// CHECK-NEXT: 0010: 05434F52 5445582D 41380006 0A074108 +// CHECK-NEXT: 0020: 0109020A 030C0214 01150117 01180119 +// CHECK-NEXT: 0030: 011B001C 0124012A 012C0244 036EA001 +// CHECK-NEXT: 0040: 810101FA 0101 +// CHECK-NEXT: ) diff --git a/test/CodeGen/ARM/byval_load_align.ll b/test/CodeGen/ARM/byval_load_align.ll new file mode 100644 index 0000000..2c0910c --- /dev/null +++ b/test/CodeGen/ARM/byval_load_align.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -mtriple thumbv7-apple-ios -O1 | FileCheck %s + +; rdar://15144402 +; Make sure we don't assume 4-byte alignment when loading from a byval argument +; with alignment of 2. +; CHECK: ldr r1, [r[[REG:[0-9]+]]] +; CHECK: ldr r2, [r[[REG]], #4] +; CHECK: ldr r3, [r[[REG]], #8] +; CHECK-NOT: ldm +; CHECK: .align 1 @ @sID + +%struct.ModuleID = type { [32 x i8], [32 x i8], i16 } + +@sID = internal constant %struct.ModuleID { [32 x i8] c"TEST\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", [32 x i8] c"1.0\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00", i16 23 }, align 2 + +; Function Attrs: nounwind ssp +define void @Client() #0 { +entry: + tail call void @Logger(i8 signext 97, %struct.ModuleID* byval @sID) #2 + ret void +} + +declare void @Logger(i8 signext, %struct.ModuleID* byval) #1 + +attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind } diff --git a/test/CodeGen/ARM/coalesce-dbgvalue.ll b/test/CodeGen/ARM/coalesce-dbgvalue.ll index d4be6ee..86106a0 100644 --- a/test/CodeGen/ARM/coalesce-dbgvalue.ll +++ b/test/CodeGen/ARM/coalesce-dbgvalue.ll @@ -17,7 +17,7 @@ target triple = "thumbv7-apple-ios3.0.0" ; Function Attrs: nounwind ssp define i32 @pr16110() #0 { for.cond1.preheader: - store i32 0, i32* @c, align 4, !dbg !21, !tbaa !23 + store i32 0, i32* @c, align 4, !dbg !21 br label %for.cond1.outer, !dbg !26 for.cond1: ; preds = %for.end9, %for.cond1.outer @@ -26,9 +26,9 @@ for.cond1: ; preds = %for.end9, %for.cond br i1 %cmp, label %for.body2, label %for.end9, !dbg !26 for.body2: ; preds = %for.cond1 - store i32 %storemerge11, i32* @b, align 4, !dbg !26, !tbaa !23 + store i32 %storemerge11, i32* @b, align 4, !dbg !26 tail call void @llvm.dbg.value(metadata !27, i64 0, metadata !11), !dbg !28 - %0 = load i64* @a, align 8, !dbg !29, !tbaa !30 + %0 = load i64* @a, align 8, !dbg !29 %xor = xor i64 %0, %e.1.ph, !dbg !29 %conv3 = trunc i64 %xor to i32, !dbg !29 tail call void @llvm.dbg.value(metadata !{i32 %conv3}, i64 0, metadata !10), !dbg !29 @@ -44,7 +44,7 @@ land.end: ; preds = %land.rhs, %for.body %1 = phi i1 [ false, %for.body2 ], [ %tobool5, %land.rhs ] %land.ext = zext i1 %1 to i32 %call6 = tail call i32 bitcast (i32 (...)* @fn2 to i32 (i32, i32*)*)(i32 %land.ext, i32* null) #3 - %2 = load i32* @b, align 4, !dbg !26, !tbaa !23 + %2 = load i32* @b, align 4, !dbg !26 %inc8 = add nsw i32 %2, 1, !dbg !26 %phitmp = and i64 %xor, 4294967295, !dbg !26 br label %for.cond1.outer, !dbg !26 @@ -52,7 +52,7 @@ land.end: ; preds = %land.rhs, %for.body for.cond1.outer: ; preds = %land.end, %for.cond1.preheader %storemerge11.ph = phi i32 [ %inc8, %land.end ], [ 0, %for.cond1.preheader ] %e.1.ph = phi i64 [ %phitmp, %land.end ], [ 0, %for.cond1.preheader ] - %3 = load i32* @d, align 4, !dbg !31, !tbaa !23 + %3 = load i32* @d, align 4, !dbg !31 %tobool10 = icmp eq i32 %3, 0, !dbg !31 br label %for.cond1 @@ -60,7 +60,7 @@ for.end9: ; preds = %for.cond1 br i1 %tobool10, label %if.end, label %for.cond1, !dbg !31 if.end: ; preds = %for.end9 - store i32 %storemerge11, i32* @b, align 4, !dbg !26, !tbaa !23 + store i32 %storemerge11, i32* @b, align 4, !dbg !26 ret i32 0, !dbg !32 } @@ -71,12 +71,13 @@ declare i32 @fn3(...) #1 ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata) #2 -attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } !llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!33} !0 = metadata !{i32 786449, metadata !1, i32 12, metadata !"clang version 3.4 (trunk 182024) (llvm/trunk 182023)", i1 true, metadata !"", i32 0, metadata !2, metadata !2, metadata !3, metadata !15, metadata !2, metadata !""} ; [ DW_TAG_compile_unit ] [/d/b/pr16110.c] [DW_LANG_C99] !1 = metadata !{metadata !"pr16110.c", metadata !"/d/b"} @@ -84,7 +85,7 @@ attributes #3 = { nounwind } !3 = metadata !{metadata !4} !4 = metadata !{i32 786478, metadata !1, metadata !5, metadata !"pr16110", metadata !"pr16110", metadata !"", i32 7, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i32 0, i1 true, i32 ()* @pr16110, null, null, metadata !9, i32 7} ; [ DW_TAG_subprogram ] [line 7] [def] [pr16110] !5 = metadata !{i32 786473, metadata !1} ; [ DW_TAG_file_type ] [/d/b/pr16110.c] -!6 = metadata !{i32 786453, i32 0, i32 0, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!6 = metadata !{i32 786453, i32 0, null, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !7 = metadata !{metadata !8} !8 = metadata !{i32 786468, null, null, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] !9 = metadata !{metadata !10, metadata !11} @@ -101,13 +102,10 @@ attributes #3 = { nounwind } !20 = metadata !{i32 786484, i32 0, null, metadata !"d", metadata !"d", metadata !"", metadata !5, i32 4, metadata !8, i32 0, i32 1, i32* @d, null} ; [ DW_TAG_variable ] [d] [line 4] [def] !21 = metadata !{i32 10, i32 0, metadata !22, null} !22 = metadata !{i32 786443, metadata !1, metadata !4, i32 10, i32 0, i32 0} ; [ DW_TAG_lexical_block ] [/d/b/pr16110.c] -!23 = metadata !{metadata !"int", metadata !24} -!24 = metadata !{metadata !"omnipotent char", metadata !25} -!25 = metadata !{metadata !"Simple C/C++ TBAA"} !26 = metadata !{i32 12, i32 0, metadata !13, null} !27 = metadata !{i32* null} !28 = metadata !{i32 13, i32 0, metadata !12, null} !29 = metadata !{i32 14, i32 0, metadata !12, null} -!30 = metadata !{metadata !"long long", metadata !24} !31 = metadata !{i32 16, i32 0, metadata !4, null} !32 = metadata !{i32 18, i32 0, metadata !4, null} +!33 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/constantfp.ll b/test/CodeGen/ARM/constantfp.ll new file mode 100644 index 0000000..974bdd7 --- /dev/null +++ b/test/CodeGen/ARM/constantfp.ll @@ -0,0 +1,68 @@ +; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=swift %s -o - | FileCheck %s +; RUN: llc -mtriple=armv7 -mattr=+neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEONFP %s +; RUN: llc -mtriple=armv7 -mattr=-neon -mcpu=cortex-a8 %s -o - | FileCheck --check-prefix=CHECK-NONEON %s + +define arm_aapcs_vfpcc float @test_vmov_f32() { +; CHECK-LABEL: test_vmov_f32: +; CHECK: vmov.f32 d0, #1.0 + +; CHECK-NONEONFP: vmov.f32 s0, #1.0 + ret float 1.0 +} + +define arm_aapcs_vfpcc float @test_vmov_imm() { +; CHECK-LABEL: test_vmov_imm: +; CHECK: vmov.i32 d0, #0 + +; CHECK-NONEON-LABEL: test_vmov_imm: +; CHECK_NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} + ret float 0.0 +} + +define arm_aapcs_vfpcc float @test_vmvn_imm() { +; CHECK-LABEL: test_vmvn_imm: +; CHECK: vmvn.i32 d0, #0xb0000000 + +; CHECK-NONEON-LABEL: test_vmvn_imm: +; CHECK_NONEON: vldr s0, {{.?LCPI[0-9]+_[0-9]+}} + ret float 8589934080.0 +} + +define arm_aapcs_vfpcc double @test_vmov_f64() { +; CHECK-LABEL: test_vmov_f64: +; CHECK: vmov.f64 d0, #1.0 + +; CHECK-NONEON-LABEL: test_vmov_f64: +; CHECK_NONEON: vmov.f64 d0, #1.0 + + ret double 1.0 +} + +define arm_aapcs_vfpcc double @test_vmov_double_imm() { +; CHECK-LABEL: test_vmov_double_imm: +; CHECK: vmov.i32 d0, #0 + +; CHECK-NONEON-LABEL: test_vmov_double_imm: +; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} + ret double 0.0 +} + +define arm_aapcs_vfpcc double @test_vmvn_double_imm() { +; CHECK-LABEL: test_vmvn_double_imm: +; CHECK: vmvn.i32 d0, #0xb0000000 + +; CHECK-NONEON-LABEL: test_vmvn_double_imm: +; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} + ret double 0x4fffffff4fffffff +} + +; Make sure we don't ignore the high half of 64-bit values when deciding whether +; a vmov/vmvn is possible. +define arm_aapcs_vfpcc double @test_notvmvn_double_imm() { +; CHECK-LABEL: test_notvmvn_double_imm: +; CHECK: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} + +; CHECK-NONEON-LABEL: test_notvmvn_double_imm: +; CHECK_NONEON: vldr d0, {{.?LCPI[0-9]+_[0-9]+}} + ret double 0x4fffffffffffffff +} diff --git a/test/CodeGen/ARM/dagcombine-concatvector.ll b/test/CodeGen/ARM/dagcombine-concatvector.ll index d8c6c64..2927ea2 100644 --- a/test/CodeGen/ARM/dagcombine-concatvector.ll +++ b/test/CodeGen/ARM/dagcombine-concatvector.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 -mcpu=generic | FileCheck %s ; PR15525 ; CHECK-LABEL: test1: diff --git a/test/CodeGen/ARM/darwin-eabi.ll b/test/CodeGen/ARM/darwin-eabi.ll new file mode 100644 index 0000000..f2cde71 --- /dev/null +++ b/test/CodeGen/ARM/darwin-eabi.ll @@ -0,0 +1,24 @@ +; RUN: llc -mtriple=thumbv7m-apple-darwin -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3 +; RUN: llc -mtriple=thumbv7em-apple-darwin -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4 +; RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3 +; RUN: llc -mtriple=thumbv7-apple-darwin -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4 + +define float @float_op(float %lhs, float %rhs) { + %sum = fadd float %lhs, %rhs + ret float %sum +; CHECK-M3-LABEL: float_op: +; CHECK-M3: blx ___addsf3 + +; CHECK-M4-LABEL: float_op: +; CHECK-M4: vadd.f32 +} + +define double @double_op(double %lhs, double %rhs) { + %sum = fadd double %lhs, %rhs + ret double %sum +; CHECK-M3-LABEL: double_op: +; CHECK-M3: blx ___adddf3 + +; CHECK-M4-LABEL: double_op: +; CHECK-M4: blx ___adddf3 +} diff --git a/test/CodeGen/ARM/debug-info-arg.ll b/test/CodeGen/ARM/debug-info-arg.ll index 89ccb20..e8bf3ba 100644 --- a/test/CodeGen/ARM/debug-info-arg.ll +++ b/test/CodeGen/ARM/debug-info-arg.ll @@ -30,15 +30,16 @@ declare void @foobar(i64, i64) declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!33} !0 = metadata !{i32 786449, metadata !32, i32 12, metadata !"Apple clang version 3.0 (tags/Apple/clang-211.10.1) (based on LLVM 3.0svn)", i1 true, metadata !"", i32 0, metadata !4, metadata !4, metadata !30, null, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, metadata !2, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, metadata !31, i32 11} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786478, metadata !2, metadata !2, metadata !"foo", metadata !"foo", metadata !"", i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void (%struct.tag_s*, %struct.tag_s*, i64, i64, %struct.tag_s*, %struct.tag_s*)* @foo, null, null, metadata !31, i32 11} ; [ DW_TAG_subprogram ] [line 11] [def] [foo] !2 = metadata !{i32 786473, metadata !32} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786453, metadata !32, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!3 = metadata !{i32 786453, metadata !32, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !4 = metadata !{null} !5 = metadata !{i32 786689, metadata !1, metadata !"this", metadata !2, i32 16777227, metadata !6, i32 0, null} ; [ DW_TAG_arg_variable ] !6 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] -!7 = metadata !{i32 786451, metadata !32, metadata !0, metadata !"tag_s", i32 5, i64 96, i64 32, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!7 = metadata !{i32 786451, metadata !32, metadata !0, metadata !"tag_s", i32 5, i64 96, i64 32, i32 0, i32 0, null, metadata !8, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [tag_s] [line 5, size 96, align 32, offset 0] [def] [from ] !8 = metadata !{metadata !9, metadata !11, metadata !12} !9 = metadata !{i32 786445, metadata !32, metadata !7, metadata !"x", i32 6, i64 32, i64 32, i64 0, i32 0, metadata !10} ; [ DW_TAG_member ] !10 = metadata !{i32 786468, null, metadata !0, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] @@ -64,3 +65,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !30 = metadata !{metadata !1} !31 = metadata !{metadata !5, metadata !13, metadata !14, metadata !17, metadata !18, metadata!19} !32 = metadata !{metadata !"one.c", metadata !"/Volumes/Athwagate/R10048772"} +!33 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/debug-info-blocks.ll b/test/CodeGen/ARM/debug-info-blocks.ll index bd55786..6cbe4b4 100644 --- a/test/CodeGen/ARM/debug-info-blocks.ll +++ b/test/CodeGen/ARM/debug-info-blocks.ll @@ -93,37 +93,38 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load } !llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!162} !0 = metadata !{i32 786449, metadata !153, i32 16, metadata !"Apple clang version 2.1", i1 false, metadata !"", i32 2, metadata !147, metadata !26, metadata !148, null, null, metadata !""} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786433, metadata !160, metadata !0, metadata !"", i32 248, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !3, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!1 = metadata !{i32 786436, metadata !160, metadata !0, metadata !"", i32 248, i64 32, i64 32, i32 0, i32 0, null, metadata !3, i32 0, null, null, null} ; [ DW_TAG_enumeration_type ] [line 248, size 32, align 32, offset 0] [def] [from ] !2 = metadata !{i32 786473, metadata !160} ; [ DW_TAG_file_type ] !3 = metadata !{metadata !4} !4 = metadata !{i32 786472, metadata !"Ver1", i64 0} ; [ DW_TAG_enumerator ] -!5 = metadata !{i32 786433, metadata !160, metadata !0, metadata !"Mode", i32 79, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !7, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!5 = metadata !{i32 786436, metadata !160, metadata !0, metadata !"Mode", i32 79, i64 32, i64 32, i32 0, i32 0, null, metadata !7, i32 0, null, null, null} ; [ DW_TAG_enumeration_type ] [Mode] [line 79, size 32, align 32, offset 0] [def] [from ] !6 = metadata !{i32 786473, metadata !161} ; [ DW_TAG_file_type ] !7 = metadata !{metadata !8} !8 = metadata !{i32 786472, metadata !"One", i64 0} ; [ DW_TAG_enumerator ] -!9 = metadata !{i32 786433, metadata !149, metadata !0, metadata !"", i32 15, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !11, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!9 = metadata !{i32 786436, metadata !149, metadata !0, metadata !"", i32 15, i64 32, i64 32, i32 0, i32 0, null, metadata !11, i32 0, null, null, null} ; [ DW_TAG_enumeration_type ] [line 15, size 32, align 32, offset 0] [def] [from ] !10 = metadata !{i32 786473, metadata !149} ; [ DW_TAG_file_type ] !11 = metadata !{metadata !12, metadata !13} !12 = metadata !{i32 786472, metadata !"Unknown", i64 0} ; [ DW_TAG_enumerator ] !13 = metadata !{i32 786472, metadata !"Known", i64 1} ; [ DW_TAG_enumerator ] -!14 = metadata !{i32 786433, metadata !150, metadata !0, metadata !"", i32 20, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!14 = metadata !{i32 786436, metadata !150, metadata !0, metadata !"", i32 20, i64 32, i64 32, i32 0, i32 0, null, metadata !16, i32 0, null, null, null} ; [ DW_TAG_enumeration_type ] [line 20, size 32, align 32, offset 0] [def] [from ] !15 = metadata !{i32 786473, metadata !150} ; [ DW_TAG_file_type ] !16 = metadata !{metadata !17, metadata !18} !17 = metadata !{i32 786472, metadata !"Single", i64 0} ; [ DW_TAG_enumerator ] !18 = metadata !{i32 786472, metadata !"Double", i64 1} ; [ DW_TAG_enumerator ] -!19 = metadata !{i32 786433, metadata !151, metadata !0, metadata !"", i32 14, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_enumeration_type ] +!19 = metadata !{i32 786436, metadata !151, metadata !0, metadata !"", i32 14, i64 32, i64 32, i32 0, i32 0, null, metadata !21, i32 0, null, null, null} ; [ DW_TAG_enumeration_type ] [line 14, size 32, align 32, offset 0] [def] [from ] !20 = metadata !{i32 786473, metadata !151} ; [ DW_TAG_file_type ] !21 = metadata !{metadata !22} !22 = metadata !{i32 786472, metadata !"Eleven", i64 0} ; [ DW_TAG_enumerator ] -!23 = metadata !{i32 786478, metadata !152, metadata !24, metadata !"foobar_func_block_invoke_0", metadata !"foobar_func_block_invoke_0", metadata !"", i32 609, metadata !25, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null, i32 609} ; [ DW_TAG_subprogram ] +!23 = metadata !{i32 786478, metadata !152, metadata !24, metadata !"foobar_func_block_invoke_0", metadata !"foobar_func_block_invoke_0", metadata !"", i32 609, metadata !25, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 false, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null, null, i32 609} ; [ DW_TAG_subprogram ] [line 609] [local] [def] [foobar_func_block_invoke_0] !24 = metadata !{i32 786473, metadata !152} ; [ DW_TAG_file_type ] -!25 = metadata !{i32 786453, metadata !152, metadata !24, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !26, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!25 = metadata !{i32 786453, metadata !152, metadata !24, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !26, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !26 = metadata !{null} !27 = metadata !{i32 786689, metadata !23, metadata !".block_descriptor", metadata !24, i32 16777825, metadata !28, i32 64, null} ; [ DW_TAG_arg_variable ] !28 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 0, i64 0, i32 0, metadata !29} ; [ DW_TAG_pointer_type ] -!29 = metadata !{i32 786451, metadata !152, metadata !24, metadata !"__block_literal_14", i32 609, i64 256, i64 32, i32 0, i32 0, i32 0, metadata !30, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!29 = metadata !{i32 786451, metadata !152, metadata !24, metadata !"__block_literal_14", i32 609, i64 256, i64 32, i32 0, i32 0, null, metadata !30, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [__block_literal_14] [line 609, size 256, align 32, offset 0] [def] [from ] !30 = metadata !{metadata !31, metadata !33, metadata !35, metadata !36, metadata !37, metadata !48, metadata !89, metadata !124} !31 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__isa", i32 609, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_member ] !32 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] @@ -133,7 +134,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !36 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__FuncPtr", i32 609, i64 32, i64 32, i64 96, i32 0, metadata !32} ; [ DW_TAG_member ] !37 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__descriptor", i32 609, i64 32, i64 32, i64 128, i32 0, metadata !38} ; [ DW_TAG_member ] !38 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !39} ; [ DW_TAG_pointer_type ] -!39 = metadata !{i32 786451, metadata !153, metadata !0, metadata !"__block_descriptor_withcopydispose", i32 307, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !41, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!39 = metadata !{i32 786451, metadata !153, metadata !0, metadata !"__block_descriptor_withcopydispose", i32 307, i64 128, i64 32, i32 0, i32 0, null, metadata !41, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [__block_descriptor_withcopydispose] [line 307, size 128, align 32, offset 0] [def] [from ] !40 = metadata !{i32 786473, metadata !153} ; [ DW_TAG_file_type ] !41 = metadata !{metadata !42, metadata !44, metadata !45, metadata !47} !42 = metadata !{i32 786445, metadata !153, metadata !40, metadata !"reserved", i32 307, i64 32, i64 32, i64 0, i32 0, metadata !43} ; [ DW_TAG_member ] @@ -144,7 +145,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !47 = metadata !{i32 786445, metadata !153, metadata !40, metadata !"DestroyFuncPtr", i32 307, i64 32, i64 32, i64 96, i32 0, metadata !46} ; [ DW_TAG_member ] !48 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"mydata", i32 609, i64 32, i64 32, i64 160, i32 0, metadata !49} ; [ DW_TAG_member ] !49 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 0, i64 0, i32 0, metadata !50} ; [ DW_TAG_pointer_type ] -!50 = metadata !{i32 786451, metadata !152, metadata !24, metadata !"", i32 0, i64 224, i64 0, i32 0, i32 16, i32 0, metadata !51, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!50 = metadata !{i32 786451, metadata !152, metadata !24, metadata !"", i32 0, i64 224, i64 0, i32 0, i32 16, null, metadata !51, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [line 0, size 224, align 0, offset 0] [def] [from ] !51 = metadata !{metadata !52, metadata !53, metadata !54, metadata !55, metadata !56, metadata !57, metadata !58} !52 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__isa", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_member ] !53 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__forwarding", i32 0, i64 32, i64 32, i64 32, i32 0, metadata !32} ; [ DW_TAG_member ] @@ -154,17 +155,17 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !57 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"__destroy_helper", i32 0, i64 32, i64 32, i64 160, i32 0, metadata !32} ; [ DW_TAG_member ] !58 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"mydata", i32 0, i64 32, i64 32, i64 192, i32 0, metadata !59} ; [ DW_TAG_member ] !59 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !60} ; [ DW_TAG_pointer_type ] -!60 = metadata !{i32 786451, metadata !154, metadata !24, metadata !"UIMydata", i32 26, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !62, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!60 = metadata !{i32 786451, metadata !154, metadata !24, metadata !"UIMydata", i32 26, i64 128, i64 32, i32 0, i32 0, null, metadata !62, i32 16, null, null, null} ; [ DW_TAG_structure_type ] [UIMydata] [line 26, size 128, align 32, offset 0] [def] [from ] !61 = metadata !{i32 786473, metadata !154} ; [ DW_TAG_file_type ] !62 = metadata !{metadata !63, metadata !71, metadata !75, metadata !79} !63 = metadata !{i32 786460, metadata !60, null, metadata !61, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_inheritance ] -!64 = metadata !{i32 786451, metadata !155, metadata !40, metadata !"NSO", i32 66, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !66, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!64 = metadata !{i32 786451, metadata !155, metadata !40, metadata !"NSO", i32 66, i64 32, i64 32, i32 0, i32 0, null, metadata !66, i32 16, null, null, null} ; [ DW_TAG_structure_type ] [NSO] [line 66, size 32, align 32, offset 0] [def] [from ] !65 = metadata !{i32 786473, metadata !155} ; [ DW_TAG_file_type ] !66 = metadata !{metadata !67} !67 = metadata !{i32 786445, metadata !155, metadata !65, metadata !"isa", i32 67, i64 32, i64 32, i64 0, i32 2, metadata !68, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !68 = metadata !{i32 786454, metadata !153, metadata !0, metadata !"Class", i32 197, i64 0, i64 0, i64 0, i32 0, metadata !69} ; [ DW_TAG_typedef ] !69 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !70} ; [ DW_TAG_pointer_type ] -!70 = metadata !{i32 786451, metadata !153, metadata !0, metadata !"objc_class", i32 0, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!70 = metadata !{i32 786451, metadata !153, metadata !0, metadata !"objc_class", i32 0, i64 0, i64 0, i32 0, i32 4, null, null, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [objc_class] [line 0, size 0, align 0, offset 0] [decl] [from ] !71 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"_mydataRef", i32 28, i64 32, i64 32, i64 32, i32 0, metadata !72, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !72 = metadata !{i32 786454, metadata !152, metadata !0, metadata !"CFTypeRef", i32 313, i64 0, i64 0, i64 0, i32 0, metadata !73} ; [ DW_TAG_typedef ] !73 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !74} ; [ DW_TAG_pointer_type ] @@ -174,7 +175,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !77 = metadata !{i32 786473, metadata !156} ; [ DW_TAG_file_type ] !78 = metadata !{i32 786468, null, metadata !0, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] !79 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"_mydataFlags", i32 37, i64 8, i64 8, i64 96, i32 0, metadata !80, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] -!80 = metadata !{i32 786451, metadata !154, metadata !0, metadata !"", i32 30, i64 8, i64 8, i32 0, i32 0, i32 0, metadata !81, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!80 = metadata !{i32 786451, metadata !154, metadata !0, metadata !"", i32 30, i64 8, i64 8, i32 0, i32 0, null, metadata !81, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [line 30, size 8, align 8, offset 0] [def] [from ] !81 = metadata !{metadata !82, metadata !84, metadata !85, metadata !86, metadata !87, metadata !88} !82 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"named", i32 31, i64 1, i64 32, i64 0, i32 0, metadata !83} ; [ DW_TAG_member ] !83 = metadata !{i32 786468, null, metadata !0, metadata !"unsigned int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] @@ -185,10 +186,10 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !88 = metadata !{i32 786445, metadata !154, metadata !61, metadata !"isCIMydata", i32 36, i64 1, i64 32, i64 7, i32 0, metadata !83} ; [ DW_TAG_member ] !89 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"self", i32 609, i64 32, i64 32, i64 192, i32 0, metadata !90} ; [ DW_TAG_member ] !90 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !91} ; [ DW_TAG_pointer_type ] -!91 = metadata !{i32 786451, metadata !152, metadata !40, metadata !"MyWork", i32 36, i64 384, i64 32, i32 0, i32 0, i32 0, metadata !92, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!91 = metadata !{i32 786451, metadata !152, metadata !40, metadata !"MyWork", i32 36, i64 384, i64 32, i32 0, i32 0, null, metadata !92, i32 16, null, null, null} ; [ DW_TAG_structure_type ] [MyWork] [line 36, size 384, align 32, offset 0] [def] [from ] !92 = metadata !{metadata !93, metadata !98, metadata !101, metadata !107, metadata !123} !93 = metadata !{i32 786460, metadata !152, metadata !91, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !94} ; [ DW_TAG_inheritance ] -!94 = metadata !{i32 786451, metadata !157, metadata !40, metadata !"twork", i32 43, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !96, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!94 = metadata !{i32 786451, metadata !157, metadata !40, metadata !"twork", i32 43, i64 32, i64 32, i32 0, i32 0, null, metadata !96, i32 16, null, null, null} ; [ DW_TAG_structure_type ] [twork] [line 43, size 32, align 32, offset 0] [def] [from ] !95 = metadata !{i32 786473, metadata !157} ; [ DW_TAG_file_type ] !96 = metadata !{metadata !97} !97 = metadata !{i32 786460, metadata !94, null, metadata !95, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_inheritance ] @@ -197,23 +198,23 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !100 = metadata !{i32 786468, null, metadata !0, metadata !"long long unsigned int", i32 0, i64 64, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] !101 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_library", i32 39, i64 32, i64 32, i64 96, i32 1, metadata !102, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !102 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !103} ; [ DW_TAG_pointer_type ] -!103 = metadata !{i32 786451, metadata !158, metadata !40, metadata !"MyLibrary2", i32 22, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !105, i32 16, i32 0} ; [ DW_TAG_structure_type ] +!103 = metadata !{i32 786451, metadata !158, metadata !40, metadata !"MyLibrary2", i32 22, i64 32, i64 32, i32 0, i32 0, null, metadata !105, i32 16, null, null, null} ; [ DW_TAG_structure_type ] [MyLibrary2] [line 22, size 32, align 32, offset 0] [def] [from ] !104 = metadata !{i32 786473, metadata !158} ; [ DW_TAG_file_type ] !105 = metadata !{metadata !106} !106 = metadata !{i32 786460, metadata !103, null, metadata !104, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !64} ; [ DW_TAG_inheritance ] !107 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"_bounds", i32 40, i64 128, i64 32, i64 128, i32 1, metadata !108, metadata !"", metadata !"", metadata !"", i32 0} ; [ DW_TAG_member ] !108 = metadata !{i32 786454, metadata !153, metadata !0, metadata !"CR", i32 33, i64 0, i64 0, i64 0, i32 0, metadata !109} ; [ DW_TAG_typedef ] -!109 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"CR", i32 29, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !110, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!109 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"CR", i32 29, i64 128, i64 32, i32 0, i32 0, null, metadata !110, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [CR] [line 29, size 128, align 32, offset 0] [def] [from ] !110 = metadata !{metadata !111, metadata !117} !111 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"origin", i32 30, i64 64, i64 32, i64 0, i32 0, metadata !112} ; [ DW_TAG_member ] !112 = metadata !{i32 786454, metadata !156, metadata !0, metadata !"CP", i32 17, i64 0, i64 0, i64 0, i32 0, metadata !113} ; [ DW_TAG_typedef ] -!113 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"CP", i32 13, i64 64, i64 32, i32 0, i32 0, i32 0, metadata !114, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!113 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"CP", i32 13, i64 64, i64 32, i32 0, i32 0, null, metadata !114, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [CP] [line 13, size 64, align 32, offset 0] [def] [from ] !114 = metadata !{metadata !115, metadata !116} !115 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"x", i32 14, i64 32, i64 32, i64 0, i32 0, metadata !76} ; [ DW_TAG_member ] !116 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"y", i32 15, i64 32, i64 32, i64 32, i32 0, metadata !76} ; [ DW_TAG_member ] !117 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"size", i32 31, i64 64, i64 32, i64 64, i32 0, metadata !118} ; [ DW_TAG_member ] !118 = metadata !{i32 786454, metadata !156, metadata !0, metadata !"Size", i32 25, i64 0, i64 0, i64 0, i32 0, metadata !119} ; [ DW_TAG_typedef ] -!119 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"Size", i32 21, i64 64, i64 32, i32 0, i32 0, i32 0, metadata !120, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!119 = metadata !{i32 786451, metadata !156, metadata !0, metadata !"Size", i32 21, i64 64, i64 32, i32 0, i32 0, null, metadata !120, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [Size] [line 21, size 64, align 32, offset 0] [def] [from ] !120 = metadata !{metadata !121, metadata !122} !121 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"width", i32 22, i64 32, i64 32, i64 0, i32 0, metadata !76} ; [ DW_TAG_member ] !122 = metadata !{i32 786445, metadata !156, metadata !77, metadata !"height", i32 23, i64 32, i64 32, i64 32, i32 0, metadata !76} ; [ DW_TAG_member ] @@ -221,7 +222,7 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !124 = metadata !{i32 786445, metadata !152, metadata !24, metadata !"semi", i32 609, i64 32, i64 32, i64 224, i32 0, metadata !125} ; [ DW_TAG_member ] !125 = metadata !{i32 786454, metadata !152, metadata !0, metadata !"d_t", i32 35, i64 0, i64 0, i64 0, i32 0, metadata !126} ; [ DW_TAG_typedef ] !126 = metadata !{i32 786447, null, metadata !0, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !127} ; [ DW_TAG_pointer_type ] -!127 = metadata !{i32 786451, metadata !159, metadata !0, metadata !"my_struct", i32 49, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!127 = metadata !{i32 786451, metadata !159, metadata !0, metadata !"my_struct", i32 49, i64 0, i64 0, i32 0, i32 4, null, null, i32 0, null, null, null} ; [ DW_TAG_structure_type ] [my_struct] [line 49, size 0, align 0, offset 0] [decl] [from ] !128 = metadata !{i32 786473, metadata !159} ; [ DW_TAG_file_type ] !129 = metadata !{i32 609, i32 144, metadata !23, null} !130 = metadata !{i32 786689, metadata !23, metadata !"loadedMydata", metadata !24, i32 33555041, metadata !59, i32 0, null} ; [ DW_TAG_arg_variable ] @@ -256,3 +257,4 @@ define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %load !159 = metadata !{metadata !"header15.h", metadata !"/Volumes/Sandbox/llvm"} !160 = metadata !{metadata !"header.h", metadata !"/Volumes/Sandbox/llvm"} !161 = metadata !{metadata !"header2.h", metadata !"/Volumes/Sandbox/llvm"} +!162 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll index 052fd22..8505f53 100644 --- a/test/CodeGen/ARM/debug-info-branch-folding.ll +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -38,23 +38,25 @@ declare i32 @printf(i8* nocapture, ...) nounwind declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +!llvm.module.flags = !{!56} + !0 = metadata !{i32 786478, metadata !54, null, metadata !"test0001", metadata !"test0001", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 0} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !54} ; [ DW_TAG_file_type ] !2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, metadata !17, metadata !17, metadata !50, null, null, null} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] -!6 = metadata !{i32 786433, metadata !54, metadata !2, metadata !"", i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ] +!6 = metadata !{i32 786433, metadata !54, metadata !2, metadata !"", i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float] !7 = metadata !{i32 786468, null, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] !8 = metadata !{metadata !9} !9 = metadata !{i32 786465, i64 0, i64 4} ; [ DW_TAG_subrange_type ] -!10 = metadata !{i32 786478, metadata !54, null, metadata !"main", metadata !"main", metadata !"", i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**, i1)* @main, null, null, metadata !52, i32 0} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!10 = metadata !{i32 786478, metadata !54, null, metadata !"main", metadata !"main", metadata !"", i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**, i1)* @main, null, null, metadata !52, i32 0} ; [ DW_TAG_subprogram ] [line 59] [def] [scope 0] [main] +!11 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !12, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !12 = metadata !{metadata !13} !13 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{i32 786478, metadata !55, null, metadata !"printFV", metadata !"printFV", metadata !"", i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 0} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 786478, metadata !55, null, metadata !"printFV", metadata !"printFV", metadata !"", i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !53, i32 0} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [scope 0] [printFV] !15 = metadata !{i32 786473, metadata !55} ; [ DW_TAG_file_type ] -!16 = metadata !{i32 786453, metadata !55, metadata !15, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!16 = metadata !{i32 786453, metadata !55, metadata !15, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !17, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !17 = metadata !{null} !18 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 16777219, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] !19 = metadata !{i32 786689, metadata !10, metadata !"argc", metadata !1, i32 16777275, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] @@ -94,3 +96,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !53 = metadata !{metadata !30} !54 = metadata !{metadata !"build2.c", metadata !"/private/tmp"} !55 = metadata !{metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp"} +!56 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll index 11631ae..30a3e2d 100644 --- a/test/CodeGen/ARM/debug-info-d16-reg.ll +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -57,11 +57,12 @@ entry: declare i32 @puts(i8* nocapture) nounwind !llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!48} !0 = metadata !{i32 786478, metadata !46, metadata !1, metadata !"printer", metadata !"printer", metadata !"printer", i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @printer, null, null, metadata !43, i32 12} ; [ DW_TAG_subprogram ] !1 = metadata !{i32 786473, metadata !46} ; [ DW_TAG_file_type ] !2 = metadata !{i32 786449, metadata !46, i32 1, metadata !"(LLVM build 00)", i1 true, metadata !"", i32 0, metadata !47, metadata !47, metadata !42, null, null, metadata !""} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !46, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!3 = metadata !{i32 786453, metadata !46, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !4 = metadata !{metadata !5, metadata !6, metadata !7, metadata !8} !5 = metadata !{i32 786468, metadata !46, metadata !1, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] !6 = metadata !{i32 786447, metadata !46, metadata !1, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] @@ -69,7 +70,7 @@ declare i32 @puts(i8* nocapture) nounwind !8 = metadata !{i32 786468, metadata !46, metadata !1, metadata !"unsigned char", i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] !9 = metadata !{i32 786478, metadata !46, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"inlineprinter", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @inlineprinter, null, null, metadata !44, i32 5} ; [ DW_TAG_subprogram ] !10 = metadata !{i32 786478, metadata !46, metadata !1, metadata !"main", metadata !"main", metadata !"main", i32 18, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !45, i32 18} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 786453, metadata !46, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!11 = metadata !{i32 786453, metadata !46, metadata !1, metadata !"", i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !12 = metadata !{metadata !5, metadata !5, metadata !13} !13 = metadata !{i32 786447, metadata !46, metadata !1, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] !14 = metadata !{i32 786447, metadata !46, metadata !1, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !15} ; [ DW_TAG_pointer_type ] @@ -106,3 +107,4 @@ declare i32 @puts(i8* nocapture) nounwind !45 = metadata !{metadata !22, metadata !23, metadata !24} !46 = metadata !{metadata !"a.c", metadata !"/tmp/"} !47 = metadata !{i32 0} +!48 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll index af61f6c..ee515fd5 100644 --- a/test/CodeGen/ARM/debug-info-qreg.ll +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -36,24 +36,25 @@ declare i32 @printf(i8* nocapture, ...) nounwind declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!56} -!0 = metadata !{i32 786478, metadata !54, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 3} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786478, metadata !54, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, <4 x float> (float)* @test0001, null, null, metadata !51, i32 3} ; [ DW_TAG_subprogram ] [line 3] [def] [test0001] !1 = metadata !{i32 786473, metadata !54} ; [ DW_TAG_file_type ] !2 = metadata !{i32 786449, metadata !54, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, metadata !17, metadata !17, metadata !50, null, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!3 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786454, metadata !54, metadata !2, metadata !"v4f32", i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] -!6 = metadata !{i32 786433, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ] +!6 = metadata !{i32 786433, metadata !2, null, metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 128, align 128, offset 0] [from float] !7 = metadata !{i32 786468, null, metadata !2, metadata !"float", i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] !8 = metadata !{metadata !9} !9 = metadata !{i32 786465, i64 0, i64 4} ; [ DW_TAG_subrange_type ] -!10 = metadata !{i32 786478, metadata !54, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !52, i32 59} ; [ DW_TAG_subprogram ] -!11 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!10 = metadata !{i32 786478, metadata !54, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !52, i32 59} ; [ DW_TAG_subprogram ] [line 59] [def] [main] +!11 = metadata !{i32 786453, metadata !54, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !12, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !12 = metadata !{metadata !13} !13 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!14 = metadata !{i32 786478, metadata !55, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null, null, metadata !53, i32 41} ; [ DW_TAG_subprogram ] +!14 = metadata !{i32 786478, metadata !55, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, null, i32 256, i1 true, null, null, null, metadata !53, i32 41} ; [ DW_TAG_subprogram ] [line 41] [local] [def] [printFV] !15 = metadata !{i32 786473, metadata !55} ; [ DW_TAG_file_type ] -!16 = metadata !{i32 786453, metadata !55, metadata !15, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!16 = metadata !{i32 786453, metadata !55, metadata !15, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !17, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !17 = metadata !{null} !18 = metadata !{i32 786689, metadata !0, metadata !"a", metadata !1, i32 16777219, metadata !7, i32 0, null} ; [ DW_TAG_arg_variable ] !19 = metadata !{i32 786689, metadata !10, metadata !"argc", metadata !1, i32 16777275, metadata !13, i32 0, null} ; [ DW_TAG_arg_variable ] @@ -70,7 +71,7 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !30 = metadata !{i32 786689, metadata !14, metadata !"F", metadata !15, i32 16777257, metadata !31, i32 0, null} ; [ DW_TAG_arg_variable ] !31 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] !32 = metadata !{i32 786454, metadata !55, metadata !2, metadata !"FV", i32 25, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ] -!33 = metadata !{i32 786455, metadata !55, metadata !2, metadata !"", i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, i32 0} ; [ DW_TAG_union_type ] +!33 = metadata !{i32 786455, metadata !55, metadata !2, metadata !"", i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, null} ; [ DW_TAG_union_type ] !34 = metadata !{metadata !35, metadata !37} !35 = metadata !{i32 786445, metadata !55, metadata !15, metadata !"V", i32 23, i64 128, i64 128, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] !36 = metadata !{i32 786454, metadata !55, metadata !2, metadata !"v4sf", i32 3, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] @@ -93,3 +94,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !53 = metadata !{metadata !30} !54 = metadata !{metadata !"build2.c", metadata !"/private/tmp"} !55 = metadata !{metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp"} +!56 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll index 83e7dac..e92d977 100644 --- a/test/CodeGen/ARM/debug-info-s16-reg.ll +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -62,15 +62,16 @@ declare i32 @puts(i8* nocapture) nounwind optsize declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!2} +!llvm.module.flags = !{!53} -!0 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null, null, metadata !48, i32 5} ; [ DW_TAG_subprogram ] +!0 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null, null, metadata !48, i32 5} ; [ DW_TAG_subprogram ] [line 5] [def] [inlineprinter] !1 = metadata !{i32 786473, metadata !51} ; [ DW_TAG_file_type ] !2 = metadata !{i32 786449, metadata !51, i32 12, metadata !"clang version 3.0 (trunk 129915)", i1 true, metadata !"", i32 0, metadata !52, metadata !52, metadata !47, null, null, null} ; [ DW_TAG_compile_unit ] -!3 = metadata !{i32 786453, metadata !51, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!3 = metadata !{i32 786453, metadata !51, metadata !1, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !4 = metadata !{metadata !5} !5 = metadata !{i32 786468, null, metadata !2, metadata !"int", i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"printer", metadata !"printer", metadata !"", i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @printer, null, null, metadata !49, i32 12} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !50, i32 18} ; [ DW_TAG_subprogram ] +!6 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"printer", metadata !"printer", metadata !"", i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, float, i8)* @printer, null, null, metadata !49, i32 12} ; [ DW_TAG_subprogram ] [line 12] [def] [printer] +!7 = metadata !{i32 786478, metadata !51, metadata !1, metadata !"main", metadata !"main", metadata !"", i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main, null, null, metadata !50, i32 18} ; [ DW_TAG_subprogram ] [line 18] [def] [main] !8 = metadata !{i32 786689, metadata !0, metadata !"ptr", metadata !1, i32 16777220, metadata !9, i32 0, null} ; [ DW_TAG_arg_variable ] !9 = metadata !{i32 786447, null, metadata !2, metadata !"", i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] !10 = metadata !{i32 786689, metadata !0, metadata !"val", metadata !1, i32 33554436, metadata !11, i32 0, null} ; [ DW_TAG_arg_variable ] @@ -116,3 +117,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !50 = metadata !{metadata !17, metadata !18, metadata !22} !51 = metadata !{metadata !"a.c", metadata !"/private/tmp"} !52 = metadata !{i32 0} +!53 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll index cc2e831..854fcab 100644 --- a/test/CodeGen/ARM/debug-info-sreg2.ll +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -40,11 +40,12 @@ declare float @_Z2f3f(float) optsize declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!20} !0 = metadata !{i32 786449, metadata !18, i32 4, metadata !"clang version 3.0 (trunk 130845)", i1 true, metadata !"", i32 0, metadata !19, metadata !19, metadata !16, null, null, null} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 786478, metadata !18, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3foov", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @_Z3foov, null, null, metadata !17, i32 5} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 786478, metadata !18, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3foov", i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, void ()* @_Z3foov, null, null, metadata !17, i32 5} ; [ DW_TAG_subprogram ] [line 5] [def] [foo] !2 = metadata !{i32 786473, metadata !18} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 786453, metadata !18, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!3 = metadata !{i32 786453, metadata !18, metadata !2, metadata !"", i32 0, i64 0, i64 0, i32 0, i32 0, null, metadata !4, i32 0, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] !4 = metadata !{null} !5 = metadata !{i32 786688, metadata !6, metadata !"k", metadata !2, i32 6, metadata !7, i32 0, null} ; [ DW_TAG_auto_variable ] !6 = metadata !{i32 786443, metadata !18, metadata !1, i32 5, i32 12, i32 0} ; [ DW_TAG_lexical_block ] @@ -61,3 +62,4 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone !17 = metadata !{metadata !5, metadata !8} !18 = metadata !{metadata !"k.cc", metadata !"/private/tmp"} !19 = metadata !{i32 0} +!20 = metadata !{i32 1, metadata !"Debug Info Version", i32 1} diff --git a/test/CodeGen/ARM/divmod.ll b/test/CodeGen/ARM/divmod.ll index 06d6172..7be0c79 100644 --- a/test/CodeGen/ARM/divmod.ll +++ b/test/CodeGen/ARM/divmod.ll @@ -60,7 +60,7 @@ bb: %3 = load i32* @tabsize, align 4 %4 = srem i32 %cols, %3 %5 = sdiv i32 %cols, %3 - %6 = tail call i32 @llvm.objectsize.i32(i8* null, i1 false) + %6 = tail call i32 @llvm.objectsize.i32.p0i8(i8* null, i1 false) %7 = tail call i8* @__memset_chk(i8* null, i32 9, i32 %5, i32 %6) nounwind br label %bb1 @@ -71,7 +71,7 @@ bb1: ret void } -declare i32 @llvm.objectsize.i32(i8*, i1) nounwind readnone +declare i32 @llvm.objectsize.i32.p0i8(i8*, i1) nounwind readnone declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind ; rdar://11714607 diff --git a/test/CodeGen/ARM/fast-isel-align.ll b/test/CodeGen/ARM/fast-isel-align.ll index 4e28a10..9c9a188 100644 --- a/test/CodeGen/ARM/fast-isel-align.ll +++ b/test/CodeGen/ARM/fast-isel-align.ll @@ -1,22 +1,22 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN - -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN - -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl | FileCheck %s --check-prefix=ARM-STRICT-ALIGN - -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN -; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown | FileCheck %s --check-prefix=ARM-STRICT-ALIGN -; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN + +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN + +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -arm-strict-align -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-nacl -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN + +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN +; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -arm-no-strict-align -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=armv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=ARM-STRICT-ALIGN +; RUN: llc < %s -O0 -relocation-model=dynamic-no-pic -mtriple=thumbv7-unknown-unknown -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-STRICT-ALIGN ; Check unaligned stores %struct.anon = type <{ float }> diff --git a/test/CodeGen/ARM/fast-isel-binary.ll b/test/CodeGen/ARM/fast-isel-binary.ll index 3159627..e1a2a4f 100644 --- a/test/CodeGen/ARM/fast-isel-binary.ll +++ b/test/CodeGen/ARM/fast-isel-binary.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -verify-machineinstrs -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Test add with non-legal types diff --git a/test/CodeGen/ARM/fast-isel-br-phi.ll b/test/CodeGen/ARM/fast-isel-br-phi.ll index a0aba69..3b9d465 100644 --- a/test/CodeGen/ARM/fast-isel-br-phi.ll +++ b/test/CodeGen/ARM/fast-isel-br-phi.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios ; This test ensures HandlePHINodesInSuccessorBlocks() is able to promote basic ; non-legal integer types (i.e., i1, i8, i16). diff --git a/test/CodeGen/ARM/fast-isel-call.ll b/test/CodeGen/ARM/fast-isel-call.ll index d10a381..917a15d 100644 --- a/test/CodeGen/ARM/fast-isel-call.ll +++ b/test/CodeGen/ARM/fast-isel-call.ll @@ -1,12 +1,14 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-vfp2 | FileCheck %s --check-prefix=ARM-NOVFP +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-vfp2 | FileCheck %s --check-prefix=THUMB-NOVFP + +; XFAIL: vg_leak ; Note that some of these tests assume that relocations are either ; movw/movt or constant pool loads. Different platforms will select diff --git a/test/CodeGen/ARM/fast-isel-cmp-imm.ll b/test/CodeGen/ARM/fast-isel-cmp-imm.ll index 45ef4ed..55baf48 100644 --- a/test/CodeGen/ARM/fast-isel-cmp-imm.ll +++ b/test/CodeGen/ARM/fast-isel-cmp-imm.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB define void @t1a(float %a) uwtable ssp { entry: diff --git a/test/CodeGen/ARM/fast-isel-conversion.ll b/test/CodeGen/ARM/fast-isel-conversion.ll index e40891a..5983493 100644 --- a/test/CodeGen/ARM/fast-isel-conversion.ll +++ b/test/CodeGen/ARM/fast-isel-conversion.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB ; Test sitofp diff --git a/test/CodeGen/ARM/fast-isel-ext.ll b/test/CodeGen/ARM/fast-isel-ext.ll index 15d0d3c..de0dd19 100644 --- a/test/CodeGen/ARM/fast-isel-ext.ll +++ b/test/CodeGen/ARM/fast-isel-ext.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=v7 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=v7 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi | FileCheck %s --check-prefix=prev6 -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=v7 +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=v7 +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv4t-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=prev6 +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv5-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=prev6 +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=v7 ; Can't test pre-ARMv6 Thumb because ARM FastISel currently only supports ; Thumb2. The ARMFastISel::ARMEmitIntExt code should work for Thumb by always diff --git a/test/CodeGen/ARM/fast-isel-icmp.ll b/test/CodeGen/ARM/fast-isel-icmp.ll index 3dc1109..85f449e 100644 --- a/test/CodeGen/ARM/fast-isel-icmp.ll +++ b/test/CodeGen/ARM/fast-isel-icmp.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB define i32 @icmp_i16_signed(i16 %a, i16 %b) nounwind { entry: diff --git a/test/CodeGen/ARM/fast-isel-intrinsic.ll b/test/CodeGen/ARM/fast-isel-intrinsic.ll index 572ac3a..b08b72b 100644 --- a/test/CodeGen/ARM/fast-isel-intrinsic.ll +++ b/test/CodeGen/ARM/fast-isel-intrinsic.ll @@ -1,9 +1,11 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls | FileCheck %s --check-prefix=ARM-LONG -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls | FileCheck %s --check-prefix=THUMB-LONG +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=ARM-LONG +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -arm-long-calls -verify-machineinstrs | FileCheck %s --check-prefix=THUMB-LONG + +; XFAIL: vg_leak ; Note that some of these tests assume that relocations are either ; movw/movt or constant pool loads. Different platforms will select diff --git a/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll b/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll index 2a88678..d9c9cc4 100644 --- a/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll +++ b/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB define i32 @t1(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t1 %add.ptr = getelementptr inbounds i32* %ptr, i32 -1 - %0 = load i32* %add.ptr, align 4, !tbaa !0 + %0 = load i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0, #-4] ret i32 %0 } @@ -13,7 +13,7 @@ define i32 @t2(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t2 %add.ptr = getelementptr inbounds i32* %ptr, i32 -63 - %0 = load i32* %add.ptr, align 4, !tbaa !0 + %0 = load i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0, #-252] ret i32 %0 } @@ -22,7 +22,7 @@ define i32 @t3(i32* nocapture %ptr) nounwind readonly { entry: ; THUMB: t3 %add.ptr = getelementptr inbounds i32* %ptr, i32 -64 - %0 = load i32* %add.ptr, align 4, !tbaa !0 + %0 = load i32* %add.ptr, align 4 ; THUMB: ldr r{{[0-9]}}, [r0] ret i32 %0 } @@ -31,7 +31,7 @@ define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t4 %add.ptr = getelementptr inbounds i16* %ptr, i32 -1 - %0 = load i16* %add.ptr, align 2, !tbaa !3 + %0 = load i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0, #-2] ret i16 %0 } @@ -40,7 +40,7 @@ define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t5 %add.ptr = getelementptr inbounds i16* %ptr, i32 -127 - %0 = load i16* %add.ptr, align 2, !tbaa !3 + %0 = load i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0, #-254] ret i16 %0 } @@ -49,7 +49,7 @@ define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly { entry: ; THUMB: t6 %add.ptr = getelementptr inbounds i16* %ptr, i32 -128 - %0 = load i16* %add.ptr, align 2, !tbaa !3 + %0 = load i16* %add.ptr, align 2 ; THUMB: ldrh r{{[0-9]}}, [r0] ret i16 %0 } @@ -58,7 +58,7 @@ define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t7 %add.ptr = getelementptr inbounds i8* %ptr, i32 -1 - %0 = load i8* %add.ptr, align 1, !tbaa !1 + %0 = load i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0, #-1] ret i8 %0 } @@ -67,7 +67,7 @@ define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t8 %add.ptr = getelementptr inbounds i8* %ptr, i32 -255 - %0 = load i8* %add.ptr, align 1, !tbaa !1 + %0 = load i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0, #-255] ret i8 %0 } @@ -76,7 +76,7 @@ define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly { entry: ; THUMB: t9 %add.ptr = getelementptr inbounds i8* %ptr, i32 -256 - %0 = load i8* %add.ptr, align 1, !tbaa !1 + %0 = load i8* %add.ptr, align 1 ; THUMB: ldrb r{{[0-9]}}, [r0] ret i8 %0 } @@ -85,7 +85,7 @@ define void @t10(i32* nocapture %ptr) nounwind { entry: ; THUMB: t10 %add.ptr = getelementptr inbounds i32* %ptr, i32 -1 - store i32 0, i32* %add.ptr, align 4, !tbaa !0 + store i32 0, i32* %add.ptr, align 4 ; THUMB: str r{{[0-9]}}, [r0, #-4] ret void } @@ -94,7 +94,7 @@ define void @t11(i32* nocapture %ptr) nounwind { entry: ; THUMB: t11 %add.ptr = getelementptr inbounds i32* %ptr, i32 -63 - store i32 0, i32* %add.ptr, align 4, !tbaa !0 + store i32 0, i32* %add.ptr, align 4 ; THUMB: str r{{[0-9]}}, [r0, #-252] ret void } @@ -103,7 +103,7 @@ define void @t12(i32* nocapture %ptr) nounwind { entry: ; THUMB: t12 %add.ptr = getelementptr inbounds i32* %ptr, i32 -64 - store i32 0, i32* %add.ptr, align 4, !tbaa !0 + store i32 0, i32* %add.ptr, align 4 ; THUMB: str r{{[0-9]}}, [r0] ret void } @@ -112,7 +112,7 @@ define void @t13(i16* nocapture %ptr) nounwind { entry: ; THUMB: t13 %add.ptr = getelementptr inbounds i16* %ptr, i32 -1 - store i16 0, i16* %add.ptr, align 2, !tbaa !3 + store i16 0, i16* %add.ptr, align 2 ; THUMB: strh r{{[0-9]}}, [r0, #-2] ret void } @@ -121,7 +121,7 @@ define void @t14(i16* nocapture %ptr) nounwind { entry: ; THUMB: t14 %add.ptr = getelementptr inbounds i16* %ptr, i32 -127 - store i16 0, i16* %add.ptr, align 2, !tbaa !3 + store i16 0, i16* %add.ptr, align 2 ; THUMB: strh r{{[0-9]}}, [r0, #-254] ret void } @@ -130,7 +130,7 @@ define void @t15(i16* nocapture %ptr) nounwind { entry: ; THUMB: t15 %add.ptr = getelementptr inbounds i16* %ptr, i32 -128 - store i16 0, i16* %add.ptr, align 2, !tbaa !3 + store i16 0, i16* %add.ptr, align 2 ; THUMB: strh r{{[0-9]}}, [r0] ret void } @@ -139,7 +139,7 @@ define void @t16(i8* nocapture %ptr) nounwind { entry: ; THUMB: t16 %add.ptr = getelementptr inbounds i8* %ptr, i32 -1 - store i8 0, i8* %add.ptr, align 1, !tbaa !1 + store i8 0, i8* %add.ptr, align 1 ; THUMB: strb r{{[0-9]}}, [r0, #-1] ret void } @@ -148,7 +148,7 @@ define void @t17(i8* nocapture %ptr) nounwind { entry: ; THUMB: t17 %add.ptr = getelementptr inbounds i8* %ptr, i32 -255 - store i8 0, i8* %add.ptr, align 1, !tbaa !1 + store i8 0, i8* %add.ptr, align 1 ; THUMB: strb r{{[0-9]}}, [r0, #-255] ret void } @@ -157,12 +157,7 @@ define void @t18(i8* nocapture %ptr) nounwind { entry: ; THUMB: t18 %add.ptr = getelementptr inbounds i8* %ptr, i32 -256 - store i8 0, i8* %add.ptr, align 1, !tbaa !1 + store i8 0, i8* %add.ptr, align 1 ; THUMB: strb r{{[0-9]}}, [r0] ret void } - -!0 = metadata !{metadata !"int", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} -!3 = metadata !{metadata !"short", metadata !1} diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll index ad0f159..838c103 100644 --- a/test/CodeGen/ARM/fast-isel-pic.ll +++ b/test/CodeGen/ARM/fast-isel-pic.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7 ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-none-linux-gnueabi | FileCheck %s --check-prefix=THUMB-ELF -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=pic -mtriple=armv7-none-linux-gnueabi | FileCheck %s --check-prefix=ARMv7-ELF @g = global i32 0, align 4 @@ -25,6 +25,8 @@ entry: ; ARMv7: add [[reg2]], pc, [[reg2]] ; ARMv7-ELF: LoadGV ; ARMv7-ELF: ldr r[[reg2:[0-9]+]], +; ARMv7-ELF: .LPC +; ARMv7-ELF-NEXT: add r[[reg2]], pc ; ARMv7-ELF: ldr r[[reg3:[0-9]+]], ; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]] %tmp = load i32* @g @@ -54,6 +56,8 @@ entry: ; ARMv7: ldr r[[reg5]], [r[[reg5]]] ; ARMv7-ELF: LoadIndirectSymbol ; ARMv7-ELF: ldr r[[reg5:[0-9]+]], +; ARMv7-ELF: .LPC +; ARMv7-ELF-NEXT: add r[[reg5]], pc ; ARMv7-ELF: ldr r[[reg6:[0-9]+]], ; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]] %tmp = load i32* @i diff --git a/test/CodeGen/ARM/fast-isel-ret.ll b/test/CodeGen/ARM/fast-isel-ret.ll index ba5412c..8a68309 100644 --- a/test/CodeGen/ARM/fast-isel-ret.ll +++ b/test/CodeGen/ARM/fast-isel-ret.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s ; Sign-extend of i1 currently not supported by fast-isel ;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp { diff --git a/test/CodeGen/ARM/fast-isel-select.ll b/test/CodeGen/ARM/fast-isel-select.ll index bb88814..40f8807 100644 --- a/test/CodeGen/ARM/fast-isel-select.ll +++ b/test/CodeGen/ARM/fast-isel-select.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv8-apple-ios | FileCheck %s --check-prefix=THUMB define i32 @t1(i1 %c) nounwind readnone { entry: @@ -39,15 +40,16 @@ define i32 @t3(i1 %c, i32 %a, i32 %b) nounwind readnone { entry: ; ARM: t3 ; ARM: cmp r0, #0 -; ARM: movne r{{[1-9]}}, r{{[1-9]}} -; ARM: mov r0, r{{[1-9]}} +; ARM: movne r2, r1 +; ARM: add r0, r2, r1 ; THUMB: t3 ; THUMB: cmp r0, #0 ; THUMB: it ne -; THUMB: movne r{{[1-9]}}, r{{[1-9]}} -; THUMB: mov r0, r{{[1-9]}} +; THUMB: movne r2, r1 +; THUMB: add.w r0, r2, r1 %0 = select i1 %c, i32 %a, i32 %b - ret i32 %0 + %1 = add i32 %0, %a + ret i32 %1 } define i32 @t4(i1 %c) nounwind readnone { diff --git a/test/CodeGen/ARM/fast-isel-shifter.ll b/test/CodeGen/ARM/fast-isel-shifter.ll index dbb1ce2..eb4b2b2 100644 --- a/test/CodeGen/ARM/fast-isel-shifter.ll +++ b/test/CodeGen/ARM/fast-isel-shifter.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM define i32 @shl() nounwind ssp { entry: diff --git a/test/CodeGen/ARM/fast-isel-static.ll b/test/CodeGen/ARM/fast-isel-static.ll index 7d86cb9..93c14a0 100644 --- a/test/CodeGen/ARM/fast-isel-static.ll +++ b/test/CodeGen/ARM/fast-isel-static.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s -; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=LONG %s -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=NORM %s -; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=NORM %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static -arm-long-calls | FileCheck -check-prefix=CHECK-LONG %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s +; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -O0 -verify-machineinstrs -fast-isel-abort -relocation-model=static | FileCheck -check-prefix=CHECK-NORM %s define void @myadd(float* %sum, float* %addend) nounwind { entry: diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 0cebc90..5981cab 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=THUMB ; Very basic fast-isel functionality. define i32 @test0(i32 %a, i32 %b) nounwind { diff --git a/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll b/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll new file mode 100644 index 0000000..a32ab6d --- /dev/null +++ b/test/CodeGen/ARM/fastisel-gep-promote-before-add.ll @@ -0,0 +1,18 @@ +; fastisel should not fold add with non-pointer bitwidth +; sext(a) + sext(b) != sext(a + b) +; RUN: llc -mtriple=armv7-apple-ios %s -O0 -o - | FileCheck %s + +define zeroext i8 @gep_promotion(i8* %ptr) nounwind uwtable ssp { +entry: + %ptr.addr = alloca i8*, align 8 + %add = add i8 64, 64 ; 0x40 + 0x40 + %0 = load i8** %ptr.addr, align 8 + + ; CHECK-LABEL: _gep_promotion: + ; CHECK: ldrb {{r[0-9]+}}, {{\[r[0-9]+\]}} + %arrayidx = getelementptr inbounds i8* %0, i8 %add + + %1 = load i8* %arrayidx, align 1 + ret i8 %1 +} + diff --git a/test/CodeGen/ARM/fold-stack-adjust.ll b/test/CodeGen/ARM/fold-stack-adjust.ll new file mode 100644 index 0000000..67fd129 --- /dev/null +++ b/test/CodeGen/ARM/fold-stack-adjust.ll @@ -0,0 +1,164 @@ +; RUN: llc -mtriple=thumbv7-apple-darwin-eabi < %s | FileCheck %s +; RUN: llc -mtriple=thumbv6m-apple-darwin-eabi -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-T1 +; RUN: llc -mtriple=thumbv7-apple-darwin-ios -disable-fp-elim < %s | FileCheck %s --check-prefix=CHECK-IOS + + +declare void @bar(i8*) + +%bigVec = type [2 x double] + +@var = global %bigVec zeroinitializer + +define void @check_simple() minsize { +; CHECK-LABEL: check_simple: +; CHECK: push.w {r7, r8, r9, r10, r11, lr} +; CHECK-NOT: sub sp, sp, +; ... +; CHECK-NOT: add sp, sp, +; CHECK: pop.w {r0, r1, r2, r3, r11, pc} + +; CHECK-T1-LABEL: check_simple: +; CHECK-T1: push {r3, r4, r5, r6, r7, lr} +; CHECK-T1: add r7, sp, #16 +; CHECK-T1-NOT: sub sp, sp, +; ... +; CHECK-T1-NOT: add sp, sp, +; CHECK-T1: pop {r0, r1, r2, r3, r7, pc} + + ; iOS always has a frame pointer and messing with the push affects + ; how it's set in the prologue. Make sure we get that right. +; CHECK-IOS-LABEL: check_simple: +; CHECK-IOS: push {r3, r4, r5, r6, r7, lr} +; CHECK-NOT: sub sp, +; CHECK-IOS: add r7, sp, #16 +; CHECK-NOT: sub sp, +; ... +; CHECK-NOT: add sp, +; CHEC: pop {r3, r4, r5, r6, r7, pc} + + %var = alloca i8, i32 16 + call void @bar(i8* %var) + ret void +} + +define void @check_simple_too_big() minsize { +; CHECK-LABEL: check_simple_too_big: +; CHECK: push.w {r11, lr} +; CHECK: sub sp, +; ... +; CHECK: add sp, +; CHECK: pop.w {r11, pc} + %var = alloca i8, i32 64 + call void @bar(i8* %var) + ret void +} + +define void @check_vfp_fold() minsize { +; CHECK-LABEL: check_vfp_fold: +; CHECK: push {r[[GLOBREG:[0-9]+]], lr} +; CHECK: vpush {d6, d7, d8, d9} +; CHECK-NOT: sub sp, +; ... +; CHECK: vldmia r[[GLOBREG]], {d8, d9} +; ... +; CHECK-NOT: add sp, +; CHECK: vpop {d6, d7, d8, d9} +; CHECKL pop {r[[GLOBREG]], pc} + + ; iOS uses aligned NEON stores here, which is convenient since we + ; want to make sure that works too. +; CHECK-IOS-LABEL: check_vfp_fold: +; CHECK-IOS: push {r0, r1, r2, r3, r4, r7, lr} +; CHECK-IOS: sub.w r4, sp, #16 +; CHECK-IOS: bic r4, r4, #15 +; CHECK-IOS: mov sp, r4 +; CHECK-IOS: vst1.64 {d8, d9}, [r4:128] +; ... +; CHECK-IOS: add r4, sp, #16 +; CHECK-IOS: vld1.64 {d8, d9}, [r4:128] +; CHECK-IOS: mov sp, r4 +; CHECK-IOS: pop {r4, r7, pc} + + %var = alloca i8, i32 16 + + %tmp = load %bigVec* @var + call void @bar(i8* %var) + store %bigVec %tmp, %bigVec* @var + + ret void +} + +; This function should use just enough space that the "add sp, sp, ..." could be +; folded in except that doing so would clobber the value being returned. +define i64 @check_no_return_clobber() minsize { +; CHECK-LABEL: check_no_return_clobber: +; CHECK: push.w {r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-NOT: sub sp, +; ... +; CHECK: add sp, #40 +; CHECK: pop.w {r11, pc} + + ; Just to keep iOS FileCheck within previous function: +; CHECK-IOS-LABEL: check_no_return_clobber: + + %var = alloca i8, i32 40 + call void @bar(i8* %var) + ret i64 0 +} + +define arm_aapcs_vfpcc double @check_vfp_no_return_clobber() minsize { +; CHECK-LABEL: check_vfp_no_return_clobber: +; CHECK: push {r[[GLOBREG:[0-9]+]], lr} +; CHECK: vpush {d0, d1, d2, d3, d4, d5, d6, d7, d8, d9} +; CHECK-NOT: sub sp, +; ... +; CHECK: add sp, #64 +; CHECK: vpop {d8, d9} +; CHECK: pop {r[[GLOBREG]], pc} + + %var = alloca i8, i32 64 + + %tmp = load %bigVec* @var + call void @bar(i8* %var) + store %bigVec %tmp, %bigVec* @var + + ret double 1.0 +} + +@dbl = global double 0.0 + +; PR18136: there was a bug determining where the first eligible pop in a +; basic-block was when the entire block was epilogue code. +define void @test_fold_point(i1 %tst) minsize { +; CHECK-LABEL: test_fold_point: + + ; Important to check for beginning of basic block, because if it gets + ; if-converted the test is probably no longer checking what it should. +; CHECK: {{LBB[0-9]+_2}}: +; CHECK-NEXT: vpop {d7, d8} +; CHECK-NEXT: pop {r4, pc} + + ; With a guaranteed frame-pointer, we want to make sure that its offset in the + ; push block is correct, even if a few registers have been tacked onto a later + ; vpush (PR18160). +; CHECK-IOS-LABEL: test_fold_point: +; CHECK-IOS: push {r4, r7, lr} +; CHECK-IOS-NEXT: add r7, sp, #4 +; CHECK-IOS-NEXT: vpush {d7, d8} + + ; We want some memory so there's a stack adjustment to fold... + %var = alloca i8, i32 8 + + ; We want a long-lived floating register so that a callee-saved dN is used and + ; there's both a vpop and a pop. + %live_val = load double* @dbl + br i1 %tst, label %true, label %end +true: + call void @bar(i8* %var) + store double %live_val, double* @dbl + br label %end +end: + ; We want the epilogue to be the only thing in a basic block so that we hit + ; the correct edge-case (first inst in block is correct one to adjust). + ret void +}
\ No newline at end of file diff --git a/test/CodeGen/ARM/ifconv-kills.ll b/test/CodeGen/ARM/ifconv-kills.ll new file mode 100644 index 0000000..bf54ba2 --- /dev/null +++ b/test/CodeGen/ARM/ifconv-kills.ll @@ -0,0 +1,30 @@ +; RUN: llc < %s -march arm -mcpu swift -verify-machineinstrs + +declare i32 @f(i32 %p0, i32 %p1) + +define i32 @foo(i32* %ptr) { +entry: + %cmp = icmp ne i32* %ptr, null + br i1 %cmp, label %if.then, label %if.else + +; present something which can be easily if-converted +if.then: + ; %R0 should be killed here + %valt = load i32* %ptr, align 4 + br label %return + +if.else: + ; %R0 should be killed here, however after if-conversion the %R0 kill + ; has to be removed because if.then will follow after this and still + ; read it. + %addr = getelementptr inbounds i32* %ptr, i32 4 + %vale = load i32* %addr, align 4 + br label %return + +return: + %phival = phi i32 [ %valt, %if.then ], [ %vale, %if.else ] + ; suggest to bring %phival/%valt/%vale into %R1 (because otherwise there + ; will be no kills in if.then/if.else) + %retval = call i32 @f (i32 0, i32 %phival) + ret i32 %retval +} diff --git a/test/CodeGen/ARM/ifconv-regmask.ll b/test/CodeGen/ARM/ifconv-regmask.ll new file mode 100644 index 0000000..d45f65f --- /dev/null +++ b/test/CodeGen/ARM/ifconv-regmask.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -mtriple=thumbv7s-apple-ios6.0.0 -verify-machineinstrs + +%union.opcode = type { i32 } + +@opcode = external global %union.opcode, align 4 + +; Function Attrs: nounwind ssp +define i32 @sfu() { +entry: + %bf.load = load i32* getelementptr inbounds (%union.opcode* @opcode, i32 0, i32 0), align 4 + %bf.lshr = lshr i32 %bf.load, 26 + %bf.clear = and i32 %bf.lshr, 7 + switch i32 %bf.clear, label %return [ + i32 0, label %sw.bb + i32 1, label %sw.bb1 + ] + +sw.bb: ; preds = %entry + %call = tail call i32 @func0() + br label %return + +sw.bb1: ; preds = %entry + %call2 = tail call i32 @func1() + br label %return + +return: ; preds = %sw.bb1, %sw.bb, %entry + %retval.0 = phi i32 [ %call2, %sw.bb1 ], [ %call, %sw.bb ], [ -1, %entry ] + ret i32 %retval.0 +} + +; Function Attrs: nounwind ssp +declare i32 @func0() + +; Function Attrs: nounwind ssp +declare i32 @func1() diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index 99e84a6..1aeeb91 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -relocation-model=static -mtriple=thumbv8-apple-darwin | FileCheck %s -check-prefix=THUMB2 @nextaddr = global i8* null ; <i8**> [#uses=2] @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] @@ -48,14 +49,17 @@ L2: ; preds = %L3, %bb2 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] +; ARM-LABEL: %L1 ; ARM: ldr [[R1:r[0-9]+]], LCPI ; ARM: add [[R1b:r[0-9]+]], pc, [[R1]] ; ARM: str [[R1b]] +; THUMB-LABEL: %L1 ; THUMB: ldr ; THUMB: add ; THUMB: ldr [[R2:r[0-9]+]], LCPI ; THUMB: add [[R2]], pc ; THUMB: str [[R2]] +; THUMB2-LABEL: %L1 ; THUMB2: ldr [[R2:r[0-9]+]], LCPI ; THUMB2-NEXT: str{{(.w)?}} [[R2]] store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 diff --git a/test/CodeGen/ARM/inlineasm-64bit.ll b/test/CodeGen/ARM/inlineasm-64bit.ll index b23db10..683a0c4 100644 --- a/test/CodeGen/ARM/inlineasm-64bit.ll +++ b/test/CodeGen/ARM/inlineasm-64bit.ll @@ -85,3 +85,22 @@ define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind { tail call void asm sideeffect "strd $0, ${0:H}, [$1]", "r,r"(i64 %4, i64* %p) nounwind ret void } + +; Make sure we don't untie operands by mistake. +define i64 @tied_64bit_test(i64 %in) nounwind { +; CHECK-LABEL: tied_64bit_test: +; CHECK: OUT([[OUTREG:r[0-9]+]]), IN([[OUTREG]]) + %addr = alloca i64 + call void asm "OUT($0), IN($1)", "=*rm,0"(i64* %addr, i64 %in) + ret i64 %in +} + +; If we explicitly name a tied operand, then the code should lookup the operand +; we were tied to for information about register class and so on. +define i64 @tied_64bit_lookback_test(i64 %in) nounwind { +; CHECK-LABEL: tied_64bit_lookback_test: +; CHECK: OUTLO([[LO:r[0-9]+]]) OUTHI([[HI:r[0-9]+]]) INLO([[LO]]) INHI([[HI]]) + %vars = call {i64, i32, i64} asm "OUTLO(${2:Q}) OUTHI(${2:R}) INLO(${3:Q}) INHI(${3:R})", "=r,=r,=r,2"(i64 %in) + %res = extractvalue {i64, i32, i64} %vars, 2 + ret i64 %res +} diff --git a/test/CodeGen/ARM/interrupt-attr.ll b/test/CodeGen/ARM/interrupt-attr.ll new file mode 100644 index 0000000..217fd69 --- /dev/null +++ b/test/CodeGen/ARM/interrupt-attr.ll @@ -0,0 +1,130 @@ +; RUN: llc -mtriple=arm-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A %s +; RUN: llc -mtriple=thumb-none-none-eabi -mcpu=cortex-a15 -o - %s | FileCheck --check-prefix=CHECK-A-THUMB %s +; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-m3 -o - %s | FileCheck --check-prefix=CHECK-M %s + +declare arm_aapcscc void @bar() + +@bigvar = global [16 x i32] zeroinitializer + +define arm_aapcscc void @irq_fn() alignstack(8) "interrupt"="IRQ" { + ; Must save all registers except banked sp and lr (we save lr anyway because + ; we actually need it at the end to execute the return ourselves). + + ; Also need special function return setting pc and CPSR simultaneously. +; CHECK-A-LABEL: irq_fn: +; CHECK-A: push {r0, r1, r2, r3, r11, lr} +; CHECK-A: add r11, sp, #16 +; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: bic sp, sp, #7 +; CHECK-A: bl bar +; CHECK-A: sub sp, r11, #16 +; CHECK-A: pop {r0, r1, r2, r3, r11, lr} +; CHECK-A: subs pc, lr, #4 + +; CHECK-A-THUMB-LABEL: irq_fn: +; CHECK-A-THUMB: push {r0, r1, r2, r3, r4, r7, lr} +; CHECK-A-THUMB: mov r4, sp +; CHECK-A-THUMB: add r7, sp, #20 +; CHECK-A-THUMB: bic r4, r4, #7 +; CHECK-A-THUMB: bl bar +; CHECK-A-THUMB: sub.w r4, r7, #20 +; CHECK-A-THUMB: mov sp, r4 +; CHECK-A-THUMB: pop.w {r0, r1, r2, r3, r4, r7, lr} +; CHECK-A-THUMB: subs pc, lr, #4 + + ; Normal AAPCS function (r0-r3 pushed onto stack by hardware, lr set to + ; appropriate sentinel so no special return needed). +; CHECK-M: push {r4, r7, lr} +; CHECK-M: add r7, sp, #4 +; CHECK-M: sub sp, #4 +; CHECK-M: mov r4, sp +; CHECK-M: mov sp, r4 +; CHECK-M: blx _bar +; CHECK-M: subs r4, r7, #4 +; CHECK-M: mov sp, r4 +; CHECK-M: pop {r4, r7, pc} + + call arm_aapcscc void @bar() + ret void +} + +define arm_aapcscc void @fiq_fn() alignstack(8) "interrupt"="FIQ" { +; CHECK-A-LABEL: fiq_fn: +; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r11, lr} + ; 32 to get past r0, r1, ..., r7 +; CHECK-A: add r11, sp, #32 +; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: bic sp, sp, #7 +; [...] + ; 32 must match above +; CHECK-A: sub sp, r11, #32 +; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r11, lr} +; CHECK-A: subs pc, lr, #4 + + %val = load volatile [16 x i32]* @bigvar + store volatile [16 x i32] %val, [16 x i32]* @bigvar + ret void +} + +define arm_aapcscc void @swi_fn() alignstack(8) "interrupt"="SWI" { +; CHECK-A-LABEL: swi_fn: +; CHECK-A: push {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-A: add r11, sp, #44 +; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: bic sp, sp, #7 +; [...] +; CHECK-A: sub sp, r11, #44 +; CHECK-A: pop {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, lr} +; CHECK-A: subs pc, lr, #0 + + %val = load volatile [16 x i32]* @bigvar + store volatile [16 x i32] %val, [16 x i32]* @bigvar + ret void +} + +define arm_aapcscc void @undef_fn() alignstack(8) "interrupt"="UNDEF" { +; CHECK-A-LABEL: undef_fn: +; CHECK-A: push {r0, r1, r2, r3, r11, lr} +; CHECK-A: add r11, sp, #16 +; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: bic sp, sp, #7 +; [...] +; CHECK-A: sub sp, r11, #16 +; CHECK-A: pop {r0, r1, r2, r3, r11, lr} +; CHECK-A: subs pc, lr, #0 + + call void @bar() + ret void +} + +define arm_aapcscc void @abort_fn() alignstack(8) "interrupt"="ABORT" { +; CHECK-A-LABEL: abort_fn: +; CHECK-A: push {r0, r1, r2, r3, r11, lr} +; CHECK-A: add r11, sp, #16 +; CHECK-A: sub sp, sp, #{{[0-9]+}} +; CHECK-A: bic sp, sp, #7 +; [...] +; CHECK-A: sub sp, r11, #16 +; CHECK-A: pop {r0, r1, r2, r3, r11, lr} +; CHECK-A: subs pc, lr, #4 + + call void @bar() + ret void +} + +@var = global double 0.0 + +; We don't save VFP regs, since it would be a massive overhead in the general +; case. +define arm_aapcscc void @floating_fn() alignstack(8) "interrupt"="IRQ" { +; CHECK-A-LABEL: floating_fn: +; CHECK-A-NOT: vpush +; CHECK-A-NOT: vstr +; CHECK-A-NOT: vstm +; CHECK-A: vadd.f64 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} + %lhs = load volatile double* @var + %rhs = load volatile double* @var + %sum = fadd double %lhs, %rhs + store double %sum, double* @var + ret void +} diff --git a/test/CodeGen/ARM/intrinsics-crypto.ll b/test/CodeGen/ARM/intrinsics-crypto.ll new file mode 100644 index 0000000..c038fe6 --- /dev/null +++ b/test/CodeGen/ARM/intrinsics-crypto.ll @@ -0,0 +1,57 @@ +; RUN: llc < %s -mtriple=armv8 -mattr=+crypto | FileCheck %s + +define arm_aapcs_vfpcc <16 x i8> @test_aesde(<16 x i8>* %a, <16 x i8> *%b) { + %tmp = load <16 x i8>* %a + %tmp2 = load <16 x i8>* %b + %tmp3 = call <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8> %tmp, <16 x i8> %tmp2) + ; CHECK: aesd.8 q{{[0-9]+}}, q{{[0-9]+}} + %tmp4 = call <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8> %tmp3, <16 x i8> %tmp2) + ; CHECK: aese.8 q{{[0-9]+}}, q{{[0-9]+}} + %tmp5 = call <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8> %tmp4) + ; CHECK: aesimc.8 q{{[0-9]+}}, q{{[0-9]+}} + %tmp6 = call <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8> %tmp5) + ; CHECK: aesmc.8 q{{[0-9]+}}, q{{[0-9]+}} + ret <16 x i8> %tmp6 +} + +define arm_aapcs_vfpcc <4 x i32> @test_sha(<4 x i32> *%a, <4 x i32> *%b, <4 x i32> *%c) { + %tmp = load <4 x i32>* %a + %tmp2 = load <4 x i32>* %b + %tmp3 = load <4 x i32>* %c + %res1 = call <4 x i32> @llvm.arm.neon.sha1h.v4i32(<4 x i32> %tmp) + ; CHECK: sha1h.32 q{{[0-9]+}}, q{{[0-9]+}} + %res2 = call <4 x i32> @llvm.arm.neon.sha1c.v4i32(<4 x i32> %tmp2, <4 x i32> %tmp3, <4 x i32> %res1) + ; CHECK: sha1c.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %res3 = call <4 x i32> @llvm.arm.neon.sha1m.v4i32(<4 x i32> %res2, <4 x i32> %tmp3, <4 x i32> %res1) + ; CHECK: sha1m.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %res4 = call <4 x i32> @llvm.arm.neon.sha1p.v4i32(<4 x i32> %res3, <4 x i32> %tmp3, <4 x i32> %res1) + ; CHECK: sha1p.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %res5 = call <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32> %res4, <4 x i32> %tmp3, <4 x i32> %res1) + ; CHECK: sha1su0.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %res6 = call <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32> %res5, <4 x i32> %res1) + ; CHECK: sha1su1.32 q{{[0-9]+}}, q{{[0-9]+}} + %res7 = call <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32> %res6, <4 x i32> %tmp3, <4 x i32> %res1) + ; CHECK: sha256h.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %res8 = call <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32> %res7, <4 x i32> %tmp3, <4 x i32> %res1) + ; CHECK: sha256h2.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %res9 = call <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32> %res8, <4 x i32> %tmp3, <4 x i32> %res1) + ; CHECK: sha256su1.32 q{{[0-9]+}}, q{{[0-9]+}}, q{{[0-9]+}} + %res10 = call <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32> %res9, <4 x i32> %tmp3) + ; CHECK: sha256su0.32 q{{[0-9]+}}, q{{[0-9]+}} + ret <4 x i32> %res10 +} + +declare <16 x i8> @llvm.arm.neon.aesd.v16i8(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.arm.neon.aesimc.v16i8(<16 x i8>) +declare <16 x i8> @llvm.arm.neon.aesmc.v16i8(<16 x i8>) +declare <4 x i32> @llvm.arm.neon.sha1h.v4i32(<4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha1c.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha1m.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha1p.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha1su0.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha256h.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha256h2.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha256su0.v4i32(<4 x i32>, <4 x i32>) +declare <4 x i32> @llvm.arm.neon.sha1su1.v4i32(<4 x i32>, <4 x i32>) diff --git a/test/CodeGen/ARM/intrinsics-v8.ll b/test/CodeGen/ARM/intrinsics-v8.ll new file mode 100644 index 0000000..247bfc1 --- /dev/null +++ b/test/CodeGen/ARM/intrinsics-v8.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -mtriple=armv8 -mattr=+db | FileCheck %s + +define void @test() { + ; CHECK: dmb sy + call void @llvm.arm.dmb(i32 15) + ; CHECK: dmb osh + call void @llvm.arm.dmb(i32 3) + ; CHECK: dsb sy + call void @llvm.arm.dsb(i32 15) + ; CHECK: dsb ishld + call void @llvm.arm.dsb(i32 9) + ; CHECK: sevl + tail call void @llvm.arm.sevl() nounwind + ret void +} + +declare void @llvm.arm.dmb(i32) +declare void @llvm.arm.dsb(i32) +declare void @llvm.arm.sevl() nounwind diff --git a/test/CodeGen/ARM/lit.local.cfg b/test/CodeGen/ARM/lit.local.cfg index 4d75f58..8a3ba96 100644 --- a/test/CodeGen/ARM/lit.local.cfg +++ b/test/CodeGen/ARM/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.ll', '.c', '.cpp', '.test'] - targets = set(config.root.targets_to_build.split()) if not 'ARM' in targets: config.unsupported = True diff --git a/test/CodeGen/ARM/long_shift.ll b/test/CodeGen/ARM/long_shift.ll index a99a7ec..3e986d80 100644 --- a/test/CodeGen/ARM/long_shift.ll +++ b/test/CodeGen/ARM/long_shift.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s define i64 @f0(i64 %A, i64 %B) { -; CHECK: f0 +; CHECK-LABEL: f0: ; CHECK: lsrs r3, r3, #1 ; CHECK-NEXT: rrx r2, r2 ; CHECK-NEXT: subs r0, r0, r2 @@ -13,7 +13,7 @@ define i64 @f0(i64 %A, i64 %B) { } define i32 @f1(i64 %x, i64 %y) { -; CHECK: f1 +; CHECK-LABEL: f1: ; CHECK: lsl{{.*}}r2 %a = shl i64 %x, %y %b = trunc i64 %a to i32 @@ -21,7 +21,7 @@ define i32 @f1(i64 %x, i64 %y) { } define i32 @f2(i64 %x, i64 %y) { -; CHECK: f2 +; CHECK-LABEL: f2: ; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: sub r2, r2, #32 @@ -34,7 +34,7 @@ define i32 @f2(i64 %x, i64 %y) { } define i32 @f3(i64 %x, i64 %y) { -; CHECK: f3 +; CHECK-LABEL: f3: ; CHECK: lsr{{.*}}r2 ; CHECK-NEXT: rsb r3, r2, #32 ; CHECK-NEXT: sub r2, r2, #32 diff --git a/test/CodeGen/ARM/misched-copy-arm.ll b/test/CodeGen/ARM/misched-copy-arm.ll index c274545..5da335f 100644 --- a/test/CodeGen/ARM/misched-copy-arm.ll +++ b/test/CodeGen/ARM/misched-copy-arm.ll @@ -65,7 +65,7 @@ if.end28: ; preds = %if.then24, %while.c %dst.1 = phi %struct.rtx_def* [ undef, %if.then24 ], [ %dst.0, %while.cond ], [ %dst.0, %while.cond ] %arrayidx30 = getelementptr inbounds %struct.rtx_def* %dst.1, i32 0, i32 1, i32 0 %rtx31 = bitcast %union.rtunion_def* %arrayidx30 to %struct.rtx_def** - %0 = load %struct.rtx_def** %rtx31, align 4, !tbaa !0 + %0 = load %struct.rtx_def** %rtx31, align 4 br label %while.cond if.then46: ; preds = %while.cond @@ -77,7 +77,3 @@ if.end47: ; preds = %while.cond } attributes #0 = { nounwind ssp } - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} diff --git a/test/CodeGen/ARM/neon-spfp.ll b/test/CodeGen/ARM/neon-spfp.ll index 5385668..dd2e67f 100644 --- a/test/CodeGen/ARM/neon-spfp.ll +++ b/test/CodeGen/ARM/neon-spfp.ll @@ -1,20 +1,20 @@ -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a5 | FileCheck %s -check-prefix=LINUXA5 -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=LINUXA8 -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a9 | FileCheck %s -check-prefix=LINUXA9 -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a15 | FileCheck %s -check-prefix=LINUXA15 -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=swift | FileCheck %s -check-prefix=LINUXSWIFT +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a5 | FileCheck %s -check-prefix=CHECK-LINUXA5 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-LINUXA8 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a9 | FileCheck %s -check-prefix=CHECK-LINUXA9 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a15 | FileCheck %s -check-prefix=CHECK-LINUXA15 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=swift | FileCheck %s -check-prefix=CHECK-LINUXSWIFT -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a5 --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFEA5 -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFEA8 -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a9 --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFEA9 -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a15 --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFEA15 -; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=swift --enable-unsafe-fp-math | FileCheck %s -check-prefix=UNSAFESWIFT +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a5 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CHECK-UNSAFEA5 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a8 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CHECK-UNSAFEA8 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a9 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CHECK-UNSAFEA9 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=cortex-a15 --enable-unsafe-fp-math | FileCheck %s -check-prefix=CHECK-UNSAFEA15 +; RUN: llc < %s -mtriple armv7a-none-linux-gnueabihf -mcpu=swift --enable-unsafe-fp-math | FileCheck %s -check-prefix=CHECK-UNSAFESWIFT -; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a5 | FileCheck %s -check-prefix=DARWINA5 -; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=DARWINA8 -; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=DARWINA9 -; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a15 | FileCheck %s -check-prefix=DARWINA15 -; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=swift | FileCheck %s -check-prefix=DARWINSWIFT +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a5 | FileCheck %s -check-prefix=CHECK-DARWINA5 +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK-DARWINA8 +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=CHECK-DARWINA9 +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=cortex-a15 | FileCheck %s -check-prefix=CHECK-DARWINA15 +; RUN: llc < %s -mtriple armv7a-none-darwin -mcpu=swift | FileCheck %s -check-prefix=CHECK-DARWINSWIFT ; This test makes sure we're not lowering VMUL.f32 D* (aka. NEON) for single-prec. FP ops, since ; NEON is not fully IEEE 754 compliant, unless unsafe-math is selected. diff --git a/test/CodeGen/ARM/neon_spill.ll b/test/CodeGen/ARM/neon_spill.ll index 277bd05..d286d16 100644 --- a/test/CodeGen/ARM/neon_spill.ll +++ b/test/CodeGen/ARM/neon_spill.ll @@ -24,7 +24,7 @@ declare arm_aapcs_vfpcc %2** @func4() define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 { call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind %2 = call arm_aapcs_vfpcc %0** @func2() nounwind - %3 = load %0** %2, align 4, !tbaa !0 + %3 = load %0** %2, align 4 store float 0.000000e+00, float* undef, align 4 %4 = call arm_aapcs_vfpcc %2* @func3(%2* undef, %2* undef, i32 2956) nounwind call arm_aapcs_vfpcc void @func1(%0* %3, float* undef, float* undef, %2* undef) @@ -35,11 +35,11 @@ define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 { %6 = call arm_aapcs_vfpcc %2** @func4() nounwind %7 = call arm_aapcs_vfpcc %2* @func3(%2* undef, %2* undef, i32 2971) nounwind %8 = fadd float undef, -1.000000e+05 - store float %8, float* undef, align 16, !tbaa !3 + store float %8, float* undef, align 16 %9 = call arm_aapcs_vfpcc i32 @rand() nounwind %10 = fmul float undef, 2.000000e+05 %11 = fadd float %10, -1.000000e+05 - store float %11, float* undef, align 4, !tbaa !3 + store float %11, float* undef, align 4 call void @llvm.arm.neon.vst4.v4i32(i8* undef, <4 x i32> <i32 0, i32 1065353216, i32 1073741824, i32 1077936128>, <4 x i32> <i32 1082130432, i32 1084227584, i32 1086324736, i32 1088421888>, <4 x i32> <i32 1090519040, i32 1091567616, i32 1092616192, i32 1093664768>, <4 x i32> <i32 1094713344, i32 1095761920, i32 1096810496, i32 1097859072>, i32 16) nounwind ret void } @@ -47,8 +47,3 @@ define arm_aapcs_vfpcc void @foo(%3* nocapture) nounwind align 2 { declare void @llvm.arm.neon.vst4.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind declare arm_aapcs_vfpcc i32 @rand() - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} -!3 = metadata !{metadata !"float", metadata !1} diff --git a/test/CodeGen/ARM/no-fpu.ll b/test/CodeGen/ARM/no-fpu.ll new file mode 100644 index 0000000..fff4bcc --- /dev/null +++ b/test/CodeGen/ARM/no-fpu.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,-vfp2 | FileCheck --check-prefix=NONEON-NOVFP %s +; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon | FileCheck --check-prefix=NONEON %s +; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-vfp2 | FileCheck --check-prefix=NOVFP %s +; RUN: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,+vfp2 | FileCheck --check-prefix=NONEON-VFP %s + +; Check no NEON instructions are selected when feature is disabled. +define void @neonop(i64* nocapture readonly %a, i64* nocapture %b) #0 { + %1 = bitcast i64* %a to <2 x i64>* + %wide.load = load <2 x i64>* %1, align 8 + ; NONEON-NOVFP-NOT: vld1.64 + ; NONEON-NOT: vld1.64 + %add = add <2 x i64> %wide.load, %wide.load + ; NONEON-NOVFP-NOT: vadd.i64 + ; NONEON-NOT: vadd.i64 + %2 = bitcast i64* %b to <2 x i64>* + store <2 x i64> %add, <2 x i64>* %2, align 8 + ; NONEON-NOVFP-NOT: vst1.64 + ; NONEON-NOT: vst1.64 + ret void +} + +; Likewise with VFP instructions. +define double @fpmult(double %a, double %b) { + %res = fmul double %a, %b + ; NONEON-NOVFP-NOT: vmov + ; NONEON-NOVFP-NOT: vmul.f64 + ; NOVFP-NOT: vmov + ; NOVFP-NOT: vmul.f64 + ; NONEON-VFP: vmov + ; NONEON-VFP: vmul.f64 + ret double %res +} + diff --git a/test/CodeGen/ARM/noreturn.ll b/test/CodeGen/ARM/noreturn.ll new file mode 100644 index 0000000..4c876ce --- /dev/null +++ b/test/CodeGen/ARM/noreturn.ll @@ -0,0 +1,50 @@ +; RUN: llc -O3 -o - %s | FileCheck %s +; Test case from PR16882. +target triple = "thumbv7s-apple-ios" + +define i32 @test1() { +; CHECK-LABEL: @test1 +; CHECK-NOT: push +entry: + tail call void @overflow() #0 + unreachable +} + +; Function Attrs: noreturn nounwind +declare void @overflow() #0 + +define i32 @test2(i32 %x, i32 %y) { +; CHECK-LABEL: @test2 +; CHECK-NOT: push +; CHECK-NOT: pop +entry: + %conv = sext i32 %x to i64 + %conv1 = sext i32 %y to i64 + %mul = mul nsw i64 %conv1, %conv + %conv2 = trunc i64 %mul to i32 + %conv3 = sext i32 %conv2 to i64 + %cmp = icmp eq i64 %mul, %conv3 + br i1 %cmp, label %if.end, label %if.then + +if.then: ; preds = %entry + tail call void @overflow() #0 + unreachable + +if.end: ; preds = %entry + ret i32 %conv2 +} + +; Test case for PR17825. +define i32 @test3() { +; CHECK-LABEL: @test3 +; CHECK: push +entry: + tail call void @overflow_with_unwind() #1 + unreachable +} + +; Function Attrs: noreturn +declare void @overflow_with_unwind() #1 + +attributes #0 = { noreturn nounwind } +attributes #1 = { noreturn } diff --git a/test/CodeGen/ARM/optselect-regclass.ll b/test/CodeGen/ARM/optselect-regclass.ll new file mode 100644 index 0000000..1aa4520 --- /dev/null +++ b/test/CodeGen/ARM/optselect-regclass.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=arm -mcpu=swift -verify-machineinstrs +%union.opcode.0.2.5.8.15.28 = type { i32 } + +@opcode = external global %union.opcode.0.2.5.8.15.28, align 4 +@operands = external hidden global [50 x i8], align 4 +@.str86 = external hidden unnamed_addr constant [13 x i8], align 1 + +; Function Attrs: nounwind ssp +define void @xfr() { +entry: + %bf.load4 = load i32* getelementptr inbounds (%union.opcode.0.2.5.8.15.28* @opcode, i32 0, i32 0), align 4 + %bf.clear10 = and i32 %bf.load4, 65535 + %and11 = and i32 %bf.load4, 32768 + %tobool12 = icmp ne i32 %and11, 0 + %cond13 = select i1 %tobool12, i32 1073676288, i32 0 + %or = or i32 %cond13, %bf.clear10 + %shl = shl nuw i32 %or, 2 + %add = add i32 0, %shl + tail call void (i8*, i32, i32, i8*, ...)* @__sprintf_chk(i8* getelementptr inbounds ([50 x i8]* @operands, i32 0, i32 0), i32 0, i32 50, i8* getelementptr inbounds ([13 x i8]* @.str86, i32 0, i32 0), i32 undef, i32 undef, i32 %add) + ret void +} + +declare void @__sprintf_chk(i8*, i32, i32, i8*, ...) diff --git a/test/CodeGen/ARM/pic.ll b/test/CodeGen/ARM/pic.ll new file mode 100644 index 0000000..9fc7a63 --- /dev/null +++ b/test/CodeGen/ARM/pic.ll @@ -0,0 +1,23 @@ +; Check the function call in PIC relocation model. + +; If the relocation model is PIC, then the "bl" instruction for the function +; call to the external function should come with PLT fixup type. + +; RUN: llc < %s -mtriple=armv7-unknown-linux-gnueabi \ +; RUN: -relocation-model=pic -fast-isel -verify-machineinstrs \ +; RUN: | FileCheck %s + +define void @test() { +entry: + + %0 = call i32 @get() +; CHECK: bl get(PLT) + + call void @put(i32 %0) +; CHECK: bl put(PLT) + + ret void +} + +declare i32 @get() +declare void @put(i32) diff --git a/test/CodeGen/ARM/prefetch-thumb.ll b/test/CodeGen/ARM/prefetch-thumb.ll new file mode 100644 index 0000000..e6f6ae8 --- /dev/null +++ b/test/CodeGen/ARM/prefetch-thumb.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2 +; TODO: This test case will be merged back into prefetch.ll when ARM mode issue is solved. + +declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind + +define void @t6() { +entry: +;ARM: t6: +;ARM: pld [sp] +;ARM: pld [sp, #50] + +;THUMB2: t6: +;THUMB2: pld [sp] +;THUMB2: pld [sp, #50] + +%red = alloca [100 x i8], align 1 +%0 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 0 +%1 = getelementptr inbounds [100 x i8]* %red, i32 0, i32 50 +call void @llvm.prefetch(i8* %0, i32 0, i32 3, i32 1) +call void @llvm.prefetch(i8* %1, i32 0, i32 3, i32 1) +ret void +} diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 3fe2bb8..25484f4 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -239,10 +239,9 @@ bb14: ; preds = %bb6 ; PR7157 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK-LABEL: t9: -; CHECK: vldr -; CHECK-NOT: vmov d{{.*}}, d16 -; CHECK: vmov.i32 d17 +; CHECK: vmov.i32 d16, #0x0 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] +; CHECK-NEXT: vorr d17, d16, d16 ; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128] %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 5e7506a..6f4bfb8 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -11,7 +11,7 @@ entry: ; ARMT2-LABEL: t1: ; ARMT2: movw [[R:r[0-1]]], #357 -; ARMT2: movgt [[R]], #123 +; ARMT2: movwgt [[R]], #123 ; THUMB2-LABEL: t1: ; THUMB2: movw [[R:r[0-1]]], #357 @@ -25,9 +25,9 @@ entry: define i32 @t2(i32 %c) nounwind readnone { entry: ; ARM-LABEL: t2: -; ARM: mov [[R:r[0-1]]], #123 -; ARM: movgt [[R]], #101 -; ARM: orrgt [[R]], [[R]], #256 +; ARM: mov [[R:r[0-9]+]], #101 +; ARM: orr [[R]], [[R]], #256 +; ARM: movle [[R]], #123 ; ARMT2-LABEL: t2: ; ARMT2: mov [[R:r[0-1]]], #123 @@ -50,7 +50,7 @@ entry: ; ARMT2-LABEL: t3: ; ARMT2: mov [[R:r[0-1]]], #0 -; ARMT2: moveq [[R]], #1 +; ARMT2: movweq [[R]], #1 ; THUMB2-LABEL: t3: ; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #0 diff --git a/test/CodeGen/ARM/select-undef.ll b/test/CodeGen/ARM/select-undef.ll new file mode 100644 index 0000000..23f7eb8 --- /dev/null +++ b/test/CodeGen/ARM/select-undef.ll @@ -0,0 +1,7 @@ +; RUN: llc < %s -march=arm -mcpu=swift -verify-machineinstrs +define i32 @func(i32 %arg0, i32 %arg1) { +entry: + %cmp = icmp slt i32 %arg0, 10 + %v = select i1 %cmp, i32 undef, i32 %arg1 + ret i32 %v +} diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll index d5c3a27..ed006d6 100644 --- a/test/CodeGen/ARM/select.ll +++ b/test/CodeGen/ARM/select.ll @@ -59,7 +59,7 @@ entry: define double @f7(double %a, double %b) { ;CHECK-LABEL: f7: ;CHECK: movlt -;CHECK: movlt +;CHECK: movge ;CHECK-VFP-LABEL: f7: ;CHECK-VFP: vmovmi %tmp = fcmp olt double %a, 1.234e+00 @@ -75,7 +75,7 @@ define double @f7(double %a, double %b) { ; into the constant pool based on the value of the "icmp". If we have one "it" ; block generated, odds are good that we have close to the ideal code for this: ; -; CHECK-NEON: _f8: +; CHECK-NEON-LABEL: f8: ; CHECK-NEON: movw [[R3:r[0-9]+]], #1123 ; CHECK-NEON: adr [[R2:r[0-9]+]], LCPI7_0 ; CHECK-NEON-NEXT: cmp r0, [[R3]] @@ -113,7 +113,7 @@ entry: ret void } -; CHECK: f10 +; CHECK-LABEL: f10: define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp { ; CHECK-NOT: floatsisf %1 = icmp eq i32 %a, %b @@ -122,7 +122,7 @@ define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp { ret float %3 } -; CHECK: f11 +; CHECK-LABEL: f11: define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp { ; CHECK-NOT: floatsisf %1 = icmp eq i32 %a, %b @@ -130,7 +130,7 @@ define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp { ret float %2 } -; CHECK: f12 +; CHECK-LABEL: f12: define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp { ; CHECK-NOT: floatunsisf %1 = icmp eq i32 %a, %b diff --git a/test/CodeGen/ARM/setcc-sentinals.ll b/test/CodeGen/ARM/setcc-sentinals.ll new file mode 100644 index 0000000..8878f9b --- /dev/null +++ b/test/CodeGen/ARM/setcc-sentinals.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mcpu=cortex-a8 -march=arm -asm-verbose=false | FileCheck %s + +define zeroext i1 @test0(i32 %x) nounwind { +; CHECK-LABEL: test0: +; CHECK-NEXT: add [[REG:(r[0-9]+)|(lr)]], r0, #1 +; CHECK-NEXT: mov r0, #0 +; CHECK-NEXT: cmp [[REG]], #1 +; CHECK-NEXT: movwhi r0, #1 +; CHECK-NEXT: bx lr + %cmp1 = icmp ne i32 %x, -1 + %not.cmp = icmp ne i32 %x, 0 + %.cmp1 = and i1 %cmp1, %not.cmp + ret i1 %.cmp1 +} diff --git a/test/CodeGen/ARM/sincos.ll b/test/CodeGen/ARM/sincos.ll new file mode 100644 index 0000000..30b2664 --- /dev/null +++ b/test/CodeGen/ARM/sincos.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -mtriple=armv7-apple-ios6 -mcpu=cortex-a8 | FileCheck %s --check-prefix=NOOPT +; RUN: llc < %s -mtriple=armv7-apple-ios7 -mcpu=cortex-a8 | FileCheck %s --check-prefix=SINCOS + +; Combine sin / cos into a single call. +; rdar://12856873 + +define float @test1(float %x) nounwind { +entry: +; SINCOS-LABEL: test1: +; SINCOS: bl ___sincosf_stret + +; NOOPT-LABEL: test1: +; NOOPT: bl _sinf +; NOOPT: bl _cosf + %call = tail call float @sinf(float %x) nounwind readnone + %call1 = tail call float @cosf(float %x) nounwind readnone + %add = fadd float %call, %call1 + ret float %add +} + +define double @test2(double %x) nounwind { +entry: +; SINCOS-LABEL: test2: +; SINCOS: bl ___sincos_stret + +; NOOPT-LABEL: test2: +; NOOPT: bl _sin +; NOOPT: bl _cos + %call = tail call double @sin(double %x) nounwind readnone + %call1 = tail call double @cos(double %x) nounwind readnone + %add = fadd double %call, %call1 + ret double %add +} + +declare float @sinf(float) readonly +declare double @sin(double) readonly +declare float @cosf(float) readonly +declare double @cos(double) readonly diff --git a/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll b/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll new file mode 100644 index 0000000..f5cda14 --- /dev/null +++ b/test/CodeGen/ARM/stack-protector-bmovpcb_call.ll @@ -0,0 +1,32 @@ +; RUN: llc -O3 -mcpu=swift -mtriple=armv7s-apple-ios6.0.0 %s -o /dev/null +; rdar://14811848 + +; Make sure that we do not emit the BMOVPCB_CALL instruction for now or if we +; fix the assumptions in its implementation that we do not crash when doing it. + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32-S32" +target triple = "armv7s-apple-ios6.0.0" + +@main.title = private unnamed_addr constant [15 x i8] c"foo and stuff\0A\00", align 1 +@.str = private unnamed_addr constant [3 x i8] c"%s\00", align 1 + +; Function Attrs: nounwind optsize ssp +define i32 @main() #0 { +entry: + %title = alloca [15 x i8], align 1 + %0 = getelementptr inbounds [15 x i8]* %title, i32 0, i32 0 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %0, i8* getelementptr inbounds ([15 x i8]* @main.title, i32 0, i32 0), i32 15, i32 1, i1 false) + %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i8* %0) #3 + ret i32 0 +} + +; Function Attrs: nounwind +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture readonly, i32, i32, i1) #1 + +; Function Attrs: nounwind optsize +declare i32 @printf(i8* nocapture readonly, ...) #2 + +attributes #0 = { nounwind optsize ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind } +attributes #2 = { nounwind optsize "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind optsize } diff --git a/test/CodeGen/ARM/struct-byval-frame-index.ll b/test/CodeGen/ARM/struct-byval-frame-index.ll index ae68ce5..465ee12 100644 --- a/test/CodeGen/ARM/struct-byval-frame-index.ll +++ b/test/CodeGen/ARM/struct-byval-frame-index.ll @@ -72,10 +72,10 @@ declare void @SetMotionVectorsMB(%structK* nocapture, i32) #1 ; Function Attrs: nounwind define void @set_stored_macroblock_parameters() #1 { entry: - %0 = load %structB** @img, align 4, !tbaa !0 - %1 = load i32* undef, align 4, !tbaa !3 + %0 = load %structB** @img, align 4 + %1 = load i32* undef, align 4 %mb_data = getelementptr inbounds %structB* %0, i32 0, i32 61 - %2 = load %structK** %mb_data, align 4, !tbaa !0 + %2 = load %structK** %mb_data, align 4 br label %for.body for.body: ; preds = %for.body, %entry @@ -109,7 +109,7 @@ for.body119: ; preds = %for.body119, %for.c br i1 undef, label %for.body119, label %if.end164 if.end164: ; preds = %for.body119, %for.cond47.preheader, %if.end43 - store i32*** null, i32**** @cofDC, align 4, !tbaa !0 + store i32*** null, i32**** @cofDC, align 4 %mb_type = getelementptr inbounds %structK* %2, i32 %1, i32 8 br i1 undef, label %if.end230, label %if.then169 @@ -134,7 +134,7 @@ if.then233: ; preds = %if.end230 if.end236: ; preds = %if.end230 %cmp242 = icmp ne i16 undef, 8 - %4 = load i32* @luma_transform_size_8x8_flag, align 4, !tbaa !3 + %4 = load i32* @luma_transform_size_8x8_flag, align 4 %tobool245 = icmp ne i32 %4, 0 %or.cond812 = or i1 %cmp242, %tobool245 br i1 %or.cond812, label %if.end249, label %land.lhs.true246 @@ -150,11 +150,11 @@ if.then248: ; preds = %land.lhs.true246 br label %if.end249 if.end249: ; preds = %if.then248, %land.lhs.true246, %if.end236 - %5 = load i32* @luma_transform_size_8x8_flag, align 4, !tbaa !3 - %6 = load %structA** @rdopt, align 4, !tbaa !0 + %5 = load i32* @luma_transform_size_8x8_flag, align 4 + %6 = load %structA** @rdopt, align 4 %luma_transform_size_8x8_flag264 = getelementptr inbounds %structA* %6, i32 0, i32 21 - store i32 %5, i32* %luma_transform_size_8x8_flag264, align 4, !tbaa !3 - %7 = load i32* undef, align 4, !tbaa !3 + store i32 %5, i32* %luma_transform_size_8x8_flag264, align 4 + %7 = load i32* undef, align 4 %add281 = add nsw i32 %7, 0 br label %for.body285 @@ -162,36 +162,36 @@ for.body285: ; preds = %for.inc503, %if.end %8 = phi %structB* [ undef, %if.end249 ], [ %.pre1155, %for.inc503 ] %i.21103 = phi i32 [ 0, %if.end249 ], [ %inc504, %for.inc503 ] %block_x286 = getelementptr inbounds %structB* %8, i32 0, i32 37 - %9 = load i32* %block_x286, align 4, !tbaa !3 + %9 = load i32* %block_x286, align 4 %add287 = add nsw i32 %9, %i.21103 %shr289 = ashr i32 %i.21103, 1 %add290 = add nsw i32 %shr289, 0 %arrayidx292 = getelementptr inbounds %structK* %2, i32 %1, i32 15, i32 %add290 - %10 = load %structM** @enc_picture, align 4, !tbaa !0 + %10 = load %structM** @enc_picture, align 4 %ref_idx = getelementptr inbounds %structM* %10, i32 0, i32 35 - %11 = load i8**** %ref_idx, align 4, !tbaa !0 - %12 = load i8*** %11, align 4, !tbaa !0 + %11 = load i8**** %ref_idx, align 4 + %12 = load i8*** %11, align 4 %arrayidx313 = getelementptr inbounds i8** %12, i32 %add281 - %13 = load i8** %arrayidx313, align 4, !tbaa !0 + %13 = load i8** %arrayidx313, align 4 %arrayidx314 = getelementptr inbounds i8* %13, i32 %add287 - store i8 -1, i8* %arrayidx314, align 1, !tbaa !1 - %14 = load %structB** @img, align 4, !tbaa !0 + store i8 -1, i8* %arrayidx314, align 1 + %14 = load %structB** @img, align 4 %MbaffFrameFlag327 = getelementptr inbounds %structB* %14, i32 0, i32 100 - %15 = load i32* %MbaffFrameFlag327, align 4, !tbaa !3 + %15 = load i32* %MbaffFrameFlag327, align 4 %tobool328 = icmp eq i32 %15, 0 br i1 %tobool328, label %if.end454, label %if.then329 if.then329: ; preds = %for.body285 - %16 = load %structA** @rdopt, align 4, !tbaa !0 + %16 = load %structA** @rdopt, align 4 br label %if.end454 if.end454: ; preds = %if.then329, %for.body285 - %17 = load i32* %arrayidx292, align 4, !tbaa !3 + %17 = load i32* %arrayidx292, align 4 %cmp457 = icmp eq i32 %17, 0 br i1 %cmp457, label %if.then475, label %lor.lhs.false459 lor.lhs.false459: ; preds = %if.end454 - %18 = load i32* %mb_type, align 4, !tbaa !3 + %18 = load i32* %mb_type, align 4 switch i32 %18, label %for.inc503 [ i32 9, label %if.then475 i32 10, label %if.then475 @@ -200,12 +200,12 @@ lor.lhs.false459: ; preds = %if.end454 ] if.then475: ; preds = %lor.lhs.false459, %lor.lhs.false459, %lor.lhs.false459, %lor.lhs.false459, %if.end454 - store i16 0, i16* undef, align 2, !tbaa !4 + store i16 0, i16* undef, align 2 br label %for.inc503 for.inc503: ; preds = %if.then475, %lor.lhs.false459 %inc504 = add nsw i32 %i.21103, 1 - %.pre1155 = load %structB** @img, align 4, !tbaa !0 + %.pre1155 = load %structB** @img, align 4 br label %for.body285 } @@ -216,10 +216,4 @@ declare void @update_offset_params(i32, i32) #1 declare void @RestoreMVBlock8x8(i32, i32, %structN* byval nocapture, i32) #1 attributes #0 = { nounwind } -attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } - -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"int", metadata !1} -!4 = metadata !{metadata !"short", metadata !1} +attributes #1 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll index 012b994..130925a 100644 --- a/test/CodeGen/ARM/struct_byval.ll +++ b/test/CodeGen/ARM/struct_byval.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios6.0 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-ios6.0 | FileCheck %s -check-prefix=THUMB ; rdar://9877866 %struct.SmallStruct = type { i32, [8 x i32], [37 x i8] } @@ -10,6 +11,10 @@ entry: ; CHECK: ldr ; CHECK: str ; CHECK-NOT:bne +; THUMB-LABEL: f: +; THUMB: ldr +; THUMB: str +; THUMB-NOT:bne %st = alloca %struct.SmallStruct, align 4 %call = call i32 @e1(%struct.SmallStruct* byval %st) ret i32 0 @@ -23,6 +28,11 @@ entry: ; CHECK: sub ; CHECK: str ; CHECK: bne +; THUMB-LABEL: g: +; THUMB: ldr +; THUMB: sub +; THUMB: str +; THUMB: bne %st = alloca %struct.LargeStruct, align 4 %call = call i32 @e2(%struct.LargeStruct* byval %st) ret i32 0 @@ -36,6 +46,11 @@ entry: ; CHECK: sub ; CHECK: vst1 ; CHECK: bne +; THUMB-LABEL: h: +; THUMB: vld1 +; THUMB: sub +; THUMB: vst1 +; THUMB: bne %st = alloca %struct.LargeStruct, align 16 %call = call i32 @e3(%struct.LargeStruct* byval align 16 %st) ret i32 0 @@ -49,8 +64,10 @@ declare i32 @e3(%struct.LargeStruct* nocapture byval align 16 %in) nounwind ; We can't do tail call since address of s is passed to the callee and part of ; s is in caller's local frame. define void @f3(%struct.SmallStruct* nocapture byval %s) nounwind optsize { -; CHECK: f3 +; CHECK-LABEL: f3 ; CHECK: bl _consumestruct +; THUMB-LABEL: f3 +; THUMB: blx _consumestruct entry: %0 = bitcast %struct.SmallStruct* %s to i8* tail call void @consumestruct(i8* %0, i32 80) optsize @@ -58,8 +75,10 @@ entry: } define void @f4(%struct.SmallStruct* nocapture byval %s) nounwind optsize { -; CHECK: f4 +; CHECK-LABEL: f4 ; CHECK: bl _consumestruct +; THUMB-LABEL: f4 +; THUMB: blx _consumestruct entry: %addr = getelementptr inbounds %struct.SmallStruct* %s, i32 0, i32 0 %0 = bitcast i32* %addr to i8* @@ -69,8 +88,10 @@ entry: ; We can do tail call here since s is in the incoming argument area. define void @f5(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize { -; CHECK: f5 +; CHECK-LABEL: f5 ; CHECK: b _consumestruct +; THUMB-LABEL: f5 +; THUMB: b.w _consumestruct entry: %0 = bitcast %struct.SmallStruct* %s to i8* tail call void @consumestruct(i8* %0, i32 80) optsize @@ -78,8 +99,10 @@ entry: } define void @f6(i32 %a, i32 %b, i32 %c, i32 %d, %struct.SmallStruct* nocapture byval %s) nounwind optsize { -; CHECK: f6 +; CHECK-LABEL: f6 ; CHECK: b _consumestruct +; THUMB-LABEL: f6 +; THUMB: b.w _consumestruct entry: %addr = getelementptr inbounds %struct.SmallStruct* %s, i32 0, i32 0 %0 = bitcast i32* %addr to i8* @@ -88,3 +111,19 @@ entry: } declare void @consumestruct(i8* nocapture %structp, i32 %structsize) nounwind + +; PR17309 +%struct.I.8 = type { [10 x i32], [3 x i8] } + +declare void @use_I(%struct.I.8* byval) +define void @test_I_16() { +; CHECK-LABEL: test_I_16 +; CHECK: ldrb +; CHECK: strb +; THUMB-LABEL: test_I_16 +; THUMB: ldrb +; THUMB: strb +entry: + call void @use_I(%struct.I.8* byval align 16 undef) + ret void +} diff --git a/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll b/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll new file mode 100644 index 0000000..1899269 --- /dev/null +++ b/test/CodeGen/ARM/struct_byval_arm_t1_t2.ll @@ -0,0 +1,1523 @@ +;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple armv7-none-linux-gnueabi -disassemble - | FileCheck %s --check-prefix=ARM +;RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabi -mattr=+neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv7-none-linux-gnueabi -disassemble - | FileCheck %s --check-prefix=THUMB2 +;RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mattr=-neon -verify-machineinstrs -filetype=obj | llvm-objdump -triple armv7-none-linux-gnueabi -disassemble - | FileCheck %s --check-prefix=NO_NEON +;We want to have both positive and negative checks for thumb1. These checks +;are not easy to do in a single pass so we generate the output once to a +;temp file and run filecheck twice with different prefixes. +;RUN: llc < %s -mtriple=thumbv5-none-linux-gnueabi -verify-machineinstrs -filetype=obj | llvm-objdump -triple thumbv5-none-linux-gnueabi -disassemble - > %t +;RUN: cat %t | FileCheck %s --check-prefix=THUMB1 +;RUN: cat %t | FileCheck %s --check-prefix=T1POST + +;This file contains auto generated tests for the lowering of passing structs +;byval in the arm backend. We have tests for both packed and unpacked +;structs at varying alignments. Each test is run for arm, thumb2 and thumb1. +;We check for the strings in the generated object code using llvm-objdump +;because it provides better assurance that we are generating instructions +;for the correct architecture. Otherwise we could accidently generate an +;ARM instruction for THUMB1 and wouldn't detect it because the assembly +;code representation is the same, but the object code would be generated +;incorrectly. For each test we check for the label, a load instruction of the +;correct form, a branch if it will be generated with a loop, and the leftover +;cleanup if the number of bytes does not divide evenly by the store size + +%struct.A = type <{ [ 10 x i32 ] }> ; 40 bytes +declare void @use_A(%struct.A* byval) +%struct.B = type <{ [ 10 x i32 ], i8 }> ; 41 bytes +declare void @use_B(%struct.B* byval) +%struct.C = type <{ [ 10 x i32 ], [ 3 x i8 ] }> ; 43 bytes +declare void @use_C(%struct.C* byval) +%struct.D = type <{ [ 100 x i32 ] }> ; 400 bytes +declare void @use_D(%struct.D* byval) +%struct.E = type <{ [ 100 x i32 ], i8 }> ; 401 bytes +declare void @use_E(%struct.E* byval) +%struct.F = type <{ [ 100 x i32 ], [ 3 x i8 ] }> ; 403 bytes +declare void @use_F(%struct.F* byval) +%struct.G = type { [ 10 x i32 ] } ; 40 bytes +declare void @use_G(%struct.G* byval) +%struct.H = type { [ 10 x i32 ], i8 } ; 41 bytes +declare void @use_H(%struct.H* byval) +%struct.I = type { [ 10 x i32 ], [ 3 x i8 ] } ; 43 bytes +declare void @use_I(%struct.I* byval) +%struct.J = type { [ 100 x i32 ] } ; 400 bytes +declare void @use_J(%struct.J* byval) +%struct.K = type { [ 100 x i32 ], i8 } ; 401 bytes +declare void @use_K(%struct.K* byval) +%struct.L = type { [ 100 x i32 ], [ 3 x i8 ] } ; 403 bytes +declare void @use_L(%struct.L* byval) + +;ARM-LABEL: test_A_1: +;THUMB2-LABEL: test_A_1: +;NO_NEON-LABEL:test_A_1: +;THUMB1-LABEL: test_A_1: +;T1POST-LABEL: test_A_1: + define void @test_A_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.A, align 1 + call void @use_A(%struct.A* byval align 1 %a) + ret void + } +;ARM-LABEL: test_A_2: +;THUMB2-LABEL: test_A_2: +;NO_NEON-LABEL:test_A_2: +;THUMB1-LABEL: test_A_2: +;T1POST-LABEL: test_A_2: + define void @test_A_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.A, align 2 + call void @use_A(%struct.A* byval align 2 %a) + ret void + } +;ARM-LABEL: test_A_4: +;THUMB2-LABEL: test_A_4: +;NO_NEON-LABEL:test_A_4: +;THUMB1-LABEL: test_A_4: +;T1POST-LABEL: test_A_4: + define void @test_A_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.A, align 4 + call void @use_A(%struct.A* byval align 4 %a) + ret void + } +;ARM-LABEL: test_A_8: +;THUMB2-LABEL: test_A_8: +;NO_NEON-LABEL:test_A_8: +;THUMB1-LABEL: test_A_8: +;T1POST-LABEL: test_A_8: + define void @test_A_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.A, align 8 + call void @use_A(%struct.A* byval align 8 %a) + ret void + } +;ARM-LABEL: test_A_16: +;THUMB2-LABEL: test_A_16: +;NO_NEON-LABEL:test_A_16: +;THUMB1-LABEL: test_A_16: +;T1POST-LABEL: test_A_16: + define void @test_A_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.A, align 16 + call void @use_A(%struct.A* byval align 16 %a) + ret void + } +;ARM-LABEL: test_B_1: +;THUMB2-LABEL: test_B_1: +;NO_NEON-LABEL:test_B_1: +;THUMB1-LABEL: test_B_1: +;T1POST-LABEL: test_B_1: + define void @test_B_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.B, align 1 + call void @use_B(%struct.B* byval align 1 %a) + ret void + } +;ARM-LABEL: test_B_2: +;THUMB2-LABEL: test_B_2: +;NO_NEON-LABEL:test_B_2: +;THUMB1-LABEL: test_B_2: +;T1POST-LABEL: test_B_2: + define void @test_B_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.B, align 2 + call void @use_B(%struct.B* byval align 2 %a) + ret void + } +;ARM-LABEL: test_B_4: +;THUMB2-LABEL: test_B_4: +;NO_NEON-LABEL:test_B_4: +;THUMB1-LABEL: test_B_4: +;T1POST-LABEL: test_B_4: + define void @test_B_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.B, align 4 + call void @use_B(%struct.B* byval align 4 %a) + ret void + } +;ARM-LABEL: test_B_8: +;THUMB2-LABEL: test_B_8: +;NO_NEON-LABEL:test_B_8: +;THUMB1-LABEL: test_B_8: +;T1POST-LABEL: test_B_8: + define void @test_B_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.B, align 8 + call void @use_B(%struct.B* byval align 8 %a) + ret void + } +;ARM-LABEL: test_B_16: +;THUMB2-LABEL: test_B_16: +;NO_NEON-LABEL:test_B_16: +;THUMB1-LABEL: test_B_16: +;T1POST-LABEL: test_B_16: + define void @test_B_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.B, align 16 + call void @use_B(%struct.B* byval align 16 %a) + ret void + } +;ARM-LABEL: test_C_1: +;THUMB2-LABEL: test_C_1: +;NO_NEON-LABEL:test_C_1: +;THUMB1-LABEL: test_C_1: +;T1POST-LABEL: test_C_1: + define void @test_C_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.C, align 1 + call void @use_C(%struct.C* byval align 1 %a) + ret void + } +;ARM-LABEL: test_C_2: +;THUMB2-LABEL: test_C_2: +;NO_NEON-LABEL:test_C_2: +;THUMB1-LABEL: test_C_2: +;T1POST-LABEL: test_C_2: + define void @test_C_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.C, align 2 + call void @use_C(%struct.C* byval align 2 %a) + ret void + } +;ARM-LABEL: test_C_4: +;THUMB2-LABEL: test_C_4: +;NO_NEON-LABEL:test_C_4: +;THUMB1-LABEL: test_C_4: +;T1POST-LABEL: test_C_4: + define void @test_C_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.C, align 4 + call void @use_C(%struct.C* byval align 4 %a) + ret void + } +;ARM-LABEL: test_C_8: +;THUMB2-LABEL: test_C_8: +;NO_NEON-LABEL:test_C_8: +;THUMB1-LABEL: test_C_8: +;T1POST-LABEL: test_C_8: + define void @test_C_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.C, align 8 + call void @use_C(%struct.C* byval align 8 %a) + ret void + } +;ARM-LABEL: test_C_16: +;THUMB2-LABEL: test_C_16: +;NO_NEON-LABEL:test_C_16: +;THUMB1-LABEL: test_C_16: +;T1POST-LABEL: test_C_16: + define void @test_C_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.C, align 16 + call void @use_C(%struct.C* byval align 16 %a) + ret void + } +;ARM-LABEL: test_D_1: +;THUMB2-LABEL: test_D_1: +;NO_NEON-LABEL:test_D_1: +;THUMB1-LABEL: test_D_1: +;T1POST-LABEL: test_D_1: + define void @test_D_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;ARM: bne + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;THUMB2: bne + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON: bne + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 +;THUMB1: bne + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.D, align 1 + call void @use_D(%struct.D* byval align 1 %a) + ret void + } +;ARM-LABEL: test_D_2: +;THUMB2-LABEL: test_D_2: +;NO_NEON-LABEL:test_D_2: +;THUMB1-LABEL: test_D_2: +;T1POST-LABEL: test_D_2: + define void @test_D_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;ARM: bne + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;THUMB2: bne + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;NO_NEON: bne + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 +;THUMB1: bne + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.D, align 2 + call void @use_D(%struct.D* byval align 2 %a) + ret void + } +;ARM-LABEL: test_D_4: +;THUMB2-LABEL: test_D_4: +;NO_NEON-LABEL:test_D_4: +;THUMB1-LABEL: test_D_4: +;T1POST-LABEL: test_D_4: + define void @test_D_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 +;ARM: bne + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.D, align 4 + call void @use_D(%struct.D* byval align 4 %a) + ret void + } +;ARM-LABEL: test_D_8: +;THUMB2-LABEL: test_D_8: +;NO_NEON-LABEL:test_D_8: +;THUMB1-LABEL: test_D_8: +;T1POST-LABEL: test_D_8: + define void @test_D_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.D, align 8 + call void @use_D(%struct.D* byval align 8 %a) + ret void + } +;ARM-LABEL: test_D_16: +;THUMB2-LABEL: test_D_16: +;NO_NEON-LABEL:test_D_16: +;THUMB1-LABEL: test_D_16: +;T1POST-LABEL: test_D_16: + define void @test_D_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.D, align 16 + call void @use_D(%struct.D* byval align 16 %a) + ret void + } +;ARM-LABEL: test_E_1: +;THUMB2-LABEL: test_E_1: +;NO_NEON-LABEL:test_E_1: +;THUMB1-LABEL: test_E_1: +;T1POST-LABEL: test_E_1: + define void @test_E_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;ARM: bne + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;THUMB2: bne + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON: bne + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 +;THUMB1: bne + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.E, align 1 + call void @use_E(%struct.E* byval align 1 %a) + ret void + } +;ARM-LABEL: test_E_2: +;THUMB2-LABEL: test_E_2: +;NO_NEON-LABEL:test_E_2: +;THUMB1-LABEL: test_E_2: +;T1POST-LABEL: test_E_2: + define void @test_E_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;ARM: bne +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;THUMB2: bne +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;NO_NEON: bne +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 +;THUMB1: bne +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.E, align 2 + call void @use_E(%struct.E* byval align 2 %a) + ret void + } +;ARM-LABEL: test_E_4: +;THUMB2-LABEL: test_E_4: +;NO_NEON-LABEL:test_E_4: +;THUMB1-LABEL: test_E_4: +;T1POST-LABEL: test_E_4: + define void @test_E_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 +;ARM: bne +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 +;THUMB2: bne +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.E, align 4 + call void @use_E(%struct.E* byval align 4 %a) + ret void + } +;ARM-LABEL: test_E_8: +;THUMB2-LABEL: test_E_8: +;NO_NEON-LABEL:test_E_8: +;THUMB1-LABEL: test_E_8: +;T1POST-LABEL: test_E_8: + define void @test_E_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.E, align 8 + call void @use_E(%struct.E* byval align 8 %a) + ret void + } +;ARM-LABEL: test_E_16: +;THUMB2-LABEL: test_E_16: +;NO_NEON-LABEL:test_E_16: +;THUMB1-LABEL: test_E_16: +;T1POST-LABEL: test_E_16: + define void @test_E_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.E, align 16 + call void @use_E(%struct.E* byval align 16 %a) + ret void + } +;ARM-LABEL: test_F_1: +;THUMB2-LABEL: test_F_1: +;NO_NEON-LABEL:test_F_1: +;THUMB1-LABEL: test_F_1: +;T1POST-LABEL: test_F_1: + define void @test_F_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;ARM: bne + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;THUMB2: bne + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON: bne + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 +;THUMB1: bne + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.F, align 1 + call void @use_F(%struct.F* byval align 1 %a) + ret void + } +;ARM-LABEL: test_F_2: +;THUMB2-LABEL: test_F_2: +;NO_NEON-LABEL:test_F_2: +;THUMB1-LABEL: test_F_2: +;T1POST-LABEL: test_F_2: + define void @test_F_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;ARM: bne +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;THUMB2: bne +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;NO_NEON: bne +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 +;THUMB1: bne +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.F, align 2 + call void @use_F(%struct.F* byval align 2 %a) + ret void + } +;ARM-LABEL: test_F_4: +;THUMB2-LABEL: test_F_4: +;NO_NEON-LABEL:test_F_4: +;THUMB1-LABEL: test_F_4: +;T1POST-LABEL: test_F_4: + define void @test_F_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 +;ARM: bne +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 +;THUMB2: bne +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.F, align 4 + call void @use_F(%struct.F* byval align 4 %a) + ret void + } +;ARM-LABEL: test_F_8: +;THUMB2-LABEL: test_F_8: +;NO_NEON-LABEL:test_F_8: +;THUMB1-LABEL: test_F_8: +;T1POST-LABEL: test_F_8: + define void @test_F_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.F, align 8 + call void @use_F(%struct.F* byval align 8 %a) + ret void + } +;ARM-LABEL: test_F_16: +;THUMB2-LABEL: test_F_16: +;NO_NEON-LABEL:test_F_16: +;THUMB1-LABEL: test_F_16: +;T1POST-LABEL: test_F_16: + define void @test_F_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.F, align 16 + call void @use_F(%struct.F* byval align 16 %a) + ret void + } +;ARM-LABEL: test_G_1: +;THUMB2-LABEL: test_G_1: +;NO_NEON-LABEL:test_G_1: +;THUMB1-LABEL: test_G_1: +;T1POST-LABEL: test_G_1: + define void @test_G_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.G, align 1 + call void @use_G(%struct.G* byval align 1 %a) + ret void + } +;ARM-LABEL: test_G_2: +;THUMB2-LABEL: test_G_2: +;NO_NEON-LABEL:test_G_2: +;THUMB1-LABEL: test_G_2: +;T1POST-LABEL: test_G_2: + define void @test_G_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.G, align 2 + call void @use_G(%struct.G* byval align 2 %a) + ret void + } +;ARM-LABEL: test_G_4: +;THUMB2-LABEL: test_G_4: +;NO_NEON-LABEL:test_G_4: +;THUMB1-LABEL: test_G_4: +;T1POST-LABEL: test_G_4: + define void @test_G_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.G, align 4 + call void @use_G(%struct.G* byval align 4 %a) + ret void + } +;ARM-LABEL: test_G_8: +;THUMB2-LABEL: test_G_8: +;NO_NEON-LABEL:test_G_8: +;THUMB1-LABEL: test_G_8: +;T1POST-LABEL: test_G_8: + define void @test_G_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.G, align 8 + call void @use_G(%struct.G* byval align 8 %a) + ret void + } +;ARM-LABEL: test_G_16: +;THUMB2-LABEL: test_G_16: +;NO_NEON-LABEL:test_G_16: +;THUMB1-LABEL: test_G_16: +;T1POST-LABEL: test_G_16: + define void @test_G_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.G, align 16 + call void @use_G(%struct.G* byval align 16 %a) + ret void + } +;ARM-LABEL: test_H_1: +;THUMB2-LABEL: test_H_1: +;NO_NEON-LABEL:test_H_1: +;THUMB1-LABEL: test_H_1: +;T1POST-LABEL: test_H_1: + define void @test_H_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.H, align 1 + call void @use_H(%struct.H* byval align 1 %a) + ret void + } +;ARM-LABEL: test_H_2: +;THUMB2-LABEL: test_H_2: +;NO_NEON-LABEL:test_H_2: +;THUMB1-LABEL: test_H_2: +;T1POST-LABEL: test_H_2: + define void @test_H_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.H, align 2 + call void @use_H(%struct.H* byval align 2 %a) + ret void + } +;ARM-LABEL: test_H_4: +;THUMB2-LABEL: test_H_4: +;NO_NEON-LABEL:test_H_4: +;THUMB1-LABEL: test_H_4: +;T1POST-LABEL: test_H_4: + define void @test_H_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.H, align 4 + call void @use_H(%struct.H* byval align 4 %a) + ret void + } +;ARM-LABEL: test_H_8: +;THUMB2-LABEL: test_H_8: +;NO_NEON-LABEL:test_H_8: +;THUMB1-LABEL: test_H_8: +;T1POST-LABEL: test_H_8: + define void @test_H_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.H, align 8 + call void @use_H(%struct.H* byval align 8 %a) + ret void + } +;ARM-LABEL: test_H_16: +;THUMB2-LABEL: test_H_16: +;NO_NEON-LABEL:test_H_16: +;THUMB1-LABEL: test_H_16: +;T1POST-LABEL: test_H_16: + define void @test_H_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.H, align 16 + call void @use_H(%struct.H* byval align 16 %a) + ret void + } +;ARM-LABEL: test_I_1: +;THUMB2-LABEL: test_I_1: +;NO_NEON-LABEL:test_I_1: +;THUMB1-LABEL: test_I_1: +;T1POST-LABEL: test_I_1: + define void @test_I_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.I, align 1 + call void @use_I(%struct.I* byval align 1 %a) + ret void + } +;ARM-LABEL: test_I_2: +;THUMB2-LABEL: test_I_2: +;NO_NEON-LABEL:test_I_2: +;THUMB1-LABEL: test_I_2: +;T1POST-LABEL: test_I_2: + define void @test_I_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.I, align 2 + call void @use_I(%struct.I* byval align 2 %a) + ret void + } +;ARM-LABEL: test_I_4: +;THUMB2-LABEL: test_I_4: +;NO_NEON-LABEL:test_I_4: +;THUMB1-LABEL: test_I_4: +;T1POST-LABEL: test_I_4: + define void @test_I_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.I, align 4 + call void @use_I(%struct.I* byval align 4 %a) + ret void + } +;ARM-LABEL: test_I_8: +;THUMB2-LABEL: test_I_8: +;NO_NEON-LABEL:test_I_8: +;THUMB1-LABEL: test_I_8: +;T1POST-LABEL: test_I_8: + define void @test_I_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.I, align 8 + call void @use_I(%struct.I* byval align 8 %a) + ret void + } +;ARM-LABEL: test_I_16: +;THUMB2-LABEL: test_I_16: +;NO_NEON-LABEL:test_I_16: +;THUMB1-LABEL: test_I_16: +;T1POST-LABEL: test_I_16: + define void @test_I_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.I, align 16 + call void @use_I(%struct.I* byval align 16 %a) + ret void + } +;ARM-LABEL: test_J_1: +;THUMB2-LABEL: test_J_1: +;NO_NEON-LABEL:test_J_1: +;THUMB1-LABEL: test_J_1: +;T1POST-LABEL: test_J_1: + define void @test_J_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;ARM: bne + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;THUMB2: bne + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON: bne + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 +;THUMB1: bne + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.J, align 1 + call void @use_J(%struct.J* byval align 1 %a) + ret void + } +;ARM-LABEL: test_J_2: +;THUMB2-LABEL: test_J_2: +;NO_NEON-LABEL:test_J_2: +;THUMB1-LABEL: test_J_2: +;T1POST-LABEL: test_J_2: + define void @test_J_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;ARM: bne + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;THUMB2: bne + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;NO_NEON: bne + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 +;THUMB1: bne + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.J, align 2 + call void @use_J(%struct.J* byval align 2 %a) + ret void + } +;ARM-LABEL: test_J_4: +;THUMB2-LABEL: test_J_4: +;NO_NEON-LABEL:test_J_4: +;THUMB1-LABEL: test_J_4: +;T1POST-LABEL: test_J_4: + define void @test_J_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 +;ARM: bne + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.J, align 4 + call void @use_J(%struct.J* byval align 4 %a) + ret void + } +;ARM-LABEL: test_J_8: +;THUMB2-LABEL: test_J_8: +;NO_NEON-LABEL:test_J_8: +;THUMB1-LABEL: test_J_8: +;T1POST-LABEL: test_J_8: + define void @test_J_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.J, align 8 + call void @use_J(%struct.J* byval align 8 %a) + ret void + } +;ARM-LABEL: test_J_16: +;THUMB2-LABEL: test_J_16: +;NO_NEON-LABEL:test_J_16: +;THUMB1-LABEL: test_J_16: +;T1POST-LABEL: test_J_16: + define void @test_J_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.J, align 16 + call void @use_J(%struct.J* byval align 16 %a) + ret void + } +;ARM-LABEL: test_K_1: +;THUMB2-LABEL: test_K_1: +;NO_NEON-LABEL:test_K_1: +;THUMB1-LABEL: test_K_1: +;T1POST-LABEL: test_K_1: + define void @test_K_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;ARM: bne + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;THUMB2: bne + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON: bne + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 +;THUMB1: bne + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.K, align 1 + call void @use_K(%struct.K* byval align 1 %a) + ret void + } +;ARM-LABEL: test_K_2: +;THUMB2-LABEL: test_K_2: +;NO_NEON-LABEL:test_K_2: +;THUMB1-LABEL: test_K_2: +;T1POST-LABEL: test_K_2: + define void @test_K_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;ARM: bne + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;THUMB2: bne + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;NO_NEON: bne + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 +;THUMB1: bne + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.K, align 2 + call void @use_K(%struct.K* byval align 2 %a) + ret void + } +;ARM-LABEL: test_K_4: +;THUMB2-LABEL: test_K_4: +;NO_NEON-LABEL:test_K_4: +;THUMB1-LABEL: test_K_4: +;T1POST-LABEL: test_K_4: + define void @test_K_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 +;ARM: bne + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.K, align 4 + call void @use_K(%struct.K* byval align 4 %a) + ret void + } +;ARM-LABEL: test_K_8: +;THUMB2-LABEL: test_K_8: +;NO_NEON-LABEL:test_K_8: +;THUMB1-LABEL: test_K_8: +;T1POST-LABEL: test_K_8: + define void @test_K_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.K, align 8 + call void @use_K(%struct.K* byval align 8 %a) + ret void + } +;ARM-LABEL: test_K_16: +;THUMB2-LABEL: test_K_16: +;NO_NEON-LABEL:test_K_16: +;THUMB1-LABEL: test_K_16: +;T1POST-LABEL: test_K_16: + define void @test_K_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.K, align 16 + call void @use_K(%struct.K* byval align 16 %a) + ret void + } +;ARM-LABEL: test_L_1: +;THUMB2-LABEL: test_L_1: +;NO_NEON-LABEL:test_L_1: +;THUMB1-LABEL: test_L_1: +;T1POST-LABEL: test_L_1: + define void @test_L_1() { +;ARM: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;ARM: bne + +;THUMB2: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;THUMB2: bne + +;NO_NEON: ldrb r{{[0-9]+}}, [{{.*}}], #1 +;NO_NEON: bne + +;THUMB1: ldrb r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #1 +;THUMB1: bne + +;T1POST-NOT: ldrb r{{[0-9]+}}, [{{.*}}], #1 + entry: + %a = alloca %struct.L, align 1 + call void @use_L(%struct.L* byval align 1 %a) + ret void + } +;ARM-LABEL: test_L_2: +;THUMB2-LABEL: test_L_2: +;NO_NEON-LABEL:test_L_2: +;THUMB1-LABEL: test_L_2: +;T1POST-LABEL: test_L_2: + define void @test_L_2() { +;ARM: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;ARM: bne + +;THUMB2: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;THUMB2: bne + +;NO_NEON: ldrh r{{[0-9]+}}, [{{.*}}], #2 +;NO_NEON: bne + +;THUMB1: ldrh r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #2 +;THUMB1: bne + +;T1POST-NOT: ldrh r{{[0-9]+}}, [{{.*}}], #2 + entry: + %a = alloca %struct.L, align 2 + call void @use_L(%struct.L* byval align 2 %a) + ret void + } +;ARM-LABEL: test_L_4: +;THUMB2-LABEL: test_L_4: +;NO_NEON-LABEL:test_L_4: +;THUMB1-LABEL: test_L_4: +;T1POST-LABEL: test_L_4: + define void @test_L_4() { +;ARM: ldr r{{[0-9]+}}, [{{.*}}], #4 +;ARM: bne + +;THUMB2: ldr r{{[0-9]+}}, [{{.*}}], #4 +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: ldr r{{[0-9]+}}, [{{.*}}], #4 + entry: + %a = alloca %struct.L, align 4 + call void @use_L(%struct.L* byval align 4 %a) + ret void + } +;ARM-LABEL: test_L_8: +;THUMB2-LABEL: test_L_8: +;NO_NEON-LABEL:test_L_8: +;THUMB1-LABEL: test_L_8: +;T1POST-LABEL: test_L_8: + define void @test_L_8() { +;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne + +;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.L, align 8 + call void @use_L(%struct.L* byval align 8 %a) + ret void + } +;ARM-LABEL: test_L_16: +;THUMB2-LABEL: test_L_16: +;NO_NEON-LABEL:test_L_16: +;THUMB1-LABEL: test_L_16: +;T1POST-LABEL: test_L_16: + define void @test_L_16() { +;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;ARM: bne + +;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! +;THUMB2: bne + +;NO_NEON: ldr r{{[0-9]+}}, [{{.*}}], #4 +;NO_NEON: bne +;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + +;THUMB1: ldr r{{[0-9]+}}, {{\[}}[[BASE:r[0-9]+]]{{\]}} +;THUMB1: adds [[BASE]], #4 +;THUMB1: bne + +;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]! + entry: + %a = alloca %struct.L, align 16 + call void @use_L(%struct.L* byval align 16 %a) + ret void + } diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll index 1b411e3..19727da 100644 --- a/test/CodeGen/ARM/sub-cmp-peephole.ll +++ b/test/CodeGen/ARM/sub-cmp-peephole.ll @@ -1,4 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s --check-prefix=V7 +; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi | FileCheck %s -check-prefix=V8 + define i32 @f(i32 %a, i32 %b) nounwind ssp { entry: @@ -84,3 +87,60 @@ land.lhs.true: ; preds = %num2long.exit if.end11: ; preds = %num2long.exit ret i32 23 } + +define float @float_sel(i32 %a, i32 %b, float %x, float %y) { +entry: +; CHECK-LABEL: float_sel: +; CHECK-NOT: cmp +; V8-LABEL: float_sel: +; V8-NOT: cmp +; V8: vseleq.f32 + %sub = sub i32 %a, %b + %cmp = icmp eq i32 %sub, 0 + %ret = select i1 %cmp, float %x, float %y + ret float %ret +} + +define double @double_sel(i32 %a, i32 %b, double %x, double %y) { +entry: +; CHECK-LABEL: double_sel: +; CHECK-NOT: cmp +; V8-LABEL: double_sel: +; V8-NOT: cmp +; V8: vseleq.f64 + %sub = sub i32 %a, %b + %cmp = icmp eq i32 %sub, 0 + %ret = select i1 %cmp, double %x, double %y + ret double %ret +} + +@t = common global i32 0 +define double @double_sub(i32 %a, i32 %b, double %x, double %y) { +entry: +; CHECK-LABEL: double_sub: +; CHECK: subs +; CHECK-NOT: cmp +; V8-LABEL: double_sub: +; V8: vsel + %cmp = icmp sgt i32 %a, %b + %sub = sub i32 %a, %b + store i32 %sub, i32* @t + %ret = select i1 %cmp, double %x, double %y + ret double %ret +} + +define double @double_sub_swap(i32 %a, i32 %b, double %x, double %y) { +entry: +; V7-LABEL: double_sub_swap: +; V7-NOT: cmp +; V7: subs +; V8-LABEL: double_sub_swap: +; V8-NOT: subs +; V8: cmp +; V8: vsel + %cmp = icmp sgt i32 %a, %b + %sub = sub i32 %b, %a + %ret = select i1 %cmp, double %x, double %y + store i32 %sub, i32* @t + ret double %ret +} diff --git a/test/CodeGen/ARM/swift-vldm.ll b/test/CodeGen/ARM/swift-vldm.ll new file mode 100644 index 0000000..67ae00a --- /dev/null +++ b/test/CodeGen/ARM/swift-vldm.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s + +; Check that we avoid producing vldm instructions using d registers that +; begin in the most-significant half of a q register. These require more +; micro-ops on swift and so aren't worth combining. + +; CHECK-LABEL: test_vldm +; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4} +; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4} + +declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4) + +define void @test_vldm(double* %x, double * %y) { +entry: + %addr1 = getelementptr double * %x, i32 1 + %addr2 = getelementptr double * %x, i32 2 + %addr3 = getelementptr double * %x, i32 3 + %d0 = load double * %y + %d1 = load double * %x + %d2 = load double * %addr1 + %d3 = load double * %addr2 + %d4 = load double * %addr3 + ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we + ; don't form a "vldmia rX, {d1, d2, d3, d4}". + ; We are relying on the calling convention and that register allocation + ; properly coalesces registers. + call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4) + ret void +} diff --git a/test/CodeGen/ARM/thumb2-it-block.ll b/test/CodeGen/ARM/thumb2-it-block.ll index a25352c..47c5dcc 100644 --- a/test/CodeGen/ARM/thumb2-it-block.ll +++ b/test/CodeGen/ARM/thumb2-it-block.ll @@ -1,14 +1,15 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv8 | FileCheck %s ; PR11107 define i32 @test(i32 %a, i32 %b) { entry: ; CHECK: cmp ; CHECK-NEXT: it mi -; CHECK-NEXT: rsbmi +; CHECK-NEXT: rsb{{s?}}mi ; CHECK-NEXT: cmp ; CHECK-NEXT: it mi -; CHECK-NEXT: rsbmi +; CHECK-NEXT: rsb{{s?}}mi %cmp1 = icmp slt i32 %a, 0 %sub1 = sub nsw i32 0, %a %abs1 = select i1 %cmp1, i32 %sub1, i32 %a diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll index db88a03..6cb26e3 100644 --- a/test/CodeGen/ARM/trap.ll +++ b/test/CodeGen/ARM/trap.ll @@ -9,13 +9,13 @@ ; RUN: llc -mtriple=armv7 -mattr=+nacl-trap -filetype=obj %s -o - \ ; RUN: | llvm-objdump -disassemble -triple armv7 -mattr=+nacl-trap - \ ; RUN: | FileCheck %s -check-prefix=ENCODING-NACL -; RUN: llc -fast-isel -mtriple=armv7-unknown-nacl -filetype=obj %s -o - \ +; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7-unknown-nacl -filetype=obj %s -o - \ ; RUN: | llvm-objdump -disassemble -triple armv7-unknown-nacl - \ ; RUN: | FileCheck %s -check-prefix=ENCODING-NACL ; RUN: llc -mtriple=armv7 -filetype=obj %s -o - \ ; RUN: | llvm-objdump -disassemble -triple armv7 - \ ; RUN: | FileCheck %s -check-prefix=ENCODING-ALL -; RUN: llc -fast-isel -mtriple=armv7 -filetype=obj %s -o - \ +; RUN: llc -verify-machineinstrs -fast-isel -mtriple=armv7 -filetype=obj %s -o - \ ; RUN: | llvm-objdump -disassemble -triple armv7 - \ ; RUN: | FileCheck %s -check-prefix=ENCODING-ALL ; rdar://7961298 diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll index a1ad37b..fcb5408 100644 --- a/test/CodeGen/ARM/vadd.ll +++ b/test/CodeGen/ARM/vadd.ll @@ -90,37 +90,6 @@ define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ret <4 x float> %tmp3 } -define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK-LABEL: vaddhni16: -;CHECK: vaddhn.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = call <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i8> %tmp3 -} - -define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK-LABEL: vaddhni32: -;CHECK: vaddhn.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B - %tmp3 = call <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i16> %tmp3 -} - -define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK-LABEL: vaddhni64: -;CHECK: vaddhn.i64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B - %tmp3 = call <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) - ret <2 x i32> %tmp3 -} - -declare <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone - define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vraddhni16: ;CHECK: vraddhn.i16 @@ -152,6 +121,33 @@ declare <8 x i8> @llvm.arm.neon.vraddhn.v8i8(<8 x i16>, <8 x i16>) nounwind rea declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone +define <8 x i8> @vaddhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK-LABEL: vaddhni16_natural: +; CHECK: vaddhn.i16 + %sum = add <8 x i16> %A, %B + %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %trunc = trunc <8 x i16> %shift to <8 x i8> + ret <8 x i8> %trunc +} + +define <4 x i16> @vaddhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK-LABEL: vaddhni32_natural: +; CHECK: vaddhn.i32 + %sum = add <4 x i32> %A, %B + %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16> + %trunc = trunc <4 x i32> %shift to <4 x i16> + ret <4 x i16> %trunc +} + +define <2 x i32> @vaddhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK-LABEL: vaddhni64_natural: +; CHECK: vaddhn.i64 + %sum = add <2 x i64> %A, %B + %shift = lshr <2 x i64> %sum, <i64 32, i64 32> + %trunc = trunc <2 x i64> %shift to <2 x i32> + ret <2 x i32> %trunc +} + define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vaddls8: ;CHECK: vaddl.s8 diff --git a/test/CodeGen/ARM/vector-DAGCombine.ll b/test/CodeGen/ARM/vector-DAGCombine.ll index 4221c98..759da22 100644 --- a/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/test/CodeGen/ARM/vector-DAGCombine.ll @@ -29,7 +29,7 @@ entry: ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is ; converted back to be used as a vector type. -; CHECK: test_vmovrrd_combine +; CHECK-LABEL: test_vmovrrd_combine: define <4 x i32> @test_vmovrrd_combine() nounwind { entry: br i1 undef, label %bb1, label %bb2 @@ -136,7 +136,7 @@ define i16 @foldBuildVectors() { ; Test that we are generating vrev and vext for reverse shuffles of v8i16 ; shuffles. -; CHECK: reverse_v8i16 +; CHECK-LABEL: reverse_v8i16: define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) { %v0 = load <8 x i16>* %loadaddr ; CHECK: vrev64.16 @@ -149,7 +149,7 @@ define void @reverse_v8i16(<8 x i16>* %loadaddr, <8 x i16>* %storeaddr) { ; Test that we are generating vrev and vext for reverse shuffles of v16i8 ; shuffles. -; CHECK: reverse_v16i8 +; CHECK-LABEL: reverse_v16i8: define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) { %v0 = load <16 x i8>* %loadaddr ; CHECK: vrev64.8 @@ -165,7 +165,7 @@ define void @reverse_v16i8(<16 x i8>* %loadaddr, <16 x i8>* %storeaddr) { ; vldr cannot handle unaligned loads. ; Fall back to vld1.32, which can, instead of using the general purpose loads ; followed by a costly sequence of instructions to build the vector register. -; CHECK: t3 +; CHECK-LABEL: t3: ; CHECK: vld1.32 {[[REG:d[0-9]+]][0]} ; CHECK: vld1.32 {[[REG]][1]} ; CHECK: vmull.u8 q{{[0-9]+}}, [[REG]], [[REG]] @@ -188,7 +188,7 @@ declare <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8>, <8 x i8>) ; Check that (insert_vector_elt (load)) => (vector_load). ; Thus, check that scalar_to_vector do not interfer with that. define <8 x i16> @t4(i8* nocapture %sp0) { -; CHECK: t4 +; CHECK-LABEL: t4: ; CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r0] entry: %pix_sp0.0.cast = bitcast i8* %sp0 to i32* @@ -202,7 +202,7 @@ entry: ; Make sure vector load is used for all three loads. ; Lowering to build vector was breaking the single use property of the load of ; %pix_sp0.0.copyload. -; CHECK: t5 +; CHECK-LABEL: t5: ; CHECK: vld1.32 {[[REG1:d[0-9]+]][1]}, [r0] ; CHECK: vorr [[REG2:d[0-9]+]], [[REG1]], [[REG1]] ; CHECK: vld1.32 {[[REG1]][0]}, [r1] @@ -224,3 +224,23 @@ entry: %vmull.i = tail call <8 x i16> @llvm.arm.neon.vmullu.v8i16(<8 x i8> %0, <8 x i8> %1) ret <8 x i16> %vmull.i } + +; <rdar://problem/14989896> Make sure we manage to truncate a vector from an +; illegal type to a legal type. +define <2 x i8> @test_truncate(<2 x i128> %in) { +; CHECK-LABEL: test_truncate: +; CHECK: mov [[BASE:r[0-9]+]], sp +; CHECK-NEXT: vld1.32 {[[REG1:d[0-9]+]][0]}, {{\[}}[[BASE]]:32] +; CHECK-NEXT: add [[BASE2:r[0-9]+]], [[BASE]], #4 +; CHECK-NEXT: vld1.32 {[[REG1]][1]}, {{\[}}[[BASE2]]:32] +; REG2 Should map on the same Q register as REG1, i.e., REG2 = REG1 - 1, but we +; cannot express that. +; CHECK-NEXT: vmov.32 [[REG2:d[0-9]+]][0], r0 +; CHECK-NEXT: vmov.32 [[REG2]][1], r1 +; The Q register used here should match floor(REG1/2), but we cannot express that. +; CHECK-NEXT: vmovn.i64 [[RES:d[0-9]+]], q{{[0-9]+}} +; CHECK-NEXT: vmov r0, r1, [[RES]] +entry: + %res = trunc <2 x i128> %in to <2 x i8> + ret <2 x i8> %res +} diff --git a/test/CodeGen/ARM/vldm-liveness.ll b/test/CodeGen/ARM/vldm-liveness.ll new file mode 100644 index 0000000..751f447 --- /dev/null +++ b/test/CodeGen/ARM/vldm-liveness.ll @@ -0,0 +1,40 @@ +; RUN: llc -mtriple thumbv7-apple-ios -verify-machineinstrs -o - %s | FileCheck %s + +; ARM load store optimizer was dealing with a sequence like: +; s1 = VLDRS [r0, 1], Q0<imp-def> +; s3 = VLDRS [r0, 2], Q0<imp-use,kill>, Q0<imp-def> +; s0 = VLDRS [r0, 0], Q0<imp-use,kill>, Q0<imp-def> +; s2 = VLDRS [r0, 4], Q0<imp-use,kill>, Q0<imp-def> +; +; It decided to combine the {s0, s1} loads into a single instruction in the +; third position. However, this leaves the instruction defining s3 with a stray +; imp-use of Q0, which is undefined. +; +; The verifier catches this, so this test just makes sure that appropriate +; liveness flags are added. +; +; I believe the change will be tested as long as the vldmia is not the first of +; the loads. Earlier optimisations may perturb the output over time, but +; fiddling the indices should be sufficient to restore the test. + +define arm_aapcs_vfpcc <4 x float> @foo(float* %ptr) { +; CHECK-LABEL: foo: +; CHECK: vldr s3, [r0, #8] +; CHECK: vldmia r0, {s0, s1} +; CHECK: vldr s2, [r0, #16] + %off0 = getelementptr float* %ptr, i32 0 + %val0 = load float* %off0 + %off1 = getelementptr float* %ptr, i32 1 + %val1 = load float* %off1 + %off4 = getelementptr float* %ptr, i32 4 + %val4 = load float* %off4 + %off2 = getelementptr float* %ptr, i32 2 + %val2 = load float* %off2 + + %vec1 = insertelement <4 x float> undef, float %val0, i32 0 + %vec2 = insertelement <4 x float> %vec1, float %val1, i32 1 + %vec3 = insertelement <4 x float> %vec2, float %val4, i32 2 + %vec4 = insertelement <4 x float> %vec3, float %val2, i32 3 + + ret <4 x float> %vec4 +} diff --git a/test/CodeGen/ARM/vldm-sched-a9.ll b/test/CodeGen/ARM/vldm-sched-a9.ll new file mode 100644 index 0000000..d0a9ac6 --- /dev/null +++ b/test/CodeGen/ARM/vldm-sched-a9.ll @@ -0,0 +1,71 @@ +; RUN: llc < %s -march=arm -mtriple=armv7-linux-gnueabihf -float-abi=hard -mcpu=cortex-a9 -O3 | FileCheck %s + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-n32-S64" + +; This test will generate spills/fills using vldmia instructions that access 64 bytes of memory. +; Check that we don't crash when we generate these instructions on Cortex-A9. + +; CHECK: test: +; CHECK: vstmia +; CHECK: vldmia +define void @test(i64* %src) #0 { +entry: + %arrayidx39 = getelementptr inbounds i64* %src, i32 13 + %vecinit285 = shufflevector <16 x i64> undef, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17> + store <16 x i64> %vecinit285, <16 x i64>* undef, align 128 + %0 = load i64* undef, align 8 + %vecinit379 = insertelement <16 x i64> undef, i64 %0, i32 9 + %1 = load i64* undef, align 8 + %vecinit419 = insertelement <16 x i64> undef, i64 %1, i32 15 + store <16 x i64> %vecinit419, <16 x i64>* undef, align 128 + %vecinit579 = insertelement <16 x i64> undef, i64 0, i32 4 + %vecinit582 = shufflevector <16 x i64> %vecinit579, <16 x i64> <i64 6, i64 7, i64 8, i64 9, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit584 = insertelement <16 x i64> %vecinit582, i64 undef, i32 9 + %vecinit586 = insertelement <16 x i64> %vecinit584, i64 0, i32 10 + %vecinit589 = shufflevector <16 x i64> %vecinit586, <16 x i64> <i64 12, i64 13, i64 14, i64 15, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 16, i32 17, i32 18, i32 19, i32 undef> + %2 = load i64* undef, align 8 + %vecinit591 = insertelement <16 x i64> %vecinit589, i64 %2, i32 15 + store <16 x i64> %vecinit591, <16 x i64>* undef, align 128 + %vecinit694 = shufflevector <16 x i64> undef, <16 x i64> <i64 13, i64 14, i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19> + store <16 x i64> %vecinit694, <16 x i64>* undef, align 128 + %3 = load i64* undef, align 8 + %vecinit1331 = insertelement <16 x i64> undef, i64 %3, i32 14 + %4 = load i64* undef, align 8 + %vecinit1468 = insertelement <16 x i64> undef, i64 %4, i32 11 + %vecinit1471 = shufflevector <16 x i64> %vecinit1468, <16 x i64> <i64 13, i64 14, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 undef, i32 undef> + %vecinit1474 = shufflevector <16 x i64> %vecinit1471, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17> + store <16 x i64> %vecinit1474, <16 x i64>* undef, align 128 + %vecinit1552 = shufflevector <16 x i64> undef, <16 x i64> <i64 10, i64 11, i64 12, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit1555 = shufflevector <16 x i64> %vecinit1552, <16 x i64> <i64 13, i64 14, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 undef, i32 undef> + %vecinit1558 = shufflevector <16 x i64> %vecinit1555, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17> + store <16 x i64> %vecinit1558, <16 x i64>* undef, align 128 + %vecinit1591 = shufflevector <16 x i64> undef, <16 x i64> <i64 3, i64 4, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit1594 = shufflevector <16 x i64> %vecinit1591, <16 x i64> <i64 5, i64 6, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit1597 = shufflevector <16 x i64> %vecinit1594, <16 x i64> <i64 7, i64 8, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit1599 = insertelement <16 x i64> %vecinit1597, i64 undef, i32 8 + %vecinit1601 = insertelement <16 x i64> %vecinit1599, i64 undef, i32 9 + %vecinit1603 = insertelement <16 x i64> %vecinit1601, i64 undef, i32 10 + %5 = load i64* undef, align 8 + %vecinit1605 = insertelement <16 x i64> %vecinit1603, i64 %5, i32 11 + %vecinit1608 = shufflevector <16 x i64> %vecinit1605, <16 x i64> <i64 13, i64 14, i64 15, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 undef> + %6 = load i64* undef, align 8 + %vecinit1610 = insertelement <16 x i64> %vecinit1608, i64 %6, i32 15 + store <16 x i64> %vecinit1610, <16 x i64>* undef, align 128 + %vecinit2226 = shufflevector <16 x i64> undef, <16 x i64> <i64 6, i64 7, i64 8, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %7 = load i64* undef, align 8 + %vecinit2228 = insertelement <16 x i64> %vecinit2226, i64 %7, i32 8 + %vecinit2230 = insertelement <16 x i64> %vecinit2228, i64 undef, i32 9 + %vecinit2233 = shufflevector <16 x i64> %vecinit2230, <16 x i64> <i64 11, i64 12, i64 13, i64 14, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 16, i32 17, i32 18, i32 19, i32 undef, i32 undef> + %vecinit2236 = shufflevector <16 x i64> %vecinit2233, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17> + store <16 x i64> %vecinit2236, <16 x i64>* undef, align 128 + %vecinit2246 = shufflevector <16 x i64> undef, <16 x i64> <i64 4, i64 5, i64 6, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit2249 = shufflevector <16 x i64> %vecinit2246, <16 x i64> <i64 7, i64 8, i64 9, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit2252 = shufflevector <16 x i64> %vecinit2249, <16 x i64> <i64 10, i64 11, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 16, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef> + %vecinit2255 = shufflevector <16 x i64> %vecinit2252, <16 x i64> <i64 12, i64 13, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 16, i32 17, i32 undef, i32 undef, i32 undef> + %8 = load i64* %arrayidx39, align 8 + %vecinit2257 = insertelement <16 x i64> %vecinit2255, i64 %8, i32 13 + %vecinit2260 = shufflevector <16 x i64> %vecinit2257, <16 x i64> <i64 15, i64 16, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 16, i32 17> + store <16 x i64> %vecinit2260, <16 x i64>* null, align 128 + ret void +} +attributes #0 = { noredzone "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/test/CodeGen/ARM/vminmaxnm.ll b/test/CodeGen/ARM/vminmaxnm.ll index afa73b9..f6ce64c 100644 --- a/test/CodeGen/ARM/vminmaxnm.ll +++ b/test/CodeGen/ARM/vminmaxnm.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple armv8 -mattr=+neon | FileCheck %s +; RUN: llc < %s -mtriple armv8 -mattr=+neon,+fp-armv8 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST define <4 x float> @vmaxnmq(<4 x float>* %A, <4 x float>* %B) nounwind { ; CHECK: vmaxnmq @@ -36,6 +37,51 @@ define <2 x float> @vminnmd(<2 x float>* %A, <2 x float>* %B) nounwind { ret <2 x float> %tmp3 } +define float @fp-armv8_vminnm_o(float %a, float %b) { +; CHECK-FAST: fp-armv8_vminnm_o +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f32 +; CHECK: fp-armv8_vminnm_o +; CHECK-NOT: vminnm.f32 + %cmp = fcmp olt float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vminnm_u(float %a, float %b) { +; CHECK-FAST: fp-armv8_vminnm_u +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vminnm.f32 +; CHECK: fp-armv8_vminnm_u +; CHECK-NOT: vminnm.f32 + %cmp = fcmp ult float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vmaxnm_o(float %a, float %b) { +; CHECK-FAST: fp-armv8_vmaxnm_o +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vmaxnm.f32 +; CHECK: fp-armv8_vmaxnm_o +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp ogt float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + +define float @fp-armv8_vmaxnm_u(float %a, float %b) { +; CHECK-FAST: fp-armv8_vmaxnm_u +; CHECK-FAST-NOT: vcmp +; CHECK-FAST: vmaxnm.f32 +; CHECK: fp-armv8_vmaxnm_u +; CHECK-NOT: vmaxnm.f32 + %cmp = fcmp ugt float %a, %b + %cond = select i1 %cmp, float %a, float %b + ret float %cond +} + + declare <4 x float> @llvm.arm.neon.vminnm.v4f32(<4 x float>, <4 x float>) nounwind readnone declare <2 x float> @llvm.arm.neon.vminnm.v2f32(<2 x float>, <2 x float>) nounwind readnone declare <4 x float> @llvm.arm.neon.vmaxnm.v4f32(<4 x float>, <4 x float>) nounwind readnone diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index 6210ad3..de329ac 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -515,6 +515,17 @@ entry: ret void } +define <8 x i8> @no_distribute(<8 x i8> %a, <8 x i8> %b) nounwind { +entry: +; CHECK: no_distribute +; CHECK: vadd.i8 +; CHECK: vmul.i8 +; CHECK-NOT: vmla.i8 + %0 = add <8 x i8> %a, %b + %1 = mul <8x i8> %0, %0 + ret <8 x i8> %1 +} + ; If one operand has a zero-extend and the other a sign-extend, vmull ; cannot be used. define i16 @vmullWithInconsistentExtensions(<8 x i8> %vec) { @@ -623,3 +634,21 @@ entry: store <4 x i32> %predphi290.v.i, <4 x i32>* undef, align 4 ret void } + +define void @foo(<4 x float> * %a, <4 x float>* nocapture %dst, float* nocapture readonly %src) nounwind { +; Look for doing a normal scalar FP load rather than an to-all-lanes load. +; e.g., "ldr s0, [r2]" rathern than "vld1.32 {d18[], d19[]}, [r2:32]" +; Then check that the vector multiply has folded the splat to all lanes +; and used a vector * scalar instruction. +; CHECK: vldr {{s[0-9]+}}, [r2] +; CHECK: vmul.f32 q8, q8, d0[0] + %tmp = load float* %src, align 4 + %tmp5 = load <4 x float>* %a, align 4 + %tmp6 = insertelement <4 x float> undef, float %tmp, i32 0 + %tmp7 = insertelement <4 x float> %tmp6, float %tmp, i32 1 + %tmp8 = insertelement <4 x float> %tmp7, float %tmp, i32 2 + %tmp9 = insertelement <4 x float> %tmp8, float %tmp, i32 3 + %tmp10 = fmul <4 x float> %tmp9, %tmp5 + store <4 x float> %tmp10, <4 x float>* %dst, align 4 + ret void +} diff --git a/test/CodeGen/ARM/vqdmul.ll b/test/CodeGen/ARM/vqdmul.ll index a28cae9..d298167 100644 --- a/test/CodeGen/ARM/vqdmul.ll +++ b/test/CodeGen/ARM/vqdmul.ll @@ -197,84 +197,92 @@ entry: declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone -define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK-LABEL: vqdmlals16: +define <4 x i32> @vqdmlals16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { +;CHECK-LABEL: vqdmlals16_natural: ;CHECK: vqdmlal.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i32> %tmp4 + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3) + %tmp5 = call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4) + ret <4 x i32> %tmp5 } -define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK-LABEL: vqdmlals32: +define <2 x i64> @vqdmlals32_natural(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { +;CHECK-LABEL: vqdmlals32_natural: ;CHECK: vqdmlal.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i64> %tmp4 + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3) + %tmp5 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4) + ret <2 x i64> %tmp5 } -define arm_aapcs_vfpcc <4 x i32> @test_vqdmlal_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone { +define arm_aapcs_vfpcc <4 x i32> @test_vqdmlal_lanes16_natural(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone { entry: -; CHECK: test_vqdmlal_lanes16 +; CHECK-LABEL: test_vqdmlal_lanes16_natural: ; CHECK: vqdmlal.s16 q0, d2, d3[1] %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] - %1 = tail call <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] - ret <4 x i32> %1 + %1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg1_int16x4_t, <4 x i16> %0) + %2 = tail call <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %1) + ret <4 x i32> %2 } -define arm_aapcs_vfpcc <2 x i64> @test_vqdmlal_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone { +define arm_aapcs_vfpcc <2 x i64> @test_vqdmlal_lanes32_natural(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone { entry: -; CHECK: test_vqdmlal_lanes32 +; CHECK-LABEL: test_vqdmlal_lanes32_natural: ; CHECK: vqdmlal.s32 q0, d2, d3[1] %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] - %1 = tail call <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %1 + %1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg1_int32x2_t, <2 x i32> %0) + %2 = call <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i64> %1) + ret <2 x i64> %2 } -declare <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqadds.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqadds.v2i64(<2 x i64>, <2 x i64>) nounwind readnone -define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK-LABEL: vqdmlsls16: +define <4 x i32> @vqdmlsls16_natural(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { +;CHECK-LABEL: vqdmlsls16_natural: ;CHECK: vqdmlsl.s16 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i16>* %B - %tmp3 = load <4 x i16>* %C - %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %tmp3) - ret <4 x i32> %tmp4 + %tmp1 = load <4 x i32>* %A + %tmp2 = load <4 x i16>* %B + %tmp3 = load <4 x i16>* %C + %tmp4 = call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %tmp2, <4 x i16> %tmp3) + %tmp5 = call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp4) + ret <4 x i32> %tmp5 } -define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK-LABEL: vqdmlsls32: +define <2 x i64> @vqdmlsls32_natural(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { +;CHECK-LABEL: vqdmlsls32_natural: ;CHECK: vqdmlsl.s32 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i32>* %B - %tmp3 = load <2 x i32>* %C - %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %tmp3) - ret <2 x i64> %tmp4 + %tmp1 = load <2 x i64>* %A + %tmp2 = load <2 x i32>* %B + %tmp3 = load <2 x i32>* %C + %tmp4 = call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %tmp2, <2 x i32> %tmp3) + %tmp5 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp4) + ret <2 x i64> %tmp5 } -define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsl_lanes16(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone { +define arm_aapcs_vfpcc <4 x i32> @test_vqdmlsl_lanes16_natural(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %arg2_int16x4_t) nounwind readnone { entry: -; CHECK: test_vqdmlsl_lanes16 +; CHECK-LABEL: test_vqdmlsl_lanes16_natural: ; CHECK: vqdmlsl.s16 q0, d2, d3[1] %0 = shufflevector <4 x i16> %arg2_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses=1] - %1 = tail call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_int16x4_t, <4 x i16> %0) ; <<4 x i32>> [#uses=1] - ret <4 x i32> %1 + %1 = tail call <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16> %arg1_int16x4_t, <4 x i16> %0) + %2 = tail call <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i32> %1) + ret <4 x i32> %2 } -define arm_aapcs_vfpcc <2 x i64> @test_vqdmlsl_lanes32(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone { +define arm_aapcs_vfpcc <2 x i64> @test_vqdmlsl_lanes32_natural(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %arg2_int32x2_t) nounwind readnone { entry: -; CHECK: test_vqdmlsl_lanes32 +; CHECK-LABEL: test_vqdmlsl_lanes32_natural: ; CHECK: vqdmlsl.s32 q0, d2, d3[1] %0 = shufflevector <2 x i32> %arg2_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] - %1 = tail call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_int32x2_t, <2 x i32> %0) ; <<2 x i64>> [#uses=1] - ret <2 x i64> %1 + %1 = tail call <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32> %arg1_int32x2_t, <2 x i32> %0) + %2 = call <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i64> %1) + ret <2 x i64> %2 } -declare <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone -declare <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone +declare <4 x i32> @llvm.arm.neon.vqsubs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.arm.neon.vqsubs.v2i64(<2 x i64>, <2 x i64>) nounwind readnone diff --git a/test/CodeGen/ARM/vsel.ll b/test/CodeGen/ARM/vsel.ll new file mode 100644 index 0000000..7e1f714 --- /dev/null +++ b/test/CodeGen/ARM/vsel.ll @@ -0,0 +1,309 @@ +; RUN: llc < %s -mtriple=armv8-linux-gnueabihf -mattr=+fp-armv8 -float-abi=hard | FileCheck %s +@varfloat = global float 0.0 +@vardouble = global double 0.0 +define void @test_vsel32sgt(i32 %lhs32, i32 %rhs32, float %a, float %b) { +; CHECK: test_vsel32sgt + %tst1 = icmp sgt i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: cmp r0, r1 +; CHECK: vselgt.f32 s0, s0, s1 + ret void +} +define void @test_vsel64sgt(i32 %lhs32, i32 %rhs32, double %a, double %b) { +; CHECK: test_vsel64sgt + %tst1 = icmp sgt i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: cmp r0, r1 +; CHECK: vselgt.f64 d16, d0, d1 + ret void +} +define void @test_vsel32sge(i32 %lhs32, i32 %rhs32, float %a, float %b) { +; CHECK: test_vsel32sge + %tst1 = icmp sge i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: cmp r0, r1 +; CHECK: vselge.f32 s0, s0, s1 + ret void +} +define void @test_vsel64sge(i32 %lhs32, i32 %rhs32, double %a, double %b) { +; CHECK: test_vsel64sge + %tst1 = icmp sge i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: cmp r0, r1 +; CHECK: vselge.f64 d16, d0, d1 + ret void +} +define void @test_vsel32eq(i32 %lhs32, i32 %rhs32, float %a, float %b) { +; CHECK: test_vsel32eq + %tst1 = icmp eq i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: cmp r0, r1 +; CHECK: vseleq.f32 s0, s0, s1 + ret void +} +define void @test_vsel64eq(i32 %lhs32, i32 %rhs32, double %a, double %b) { +; CHECK: test_vsel64eq + %tst1 = icmp eq i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: cmp r0, r1 +; CHECK: vseleq.f64 d16, d0, d1 + ret void +} +define void @test_vsel32slt(i32 %lhs32, i32 %rhs32, float %a, float %b) { +; CHECK: test_vsel32slt + %tst1 = icmp slt i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: cmp r0, r1 +; CHECK: vselgt.f32 s0, s1, s0 + ret void +} +define void @test_vsel64slt(i32 %lhs32, i32 %rhs32, double %a, double %b) { +; CHECK: test_vsel64slt + %tst1 = icmp slt i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: cmp r0, r1 +; CHECK: vselgt.f64 d16, d1, d0 + ret void +} +define void @test_vsel32sle(i32 %lhs32, i32 %rhs32, float %a, float %b) { +; CHECK: test_vsel32sle + %tst1 = icmp sle i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: cmp r0, r1 +; CHECK: vselge.f32 s0, s1, s0 + ret void +} +define void @test_vsel64sle(i32 %lhs32, i32 %rhs32, double %a, double %b) { +; CHECK: test_vsel64sle + %tst1 = icmp sle i32 %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: cmp r0, r1 +; CHECK: vselge.f64 d16, d1, d0 + ret void +} +define void @test_vsel32ogt(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32ogt + %tst1 = fcmp ogt float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselgt.f32 s0, s2, s3 + ret void +} +define void @test_vsel64ogt(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64ogt + %tst1 = fcmp ogt float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselgt.f64 d16, d1, d2 + ret void +} +define void @test_vsel32oge(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32oge + %tst1 = fcmp oge float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselge.f32 s0, s2, s3 + ret void +} +define void @test_vsel64oge(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64oge + %tst1 = fcmp oge float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselge.f64 d16, d1, d2 + ret void +} +define void @test_vsel32oeq(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32oeq + %tst1 = fcmp oeq float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vseleq.f32 s0, s2, s3 + ret void +} +define void @test_vsel64oeq(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64oeq + %tst1 = fcmp oeq float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vseleq.f64 d16, d1, d2 + ret void +} +define void @test_vsel32ugt(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32ugt + %tst1 = fcmp ugt float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s1, s0 +; CHECK: vselge.f32 s0, s3, s2 + ret void +} +define void @test_vsel64ugt(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64ugt + %tst1 = fcmp ugt float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s1, s0 +; CHECK: vselge.f64 d16, d2, d1 + ret void +} +define void @test_vsel32uge(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32uge + %tst1 = fcmp uge float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s1, s0 +; CHECK: vselgt.f32 s0, s3, s2 + ret void +} +define void @test_vsel64uge(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64uge + %tst1 = fcmp uge float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s1, s0 +; CHECK: vselgt.f64 d16, d2, d1 + ret void +} +define void @test_vsel32olt(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32olt + %tst1 = fcmp olt float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s1, s0 +; CHECK: vselgt.f32 s0, s2, s3 + ret void +} +define void @test_vsel64olt(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64olt + %tst1 = fcmp olt float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s1, s0 +; CHECK: vselgt.f64 d16, d1, d2 + ret void +} +define void @test_vsel32ult(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32ult + %tst1 = fcmp ult float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselge.f32 s0, s3, s2 + ret void +} +define void @test_vsel64ult(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64ult + %tst1 = fcmp ult float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselge.f64 d16, d2, d1 + ret void +} +define void @test_vsel32ole(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32ole + %tst1 = fcmp ole float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s1, s0 +; CHECK: vselge.f32 s0, s2, s3 + ret void +} +define void @test_vsel64ole(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64ole + %tst1 = fcmp ole float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s1, s0 +; CHECK: vselge.f64 d16, d1, d2 + ret void +} +define void @test_vsel32ule(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32ule + %tst1 = fcmp ule float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselgt.f32 s0, s3, s2 + ret void +} +define void @test_vsel64ule(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64ule + %tst1 = fcmp ule float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselgt.f64 d16, d2, d1 + ret void +} +define void @test_vsel32ord(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32ord + %tst1 = fcmp ord float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselvs.f32 s0, s3, s2 + ret void +} +define void @test_vsel64ord(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64ord + %tst1 = fcmp ord float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselvs.f64 d16, d2, d1 + ret void +} +define void @test_vsel32une(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32une + %tst1 = fcmp une float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vseleq.f32 s0, s3, s2 + ret void +} +define void @test_vsel64une(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64une + %tst1 = fcmp une float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vseleq.f64 d16, d2, d1 + ret void +} +define void @test_vsel32uno(float %lhs32, float %rhs32, float %a, float %b) { +; CHECK: test_vsel32uno + %tst1 = fcmp uno float %lhs32, %rhs32 + %val1 = select i1 %tst1, float %a, float %b + store float %val1, float* @varfloat +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselvs.f32 s0, s2, s3 + ret void +} +define void @test_vsel64uno(float %lhs32, float %rhs32, double %a, double %b) { +; CHECK: test_vsel64uno + %tst1 = fcmp uno float %lhs32, %rhs32 + %val1 = select i1 %tst1, double %a, double %b + store double %val1, double* @vardouble +; CHECK: vcmpe.f32 s0, s1 +; CHECK: vselvs.f64 d16, d1, d2 + ret void +} diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 651b6d5..34c5c70 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -13,7 +13,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store. define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK-LABEL: vst1lanei8_update: -;CHECK: vst1.8 {d16[3]}, [r2]! +;CHECK: vst1.8 {d16[3]}, [{{r[0-9]}}]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B %tmp2 = extractelement <8 x i8> %tmp1, i32 3 diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll index 89c3095..6b95b97 100644 --- a/test/CodeGen/ARM/vsub.ll +++ b/test/CodeGen/ARM/vsub.ll @@ -90,37 +90,33 @@ define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ret <4 x float> %tmp3 } -define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK-LABEL: vsubhni16: -;CHECK: vsubhn.i16 - %tmp1 = load <8 x i16>* %A - %tmp2 = load <8 x i16>* %B - %tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2) - ret <8 x i8> %tmp3 +define <8 x i8> @vsubhni16_natural(<8 x i16> %A, <8 x i16> %B) nounwind { +; CHECK-LABEL: vsubhni16_natural: +; CHECK: vsubhn.i16 + %sum = sub <8 x i16> %A, %B + %shift = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8> + %trunc = trunc <8 x i16> %shift to <8 x i8> + ret <8 x i8> %trunc } -define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK-LABEL: vsubhni32: -;CHECK: vsubhn.i32 - %tmp1 = load <4 x i32>* %A - %tmp2 = load <4 x i32>* %B - %tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2) - ret <4 x i16> %tmp3 +define <4 x i16> @vsubhni32_natural(<4 x i32> %A, <4 x i32> %B) nounwind { +; CHECK-LABEL: vsubhni32_natural: +; CHECK: vsubhn.i32 + %sum = sub <4 x i32> %A, %B + %shift = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16> + %trunc = trunc <4 x i32> %shift to <4 x i16> + ret <4 x i16> %trunc } -define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK-LABEL: vsubhni64: -;CHECK: vsubhn.i64 - %tmp1 = load <2 x i64>* %A - %tmp2 = load <2 x i64>* %B - %tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2) - ret <2 x i32> %tmp3 +define <2 x i32> @vsubhni64_natural(<2 x i64> %A, <2 x i64> %B) nounwind { +; CHECK-LABEL: vsubhni64_natural: +; CHECK: vsubhn.i64 + %sum = sub <2 x i64> %A, %B + %shift = lshr <2 x i64> %sum, <i64 32, i64 32> + %trunc = trunc <2 x i64> %shift to <2 x i32> + ret <2 x i32> %trunc } -declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone -declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone -declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone - define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { ;CHECK-LABEL: vrsubhni16: ;CHECK: vrsubhn.i16 |