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-rw-r--r--test/CodeGen/Mips/Fast-ISel/br1.ll34
-rw-r--r--test/CodeGen/Mips/Fast-ISel/callabi.ll477
-rw-r--r--test/CodeGen/Mips/Fast-ISel/fpcmpa.ll254
-rw-r--r--test/CodeGen/Mips/Fast-ISel/fpext.ll21
-rw-r--r--test/CodeGen/Mips/Fast-ISel/fpintconv.ll35
-rw-r--r--test/CodeGen/Mips/Fast-ISel/fptrunc.ll20
-rw-r--r--test/CodeGen/Mips/Fast-ISel/icmpa.ll210
-rw-r--r--test/CodeGen/Mips/Fast-ISel/loadstore2.ll2
-rw-r--r--test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll179
-rw-r--r--test/CodeGen/Mips/Fast-ISel/loadstrconst.ll21
-rw-r--r--test/CodeGen/Mips/Fast-ISel/nullvoid.ll2
-rw-r--r--test/CodeGen/Mips/Fast-ISel/shift.ll24
-rw-r--r--test/CodeGen/Mips/Fast-ISel/simplestore.ll2
-rw-r--r--test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll34
-rw-r--r--test/CodeGen/Mips/Fast-ISel/simplestorei.ll2
15 files changed, 1308 insertions, 9 deletions
diff --git a/test/CodeGen/Mips/Fast-ISel/br1.ll b/test/CodeGen/Mips/Fast-ISel/br1.ll
new file mode 100644
index 0000000..579a77f
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/br1.ll
@@ -0,0 +1,34 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+
+@b = global i32 1, align 4
+@i = global i32 0, align 4
+@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
+
+; Function Attrs: nounwind
+define void @br() #0 {
+entry:
+ %0 = load i32* @b, align 4
+ %tobool = icmp eq i32 %0, 0
+ br i1 %tobool, label %if.end, label %if.then
+
+if.then: ; preds = %entry
+ store i32 6754, i32* @i, align 4
+ br label %if.end
+
+if.end: ; preds = %entry, %if.then
+ ret void
+; FIXME: This instruction is redundant.
+; CHECK: xor $[[REG1:[0-9]+]], ${{[0-9]+}}, $zero
+; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
+; CHECK: bgtz $[[REG2]], $BB[[BL:[0-9]+_[0-9]+]]
+; CHECK: nop
+; CHECK: addiu ${{[0-9]+}}, $zero, 6754
+; CHECK: sw ${{[0-9]+}}, 0(${{[0-9]+}})
+; CHECK: $BB[[BL]]:
+
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
diff --git a/test/CodeGen/Mips/Fast-ISel/callabi.ll b/test/CodeGen/Mips/Fast-ISel/callabi.ll
new file mode 100644
index 0000000..44b94bb
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/callabi.ll
@@ -0,0 +1,477 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s -check-prefix=mips32r2
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s -check-prefix=mips32
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s -check-prefix=CHECK2
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s -check-prefix=CHECK2
+
+
+@c1 = global i8 -45, align 1
+@uc1 = global i8 27, align 1
+@s1 = global i16 -1789, align 2
+@us1 = global i16 1256, align 2
+
+; Function Attrs: nounwind
+define void @cxi() #0 {
+entry:
+; CHECK-LABEL: cxi
+ call void @xi(i32 10)
+; CHECK-DAG: addiu $4, $zero, 10
+; CHECK-DAG: lw $25, %got(xi)(${{[0-9]+}})
+; CHECK: jalr $25
+
+ ret void
+}
+
+declare void @xi(i32) #1
+
+; Function Attrs: nounwind
+define void @cxii() #0 {
+entry:
+; CHECK-LABEL: cxii
+ call void @xii(i32 746, i32 892)
+; CHECK-DAG: addiu $4, $zero, 746
+; CHECK-DAG: addiu $5, $zero, 892
+; CHECK-DAG: lw $25, %got(xii)(${{[0-9]+}})
+; CHECK: jalr $25
+
+ ret void
+}
+
+declare void @xii(i32, i32) #1
+
+; Function Attrs: nounwind
+define void @cxiii() #0 {
+entry:
+; CHECK-LABEL: cxiii
+ call void @xiii(i32 88, i32 44, i32 11)
+; CHECK-DAG: addiu $4, $zero, 88
+; CHECK-DAG: addiu $5, $zero, 44
+; CHECK-DAG: addiu $6, $zero, 11
+; CHECK-DAG: lw $25, %got(xiii)(${{[0-9]+}})
+; CHECK: jalr $25
+ ret void
+}
+
+declare void @xiii(i32, i32, i32) #1
+
+; Function Attrs: nounwind
+define void @cxiiii() #0 {
+entry:
+; CHECK-LABEL: cxiiii
+ call void @xiiii(i32 167, i32 320, i32 97, i32 14)
+; CHECK-DAG: addiu $4, $zero, 167
+; CHECK-DAG: addiu $5, $zero, 320
+; CHECK-DAG: addiu $6, $zero, 97
+; CHECK-DAG: addiu $7, $zero, 14
+; CHECK-DAG: lw $25, %got(xiiii)(${{[0-9]+}})
+; CHECK: jalr $25
+
+ ret void
+}
+
+declare void @xiiii(i32, i32, i32, i32) #1
+
+; Function Attrs: nounwind
+define void @cxiiiiconv() #0 {
+entry:
+; CHECK-LABEL: cxiiiiconv
+; mips32r2-LABEL: cxiiiiconv
+; mips32-LABEL: cxiiiiconv
+ %0 = load i8* @c1, align 1
+ %conv = sext i8 %0 to i32
+ %1 = load i8* @uc1, align 1
+ %conv1 = zext i8 %1 to i32
+ %2 = load i16* @s1, align 2
+ %conv2 = sext i16 %2 to i32
+ %3 = load i16* @us1, align 2
+ %conv3 = zext i16 %3 to i32
+ call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3)
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; mips32r2-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
+; mips32r2-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
+; mips32r2-DAG seb $3, $[[REG_C1]]
+; mips32-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
+; mips32-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
+; mips32-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
+; mips32-DAG: sra $4, $[[REG_C1_1]], 24
+; CHECK-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
+; CHECK-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
+; FIXME andi is superfulous
+; CHECK-DAG: andi $5, $[[REG_UC1]], 255
+; mips32r2-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
+; mips32r2-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
+; mips32r2-DAG: seh $6, $[[REG_S1]]
+; mips32-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
+; mips32-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
+; mips32-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
+; mips32-DAG: sra $6, $[[REG_S1_1]], 16
+; CHECK-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
+; CHECK-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])
+; FIXME andi is superfulous
+; CHECK-DAG: andi $7, $[[REG_US1]], 65535
+; mips32r2: jalr $25
+; mips32r2: jalr $25
+; CHECK: jalr $25
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @cxf() #0 {
+entry:
+; CHECK-LABEL: cxf
+ call void @xf(float 0x40BBC85560000000)
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK: lui $[[REG_FPCONST_1:[0-9]+]], 17886
+; CHECK: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067
+; CHECK: mtc1 $[[REG_FPCONST]], $f12
+; CHECK: lw $25, %got(xf)($[[REG_GP]])
+; CHECK: jalr $25
+ ret void
+}
+
+declare void @xf(float) #1
+
+; Function Attrs: nounwind
+define void @cxff() #0 {
+entry:
+; CHECK-LABEL: cxff
+ call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000)
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314
+; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349
+; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
+; CHECK-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593
+; CHECK-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642
+; CHECK-DAG: mtc1 $[[REG_FPCONST_3]], $f14
+; CHECK: lw $25, %got(xff)($[[REG_GP]])
+; CHECK: jalr $25
+ ret void
+}
+
+declare void @xff(float, float) #1
+
+; Function Attrs: nounwind
+define void @cxfi() #0 {
+entry:
+; CHECK-LABEL: cxfi
+ call void @xfi(float 0x4013906240000000, i32 102)
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540
+; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554
+; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
+; CHECK-DAG: addiu $5, $zero, 102
+; CHECK: lw $25, %got(xfi)($[[REG_GP]])
+; CHECK: jalr $25
+
+ ret void
+}
+
+declare void @xfi(float, i32) #1
+
+; Function Attrs: nounwind
+define void @cxfii() #0 {
+entry:
+; CHECK-LABEL: cxfii
+ call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922)
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142
+; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240
+; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
+; CHECK-DAG: addiu $5, $zero, 9993
+; CHECK-DAG: addiu $6, $zero, 10922
+; CHECK: lw $25, %got(xfii)($[[REG_GP]])
+; CHECK: jalr $25
+ ret void
+}
+
+declare void @xfii(float, i32, i32) #1
+
+; Function Attrs: nounwind
+define void @cxfiii() #0 {
+entry:
+; CHECK-LABEL: cxfiii
+ call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222)
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120
+; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681
+; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
+; CHECK-DAG: addiu $5, $zero, 3948
+; CHECK-DAG: lui $[[REG_I_1:[0-9]+]], 1
+; CHECK-DAG: ori $6, $[[REG_I_1]], 23475
+; CHECK-DAG: lui $[[REG_I_2:[0-9]+]], 1
+; CHECK-DAG: ori $7, $[[REG_I_2]], 45686
+; CHECK: lw $25, %got(xfiii)($[[REG_GP]])
+; CHECK: jalr $25
+ ret void
+}
+
+declare void @xfiii(float, i32, i32, i32) #1
+
+; Function Attrs: nounwind
+define void @cxd() #0 {
+entry:
+; mips32r2-LABEL: cxd:
+; mips32-LABEL: cxd:
+ call void @xd(double 5.994560e+02)
+; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514
+; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
+; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195
+; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
+; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12
+; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13
+; mips32-DAG: lw $25, %got(xd)($[[REG_GP]])
+; mips32: jalr $25
+; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514
+; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
+; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195
+; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
+; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12
+; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
+; mips32r2-DAG: lw $25, %got(xd)($[[REG_GP]])
+; mips32r2 : jalr $25
+ ret void
+}
+
+declare void @xd(double) #1
+
+; Function Attrs: nounwind
+define void @cxdd() #0 {
+; mips32r2-LABEL: cxdd:
+; mips32-LABEL: cxdd:
+entry:
+ call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917)
+; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531
+; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
+; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078
+; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
+; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12
+; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13
+; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629
+; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
+; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438
+; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
+; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f14
+; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f15
+; mips32-DAG: lw $25, %got(xdd)($[[REG_GP]])
+; mips32: jalr $25
+; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531
+; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
+; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078
+; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
+; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12
+; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
+; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629
+; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
+; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438
+; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
+; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f14
+; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f14
+; mips32r2-DAG: lw $25, %got(xdd)($[[REG_GP]])
+; mips32r2 : jalr $25
+ ret void
+}
+
+declare void @xdd(double, double) #1
+
+; Function Attrs: nounwind
+define void @cxif() #0 {
+entry:
+; CHECK-LABEL: cxif:
+ call void @xif(i32 345, float 0x407BCE5A20000000)
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: addiu $4, $zero, 345
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17374
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
+; CHECK-DAG: lw $25, %got(xif)($[[REG_GP]])
+; CHECK: jalr $25
+
+ ret void
+}
+
+declare void @xif(i32, float) #1
+
+; Function Attrs: nounwind
+define void @cxiff() #0 {
+entry:
+; CHECK-LABEL: cxiff:
+; CHECK2-LABEL: cxiff:
+ call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)
+; We need to do the two floating point parameters in a separate
+; check because we can't control the ordering of parts of the sequence
+;;
+; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK: addiu $4, $zero, 12239
+; CHECK2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK2: addiu $4, $zero, 12239
+; CHECK: lui $[[REGF_1:[0-9]+]], 17526
+; CHECK: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
+; CHECK: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+; CHECK: mfc1 $5, $f[[REGF_3]]
+; CHECK2: lui $[[REGF2_1:[0-9]+]], 16543
+; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 65326
+; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
+; CHECK2: mfc1 $6, $f[[REGF2_3]]
+; CHECK: lw $25, %got(xiff)($[[REG_GP]])
+; CHECK2: lw $25, %got(xiff)($[[REG_GP]])
+; CHECK: jalr $25
+; CHECK2: jalr $25
+ ret void
+}
+
+declare void @xiff(i32, float, float) #1
+
+; Function Attrs: nounwind
+define void @cxifi() #0 {
+entry:
+; CHECK: cxifi:
+ call void @xifi(i32 887, float 0x402277CEE0000000, i32 888)
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: addiu $4, $zero, 887
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16659
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
+; CHECk-DAG: addiu $6, $zero, 888
+; CHECK-DAG: lw $25, %got(xifi)($[[REG_GP]])
+; CHECK: jalr $25
+
+ ret void
+}
+
+declare void @xifi(i32, float, i32) #1
+
+; Function Attrs: nounwind
+define void @cxifif() #0 {
+entry:
+; CHECK: cxifif:
+; CHECK2: cxifif:
+ call void @xifif(i32 67774, float 0x408EE0FBE0000000, i32 9991, float 0x40B15C8CC0000000)
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: lui $[[REGI:[0-9]+]], 1
+; CHECK-DAG: ori $4, $[[REGI]], 2238
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17527
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 2015
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
+; CHECk-DAG: addiu $6, $zero, 888
+; CHECK2: lui $[[REGF2_1:[0-9]+]], 17802
+; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 58470
+; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
+; CHECK2: mfc1 $7, $f[[REGF2_3]]
+; CHECK: lw $25, %got(xifif)($[[REG_GP]])
+; CHECK2: lw $25, %got(xifif)($[[REG_GP]])
+; CHECK2: jalr $25
+; CHECK: jalr $25
+
+ ret void
+}
+
+declare void @xifif(i32, float, i32, float) #1
+
+; Function Attrs: nounwind
+define void @cxiffi() #0 {
+entry:
+; CHECK-label: cxiffi:
+; CHECK2-label: cxiffi:
+ call void @xiffi(i32 45, float 0x3FF6666660000000, float 0x408F333340000000, i32 234)
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: addiu $4, $zero, 45
+; CHECK2-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK2-DAG: addiu $4, $zero, 45
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16307
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 13107
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
+; CHECK2: lui $[[REGF2_1:[0-9]+]], 17529
+; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 39322
+; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
+; CHECK2: mfc1 $6, $f[[REGF2_3]]
+; CHECK-DAG: lw $25, %got(xiffi)($[[REG_GP]])
+; CHECK-DAG: addiu $7, $zero, 234
+; CHECK2-DAG: lw $25, %got(xiffi)($[[REG_GP]])
+; CHECK: jalr $25
+; CHECK2: jalr $25
+
+ ret void
+}
+
+declare void @xiffi(i32, float, float, i32) #1
+
+; Function Attrs: nounwind
+define void @cxifii() #0 {
+entry:
+; CHECK-DAG: cxifii:
+ call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234)
+; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
+; CHECK-DAG: addiu $4, $zero, 12239
+; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17526
+; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
+; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
+; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
+; CHECK-DAG: lui $[[REGI2:[0-9]+]], 15
+; CHECK-DAG: ori $6, $[[REGI2]], 15837
+; CHECk-DAG: addiu $7, $zero, 1234
+; CHECK-DAG: lw $25, %got(xifii)($[[REG_GP]])
+; CHECK: jalr $25
+ ret void
+}
+
+declare void @xifii(i32, float, i32, i32) #1
+
+; FIXME: this function will not pass yet.
+; Function Attrs: nounwind
+; define void @cxfid() #0 {
+;entry:
+; call void @xfid(float 0x4013B851E0000000, i32 811123, double 0x40934BFF487FCB92)
+; ret void
+;}
+
+declare void @xfid(float, i32, double) #1
+
+; Function Attrs: nounwind
+define void @g() #0 {
+entry:
+ call void @cxi()
+ call void @cxii()
+ call void @cxiii()
+ call void @cxiiii()
+ call void @cxiiiiconv()
+ call void @cxf()
+ call void @cxff()
+ call void @cxd()
+ call void @cxfi()
+ call void @cxfii()
+ call void @cxfiii()
+ call void @cxdd()
+ call void @cxif()
+ call void @cxiff()
+ call void @cxifi()
+ call void @cxifii()
+ call void @cxifif()
+ call void @cxiffi()
+ ret void
+}
+
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+!llvm.ident = !{!0}
+
+!0 = metadata !{metadata !"clang version 3.6.0 (gitosis@dmz-portal.mips.com:clang 43992fe7b17de5553ac06d323cb80cc6723a9ae3) (gitosis@dmz-portal.mips.com:llvm.git 0834e6839eb170197c81bb02e916258d1527e312)"}
diff --git a/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
new file mode 100644
index 0000000..c72b1e7
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll
@@ -0,0 +1,254 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+
+@f1 = common global float 0.000000e+00, align 4
+@f2 = common global float 0.000000e+00, align 4
+@b1 = common global i32 0, align 4
+@d1 = common global double 0.000000e+00, align 8
+@d2 = common global double 0.000000e+00, align 8
+
+; Function Attrs: nounwind
+define void @feq1() {
+entry:
+ %0 = load float* @f1, align 4
+ %1 = load float* @f2, align 4
+ %cmp = fcmp oeq float %0, %1
+; CHECK-LABEL: feq1:
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @fne1() {
+entry:
+ %0 = load float* @f1, align 4
+ %1 = load float* @f2, align 4
+ %cmp = fcmp une float %0, %1
+; CHECK-LABEL: fne1:
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.eq.s $f[[REG_F1]], $f[[REG_F2]]
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @flt1() {
+entry:
+ %0 = load float* @f1, align 4
+ %1 = load float* @f2, align 4
+ %cmp = fcmp olt float %0, %1
+; CHECK-LABEL: flt1:
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.olt.s $f[[REG_F1]], $f[[REG_F2]]
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @fgt1() {
+entry:
+ %0 = load float* @f1, align 4
+ %1 = load float* @f2, align 4
+ %cmp = fcmp ogt float %0, %1
+; CHECK-LABEL: fgt1:
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.ule.s $f[[REG_F1]], $f[[REG_F2]]
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @fle1() {
+entry:
+ %0 = load float* @f1, align 4
+ %1 = load float* @f2, align 4
+ %cmp = fcmp ole float %0, %1
+; CHECK-LABEL: fle1:
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.ole.s $f[[REG_F1]], $f[[REG_F2]]
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @fge1() {
+entry:
+ %0 = load float* @f1, align 4
+ %1 = load float* @f2, align 4
+ %cmp = fcmp oge float %0, %1
+; CHECK-LABEL: fge1:
+; CHECK-DAG: lw $[[REG_F2_GOT:[0-9]+]], %got(f2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_F1_GOT:[0-9]+]], %got(f1)(${{[0-9]+}})
+; CHECK-DAG: lwc1 $f[[REG_F2:[0-9]+]], 0($[[REG_F2_GOT]])
+; CHECK-DAG: lwc1 $f[[REG_F1:[0-9]+]], 0($[[REG_F1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.ult.s $f[[REG_F1]], $f[[REG_F2]]
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @deq1() {
+entry:
+ %0 = load double* @d1, align 8
+ %1 = load double* @d2, align 8
+ %cmp = fcmp oeq double %0, %1
+; CHECK-LABEL: deq1:
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @dne1() {
+entry:
+ %0 = load double* @d1, align 8
+ %1 = load double* @d2, align 8
+ %cmp = fcmp une double %0, %1
+; CHECK-LABEL: dne1:
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.eq.d $f[[REG_D1]], $f[[REG_D2]]
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @dlt1() {
+entry:
+ %0 = load double* @d1, align 8
+ %1 = load double* @d2, align 8
+ %cmp = fcmp olt double %0, %1
+; CHECK-LABEL: dlt1:
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.olt.d $f[[REG_D1]], $f[[REG_D2]]
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @dgt1() {
+entry:
+ %0 = load double* @d1, align 8
+ %1 = load double* @d2, align 8
+ %cmp = fcmp ogt double %0, %1
+; CHECK-LABEL: dgt1:
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.ule.d $f[[REG_D1]], $f[[REG_D2]]
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @dle1() {
+entry:
+ %0 = load double* @d1, align 8
+ %1 = load double* @d2, align 8
+ %cmp = fcmp ole double %0, %1
+; CHECK-LABEL: dle1:
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.ole.d $f[[REG_D1]], $f[[REG_D2]]
+; CHECK: movt $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @dge1() {
+entry:
+ %0 = load double* @d1, align 8
+ %1 = load double* @d2, align 8
+ %cmp = fcmp oge double %0, %1
+; CHECK-LABEL: dge1:
+; CHECK-DAG: lw $[[REG_D2_GOT:[0-9]+]], %got(d2)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D1_GOT:[0-9]+]], %got(d1)(${{[0-9]+}})
+; CHECK-DAG: ldc1 $f[[REG_D2:[0-9]+]], 0($[[REG_D2_GOT]])
+; CHECK-DAG: ldc1 $f[[REG_D1:[0-9]+]], 0($[[REG_D1_GOT]])
+; CHECK-DAG: addiu $[[REG_ZERO:[0-9]+]], $zero, 0
+; CHECK-DAG: addiu $[[REG_ONE:[0-9]+]], $zero, 1
+; CHECK: c.ult.d $f[[REG_D1]], $f[[REG_D2]]
+; CHECK: movf $[[REG_ZERO]], $[[REG_ONE]], $fcc0
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+
diff --git a/test/CodeGen/Mips/Fast-ISel/fpext.ll b/test/CodeGen/Mips/Fast-ISel/fpext.ll
new file mode 100644
index 0000000..98aca75
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/fpext.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+
+@f = global float 0x40147E6B80000000, align 4
+@d_f = common global double 0.000000e+00, align 8
+@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
+
+; Function Attrs: nounwind
+define void @dv() #0 {
+entry:
+ %0 = load float* @f, align 4
+ %conv = fpext float %0 to double
+; CHECK: cvt.d.s $f{{[0-9]+}}, $f{{[0-9]+}}
+ store double %conv, double* @d_f, align 8
+ ret void
+}
+
+
+attributes #1 = { nounwind }
diff --git a/test/CodeGen/Mips/Fast-ISel/fpintconv.ll b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
new file mode 100644
index 0000000..846726a
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/fpintconv.ll
@@ -0,0 +1,35 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+
+
+@f = global float 0x40D6E83280000000, align 4
+@d = global double 0x4132D68780000000, align 8
+@i_f = common global i32 0, align 4
+@i_d = common global i32 0, align 4
+@.str = private unnamed_addr constant [5 x i8] c"%i \0A\00", align 1
+
+; Function Attrs: nounwind
+define void @ifv() {
+entry:
+; CHECK-LABEL: .ent ifv
+ %0 = load float* @f, align 4
+ %conv = fptosi float %0 to i32
+; CHECK: trunc.w.s $f[[REG:[0-9]+]], $f{{[0-9]+}}
+; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]]
+ store i32 %conv, i32* @i_f, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @idv() {
+entry:
+; CHECK-LABEL: .ent idv
+ %0 = load double* @d, align 8
+ %conv = fptosi double %0 to i32
+; CHECK: trunc.w.d $f[[REG:[0-9]+]], $f{{[0-9]+}}
+; CHECK: mfc1 ${{[0-9]+}}, $f[[REG]]
+ store i32 %conv, i32* @i_d, align 4
+ ret void
+}
diff --git a/test/CodeGen/Mips/Fast-ISel/fptrunc.ll b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
new file mode 100644
index 0000000..d843dee
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/fptrunc.ll
@@ -0,0 +1,20 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+
+@d = global double 0x40147E6B74DF0446, align 8
+@f = common global float 0.000000e+00, align 4
+@.str = private unnamed_addr constant [6 x i8] c"%f \0A\00", align 1
+
+; Function Attrs: nounwind
+define void @fv() #0 {
+entry:
+ %0 = load double* @d, align 8
+ %conv = fptrunc double %0 to float
+; CHECK: cvt.s.d $f{{[0-9]+}}, $f{{[0-9]+}}
+ store float %conv, float* @f, align 4
+ ret void
+}
+
+attributes #1 = { nounwind }
diff --git a/test/CodeGen/Mips/Fast-ISel/icmpa.ll b/test/CodeGen/Mips/Fast-ISel/icmpa.ll
new file mode 100644
index 0000000..bd41a29
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/icmpa.ll
@@ -0,0 +1,210 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+
+@c = global i32 4, align 4
+@d = global i32 9, align 4
+@uc = global i32 4, align 4
+@ud = global i32 9, align 4
+@b1 = common global i32 0, align 4
+
+; Function Attrs: nounwind
+define void @eq() {
+entry:
+; CHECK-LABEL: .ent eq
+
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp eq i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
+; CHECK: sltiu $[[REG2:[0-9]+]], $[[REG1]], 1
+; FIXME: This instruction is redundant. The sltiu can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @ne() {
+entry:
+; CHECK-LABEL: .ent ne
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp ne i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: xor $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
+; CHECK: sltu $[[REG2:[0-9]+]], $zero, $[[REG1]]
+; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @ugt() {
+entry:
+; CHECK-LABEL: .ent ugt
+ %0 = load i32* @uc, align 4
+ %1 = load i32* @ud, align 4
+ %cmp = icmp ugt i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
+; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
+; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @ult() {
+entry:
+; CHECK-LABEL: .ent ult
+ %0 = load i32* @uc, align 4
+ %1 = load i32* @ud, align 4
+ %cmp = icmp ult i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
+; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
+; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @uge() {
+entry:
+; CHECK-LABEL: .ent uge
+ %0 = load i32* @uc, align 4
+ %1 = load i32* @ud, align 4
+ %cmp = icmp uge i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
+; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UC]], $[[REG_UD]]
+; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
+; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @ule() {
+entry:
+; CHECK-LABEL: .ent ule
+ %0 = load i32* @uc, align 4
+ %1 = load i32* @ud, align 4
+ %cmp = icmp ule i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_UD_GOT:[0-9+]]], %got(ud)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UC_GOT:[0-9+]]], %got(uc)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_UD:[0-9]+]], 0($[[REG_UD_GOT]])
+; CHECK-DAG: lw $[[REG_UC:[0-9]+]], 0($[[REG_UC_GOT]])
+; CHECK: sltu $[[REG1:[0-9]+]], $[[REG_UD]], $[[REG_UC]]
+; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
+; FIXME: This instruction is redundant. The sltu can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @sgt() {
+entry:
+; CHECK-LABEL: .ent sgt
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp sgt i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
+; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @slt() {
+entry:
+; CHECK-LABEL: .ent slt
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp slt i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
+; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @sge() {
+entry:
+; CHECK-LABEL: .ent sge
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp sge i32 %0, %1
+ %conv = zext i1 %cmp to i32
+ store i32 %conv, i32* @b1, align 4
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: slt $[[REG1:[0-9]+]], $[[REG_C]], $[[REG_D]]
+; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
+; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+ ret void
+}
+
+; Function Attrs: nounwind
+define void @sle() {
+entry:
+; CHECK-LABEL: .ent sle
+ %0 = load i32* @c, align 4
+ %1 = load i32* @d, align 4
+ %cmp = icmp sle i32 %0, %1
+ %conv = zext i1 %cmp to i32
+; CHECK-DAG: lw $[[REG_D_GOT:[0-9+]]], %got(d)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_C_GOT:[0-9+]]], %got(c)(${{[0-9]+}})
+; CHECK-DAG: lw $[[REG_D:[0-9]+]], 0($[[REG_D_GOT]])
+; CHECK-DAG: lw $[[REG_C:[0-9]+]], 0($[[REG_C_GOT]])
+; CHECK: slt $[[REG1:[0-9]+]], $[[REG_D]], $[[REG_C]]
+; CHECK: xori $[[REG2:[0-9]+]], $[[REG1]], 1
+; FIXME: This instruction is redundant. The slt can only produce 0 and 1.
+; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
+ store i32 %conv, i32* @b1, align 4
+ ret void
+}
diff --git a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
index f113a0e..d84478b 100644
--- a/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
+++ b/test/CodeGen/Mips/Fast-ISel/loadstore2.ll
@@ -6,6 +6,8 @@ target triple = "mips--linux-gnu"
@c1 = common global i8 0, align 1
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
@s2 = common global i16 0, align 2
@s1 = common global i16 0, align 2
diff --git a/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
new file mode 100644
index 0000000..f7f2c64
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/loadstoreconv.ll
@@ -0,0 +1,179 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s -check-prefix=mips32r2
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s -check-prefix=mips32
+
+@b2 = global i8 0, align 1
+@b1 = global i8 1, align 1
+@uc1 = global i8 0, align 1
+@uc2 = global i8 -1, align 1
+@sc1 = global i8 -128, align 1
+@sc2 = global i8 127, align 1
+@ss1 = global i16 -32768, align 2
+@ss2 = global i16 32767, align 2
+@us1 = global i16 0, align 2
+@us2 = global i16 -1, align 2
+@ssi = global i16 0, align 2
+@ssj = global i16 0, align 2
+@i = global i32 0, align 4
+@j = global i32 0, align 4
+@.str = private unnamed_addr constant [4 x i8] c"%i\0A\00", align 1
+@.str1 = private unnamed_addr constant [7 x i8] c"%i %i\0A\00", align 1
+
+; Function Attrs: nounwind
+define void @_Z3b_iv() {
+entry:
+; CHECK-LABEL: .ent _Z3b_iv
+ %0 = load i8* @b1, align 1
+ %tobool = trunc i8 %0 to i1
+ %frombool = zext i1 %tobool to i8
+ store i8 %frombool, i8* @b2, align 1
+ %1 = load i8* @b2, align 1
+ %tobool1 = trunc i8 %1 to i1
+ %conv = zext i1 %tobool1 to i32
+ store i32 %conv, i32* @i, align 4
+; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; CHECK: andi $[[REG2:[0-9]+]], $[[REG1]], 1
+; CHECK: sb $[[REG2]], 0(${{[0-9]+}})
+
+
+
+ ret void
+; CHECK: .end _Z3b_iv
+}
+
+; Function Attrs: nounwind
+define void @_Z4uc_iv() {
+entry:
+; CHECK-LABEL: .ent _Z4uc_iv
+
+ %0 = load i8* @uc1, align 1
+ %conv = zext i8 %0 to i32
+ store i32 %conv, i32* @i, align 4
+ %1 = load i8* @uc2, align 1
+ %conv1 = zext i8 %1 to i32
+; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
+
+ store i32 %conv1, i32* @j, align 4
+ ret void
+; CHECK: .end _Z4uc_iv
+
+}
+
+; Function Attrs: nounwind
+define void @_Z4sc_iv() {
+entry:
+; mips32r2-LABEL: .ent _Z4sc_iv
+; mips32-LABEL: .ent _Z4sc_iv
+
+ %0 = load i8* @sc1, align 1
+ %conv = sext i8 %0 to i32
+ store i32 %conv, i32* @i, align 4
+ %1 = load i8* @sc2, align 1
+ %conv1 = sext i8 %1 to i32
+ store i32 %conv1, i32* @j, align 4
+; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
+; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
+; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
+
+ ret void
+; CHECK: .end _Z4sc_iv
+}
+
+; Function Attrs: nounwind
+define void @_Z4us_iv() {
+entry:
+; CHECK-LABEL: .ent _Z4us_iv
+ %0 = load i16* @us1, align 2
+ %conv = zext i16 %0 to i32
+ store i32 %conv, i32* @i, align 4
+ %1 = load i16* @us2, align 2
+ %conv1 = zext i16 %1 to i32
+ store i32 %conv1, i32* @j, align 4
+ ret void
+; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 65535
+; CHECK: .end _Z4us_iv
+}
+
+; Function Attrs: nounwind
+define void @_Z4ss_iv() {
+entry:
+; mips32r2-LABEL: .ent _Z4ss_iv
+; mips32=LABEL: .ent _Z4ss_iv
+
+ %0 = load i16* @ss1, align 2
+ %conv = sext i16 %0 to i32
+ store i32 %conv, i32* @i, align 4
+ %1 = load i16* @ss2, align 2
+ %conv1 = sext i16 %1 to i32
+ store i32 %conv1, i32* @j, align 4
+; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; mips32r2: seh ${{[0-9]+}}, $[[REG1]]
+; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 16
+; mips32: sra ${{[0-9]+}}, $[[REG2]], 16
+
+ ret void
+; CHECK: .end _Z4ss_iv
+}
+
+; Function Attrs: nounwind
+define void @_Z4b_ssv() {
+entry:
+; CHECK-LABEL: .ent _Z4b_ssv
+ %0 = load i8* @b2, align 1
+ %tobool = trunc i8 %0 to i1
+ %conv = zext i1 %tobool to i16
+ store i16 %conv, i16* @ssi, align 2
+ ret void
+; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
+; CHECK: .end _Z4b_ssv
+}
+
+; Function Attrs: nounwind
+define void @_Z5uc_ssv() {
+entry:
+; CHECK-LABEL: .ent _Z5uc_ssv
+ %0 = load i8* @uc1, align 1
+ %conv = zext i8 %0 to i16
+ store i16 %conv, i16* @ssi, align 2
+ %1 = load i8* @uc2, align 1
+ %conv1 = zext i8 %1 to i16
+; CHECK: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; CHECK: andi ${{[0-9]+}}, $[[REG1]], 255
+
+ store i16 %conv1, i16* @ssj, align 2
+ ret void
+; CHECK: .end _Z5uc_ssv
+}
+
+; Function Attrs: nounwind
+define void @_Z5sc_ssv() {
+entry:
+; mips32r2-LABEL: .ent _Z5sc_ssv
+; mips32-LABEL: .ent _Z5sc_ssv
+ %0 = load i8* @sc1, align 1
+ %conv = sext i8 %0 to i16
+ store i16 %conv, i16* @ssi, align 2
+ %1 = load i8* @sc2, align 1
+ %conv1 = sext i8 %1 to i16
+ store i16 %conv1, i16* @ssj, align 2
+; mips32r2: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; mips32r2: seb ${{[0-9]+}}, $[[REG1]]
+; mips32: lbu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
+; mips32: sll $[[REG2:[0-9]+]], $[[REG1]], 24
+; mips32: sra ${{[0-9]+}}, $[[REG2]], 24
+
+ ret void
+; CHECK: .end _Z5sc_ssv
+}
+
diff --git a/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
new file mode 100644
index 0000000..93cf4c1
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
+
+@.str = private unnamed_addr constant [6 x i8] c"hello\00", align 1
+@s = common global i8* null, align 4
+
+; Function Attrs: nounwind
+define void @foo() #0 {
+entry:
+ store i8* getelementptr inbounds ([6 x i8]* @.str, i32 0, i32 0), i8** @s, align 4
+ ret void
+; CHECK: .ent foo
+; CHECK: lw $[[REG1:[0-9]+]], %got($.str)(${{[0-9]+}})
+; CHECK: addiu ${{[0-9]+}}, $[[REG1]], %lo($.str)
+
+}
+
+attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
diff --git a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
index eeaff87..c847561 100644
--- a/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
+++ b/test/CodeGen/Mips/Fast-ISel/nullvoid.ll
@@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
; Function Attrs: nounwind
define void @foo() {
diff --git a/test/CodeGen/Mips/Fast-ISel/shift.ll b/test/CodeGen/Mips/Fast-ISel/shift.ll
new file mode 100644
index 0000000..18fd5ac
--- /dev/null
+++ b/test/CodeGen/Mips/Fast-ISel/shift.ll
@@ -0,0 +1,24 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -O1 -fast-isel=true -mips-fast-isel -filetype=obj %s -o - \
+; RUN: | llvm-objdump -arch mipsel -mcpu=mips32r2 -d - | FileCheck %s
+
+; This test checks that encoding for srl is correct when fast-isel for mips32r2 is used.
+
+%struct.s = type { [4 x i8], i32 }
+
+define i32 @main() nounwind uwtable {
+entry:
+ %foo = alloca %struct.s, align 4
+ %0 = bitcast %struct.s* %foo to i32*
+ %bf.load = load i32* %0, align 4
+ %bf.lshr = lshr i32 %bf.load, 2
+ %cmp = icmp ne i32 %bf.lshr, 2
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ unreachable
+
+if.end:
+ ret i32 0
+}
+
+; CHECK: srl ${{[0-9]+}}, ${{[0-9]+}}, {{[0-9]+}}
diff --git a/test/CodeGen/Mips/Fast-ISel/simplestore.ll b/test/CodeGen/Mips/Fast-ISel/simplestore.ll
index 5d52481..83e3f3f 100644
--- a/test/CodeGen/Mips/Fast-ISel/simplestore.ll
+++ b/test/CodeGen/Mips/Fast-ISel/simplestore.ll
@@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
@abcd = external global i32
diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
index 6759c01..74723ae 100644
--- a/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
+++ b/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll
@@ -1,5 +1,11 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
+; RUN: < %s | FileCheck %s -check-prefix=mips32r2
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s -check-prefix=mips32
@f = common global float 0.000000e+00, align 4
@de = common global double 0.000000e+00, align 8
@@ -23,15 +29,25 @@ entry:
define void @d1() #0 {
entry:
store double 1.234567e+00, double* @de, align 8
-; CHECK: .ent d1
-; CHECK: lui $[[REG1a:[0-9]+]], 16371
-; CHECK: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
-; CHECK: lui $[[REG1b:[0-9]+]], 21403
-; CHECK: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
-; CHECK: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
-; CHECK: mthc1 $[[REG2a]], $f[[REG3]]
-; CHECK: sdc1 $f[[REG3]], 0(${{[0-9]+}})
-; CHECK: .end d1
+; mip32r2: .ent d1
+; mips32r2: lui $[[REG1a:[0-9]+]], 16371
+; mips32r2: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
+; mips32r2: lui $[[REG1b:[0-9]+]], 21403
+; mips32r2: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
+; mips32r2: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
+; mips32r2: mthc1 $[[REG2a]], $f[[REG3]]
+; mips32r2: sdc1 $f[[REG3]], 0(${{[0-9]+}})
+; mips32r2: .end d1
+; mips32: .ent d1
+; mips32: lui $[[REG1a:[0-9]+]], 16371
+; mips32: ori $[[REG2a:[0-9]+]], $[[REG1a]], 49353
+; mips32: lui $[[REG1b:[0-9]+]], 21403
+; mips32: ori $[[REG2b:[0-9]+]], $[[REG1b]], 34951
+; mips32: mtc1 $[[REG2b]], $f[[REG3:[0-9]+]]
+; mips32: mtc1 $[[REG2a]], $f{{[0-9]+}}
+; mips32: sdc1 $f[[REG3]], 0(${{[0-9]+}})
+; mips32: .end d1
+
ret void
}
diff --git a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
index 7d2c8e7..128e1de 100644
--- a/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
+++ b/test/CodeGen/Mips/Fast-ISel/simplestorei.ll
@@ -1,5 +1,7 @@
; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
; RUN: < %s | FileCheck %s
+; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
+; RUN: < %s | FileCheck %s
@ijk = external global i32
generated by cgit v1.1 at 2025-08-17 22:26:35 +0000