diff options
Diffstat (limited to 'test/CodeGen/Mips/llvm-ir')
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/add.ll | 123 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/and.ll | 99 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/ashr.ll | 200 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/call.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/indirectbr.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/lshr.ll | 188 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/mul.ll | 109 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/or.ll | 99 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/ret.ll | 4 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/sdiv.ll | 144 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/select.ll | 712 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/shl.ll | 200 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/srem.ll | 139 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/sub.ll | 122 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/udiv.ll | 116 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/urem.ll | 155 | ||||
| -rw-r--r-- | test/CodeGen/Mips/llvm-ir/xor.ll | 99 |
17 files changed, 2480 insertions, 37 deletions
diff --git a/test/CodeGen/Mips/llvm-ir/add.ll b/test/CodeGen/Mips/llvm-ir/add.ll new file mode 100644 index 0000000..6cccc7d --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/add.ll @@ -0,0 +1,123 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 + +define signext i1 @add_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: add_i1: + + ; ALL: addu $[[T0:[0-9]+]], $4, $5 + ; ALL: sll $[[T0]], $[[T0]], 31 + ; ALL: sra $2, $[[T0]], 31 + + %r = add i1 %a, %b + ret i1 %r +} + +define signext i8 @add_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: add_i8: + + ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seb $2, $[[T0:[0-9]+]] + + %r = add i8 %a, %b + ret i8 %r +} + +define signext i16 @add_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: add_i16: + + ; NOT-R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: addu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seh $2, $[[T0:[0-9]+]] + + %r = add i16 %a, %b + ret i16 %r +} + +define signext i32 @add_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: add_i32: + + ; ALL: addu $2, $4, $5 + + %r = add i32 %a, %b + ret i32 %r +} + +define signext i64 @add_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: add_i64: + + ; GP32: addu $3, $5, $7 + ; GP32: sltu $[[T0:[0-9]+]], $3, $7 + ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP32: addu $2, $4, $[[T1]] + + ; GP64: daddu $2, $4, $5 + + %r = add i64 %a, %b + ret i64 %r +} + +define signext i128 @add_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: add_i128: + + ; GP32: lw $[[T0:[0-9]+]], 28($sp) + ; GP32: addu $[[T1:[0-9]+]], $7, $[[T0]] + ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 24($sp) + ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]] + ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; GP32: lw $[[T7:[0-9]+]], 20($sp) + ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] + ; GP32: lw $[[T9:[0-9]+]], 16($sp) + ; GP32: addu $3, $5, $[[T8]] + ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]] + ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]] + ; GP32: addu $2, $4, $[[T11]] + ; GP32: move $4, $[[T5]] + ; GP32: move $5, $[[T1]] + + ; GP64: daddu $3, $5, $7 + ; GP64: sltu $[[T0:[0-9]+]], $3, $7 + ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP64: daddu $2, $4, $[[T1]] + + %r = add i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/and.ll b/test/CodeGen/Mips/llvm-ir/and.ll new file mode 100644 index 0000000..8ebcfe4 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/and.ll @@ -0,0 +1,99 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 + +define signext i1 @and_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: and_i1: + + ; ALL: and $2, $4, $5 + + %r = and i1 %a, %b + ret i1 %r +} + +define signext i8 @and_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: and_i8: + + ; ALL: and $2, $4, $5 + + %r = and i8 %a, %b + ret i8 %r +} + +define signext i16 @and_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: and_i16: + + ; ALL: and $2, $4, $5 + + %r = and i16 %a, %b + ret i16 %r +} + +define signext i32 @and_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: and_i32: + + ; ALL: and $2, $4, $5 + + %r = and i32 %a, %b + ret i32 %r +} + +define signext i64 @and_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: and_i64: + + ; GP32: and $2, $4, $6 + ; GP32: and $3, $5, $7 + + ; GP64: and $2, $4, $5 + + %r = and i64 %a, %b + ret i64 %r +} + +define signext i128 @and_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: and_i128: + + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: and $2, $4, $[[T2]] + ; GP32: and $3, $5, $[[T1]] + ; GP32: and $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: and $5, $7, $[[T3]] + + ; GP64: and $2, $4, $6 + ; GP64: and $3, $5, $7 + + %r = and i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/ashr.ll b/test/CodeGen/Mips/llvm-ir/ashr.ll new file mode 100644 index 0000000..7e1587c --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/ashr.ll @@ -0,0 +1,200 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=M2 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=64R6 + +define signext i1 @ashr_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: ashr_i1: + + ; ALL: move $2, $4 + + %r = ashr i1 %a, %b + ret i1 %r +} + +define signext i8 @ashr_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: ashr_i8: + + ; FIXME: The andi instruction is redundant. + ; ALL: andi $[[T0:[0-9]+]], $5, 255 + ; ALL: srav $2, $4, $[[T0]] + + %r = ashr i8 %a, %b + ret i8 %r +} + +define signext i16 @ashr_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: ashr_i16: + + ; FIXME: The andi instruction is redundant. + ; ALL: andi $[[T0:[0-9]+]], $5, 65535 + ; ALL: srav $2, $4, $[[T0]] + + %r = ashr i16 %a, %b + ret i16 %r +} + +define signext i32 @ashr_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: ashr_i32: + + ; ALL: srav $2, $4, $5 + + %r = ashr i32 %a, %b + ret i32 %r +} + +define signext i64 @ashr_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: ashr_i64: + + ; M2: srav $[[T0:[0-9]+]], $4, $7 + ; M2: andi $[[T1:[0-9]+]], $7, 32 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: move $3, $[[T0]] + ; M2: srlv $[[T2:[0-9]+]], $5, $7 + ; M2: not $[[T3:[0-9]+]], $7 + ; M2: sll $[[T4:[0-9]+]], $4, 1 + ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; M2: or $3, $[[T3]], $[[T2]] + ; M2: $[[BB0]]: + ; M2: beqz $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: nop + ; M2: sra $2, $4, 31 + ; M2: $[[BB1]]: + ; M2: jr $ra + ; M2: nop + + ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 + ; 32R1-R5: not $[[T1:[0-9]+]], $7 + ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1 + ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R1-R5: or $3, $[[T3]], $[[T0]] + ; 32R1-R5: srav $[[T4:[0-9]+]], $4, $7 + ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 + ; 32R1-R5: movn $3, $[[T4]], $[[T5]] + ; 32R1-R5: sra $4, $4, 31 + ; 32R1-R5: jr $ra + ; 32R1-R5: movn $2, $4, $[[T5]] + + ; 32R6: srav $[[T0:[0-9]+]], $4, $7 + ; 32R6: andi $[[T1:[0-9]+]], $7, 32 + ; 32R6: seleqz $[[T2:[0-9]+]], $[[T0]], $[[T1]] + ; 32R6: sra $[[T3:[0-9]+]], $4, 31 + ; 32R6: selnez $[[T4:[0-9]+]], $[[T3]], $[[T1]] + ; 32R6: or $[[T5:[0-9]+]], $[[T4]], $[[T2]] + ; 32R6: srlv $[[T6:[0-9]+]], $5, $7 + ; 32R6: not $[[T7:[0-9]+]], $7 + ; 32R6: sll $[[T8:[0-9]+]], $4, 1 + ; 32R6: sllv $[[T9:[0-9]+]], $[[T8]], $[[T7]] + ; 32R6: or $[[T10:[0-9]+]], $[[T9]], $[[T6]] + ; 32R6: seleqz $[[T11:[0-9]+]], $[[T10]], $[[T1]] + ; 32R6: selnez $[[T12:[0-9]+]], $[[T0]], $[[T1]] + ; 32R6: jr $ra + ; 32R6: or $3, $[[T0]], $[[T11]] + + ; FIXME: The sll instruction below is redundant. + ; GP64: sll $[[T0:[0-9]+]], $5, 0 + ; GP64: dsrav $2, $4, $[[T0]] + + %r = ashr i64 %a, %b + ret i64 %r +} + +define signext i128 @ashr_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: ashr_i128: + + ; GP32: lw $25, %call16(__ashrti3)($gp) + + ; M3: sll $[[T0:[0-9]+]], $7, 0 + ; M3: dsrav $[[T1:[0-9]+]], $4, $[[T0]] + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 + ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: move $3, $[[T1]] + ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] + ; M3: dsll $[[T5:[0-9]+]], $4, 1 + ; M3: not $[[T6:[0-9]+]], $[[T0]] + ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; M3: or $3, $[[T7]], $[[T4]] + ; M3: $[[BB0]]: + ; M3: beqz $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: nop + ; M3: dsra $2, $4, 31 + ; M3: $[[BB1]]: + ; M3: jr $ra + ; M3: nop + + ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 + ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] + ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] + ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] + ; GP64-NOT-R6: dsrav $2, $4, $[[T0]] + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 + + ; GP64-NOT-R6: movn $3, $2, $[[T5]] + ; GP64-NOT-R6: dsra $[[T6:[0-9]+]], $4, 31 + ; GP64-NOT-R6: jr $ra + ; GP64-NOT-R6: movn $2, $[[T6]], $[[T5]] + + ; 64R6: sll $[[T0:[0-9]+]], $7, 0 + ; 64R6: dsrav $[[T1:[0-9]+]], $4, $[[T0]] + ; 64R6: andi $[[T2:[0-9]+]], $[[T0]], 32 + ; 64R6: sll $[[T3:[0-9]+]], $[[T2]], 0 + ; 64R6: seleqz $[[T4:[0-9]+]], $[[T1]], $[[T3]] + ; 64R6: dsra $[[T5:[0-9]+]], $4, 31 + ; 64R6: selnez $[[T6:[0-9]+]], $[[T5]], $[[T3]] + ; 64R6: or $2, $[[T6]], $[[T4]] + ; 64R6: dsrlv $[[T7:[0-9]+]], $5, $[[T0]] + ; 64R6: dsll $[[T8:[0-9]+]], $4, 1 + ; 64R6: not $[[T9:[0-9]+]], $[[T0]] + ; 64R6: dsllv $[[T10:[0-9]+]], $[[T8]], $[[T9]] + ; 64R6: or $[[T11:[0-9]+]], $[[T10]], $[[T7]] + ; 64R6: seleqz $[[T12:[0-9]+]], $[[T11]], $[[T3]] + ; 64R6: selnez $[[T13:[0-9]+]], $[[T1]], $[[T3]] + ; 64R6: jr $ra + ; 64R6: or $3, $[[T13]], $[[T12]] + + %r = ashr i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/call.ll b/test/CodeGen/Mips/llvm-ir/call.ll index 4cbf43c..112ab8e 100644 --- a/test/CodeGen/Mips/llvm-ir/call.ll +++ b/test/CodeGen/Mips/llvm-ir/call.ll @@ -3,10 +3,14 @@ ; FIXME: We should remove the need for -enable-mips-tail-calls ; RUN: llc -march=mips -mcpu=mips32 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 ; RUN: llc -march=mips -mcpu=mips32r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 +; RUN: llc -march=mips -mcpu=mips32r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 +; RUN: llc -march=mips -mcpu=mips32r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 ; RUN: llc -march=mips -mcpu=mips32r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=O32 ; RUN: llc -march=mips64 -mcpu=mips4 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 ; RUN: llc -march=mips64 -mcpu=mips64 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 ; RUN: llc -march=mips64 -mcpu=mips64r2 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 +; RUN: llc -march=mips64 -mcpu=mips64r3 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 +; RUN: llc -march=mips64 -mcpu=mips64r5 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 ; RUN: llc -march=mips64 -mcpu=mips64r6 -enable-mips-tail-calls < %s | FileCheck %s -check-prefix=ALL -check-prefix=N64 declare void @extern_void_void() diff --git a/test/CodeGen/Mips/llvm-ir/indirectbr.ll b/test/CodeGen/Mips/llvm-ir/indirectbr.ll index d8fd787..debfeb3 100644 --- a/test/CodeGen/Mips/llvm-ir/indirectbr.ll +++ b/test/CodeGen/Mips/llvm-ir/indirectbr.ll @@ -2,10 +2,14 @@ ; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 ; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 ; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6 ; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 ; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=NOT-R6 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=R6 define i32 @br(i8 *%addr) { diff --git a/test/CodeGen/Mips/llvm-ir/lshr.ll b/test/CodeGen/Mips/llvm-ir/lshr.ll new file mode 100644 index 0000000..7344d95 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/lshr.ll @@ -0,0 +1,188 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=M2 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=64R6 + +define signext i1 @lshr_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: lshr_i1: + + ; ALL: move $2, $4 + + %r = lshr i1 %a, %b + ret i1 %r +} + +define zeroext i8 @lshr_i8(i8 zeroext %a, i8 zeroext %b) { +entry: +; ALL-LABEL: lshr_i8: + + ; ALL: srlv $[[T0:[0-9]+]], $4, $5 + ; ALL: andi $2, $[[T0]], 255 + + %r = lshr i8 %a, %b + ret i8 %r +} + +define zeroext i16 @lshr_i16(i16 zeroext %a, i16 zeroext %b) { +entry: +; ALL-LABEL: lshr_i16: + + ; ALL: srlv $[[T0:[0-9]+]], $4, $5 + ; ALL: andi $2, $[[T0]], 65535 + + %r = lshr i16 %a, %b + ret i16 %r +} + +define signext i32 @lshr_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: lshr_i32: + + ; ALL: srlv $2, $4, $5 + + %r = lshr i32 %a, %b + ret i32 %r +} + +define signext i64 @lshr_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: lshr_i64: + + ; M2: srlv $[[T0:[0-9]+]], $4, $7 + ; M2: andi $[[T1:[0-9]+]], $7, 32 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: move $3, $[[T0]] + ; M2: srlv $[[T2:[0-9]+]], $5, $7 + ; M2: not $[[T3:[0-9]+]], $7 + ; M2: sll $[[T4:[0-9]+]], $4, 1 + ; M2: sllv $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; M2: or $3, $[[T3]], $[[T2]] + ; M2: $[[BB0]]: + ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: addiu $2, $zero, 0 + ; M2: move $2, $[[T0]] + ; M2: $[[BB1]]: + ; M2: jr $ra + ; M2: nop + + ; 32R1-R5: srlv $[[T0:[0-9]+]], $5, $7 + ; 32R1-R5: not $[[T1:[0-9]+]], $7 + ; 32R1-R5: sll $[[T2:[0-9]+]], $4, 1 + ; 32R1-R5: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R1-R5: or $3, $[[T3]], $[[T0]] + ; 32R1-R5: srlv $[[T4:[0-9]+]], $4, $7 + ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 + ; 32R1-R5: movn $3, $[[T4]], $[[T5]] + ; 32R1-R5: jr $ra + ; 32R1-R5: movn $2, $zero, $[[T5]] + + ; 32R6: srlv $[[T0:[0-9]+]], $5, $7 + ; 32R6: not $[[T1:[0-9]+]], $7 + ; 32R6: sll $[[T2:[0-9]+]], $4, 1 + ; 32R6: sllv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R6: or $[[T4:[0-9]+]], $[[T3]], $[[T0]] + ; 32R6: andi $[[T5:[0-9]+]], $7, 32 + ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T3]] + ; 32R6: srlv $[[T7:[0-9]+]], $4, $7 + ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; 32R6: or $3, $[[T8]], $[[T6]] + ; 32R6: jr $ra + ; 32R6: seleqz $2, $[[T7]], $[[T5]] + + ; GP64: sll $[[T0:[0-9]+]], $5, 0 + ; GP64: dsrlv $2, $4, $[[T0]] + + %r = lshr i64 %a, %b + ret i64 %r +} + +define signext i128 @lshr_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: lshr_i128: + + ; GP32: lw $25, %call16(__lshrti3)($gp) + + ; M3: sll $[[T0:[0-9]+]], $7, 0 + ; M3: dsrlv $[[T1:[0-9]+]], $4, $[[T0]] + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 + ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: move $3, $[[T1]] + ; M3: dsrlv $[[T4:[0-9]+]], $5, $[[T0]] + ; M3: dsll $[[T5:[0-9]+]], $4, 1 + ; M3: not $[[T6:[0-9]+]], $[[T0]] + ; M3: dsllv $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; M3: or $3, $[[T7]], $[[T4]] + ; M3: $[[BB0]]: + ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: daddiu $2, $zero, 0 + ; M3: move $2, $[[T1]] + ; M3: $[[BB1]]: + ; M3: jr $ra + ; M3: nop + + ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 + ; GP64-NOT-R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] + ; GP64-NOT-R6: dsll $[[T2:[0-9]+]], $4, 1 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] + ; GP64-NOT-R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP64-NOT-R6: or $3, $[[T4]], $[[T1]] + ; GP64-NOT-R6: dsrlv $2, $4, $[[T0]] + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 + ; GP64-NOT-R6: movn $3, $2, $[[T5]] + ; GP64-NOT-R6: jr $ra + ; GP64-NOT-R6: movn $2, $zero, $1 + + ; 64R6: sll $[[T0:[0-9]+]], $7, 0 + ; 64R6: dsrlv $[[T1:[0-9]+]], $5, $[[T0]] + ; 64R6: dsll $[[T2:[0-9]+]], $4, 1 + ; 64R6: not $[[T3:[0-9]+]], $[[T0]] + ; 64R6: dsllv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; 64R6: or $[[T5:[0-9]+]], $[[T4]], $[[T1]] + ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 + ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 + ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] + ; 64R6: dsrlv $[[T9:[0-9]+]], $4, $[[T0]] + ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] + ; 64R6: or $3, $[[T10]], $[[T8]] + ; 64R6: jr $ra + ; 64R6: seleqz $2, $[[T0]], $[[T7]] + + %r = lshr i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/mul.ll b/test/CodeGen/Mips/llvm-ir/mul.ll index 1674124..a758280 100644 --- a/test/CodeGen/Mips/llvm-ir/mul.ll +++ b/test/CodeGen/Mips/llvm-ir/mul.ll @@ -1,19 +1,27 @@ -; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=M2 -; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R1 -; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R1-R2 -check-prefix=32R2 -; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=32R6 -; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=M4 -; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=64R1-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=64R1-R2 -; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ -; RUN: -check-prefix=ALL -check-prefix=64R6 +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=M2 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=32R1-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=32R1-R5 -check-prefix=32R2-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=32R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=M4 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=64R1-R5 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=64R1-R5 -check-prefix=GP64 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s -check-prefix=ALL \ +; RUN: -check-prefix=64R6 define signext i1 @mul_i1(i1 signext %a, i1 signext %b) { entry: @@ -24,9 +32,9 @@ entry: ; M2: sll $[[T0]], $[[T0]], 31 ; M2: sra $2, $[[T0]], 31 - ; 32R1-R2: mul $[[T0:[0-9]+]], $4, $5 - ; 32R1-R2: sll $[[T0]], $[[T0]], 31 - ; 32R1-R2: sra $2, $[[T0]], 31 + ; 32R1-R5: mul $[[T0:[0-9]+]], $4, $5 + ; 32R1-R5: sll $[[T0]], $[[T0]], 31 + ; 32R1-R5: sra $2, $[[T0]], 31 ; 32R6: mul $[[T0:[0-9]+]], $4, $5 ; 32R6: sll $[[T0]], $[[T0]], 31 @@ -37,9 +45,9 @@ entry: ; M4: sll $[[T0]], $[[T0]], 31 ; M4: sra $2, $[[T0]], 31 - ; 64R1-R2: mul $[[T0:[0-9]+]], $4, $5 - ; 64R1-R2: sll $[[T0]], $[[T0]], 31 - ; 64R1-R2: sra $2, $[[T0]], 31 + ; 64R1-R5: mul $[[T0:[0-9]+]], $4, $5 + ; 64R1-R5: sll $[[T0]], $[[T0]], 31 + ; 64R1-R5: sra $2, $[[T0]], 31 ; 64R6: mul $[[T0:[0-9]+]], $4, $5 ; 64R6: sll $[[T0]], $[[T0]], 31 @@ -62,8 +70,8 @@ entry: ; 32R1: sll $[[T0]], $[[T0]], 24 ; 32R1: sra $2, $[[T0]], 24 - ; 32R2: mul $[[T0:[0-9]+]], $4, $5 - ; 32R2: seb $2, $[[T0]] + ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5 + ; 32R2-R5: seb $2, $[[T0]] ; 32R6: mul $[[T0:[0-9]+]], $4, $5 ; 32R6: seb $2, $[[T0]] @@ -99,8 +107,8 @@ entry: ; 32R1: sll $[[T0]], $[[T0]], 16 ; 32R1: sra $2, $[[T0]], 16 - ; 32R2: mul $[[T0:[0-9]+]], $4, $5 - ; 32R2: seh $2, $[[T0]] + ; 32R2-R5: mul $[[T0:[0-9]+]], $4, $5 + ; 32R2-R5: seh $2, $[[T0]] ; 32R6: mul $[[T0:[0-9]+]], $4, $5 ; 32R6: seh $2, $[[T0]] @@ -130,10 +138,10 @@ entry: ; M2: mult $4, $5 ; M2: mflo $2 - ; 32R1-R2: mul $2, $4, $5 + ; 32R1-R5: mul $2, $4, $5 ; 32R6: mul $2, $4, $5 - ; 64R1-R2: mul $2, $4, $5 + ; 64R1-R5: mul $2, $4, $5 ; 64R6: mul $2, $4, $5 %r = mul i32 %a, %b ret i32 %r @@ -153,13 +161,13 @@ entry: ; M2: addu $[[T2:[0-9]+]], $4, $[[T1]] ; M2: addu $2, $[[T2]], $[[T0]] - ; 32R1-R2: multu $5, $7 - ; 32R1-R2: mflo $3 - ; 32R1-R2: mfhi $[[T0:[0-9]+]] - ; 32R1-R2: mul $[[T1:[0-9]+]], $4, $7 - ; 32R1-R2: mul $[[T2:[0-9]+]], $5, $6 - ; 32R1-R2: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]] - ; 32R1-R2: addu $2, $[[T0]], $[[T1]] + ; 32R1-R5: multu $5, $7 + ; 32R1-R5: mflo $3 + ; 32R1-R5: mfhi $[[T0:[0-9]+]] + ; 32R1-R5: mul $[[T1:[0-9]+]], $4, $7 + ; 32R1-R5: mul $[[T2:[0-9]+]], $5, $6 + ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]] + ; 32R1-R5: addu $2, $[[T0]], $[[T1]] ; 32R6: mul $[[T0:[0-9]+]], $5, $6 ; 32R6: muhu $[[T1:[0-9]+]], $5, $7 @@ -171,11 +179,38 @@ entry: ; M4: dmult $4, $5 ; M4: mflo $2 - ; 64R1-R2: dmult $4, $5 - ; 64R1-R2: mflo $2 + ; 64R1-R5: dmult $4, $5 + ; 64R1-R5: mflo $2 ; 64R6: dmul $2, $4, $5 %r = mul i64 %a, %b ret i64 %r } + +define signext i128 @mul_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: mul_i128: + + ; GP32: lw $25, %call16(__multi3)($gp) + + ; GP64-NOT-R6: dmult $4, $7 + ; GP64-NOT-R6: mflo $[[T0:[0-9]+]] + ; GP64-NOT-R6: dmult $5, $6 + ; GP64-NOT-R6: mflo $[[T1:[0-9]+]] + ; GP64-NOT-R6: dmultu $5, $7 + ; GP64-NOT-R6: mflo $3 + ; GP64-NOT-R6: mfhi $[[T2:[0-9]+]] + ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] + + ; 64R6: dmul $[[T0:[0-9]+]], $5, $6 + ; 64R6: dmuhu $[[T1:[0-9]+]], $5, $7 + ; 64R6: daddu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; 64R6: dmul $[[T3:[0-9]+]], $4, $7 + ; 64R6: daddu $2, $[[T2]], $[[T3]] + ; 64R6: dmul $3, $5, $7 + + %r = mul i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/or.ll b/test/CodeGen/Mips/llvm-ir/or.ll new file mode 100644 index 0000000..6215e40 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/or.ll @@ -0,0 +1,99 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 + +define signext i1 @or_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: or_i1: + + ; ALL: or $2, $4, $5 + + %r = or i1 %a, %b + ret i1 %r +} + +define signext i8 @or_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: or_i8: + + ; ALL: or $2, $4, $5 + + %r = or i8 %a, %b + ret i8 %r +} + +define signext i16 @or_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: or_i16: + + ; ALL: or $2, $4, $5 + + %r = or i16 %a, %b + ret i16 %r +} + +define signext i32 @or_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: or_i32: + + ; ALL: or $2, $4, $5 + + %r = or i32 %a, %b + ret i32 %r +} + +define signext i64 @or_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: or_i64: + + ; GP32: or $2, $4, $6 + ; GP32: or $3, $5, $7 + + ; GP64: or $2, $4, $5 + + %r = or i64 %a, %b + ret i64 %r +} + +define signext i128 @or_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: or_i128: + + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: or $2, $4, $[[T2]] + ; GP32: or $3, $5, $[[T1]] + ; GP32: or $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: or $5, $7, $[[T3]] + + ; GP64: or $2, $4, $6 + ; GP64: or $3, $5, $7 + + %r = or i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/ret.ll b/test/CodeGen/Mips/llvm-ir/ret.ll index 8f5b115..0561c24 100644 --- a/test/CodeGen/Mips/llvm-ir/ret.ll +++ b/test/CodeGen/Mips/llvm-ir/ret.ll @@ -9,10 +9,14 @@ ; RUN: llc -march=mips -mcpu=mips32 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=NO-MTHC1 -check-prefix=NOT-R6 ; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 +; RUN: llc -march=mips -mcpu=mips32r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=NOT-R6 ; RUN: llc -march=mips -mcpu=mips32r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR32 -check-prefix=MTHC1 -check-prefix=R6 ; RUN: llc -march=mips64 -mcpu=mips4 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 ; RUN: llc -march=mips64 -mcpu=mips64 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 ; RUN: llc -march=mips64 -mcpu=mips64r2 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r3 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 +; RUN: llc -march=mips64 -mcpu=mips64r5 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=NOT-R6 ; RUN: llc -march=mips64 -mcpu=mips64r6 -asm-show-inst < %s | FileCheck %s -check-prefix=ALL -check-prefix=GPR64 -check-prefix=DMTC1 -check-prefix=R6 define void @ret_void() { diff --git a/test/CodeGen/Mips/llvm-ir/sdiv.ll b/test/CodeGen/Mips/llvm-ir/sdiv.ll new file mode 100644 index 0000000..929ee88 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/sdiv.ll @@ -0,0 +1,144 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=R2-R5 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=R6 -check-prefix=64R6 + +define signext i1 @sdiv_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: sdiv_i1: + + ; NOT-R6: div $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $[[T0:[0-9]+]] + ; FIXME: The sll/sra instructions are redundant since div is signed. + ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; NOT-R6: sra $2, $[[T1]], 31 + + ; R6: div $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; FIXME: The sll/sra instructions are redundant since div is signed. + ; R6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; R6: sra $2, $[[T1]], 31 + + %r = sdiv i1 %a, %b + ret i1 %r +} + +define signext i8 @sdiv_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: sdiv_i8: + + ; NOT-R2-R6: div $zero, $4, $5 + ; NOT-R2-R6: teq $5, $zero, 7 + ; NOT-R2-R6: mflo $[[T0:[0-9]+]] + ; FIXME: The sll/sra instructions are redundant since div is signed. + ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 + ; NOT-R2-R6: sra $2, $[[T1]], 24 + + ; R2-R5: div $zero, $4, $5 + ; R2-R5: teq $5, $zero, 7 + ; R2-R5: mflo $[[T0:[0-9]+]] + ; FIXME: This instruction is redundant. + ; R2-R5: seb $2, $[[T0]] + + ; R6: div $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; FIXME: This instruction is redundant. + ; R6: seb $2, $[[T0]] + + %r = sdiv i8 %a, %b + ret i8 %r +} + +define signext i16 @sdiv_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: sdiv_i16: + + ; NOT-R2-R6: div $zero, $4, $5 + ; NOT-R2-R6: teq $5, $zero, 7 + ; NOT-R2-R6: mflo $[[T0:[0-9]+]] + ; FIXME: The sll/sra instructions are redundant since div is signed. + ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 + ; NOT-R2-R6: sra $2, $[[T1]], 16 + + ; R2-R5: div $zero, $4, $5 + ; R2-R5: teq $5, $zero, 7 + ; R2-R5: mflo $[[T0:[0-9]+]] + ; FIXME: This is instruction is redundant since div is signed. + ; R2-R5: seh $2, $[[T0]] + + ; R6: div $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; FIXME: This is instruction is redundant since div is signed. + ; R6: seh $2, $[[T0]] + + %r = sdiv i16 %a, %b + ret i16 %r +} + +define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: sdiv_i32: + + ; NOT-R6: div $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: div $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = sdiv i32 %a, %b + ret i32 %r +} + +define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: sdiv_i64: + + ; GP32: lw $25, %call16(__divdi3)($gp) + + ; GP64-NOT-R6: ddiv $zero, $4, $5 + ; GP64-NOT-R6: teq $5, $zero, 7 + ; GP64-NOT-R6: mflo $2 + + ; 64R6: ddiv $2, $4, $5 + ; 64R6: teq $5, $zero, 7 + + %r = sdiv i64 %a, %b + ret i64 %r +} + +define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) { +entry: + ; ALL-LABEL: sdiv_i128: + + ; GP32: lw $25, %call16(__divti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__divti3)($gp) + ; 64R6: ld $25, %call16(__divti3)($gp) + + %r = sdiv i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/select.ll b/test/CodeGen/Mips/llvm-ir/select.ll new file mode 100644 index 0000000..f17670a --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/select.ll @@ -0,0 +1,712 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV \ +; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV \ +; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV \ +; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV \ +; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64 + +define signext i1 @tst_select_i1_i1(i1 signext %s, + i1 signext %x, i1 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i1: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i1 %x, i1 %y + ret i1 %r +} + +define signext i8 @tst_select_i1_i8(i1 signext %s, + i8 signext %x, i8 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i8: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i8 %x, i8 %y + ret i8 %r +} + +define signext i32 @tst_select_i1_i32(i1 signext %s, + i32 signext %x, i32 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i32: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2-M3: move $5, $6 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: move $2, $5 + + ; CMOV: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV: movn $6, $5, $[[T0]] + ; CMOV: move $2, $6 + + ; SEL: andi $[[T0:[0-9]+]], $4, 1 + ; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]] + ; SEL: or $2, $[[T2]], $[[T1]] + %r = select i1 %s, i32 %x, i32 %y + ret i32 %r +} + +define signext i64 @tst_select_i1_i64(i1 signext %s, + i64 signext %x, i64 signext %y) { +entry: + ; ALL-LABEL: tst_select_i1_i64: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T1:[0-9]+]], 16($sp) + ; M2: $[[BB0]]: + ; FIXME: This branch is redundant + ; M2: bnez $[[T0]], $[[BB1:BB[0-9_]+]] + ; M2: nop + ; M2: lw $[[T2:[0-9]+]], 20($sp) + ; M2: $[[BB1]]: + ; M2: move $2, $[[T1]] + ; M2: jr $ra + ; M2: move $3, $[[T2]] + + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: lw $2, 16($sp) + ; CMOV-32: movn $2, $6, $[[T0]] + ; CMOV-32: lw $3, 20($sp) + ; CMOV-32: movn $3, $7, $[[T0]] + + ; SEL-32: andi $[[T0:[0-9]+]], $4, 1 + ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-32: lw $[[T2:[0-9]+]], 16($sp) + ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] + ; SEL-32: or $2, $[[T1]], $[[T3]] + ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]] + ; SEL-32: lw $[[T5:[0-9]+]], 20($sp) + ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]] + ; SEL-32: or $3, $[[T4]], $[[T6]] + + ; M3: andi $[[T0:[0-9]+]], $4, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: move $5, $6 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: move $2, $5 + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn $6, $5, $[[T0]] + ; CMOV-64: move $2, $6 + + ; SEL-64: andi $[[T0:[0-9]+]], $4, 1 + ; FIXME: This shift is redundant + ; SEL-64: sll $[[T0]], $[[T0]], 0 + ; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]] + ; SEL-64: selnez $[[T0]], $5, $[[T0]] + ; SEL-64: or $2, $[[T0]], $[[T1]] + %r = select i1 %s, i64 %x, i64 %y + ret i64 %r +} + +define float @tst_select_i1_float(i1 signext %s, float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_i1_float: + + ; M2-M3: andi $[[T0:[0-9]+]], $4, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: jr $ra + ; M2: mtc1 $6, $f0 + ; M3: mov.s $f13, $f14 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2: mtc1 $5, $f0 + ; M3: mov.s $f0, $f13 + + ; CMOV-32: mtc1 $6, $f0 + ; CMOV-32: mtc1 $5, $f1 + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: movn.s $f0, $f1, $[[T0]] + + ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] + ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]] + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.s $f0, $[[F1]], $[[F0]] + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.s $f14, $f13, $[[T0]] + ; CMOV-64: mov.s $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.s $f0, $f14, $f13 + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_i1_float_reordered(float %x, float %y, + i1 signext %s) { +entry: + ; ALL-LABEL: tst_select_i1_float_reordered: + + ; M2-M3: andi $[[T0:[0-9]+]], $6, 1 + ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-32: movn.s $f14, $f12, $[[T0]] + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: mtc1 $6, $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-64: movn.s $f13, $f12, $[[T0]] + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: mtc1 $6, $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + %r = select i1 %s, float %x, float %y + ret float %r +} + +define double @tst_select_i1_double(i1 signext %s, double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_i1_double: + + ; M2: andi $[[T0:[0-9]+]], $4, 1 + ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: ldc1 $f0, 16($sp) + ; M2: jr $ra + ; M2: nop + ; M2: $[[BB0]]: + ; M2: mtc1 $7, $f0 + ; M2: jr $ra + ; M2: mtc1 $6, $f1 + + ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]] + ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}} + ; CMOV-32R2-R5: mthc1 $6, $[[F0]] + ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: ldc1 $f0, 16($sp) + ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]] + + ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]] + ; SEL-32: mthc1 $6, $[[F0]] + ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp) + ; SEL-32: mtc1 $4, $f0 + ; SEL-32: sel.d $f0, $[[F1]], $[[F0]] + + ; M3: andi $[[T0:[0-9]+]], $4, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: mov.d $f13, $f14 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: mov.d $f0, $f13 + + ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-64: movn.d $f14, $f13, $[[T0]] + ; CMOV-64: mov.d $f0, $f14 + + ; SEL-64: mtc1 $4, $f0 + ; SEL-64: sel.d $f0, $f14, $f13 + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_i1_double_reordered(double %x, double %y, + i1 signext %s) { +entry: + ; ALL-LABEL: tst_select_i1_double_reordered: + + ; M2: lw $[[T0:[0-9]+]], 16($sp) + ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: nop + ; M2: mov.d $f12, $f14 + ; M2: $[[BB0]]: + ; M2: jr $ra + ; M2: mov.d $f0, $f12 + + ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp) + ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1 + ; CMOV-32: movn.d $f14, $f12, $[[T1]] + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: lw $[[T0:[0-9]+]], 16($sp) + ; SEL-32: mtc1 $[[T0]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; M3: andi $[[T0:[0-9]+]], $6, 1 + ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]] + ; M3: nop + ; M3: mov.d $f12, $f13 + ; M3: $[[BB0]]: + ; M3: jr $ra + ; M3: mov.d $f0, $f12 + + ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1 + ; CMOV-64: movn.d $f13, $f12, $[[T0]] + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: mtc1 $6, $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + %r = select i1 %s, double %x, double %y + ret double %r +} + +define float @tst_select_fcmp_olt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_float: + + ; M2: c.olt.s $f12, $f14 + ; M3: c.olt.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.olt.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.olt.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp olt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ole_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_float: + + ; M2: c.ole.s $f12, $f14 + ; M3: c.ole.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ole.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ole.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp ole float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_ogt_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_float: + + ; M2: c.ule.s $f12, $f14 + ; M3: c.ule.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ule.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.lt.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ule.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.lt.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp ogt float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oge_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_float: + + ; M2: c.ult.s $f12, $f14 + ; M3: c.ult.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ult.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.le.s $f0, $f14, $f12 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ult.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.le.s $f0, $f13, $f12 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp oge float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_oeq_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_float: + + ; M2: c.eq.s $f12, $f14 + ; M3: c.eq.s $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.eq.s $f12, $f14 + ; CMOV-32: movt.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.eq.s $f0, $f12, $f14 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.eq.s $f12, $f13 + ; CMOV-64: movt.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.eq.s $f0, $f12, $f13 + ; SEL-64: sel.s $f0, $f13, $f12 + %s = fcmp oeq float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define float @tst_select_fcmp_one_float(float %x, float %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_float: + + ; M2: c.ueq.s $f12, $f14 + ; M3: c.ueq.s $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.s $f12, $f14 + ; M3: mov.s $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.s $f0, $f12 + + ; CMOV-32: c.ueq.s $f12, $f14 + ; CMOV-32: movf.s $f14, $f12, $fcc0 + ; CMOV-32: mov.s $f0, $f14 + + ; SEL-32: cmp.ueq.s $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.s $f0, $f14, $f12 + + ; CMOV-64: c.ueq.s $f12, $f13 + ; CMOV-64: movf.s $f13, $f12, $fcc0 + ; CMOV-64: mov.s $f0, $f13 + + ; SEL-64: cmp.ueq.s $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.s $f0, $f13, $f12 + + %s = fcmp one float %x, %y + %r = select i1 %s, float %x, float %y + ret float %r +} + +define double @tst_select_fcmp_olt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_olt_double: + + ; M2: c.olt.d $f12, $f14 + ; M3: c.olt.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.olt.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.olt.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp olt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ole_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ole_double: + + ; M2: c.ole.d $f12, $f14 + ; M3: c.ole.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ole.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ole.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp ole double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_ogt_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_ogt_double: + + ; M2: c.ule.d $f12, $f14 + ; M3: c.ule.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ule.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.lt.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ule.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.lt.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp ogt double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oge_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oge_double: + + ; M2: c.ult.d $f12, $f14 + ; M3: c.ult.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ult.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.le.d $f0, $f14, $f12 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ult.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.le.d $f0, $f13, $f12 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp oge double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_oeq_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_oeq_double: + + ; M2: c.eq.d $f12, $f14 + ; M3: c.eq.d $f12, $f13 + ; M2-M3: bc1t $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.eq.d $f12, $f14 + ; CMOV-32: movt.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.eq.d $f0, $f12, $f14 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.eq.d $f12, $f13 + ; CMOV-64: movt.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.eq.d $f0, $f12, $f13 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp oeq double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} + +define double @tst_select_fcmp_one_double(double %x, double %y) { +entry: + ; ALL-LABEL: tst_select_fcmp_one_double: + + ; M2: c.ueq.d $f12, $f14 + ; M3: c.ueq.d $f12, $f13 + ; M2-M3: bc1f $[[BB0:BB[0-9_]+]] + ; M2-M3: nop + ; M2: mov.d $f12, $f14 + ; M3: mov.d $f12, $f13 + ; M2-M3: $[[BB0]]: + ; M2-M3: jr $ra + ; M2-M3: mov.d $f0, $f12 + + ; CMOV-32: c.ueq.d $f12, $f14 + ; CMOV-32: movf.d $f14, $f12, $fcc0 + ; CMOV-32: mov.d $f0, $f14 + + ; SEL-32: cmp.ueq.d $f0, $f12, $f14 + ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: not $[[T0]], $[[T0]] + ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-32: sel.d $f0, $f14, $f12 + + ; CMOV-64: c.ueq.d $f12, $f13 + ; CMOV-64: movf.d $f13, $f12, $fcc0 + ; CMOV-64: mov.d $f0, $f13 + + ; SEL-64: cmp.ueq.d $f0, $f12, $f13 + ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: not $[[T0]], $[[T0]] + ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0 + ; SEL-64: sel.d $f0, $f13, $f12 + %s = fcmp one double %x, %y + %r = select i1 %s, double %x, double %y + ret double %r +} diff --git a/test/CodeGen/Mips/llvm-ir/shl.ll b/test/CodeGen/Mips/llvm-ir/shl.ll new file mode 100644 index 0000000..6640320 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/shl.ll @@ -0,0 +1,200 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=M2 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 -check-prefix=NOT-R2-R6 \ +; RUN: -check-prefix=32R1-R5 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R1-R5 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 \ +; RUN: -check-prefix=32R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=M3 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 \ +; RUN: -check-prefix=64R6 -check-prefix=R2-R6 + +define signext i1 @shl_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: shl_i1: + + ; ALL: move $2, $4 + + %r = shl i1 %a, %b + ret i1 %r +} + +define signext i8 @shl_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: shl_i8: + + ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 + ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 24 + ; NOT-R2-R6: sra $2, $[[T2]], 24 + + ; R2-R6: andi $[[T0:[0-9]+]], $5, 255 + ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; R2-R6: seb $2, $[[T1]] + + %r = shl i8 %a, %b + ret i8 %r +} + +define signext i16 @shl_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: shl_i16: + + ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 + ; NOT-R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; NOT-R2-R6: sll $[[T2:[0-9]+]], $[[T1]], 16 + ; NOT-R2-R6: sra $2, $[[T2]], 16 + + ; R2-R6: andi $[[T0:[0-9]+]], $5, 65535 + ; R2-R6: sllv $[[T1:[0-9]+]], $4, $[[T0]] + ; R2-R6: seh $2, $[[T1]] + + %r = shl i16 %a, %b + ret i16 %r +} + +define signext i32 @shl_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: shl_i32: + + ; ALL: sllv $2, $4, $5 + + %r = shl i32 %a, %b + ret i32 %r +} + +define signext i64 @shl_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: shl_i64: + + ; M2: sllv $[[T0:[0-9]+]], $5, $7 + ; M2: andi $[[T1:[0-9]+]], $7, 32 + ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]] + ; M2: move $2, $[[T0]] + ; M2: sllv $[[T2:[0-9]+]], $4, $7 + ; M2: not $[[T3:[0-9]+]], $7 + ; M2: srl $[[T4:[0-9]+]], $5, 1 + ; M2: srlv $[[T5:[0-9]+]], $[[T4]], $[[T3]] + ; M2: or $2, $[[T2]], $[[T3]] + ; M2: $[[BB0]]: + ; M2: bnez $[[T1]], $[[BB1:BB[0-9_]+]] + ; M2: addiu $3, $zero, 0 + ; M2: move $3, $[[T0]] + ; M2: $[[BB1]]: + ; M2: jr $ra + ; M2: nop + + ; 32R1-R5: sllv $[[T0:[0-9]+]], $4, $7 + ; 32R1-R5: not $[[T1:[0-9]+]], $7 + ; 32R1-R5: srl $[[T2:[0-9]+]], $5, 1 + ; 32R1-R5: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R1-R5: or $2, $[[T0]], $[[T3]] + ; 32R1-R5: sllv $[[T4:[0-9]+]], $5, $7 + ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32 + ; 32R1-R5: movn $2, $[[T4]], $[[T5]] + ; 32R1-R5: jr $ra + ; 32R1-R5: movn $3, $zero, $[[T5]] + + ; 32R6: sllv $[[T0:[0-9]+]], $4, $7 + ; 32R6: not $[[T1:[0-9]+]], $7 + ; 32R6: srl $[[T2:[0-9]+]], $5, 1 + ; 32R6: srlv $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 32R6: or $[[T4:[0-9]+]], $[[T0]], $[[T3]] + ; 32R6: andi $[[T5:[0-9]+]], $7, 32 + ; 32R6: seleqz $[[T6:[0-9]+]], $[[T4]], $[[T2]] + ; 32R6: sllv $[[T7:[0-9]+]], $5, $7 + ; 32R6: selnez $[[T8:[0-9]+]], $[[T7]], $[[T5]] + ; 32R6: or $2, $[[T8]], $[[T6]] + ; 32R6: jr $ra + ; 32R6: seleqz $3, $[[T7]], $[[T5]] + + ; GP64: sll $[[T0:[0-9]+]], $5, 0 + ; GP64: dsllv $2, $4, $1 + + %r = shl i64 %a, %b + ret i64 %r +} + +define signext i128 @shl_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: shl_i128: + + ; GP32: lw $25, %call16(__ashlti3)($gp) + + ; M3: sll $[[T0:[0-9]+]], $7, 0 + ; M3: dsllv $[[T1:[0-9]+]], $5, $[[T0]] + ; M3: andi $[[T2:[0-9]+]], $[[T0]], 32 + ; M3: bnez $[[T3:[0-9]+]], $[[BB0:BB[0-9_]+]] + ; M3: move $2, $[[T1]] + ; M3: dsllv $[[T4:[0-9]+]], $4, $[[T0]] + ; M3: dsrl $[[T5:[0-9]+]], $5, 1 + ; M3: not $[[T6:[0-9]+]], $[[T0]] + ; M3: dsrlv $[[T7:[0-9]+]], $[[T5]], $[[T6]] + ; M3: or $2, $[[T4]], $[[T7]] + ; M3: $[[BB0]]: + ; M3: bnez $[[T3]], $[[BB1:BB[0-9_]+]] + ; M3: daddiu $3, $zero, 0 + ; M3: move $3, $[[T1]] + ; M3: $[[BB1]]: + ; M3: jr $ra + ; M3: nop + + ; GP64-NOT-R6: sll $[[T0:[0-9]+]], $7, 0 + ; GP64-NOT-R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] + ; GP64-NOT-R6: dsrl $[[T2:[0-9]+]], $5, 1 + ; GP64-NOT-R6: not $[[T3:[0-9]+]], $[[T0]] + ; GP64-NOT-R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; GP64-NOT-R6: or $2, $[[T1]], $[[T4]] + ; GP64-NOT-R6: dsllv $3, $5, $[[T0]] + ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T0]], 32 + ; GP64-NOT-R6: movn $2, $3, $[[T5]] + ; GP64-NOT-R6: jr $ra + ; GP64-NOT-R6: movn $3, $zero, $1 + + ; 64R6: sll $[[T0:[0-9]+]], $7, 0 + ; 64R6: dsllv $[[T1:[0-9]+]], $4, $[[T0]] + ; 64R6: dsrl $[[T2:[0-9]+]], $5, 1 + ; 64R6: not $[[T3:[0-9]+]], $[[T0]] + ; 64R6: dsrlv $[[T4:[0-9]+]], $[[T2]], $[[T3]] + ; 64R6: or $[[T5:[0-9]+]], $[[T1]], $[[T4]] + ; 64R6: andi $[[T6:[0-9]+]], $[[T0]], 32 + ; 64R6: sll $[[T7:[0-9]+]], $[[T6]], 0 + ; 64R6: seleqz $[[T8:[0-9]+]], $[[T5]], $[[T7]] + ; 64R6: dsllv $[[T9:[0-9]+]], $5, $[[T0]] + ; 64R6: selnez $[[T10:[0-9]+]], $[[T9]], $[[T7]] + ; 64R6: or $2, $[[T10]], $[[T8]] + ; 64R6: jr $ra + ; 64R6: seleqz $3, $[[T0]], $[[T7]] + + %r = shl i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/srem.ll b/test/CodeGen/Mips/llvm-ir/srem.ll new file mode 100644 index 0000000..ceb53ee --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/srem.ll @@ -0,0 +1,139 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 + +define signext i1 @srem_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: srem_i1: + + ; NOT-R6: div $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mfhi $[[T0:[0-9]+]] + ; NOT-R6: sll $[[T1:[0-9]+]], $[[T0]], 31 + ; NOT-R6: sra $2, $[[T1]], 31 + + ; R6: mod $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; R6: sll $[[T3:[0-9]+]], $[[T0]], 31 + ; R6: sra $2, $[[T3]], 31 + + %r = srem i1 %a, %b + ret i1 %r +} + +define signext i8 @srem_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: srem_i8: + + ; NOT-R2-R6: div $zero, $4, $5 + ; NOT-R2-R6: teq $5, $zero, 7 + ; NOT-R2-R6: mfhi $[[T0:[0-9]+]] + ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 24 + ; NOT-R2-R6: sra $2, $[[T1]], 24 + + ; R2-R5: div $zero, $4, $5 + ; R2-R5: teq $5, $zero, 7 + ; R2-R5: mfhi $[[T0:[0-9]+]] + ; R2-R5: seb $2, $[[T0]] + + ; R6: mod $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; R6: seb $2, $[[T0]] + + %r = srem i8 %a, %b + ret i8 %r +} + +define signext i16 @srem_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: srem_i16: + + ; NOT-R2-R6: div $zero, $4, $5 + ; NOT-R2-R6: teq $5, $zero, 7 + ; NOT-R2-R6: mfhi $[[T0:[0-9]+]] + ; NOT-R2-R6: sll $[[T1:[0-9]+]], $[[T0]], 16 + ; NOT-R2-R6: sra $2, $[[T1]], 16 + + ; R2-R5: div $zero, $4, $5 + ; R2-R5: teq $5, $zero, 7 + ; R2-R5: mfhi $[[T0:[0-9]+]] + ; R2-R5: seh $2, $[[T1]] + + ; R6: mod $[[T0:[0-9]+]], $4, $5 + ; R6: teq $5, $zero, 7 + ; R6: seh $2, $[[T0]] + + %r = srem i16 %a, %b + ret i16 %r +} + +define signext i32 @srem_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: srem_i32: + + ; NOT-R6: div $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mfhi $2 + + ; R6: mod $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = srem i32 %a, %b + ret i32 %r +} + +define signext i64 @srem_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: srem_i64: + + ; GP32: lw $25, %call16(__moddi3)($gp) + + ; GP64-NOT-R6: ddiv $zero, $4, $5 + ; GP64-NOT-R6: teq $5, $zero, 7 + ; GP64-NOT-R6: mfhi $2 + + ; 64R6: dmod $2, $4, $5 + ; 64R6: teq $5, $zero, 7 + + %r = srem i64 %a, %b + ret i64 %r +} + +define signext i128 @srem_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: srem_i128: + + ; GP32: lw $25, %call16(__modti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__modti3)($gp) + ; 64-R6: ld $25, %call16(__modti3)($gp) + + %r = srem i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/sub.ll b/test/CodeGen/Mips/llvm-ir/sub.ll new file mode 100644 index 0000000..1649758 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/sub.ll @@ -0,0 +1,122 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=NOT-R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=R2-R6 -check-prefix=GP64 + +define signext i1 @sub_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: sub_i1: + + ; ALL: subu $[[T0:[0-9]+]], $4, $5 + ; ALL: sll $[[T0]], $[[T0]], 31 + ; ALL: sra $2, $[[T0]], 31 + + %r = sub i1 %a, %b + ret i1 %r +} + +define signext i8 @sub_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: sub_i8: + + ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 24 + ; NOT-R2-R6: sra $2, $[[T0]], 24 + + ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seb $2, $[[T0:[0-9]+]] + + %r = sub i8 %a, %b + ret i8 %r +} + +define signext i16 @sub_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: sub_i16: + + ; NOT-R2-R6: subu $[[T0:[0-9]+]], $4, $5 + ; NOT-R2-R6: sll $[[T0]], $[[T0]], 16 + ; NOT-R2-R6: sra $2, $[[T0]], 16 + + ; R2-R6: subu $[[T0:[0-9]+]], $4, $5 + ; R2-R6: seh $2, $[[T0:[0-9]+]] + + %r = sub i16 %a, %b + ret i16 %r +} + +define signext i32 @sub_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: sub_i32: + + ; ALL: subu $2, $4, $5 + + %r = sub i32 %a, %b + ret i32 %r +} + +define signext i64 @sub_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: sub_i64: + + ; GP32: subu $3, $5, $7 + ; GP32: sltu $[[T0:[0-9]+]], $5, $7 + ; GP32: addu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP32: subu $2, $4, $[[T1]] + + ; GP64: dsubu $2, $4, $5 + + %r = sub i64 %a, %b + ret i64 %r +} + +define signext i128 @sub_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: sub_i128: + + ; GP32: lw $[[T0:[0-9]+]], 20($sp) + ; GP32: sltu $[[T1:[0-9]+]], $5, $[[T0]] + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: addu $[[T3:[0-9]+]], $[[T1]], $[[T2]] + ; GP32: lw $[[T4:[0-9]+]], 24($sp) + ; GP32: lw $[[T5:[0-9]+]], 28($sp) + ; GP32: subu $[[T6:[0-9]+]], $7, $[[T5]] + ; GP32: subu $2, $4, $[[T3]] + ; GP32: sltu $[[T8:[0-9]+]], $6, $[[T4]] + ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T0]] + ; GP32: subu $3, $5, $[[T9]] + ; GP32: sltu $[[T10:[0-9]+]], $7, $[[T5]] + ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T4]] + ; GP32: subu $4, $6, $[[T11]] + ; GP32: move $5, $[[T6]] + + ; GP64: dsubu $3, $5, $7 + ; GP64: sltu $[[T0:[0-9]+]], $5, $7 + ; GP64: daddu $[[T1:[0-9]+]], $[[T0]], $6 + ; GP64: dsubu $2, $4, $[[T1]] + + %r = sub i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/udiv.ll b/test/CodeGen/Mips/llvm-ir/udiv.ll new file mode 100644 index 0000000..a7cafe5 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/udiv.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=R6 -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=NOT-R6 -check-prefix=GP64-NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=R6 -check-prefix=64R6 + +define zeroext i1 @udiv_i1(i1 zeroext %a, i1 zeroext %b) { +entry: +; ALL-LABEL: udiv_i1: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i1 %a, %b + ret i1 %r +} + +define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) { +entry: +; ALL-LABEL: udiv_i8: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i8 %a, %b + ret i8 %r +} + +define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) { +entry: +; ALL-LABEL: udiv_i16: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i16 %a, %b + ret i16 %r +} + +define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: udiv_i32: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mflo $2 + + ; R6: divu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = udiv i32 %a, %b + ret i32 %r +} + +define signext i64 @udiv_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: udiv_i64: + + ; GP32: lw $25, %call16(__udivdi3)($gp) + + ; GP64-NOT-R6: ddivu $zero, $4, $5 + ; GP64-NOT-R6: teq $5, $zero, 7 + ; GP64-NOT-R6: mflo $2 + + ; 64R6: ddivu $2, $4, $5 + ; 64R6: teq $5, $zero, 7 + + %r = udiv i64 %a, %b + ret i64 %r +} + +define signext i128 @udiv_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: udiv_i128: + + ; GP32: lw $25, %call16(__udivti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__udivti3)($gp) + ; 64-R6: ld $25, %call16(__udivti3)($gp) + + %r = udiv i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/urem.ll b/test/CodeGen/Mips/llvm-ir/urem.ll new file mode 100644 index 0000000..d5a231c --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/urem.ll @@ -0,0 +1,155 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s -check-prefix=GP32 \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s -check-prefix=GP32 \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s -check-prefix=GP32 \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=GP32 -check-prefix=R6 -check-prefix=R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 -check-prefix=NOT-R2-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=R2-R5 -check-prefix=R2-R6 \ +; RUN: -check-prefix=GP64-NOT-R6 -check-prefix=NOT-R6 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=64R6 -check-prefix=R6 -check-prefix=R2-R6 + +define signext i1 @urem_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: urem_i1: + + ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1 + ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1 + ; NOT-R6: divu $zero, $[[T1]], $[[T0]] + ; NOT-R6: teq $[[T0]], $zero, 7 + ; NOT-R6: mfhi $[[T2:[0-9]+]] + ; NOT-R6: sll $[[T3:[0-9]+]], $[[T2]], 31 + ; NOT-R6: sra $2, $[[T3]], 31 + + ; R6: andi $[[T0:[0-9]+]], $5, 1 + ; R6: andi $[[T1:[0-9]+]], $4, 1 + ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; R6: teq $[[T0]], $zero, 7 + ; R6: sll $[[T3:[0-9]+]], $[[T2]], 31 + ; R6: sra $2, $[[T3]], 31 + + %r = urem i1 %a, %b + ret i1 %r +} + +define signext i8 @urem_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: urem_i8: + + ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255 + ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255 + ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] + ; NOT-R2-R6: teq $[[T0]], $zero, 7 + ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] + ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 24 + ; NOT-R2-R6: sra $2, $[[T3]], 24 + + ; R2-R5: andi $[[T0:[0-9]+]], $5, 255 + ; R2-R5: andi $[[T1:[0-9]+]], $4, 255 + ; R2-R5: divu $zero, $[[T1]], $[[T0]] + ; R2-R5: teq $[[T0]], $zero, 7 + ; R2-R5: mfhi $[[T2:[0-9]+]] + ; R2-R5: seb $2, $[[T2]] + + ; R6: andi $[[T0:[0-9]+]], $5, 255 + ; R6: andi $[[T1:[0-9]+]], $4, 255 + ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; R6: teq $[[T0]], $zero, 7 + ; R6: seb $2, $[[T2]] + + %r = urem i8 %a, %b + ret i8 %r +} + +define signext i16 @urem_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: urem_i16: + + ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535 + ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 65535 + ; NOT-R2-R6: divu $zero, $[[T1]], $[[T0]] + ; NOT-R2-R6: teq $[[T0]], $zero, 7 + ; NOT-R2-R6: mfhi $[[T2:[0-9]+]] + ; NOT-R2-R6: sll $[[T3:[0-9]+]], $[[T2]], 16 + ; NOT-R2-R6: sra $2, $[[T3]], 16 + + ; R2-R5: andi $[[T0:[0-9]+]], $5, 65535 + ; R2-R5: andi $[[T1:[0-9]+]], $4, 65535 + ; R2-R5: divu $zero, $[[T1]], $[[T0]] + ; R2-R5: teq $[[T0]], $zero, 7 + ; R2-R5: mfhi $[[T3:[0-9]+]] + ; R2-R5: seh $2, $[[T2]] + + ; R6: andi $[[T0:[0-9]+]], $5, 65535 + ; R6: andi $[[T1:[0-9]+]], $4, 65535 + ; R6: modu $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; R6: teq $[[T0]], $zero, 7 + ; R6: seh $2, $[[T2]] + + %r = urem i16 %a, %b + ret i16 %r +} + +define signext i32 @urem_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: urem_i32: + + ; NOT-R6: divu $zero, $4, $5 + ; NOT-R6: teq $5, $zero, 7 + ; NOT-R6: mfhi $2 + + ; R6: modu $2, $4, $5 + ; R6: teq $5, $zero, 7 + + %r = urem i32 %a, %b + ret i32 %r +} + +define signext i64 @urem_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: urem_i64: + + ; GP32: lw $25, %call16(__umoddi3)($gp) + + ; GP64-NOT-R6: ddivu $zero, $4, $5 + ; GP64-NOT-R6: teq $5, $zero, 7 + ; GP64-NOT-R6: mfhi $2 + + ; 64R6: dmodu $2, $4, $5 + ; 64R6: teq $5, $zero, 7 + + %r = urem i64 %a, %b + ret i64 %r +} + +define signext i128 @urem_i128(i128 signext %a, i128 signext %b) { +entry: + ; ALL-LABEL: urem_i128: + + ; GP32: lw $25, %call16(__umodti3)($gp) + + ; GP64-NOT-R6: ld $25, %call16(__umodti3)($gp) + ; 64-R6: ld $25, %call16(__umodti3)($gp) + + %r = urem i128 %a, %b + ret i128 %r +} diff --git a/test/CodeGen/Mips/llvm-ir/xor.ll b/test/CodeGen/Mips/llvm-ir/xor.ll new file mode 100644 index 0000000..89af9998 --- /dev/null +++ b/test/CodeGen/Mips/llvm-ir/xor.ll @@ -0,0 +1,99 @@ +; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP32 +; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 +; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \ +; RUN: -check-prefix=ALL -check-prefix=GP64 + +define signext i1 @xor_i1(i1 signext %a, i1 signext %b) { +entry: +; ALL-LABEL: xor_i1: + + ; ALL: xor $2, $4, $5 + + %r = xor i1 %a, %b + ret i1 %r +} + +define signext i8 @xor_i8(i8 signext %a, i8 signext %b) { +entry: +; ALL-LABEL: xor_i8: + + ; ALL: xor $2, $4, $5 + + %r = xor i8 %a, %b + ret i8 %r +} + +define signext i16 @xor_i16(i16 signext %a, i16 signext %b) { +entry: +; ALL-LABEL: xor_i16: + + ; ALL: xor $2, $4, $5 + + %r = xor i16 %a, %b + ret i16 %r +} + +define signext i32 @xor_i32(i32 signext %a, i32 signext %b) { +entry: +; ALL-LABEL: xor_i32: + + ; ALL: xor $2, $4, $5 + + %r = xor i32 %a, %b + ret i32 %r +} + +define signext i64 @xor_i64(i64 signext %a, i64 signext %b) { +entry: +; ALL-LABEL: xor_i64: + + ; GP32: xor $2, $4, $6 + ; GP32: xor $3, $5, $7 + + ; GP64: xor $2, $4, $5 + + %r = xor i64 %a, %b + ret i64 %r +} + +define signext i128 @xor_i128(i128 signext %a, i128 signext %b) { +entry: +; ALL-LABEL: xor_i128: + + ; GP32: lw $[[T0:[0-9]+]], 24($sp) + ; GP32: lw $[[T1:[0-9]+]], 20($sp) + ; GP32: lw $[[T2:[0-9]+]], 16($sp) + ; GP32: xor $2, $4, $[[T2]] + ; GP32: xor $3, $5, $[[T1]] + ; GP32: xor $4, $6, $[[T0]] + ; GP32: lw $[[T3:[0-9]+]], 28($sp) + ; GP32: xor $5, $7, $[[T3]] + + ; GP64: xor $2, $4, $6 + ; GP64: xor $3, $5, $7 + + %r = xor i128 %a, %b + ret i128 %r +} |