diff options
Diffstat (limited to 'test/CodeGen/Mips/msa/2r_vector_scalar.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/2r_vector_scalar.ll | 69 |
1 files changed, 41 insertions, 28 deletions
diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll index 6f6e1b9..64e459e 100644 --- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll +++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll @@ -1,8 +1,14 @@ ; Test the MSA intrinsics that are encoded with the 2R instruction format and ; convert scalars to vectors. -; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s -; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s +; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 +; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS32 +; RUN: llc -march=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 +; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=+msa,+fp64 < %s | \ +; RUN: FileCheck %s -check-prefix=MIPS-ANY -check-prefix=MIPS64 @llvm_mips_fill_b_ARG1 = global i32 23, align 16 @llvm_mips_fill_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16 @@ -17,11 +23,12 @@ entry: declare <16 x i8> @llvm.mips.fill.b(i32) nounwind -; CHECK: llvm_mips_fill_b_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], -; CHECK-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]] -; CHECK-DAG: st.b [[R2]], -; CHECK: .size llvm_mips_fill_b_test +; MIPS-ANY: llvm_mips_fill_b_test: +; MIPS32-DAG: lw [[R1:\$[0-9]+]], +; MIPS64-DAG: ld [[R1:\$[0-9]+]], +; MIPS-ANY-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]] +; MIPS-ANY-DAG: st.b [[R2]], +; MIPS-ANY: .size llvm_mips_fill_b_test ; @llvm_mips_fill_h_ARG1 = global i32 23, align 16 @llvm_mips_fill_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16 @@ -36,11 +43,12 @@ entry: declare <8 x i16> @llvm.mips.fill.h(i32) nounwind -; CHECK: llvm_mips_fill_h_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], -; CHECK-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]] -; CHECK-DAG: st.h [[R2]], -; CHECK: .size llvm_mips_fill_h_test +; MIPS-ANY: llvm_mips_fill_h_test: +; MIPS32-DAG: lw [[R1:\$[0-9]+]], +; MIPS64-DAG: ld [[R1:\$[0-9]+]], +; MIPS-ANY-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]] +; MIPS-ANY-DAG: st.h [[R2]], +; MIPS-ANY: .size llvm_mips_fill_h_test ; @llvm_mips_fill_w_ARG1 = global i32 23, align 16 @llvm_mips_fill_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16 @@ -55,11 +63,12 @@ entry: declare <4 x i32> @llvm.mips.fill.w(i32) nounwind -; CHECK: llvm_mips_fill_w_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], -; CHECK-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]] -; CHECK-DAG: st.w [[R2]], -; CHECK: .size llvm_mips_fill_w_test +; MIPS-ANY: llvm_mips_fill_w_test: +; MIPS32-DAG: lw [[R1:\$[0-9]+]], +; MIPS64-DAG: ld [[R1:\$[0-9]+]], +; MIPS-ANY-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]] +; MIPS-ANY-DAG: st.w [[R2]], +; MIPS-ANY: .size llvm_mips_fill_w_test ; @llvm_mips_fill_d_ARG1 = global i64 23, align 16 @llvm_mips_fill_d_RES = global <2 x i64> <i64 0, i64 0>, align 16 @@ -74,14 +83,18 @@ entry: declare <2 x i64> @llvm.mips.fill.d(i64) nounwind -; CHECK: llvm_mips_fill_d_test: -; CHECK-DAG: lw [[R1:\$[0-9]+]], 0( -; CHECK-DAG: lw [[R2:\$[0-9]+]], 4( -; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 0 -; CHECK-DAG: insert.w [[R3]][0], [[R1]] -; CHECK-DAG: insert.w [[R3]][1], [[R2]] -; CHECK-DAG: insert.w [[R3]][2], [[R1]] -; CHECK-DAG: insert.w [[R3]][3], [[R2]] -; CHECK-DAG: st.w [[R3]], -; CHECK: .size llvm_mips_fill_d_test -; +; MIPS-ANY: llvm_mips_fill_d_test: +; MIPS32-DAG: lw [[R1:\$[0-9]+]], 0( +; MIPS32-DAG: lw [[R2:\$[0-9]+]], 4( +; MIPS64-DAG: ld [[R1:\$[0-9]+]], %got_disp(llvm_mips_fill_d_ARG1) +; MIPS32-DAG: ldi.b [[R3:\$w[0-9]+]], 0 +; MIPS32-DAG: insert.w [[R3]][0], [[R1]] +; MIPS32-DAG: insert.w [[R3]][1], [[R2]] +; MIPS32-DAG: insert.w [[R3]][2], [[R1]] +; MIPS32-DAG: insert.w [[R3]][3], [[R2]] +; MIPS64-DAG: fill.d [[WD:\$w[0-9]+]], [[R1]] +; MIPS32-DAG: st.w [[R3]], +; MIPS64-DAG: ld [[RD:\$[0-9]+]], %got_disp(llvm_mips_fill_d_RES) +; MIPS64-DAG: st.d [[WD]], 0([[RD]]) +; MIPS-ANY: .size llvm_mips_fill_d_test +;
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