diff options
Diffstat (limited to 'test/CodeGen/Mips/msa/2rf_int_float.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/2rf_int_float.ll | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/test/CodeGen/Mips/msa/2rf_int_float.ll b/test/CodeGen/Mips/msa/2rf_int_float.ll index 4665ae0..77d1404 100644 --- a/test/CodeGen/Mips/msa/2rf_int_float.ll +++ b/test/CodeGen/Mips/msa/2rf_int_float.ll @@ -10,7 +10,7 @@ define void @llvm_mips_fclass_w_test() nounwind { entry: - %0 = load <4 x float>* @llvm_mips_fclass_w_ARG1 + %0 = load <4 x float>, <4 x float>* @llvm_mips_fclass_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.fclass.w(<4 x float> %0) store <4 x i32> %1, <4 x i32>* @llvm_mips_fclass_w_RES ret void @@ -31,7 +31,7 @@ declare <4 x i32> @llvm.mips.fclass.w(<4 x float>) nounwind define void @llvm_mips_fclass_d_test() nounwind { entry: - %0 = load <2 x double>* @llvm_mips_fclass_d_ARG1 + %0 = load <2 x double>, <2 x double>* @llvm_mips_fclass_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.fclass.d(<2 x double> %0) store <2 x i64> %1, <2 x i64>* @llvm_mips_fclass_d_RES ret void @@ -52,7 +52,7 @@ declare <2 x i64> @llvm.mips.fclass.d(<2 x double>) nounwind define void @llvm_mips_ftrunc_s_w_test() nounwind { entry: - %0 = load <4 x float>* @llvm_mips_ftrunc_s_w_ARG1 + %0 = load <4 x float>, <4 x float>* @llvm_mips_ftrunc_s_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float> %0) store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_s_w_RES ret void @@ -73,7 +73,7 @@ declare <4 x i32> @llvm.mips.ftrunc.s.w(<4 x float>) nounwind define void @llvm_mips_ftrunc_s_d_test() nounwind { entry: - %0 = load <2 x double>* @llvm_mips_ftrunc_s_d_ARG1 + %0 = load <2 x double>, <2 x double>* @llvm_mips_ftrunc_s_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double> %0) store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_s_d_RES ret void @@ -94,7 +94,7 @@ declare <2 x i64> @llvm.mips.ftrunc.s.d(<2 x double>) nounwind define void @llvm_mips_ftrunc_u_w_test() nounwind { entry: - %0 = load <4 x float>* @llvm_mips_ftrunc_u_w_ARG1 + %0 = load <4 x float>, <4 x float>* @llvm_mips_ftrunc_u_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float> %0) store <4 x i32> %1, <4 x i32>* @llvm_mips_ftrunc_u_w_RES ret void @@ -115,7 +115,7 @@ declare <4 x i32> @llvm.mips.ftrunc.u.w(<4 x float>) nounwind define void @llvm_mips_ftrunc_u_d_test() nounwind { entry: - %0 = load <2 x double>* @llvm_mips_ftrunc_u_d_ARG1 + %0 = load <2 x double>, <2 x double>* @llvm_mips_ftrunc_u_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double> %0) store <2 x i64> %1, <2 x i64>* @llvm_mips_ftrunc_u_d_RES ret void @@ -136,7 +136,7 @@ declare <2 x i64> @llvm.mips.ftrunc.u.d(<2 x double>) nounwind define void @llvm_mips_ftint_s_w_test() nounwind { entry: - %0 = load <4 x float>* @llvm_mips_ftint_s_w_ARG1 + %0 = load <4 x float>, <4 x float>* @llvm_mips_ftint_s_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.ftint.s.w(<4 x float> %0) store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_s_w_RES ret void @@ -157,7 +157,7 @@ declare <4 x i32> @llvm.mips.ftint.s.w(<4 x float>) nounwind define void @llvm_mips_ftint_s_d_test() nounwind { entry: - %0 = load <2 x double>* @llvm_mips_ftint_s_d_ARG1 + %0 = load <2 x double>, <2 x double>* @llvm_mips_ftint_s_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.ftint.s.d(<2 x double> %0) store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_s_d_RES ret void @@ -178,7 +178,7 @@ declare <2 x i64> @llvm.mips.ftint.s.d(<2 x double>) nounwind define void @llvm_mips_ftint_u_w_test() nounwind { entry: - %0 = load <4 x float>* @llvm_mips_ftint_u_w_ARG1 + %0 = load <4 x float>, <4 x float>* @llvm_mips_ftint_u_w_ARG1 %1 = tail call <4 x i32> @llvm.mips.ftint.u.w(<4 x float> %0) store <4 x i32> %1, <4 x i32>* @llvm_mips_ftint_u_w_RES ret void @@ -199,7 +199,7 @@ declare <4 x i32> @llvm.mips.ftint.u.w(<4 x float>) nounwind define void @llvm_mips_ftint_u_d_test() nounwind { entry: - %0 = load <2 x double>* @llvm_mips_ftint_u_d_ARG1 + %0 = load <2 x double>, <2 x double>* @llvm_mips_ftint_u_d_ARG1 %1 = tail call <2 x i64> @llvm.mips.ftint.u.d(<2 x double> %0) store <2 x i64> %1, <2 x i64>* @llvm_mips_ftint_u_d_RES ret void |