diff options
Diffstat (limited to 'test/CodeGen/Mips/msa/3r_4r.ll')
| -rw-r--r-- | test/CodeGen/Mips/msa/3r_4r.ll | 48 |
1 files changed, 24 insertions, 24 deletions
diff --git a/test/CodeGen/Mips/msa/3r_4r.ll b/test/CodeGen/Mips/msa/3r_4r.ll index b7fd728..73d104c 100644 --- a/test/CodeGen/Mips/msa/3r_4r.ll +++ b/test/CodeGen/Mips/msa/3r_4r.ll @@ -11,9 +11,9 @@ define void @llvm_mips_maddv_b_test() nounwind { entry: - %0 = load <16 x i8>* @llvm_mips_maddv_b_ARG1 - %1 = load <16 x i8>* @llvm_mips_maddv_b_ARG2 - %2 = load <16 x i8>* @llvm_mips_maddv_b_ARG3 + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG2 + %2 = load <16 x i8>, <16 x i8>* @llvm_mips_maddv_b_ARG3 %3 = tail call <16 x i8> @llvm.mips.maddv.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) store <16 x i8> %3, <16 x i8>* @llvm_mips_maddv_b_RES ret void @@ -36,9 +36,9 @@ declare <16 x i8> @llvm.mips.maddv.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind define void @llvm_mips_maddv_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_maddv_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_maddv_h_ARG2 - %2 = load <8 x i16>* @llvm_mips_maddv_h_ARG3 + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG2 + %2 = load <8 x i16>, <8 x i16>* @llvm_mips_maddv_h_ARG3 %3 = tail call <8 x i16> @llvm.mips.maddv.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) store <8 x i16> %3, <8 x i16>* @llvm_mips_maddv_h_RES ret void @@ -61,9 +61,9 @@ declare <8 x i16> @llvm.mips.maddv.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind define void @llvm_mips_maddv_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_maddv_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_maddv_w_ARG2 - %2 = load <4 x i32>* @llvm_mips_maddv_w_ARG3 + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG2 + %2 = load <4 x i32>, <4 x i32>* @llvm_mips_maddv_w_ARG3 %3 = tail call <4 x i32> @llvm.mips.maddv.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) store <4 x i32> %3, <4 x i32>* @llvm_mips_maddv_w_RES ret void @@ -86,9 +86,9 @@ declare <4 x i32> @llvm.mips.maddv.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind define void @llvm_mips_maddv_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_maddv_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_maddv_d_ARG2 - %2 = load <2 x i64>* @llvm_mips_maddv_d_ARG3 + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG1 + %1 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG2 + %2 = load <2 x i64>, <2 x i64>* @llvm_mips_maddv_d_ARG3 %3 = tail call <2 x i64> @llvm.mips.maddv.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) store <2 x i64> %3, <2 x i64>* @llvm_mips_maddv_d_RES ret void @@ -111,9 +111,9 @@ declare <2 x i64> @llvm.mips.maddv.d(<2 x i64>, <2 x i64>, <2 x i64>) nounwind define void @llvm_mips_msubv_b_test() nounwind { entry: - %0 = load <16 x i8>* @llvm_mips_msubv_b_ARG1 - %1 = load <16 x i8>* @llvm_mips_msubv_b_ARG2 - %2 = load <16 x i8>* @llvm_mips_msubv_b_ARG3 + %0 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG1 + %1 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG2 + %2 = load <16 x i8>, <16 x i8>* @llvm_mips_msubv_b_ARG3 %3 = tail call <16 x i8> @llvm.mips.msubv.b(<16 x i8> %0, <16 x i8> %1, <16 x i8> %2) store <16 x i8> %3, <16 x i8>* @llvm_mips_msubv_b_RES ret void @@ -136,9 +136,9 @@ declare <16 x i8> @llvm.mips.msubv.b(<16 x i8>, <16 x i8>, <16 x i8>) nounwind define void @llvm_mips_msubv_h_test() nounwind { entry: - %0 = load <8 x i16>* @llvm_mips_msubv_h_ARG1 - %1 = load <8 x i16>* @llvm_mips_msubv_h_ARG2 - %2 = load <8 x i16>* @llvm_mips_msubv_h_ARG3 + %0 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG1 + %1 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG2 + %2 = load <8 x i16>, <8 x i16>* @llvm_mips_msubv_h_ARG3 %3 = tail call <8 x i16> @llvm.mips.msubv.h(<8 x i16> %0, <8 x i16> %1, <8 x i16> %2) store <8 x i16> %3, <8 x i16>* @llvm_mips_msubv_h_RES ret void @@ -161,9 +161,9 @@ declare <8 x i16> @llvm.mips.msubv.h(<8 x i16>, <8 x i16>, <8 x i16>) nounwind define void @llvm_mips_msubv_w_test() nounwind { entry: - %0 = load <4 x i32>* @llvm_mips_msubv_w_ARG1 - %1 = load <4 x i32>* @llvm_mips_msubv_w_ARG2 - %2 = load <4 x i32>* @llvm_mips_msubv_w_ARG3 + %0 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG1 + %1 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG2 + %2 = load <4 x i32>, <4 x i32>* @llvm_mips_msubv_w_ARG3 %3 = tail call <4 x i32> @llvm.mips.msubv.w(<4 x i32> %0, <4 x i32> %1, <4 x i32> %2) store <4 x i32> %3, <4 x i32>* @llvm_mips_msubv_w_RES ret void @@ -186,9 +186,9 @@ declare <4 x i32> @llvm.mips.msubv.w(<4 x i32>, <4 x i32>, <4 x i32>) nounwind define void @llvm_mips_msubv_d_test() nounwind { entry: - %0 = load <2 x i64>* @llvm_mips_msubv_d_ARG1 - %1 = load <2 x i64>* @llvm_mips_msubv_d_ARG2 - %2 = load <2 x i64>* @llvm_mips_msubv_d_ARG3 + %0 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG1 + %1 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG2 + %2 = load <2 x i64>, <2 x i64>* @llvm_mips_msubv_d_ARG3 %3 = tail call <2 x i64> @llvm.mips.msubv.d(<2 x i64> %0, <2 x i64> %1, <2 x i64> %2) store <2 x i64> %3, <2 x i64>* @llvm_mips_msubv_d_RES ret void |