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-rw-r--r--test/CodeGen/Mips/msa/arithmetic_float.ll88
1 files changed, 44 insertions, 44 deletions
diff --git a/test/CodeGen/Mips/msa/arithmetic_float.ll b/test/CodeGen/Mips/msa/arithmetic_float.ll
index 9aae284..d2ead53 100644
--- a/test/CodeGen/Mips/msa/arithmetic_float.ll
+++ b/test/CodeGen/Mips/msa/arithmetic_float.ll
@@ -4,9 +4,9 @@
define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
; CHECK: add_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
- %2 = load <4 x float>* %b
+ %2 = load <4 x float>, <4 x float>* %b
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
%3 = fadd <4 x float> %1, %2
; CHECK-DAG: fadd.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -20,9 +20,9 @@ define void @add_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
define void @add_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
; CHECK: add_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
- %2 = load <2 x double>* %b
+ %2 = load <2 x double>, <2 x double>* %b
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
%3 = fadd <2 x double> %1, %2
; CHECK-DAG: fadd.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -36,9 +36,9 @@ define void @add_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nou
define void @sub_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
; CHECK: sub_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
- %2 = load <4 x float>* %b
+ %2 = load <4 x float>, <4 x float>* %b
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
%3 = fsub <4 x float> %1, %2
; CHECK-DAG: fsub.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -52,9 +52,9 @@ define void @sub_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
define void @sub_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
; CHECK: sub_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
- %2 = load <2 x double>* %b
+ %2 = load <2 x double>, <2 x double>* %b
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
%3 = fsub <2 x double> %1, %2
; CHECK-DAG: fsub.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -68,9 +68,9 @@ define void @sub_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nou
define void @mul_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
; CHECK: mul_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
- %2 = load <4 x float>* %b
+ %2 = load <4 x float>, <4 x float>* %b
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
%3 = fmul <4 x float> %1, %2
; CHECK-DAG: fmul.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -84,9 +84,9 @@ define void @mul_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwi
define void @mul_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
; CHECK: mul_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
- %2 = load <2 x double>* %b
+ %2 = load <2 x double>, <2 x double>* %b
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
%3 = fmul <2 x double> %1, %2
; CHECK-DAG: fmul.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -101,11 +101,11 @@ define void @fma_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
<4 x float>* %c) nounwind {
; CHECK: fma_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
- %2 = load <4 x float>* %b
+ %2 = load <4 x float>, <4 x float>* %b
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
- %3 = load <4 x float>* %c
+ %3 = load <4 x float>, <4 x float>* %c
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
%4 = tail call <4 x float> @llvm.fma.v4f32 (<4 x float> %1, <4 x float> %2,
<4 x float> %3)
@@ -121,11 +121,11 @@ define void @fma_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
<2 x double>* %c) nounwind {
; CHECK: fma_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
- %2 = load <2 x double>* %b
+ %2 = load <2 x double>, <2 x double>* %b
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
- %3 = load <2 x double>* %c
+ %3 = load <2 x double>, <2 x double>* %c
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
%4 = tail call <2 x double> @llvm.fma.v2f64 (<2 x double> %1, <2 x double> %2,
<2 x double> %3)
@@ -141,11 +141,11 @@ define void @fmsub_v4f32(<4 x float>* %d, <4 x float>* %a, <4 x float>* %b,
<4 x float>* %c) nounwind {
; CHECK: fmsub_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
- %2 = load <4 x float>* %b
+ %2 = load <4 x float>, <4 x float>* %b
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
- %3 = load <4 x float>* %c
+ %3 = load <4 x float>, <4 x float>* %c
; CHECK-DAG: ld.w [[R3:\$w[0-9]+]], 0($7)
%4 = fmul <4 x float> %2, %3
%5 = fsub <4 x float> %1, %4
@@ -161,11 +161,11 @@ define void @fmsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
<2 x double>* %c) nounwind {
; CHECK: fmsub_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
- %2 = load <2 x double>* %b
+ %2 = load <2 x double>, <2 x double>* %b
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
- %3 = load <2 x double>* %c
+ %3 = load <2 x double>, <2 x double>* %c
; CHECK-DAG: ld.d [[R3:\$w[0-9]+]], 0($7)
%4 = fmul <2 x double> %2, %3
%5 = fsub <2 x double> %1, %4
@@ -180,9 +180,9 @@ define void @fmsub_v2f64(<2 x double>* %d, <2 x double>* %a, <2 x double>* %b,
define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounwind {
; CHECK: fdiv_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
- %2 = load <4 x float>* %b
+ %2 = load <4 x float>, <4 x float>* %b
; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
%3 = fdiv <4 x float> %1, %2
; CHECK-DAG: fdiv.w [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -196,9 +196,9 @@ define void @fdiv_v4f32(<4 x float>* %c, <4 x float>* %a, <4 x float>* %b) nounw
define void @fdiv_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) nounwind {
; CHECK: fdiv_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
- %2 = load <2 x double>* %b
+ %2 = load <2 x double>, <2 x double>* %b
; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
%3 = fdiv <2 x double> %1, %2
; CHECK-DAG: fdiv.d [[R3:\$w[0-9]+]], [[R1]], [[R2]]
@@ -212,7 +212,7 @@ define void @fdiv_v2f64(<2 x double>* %c, <2 x double>* %a, <2 x double>* %b) no
define void @fabs_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
; CHECK: fabs_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <4 x float> @llvm.fabs.v4f32 (<4 x float> %1)
; CHECK-DAG: fmax_a.w [[R3:\$w[0-9]+]], [[R1]], [[R1]]
@@ -226,7 +226,7 @@ define void @fabs_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
; CHECK: fabs_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <2 x double> @llvm.fabs.v2f64 (<2 x double> %1)
; CHECK-DAG: fmax_a.d [[R3:\$w[0-9]+]], [[R1]], [[R1]]
@@ -240,7 +240,7 @@ define void @fabs_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
define void @fexp2_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
; CHECK: fexp2_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1)
; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 1
@@ -256,7 +256,7 @@ define void @fexp2_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
define void @fexp2_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
; CHECK: fexp2_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)
; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 1
@@ -272,7 +272,7 @@ define void @fexp2_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
define void @fexp2_v4f32_2(<4 x float>* %c, <4 x float>* %a) nounwind {
; CHECK: fexp2_v4f32_2:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <4 x float> @llvm.exp2.v4f32 (<4 x float> %1)
%3 = fmul <4 x float> <float 2.0, float 2.0, float 2.0, float 2.0>, %2
@@ -289,7 +289,7 @@ define void @fexp2_v4f32_2(<4 x float>* %c, <4 x float>* %a) nounwind {
define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind {
; CHECK: fexp2_v2f64_2:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <2 x double> @llvm.exp2.v2f64 (<2 x double> %1)
%3 = fmul <2 x double> <double 2.0, double 2.0>, %2
@@ -306,7 +306,7 @@ define void @fexp2_v2f64_2(<2 x double>* %c, <2 x double>* %a) nounwind {
define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
; CHECK: fsqrt_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %1)
; CHECK-DAG: fsqrt.w [[R3:\$w[0-9]+]], [[R1]]
@@ -320,7 +320,7 @@ define void @fsqrt_v4f32(<4 x float>* %c, <4 x float>* %a) nounwind {
define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
; CHECK: fsqrt_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %1)
; CHECK-DAG: fsqrt.d [[R3:\$w[0-9]+]], [[R1]]
@@ -334,7 +334,7 @@ define void @fsqrt_v2f64(<2 x double>* %c, <2 x double>* %a) nounwind {
define void @ffint_u_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
; CHECK: ffint_u_v4f32:
- %1 = load <4 x i32>* %a
+ %1 = load <4 x i32>, <4 x i32>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = uitofp <4 x i32> %1 to <4 x float>
; CHECK-DAG: ffint_u.w [[R3:\$w[0-9]+]], [[R1]]
@@ -348,7 +348,7 @@ define void @ffint_u_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
define void @ffint_u_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
; CHECK: ffint_u_v2f64:
- %1 = load <2 x i64>* %a
+ %1 = load <2 x i64>, <2 x i64>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = uitofp <2 x i64> %1 to <2 x double>
; CHECK-DAG: ffint_u.d [[R3:\$w[0-9]+]], [[R1]]
@@ -362,7 +362,7 @@ define void @ffint_u_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
define void @ffint_s_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
; CHECK: ffint_s_v4f32:
- %1 = load <4 x i32>* %a
+ %1 = load <4 x i32>, <4 x i32>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = sitofp <4 x i32> %1 to <4 x float>
; CHECK-DAG: ffint_s.w [[R3:\$w[0-9]+]], [[R1]]
@@ -376,7 +376,7 @@ define void @ffint_s_v4f32(<4 x float>* %c, <4 x i32>* %a) nounwind {
define void @ffint_s_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
; CHECK: ffint_s_v2f64:
- %1 = load <2 x i64>* %a
+ %1 = load <2 x i64>, <2 x i64>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = sitofp <2 x i64> %1 to <2 x double>
; CHECK-DAG: ffint_s.d [[R3:\$w[0-9]+]], [[R1]]
@@ -390,7 +390,7 @@ define void @ffint_s_v2f64(<2 x double>* %c, <2 x i64>* %a) nounwind {
define void @ftrunc_u_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
; CHECK: ftrunc_u_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = fptoui <4 x float> %1 to <4 x i32>
; CHECK-DAG: ftrunc_u.w [[R3:\$w[0-9]+]], [[R1]]
@@ -404,7 +404,7 @@ define void @ftrunc_u_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
define void @ftrunc_u_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
; CHECK: ftrunc_u_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = fptoui <2 x double> %1 to <2 x i64>
; CHECK-DAG: ftrunc_u.d [[R3:\$w[0-9]+]], [[R1]]
@@ -418,7 +418,7 @@ define void @ftrunc_u_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
define void @ftrunc_s_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
; CHECK: ftrunc_s_v4f32:
- %1 = load <4 x float>* %a
+ %1 = load <4 x float>, <4 x float>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = fptosi <4 x float> %1 to <4 x i32>
; CHECK-DAG: ftrunc_s.w [[R3:\$w[0-9]+]], [[R1]]
@@ -432,7 +432,7 @@ define void @ftrunc_s_v4f32(<4 x i32>* %c, <4 x float>* %a) nounwind {
define void @ftrunc_s_v2f64(<2 x i64>* %c, <2 x double>* %a) nounwind {
; CHECK: ftrunc_s_v2f64:
- %1 = load <2 x double>* %a
+ %1 = load <2 x double>, <2 x double>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = fptosi <2 x double> %1 to <2 x i64>
; CHECK-DAG: ftrunc_s.d [[R3:\$w[0-9]+]], [[R1]]
generated by cgit v1.1 at 2024-12-22 10:06:19 +0000