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-rw-r--r--test/CodeGen/Mips/msa/bitwise.ll164
1 files changed, 164 insertions, 0 deletions
diff --git a/test/CodeGen/Mips/msa/bitwise.ll b/test/CodeGen/Mips/msa/bitwise.ll
index f5da9f2..a606fdf 100644
--- a/test/CodeGen/Mips/msa/bitwise.ll
+++ b/test/CodeGen/Mips/msa/bitwise.ll
@@ -972,6 +972,170 @@ define void @ctlz_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
; CHECK: .size ctlz_v2i64
}
+define void @bsel_v16i8(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+ ; CHECK: bsel_v16i8:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <16 x i8>* %b
+ ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <16 x i8> %1, <i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6,
+ i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6, i8 6>
+ %4 = and <16 x i8> %2, <i8 249, i8 249, i8 249, i8 249,
+ i8 249, i8 249, i8 249, i8 249,
+ i8 249, i8 249, i8 249, i8 249,
+ i8 249, i8 249, i8 249, i8 249>
+ %5 = or <16 x i8> %3, %4
+ ; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 6
+ ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
+ store <16 x i8> %5, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size bsel_v16i8
+}
+
+define void @bsel_v8i16(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+ ; CHECK: bsel_v8i16:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <8 x i16>* %b
+ ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <8 x i16> %1, <i16 6, i16 6, i16 6, i16 6,
+ i16 6, i16 6, i16 6, i16 6>
+ %4 = and <8 x i16> %2, <i16 65529, i16 65529, i16 65529, i16 65529,
+ i16 65529, i16 65529, i16 65529, i16 65529>
+ %5 = or <8 x i16> %3, %4
+ ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 6
+ ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
+ store <8 x i16> %5, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size bsel_v8i16
+}
+
+define void @bsel_v4i32(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+ ; CHECK: bsel_v4i32:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <4 x i32>* %b
+ ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <4 x i32> %1, <i32 6, i32 6, i32 6, i32 6>
+ %4 = and <4 x i32> %2, <i32 4294967289, i32 4294967289, i32 4294967289, i32 4294967289>
+ %5 = or <4 x i32> %3, %4
+ ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 6
+ ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
+ store <4 x i32> %5, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size bsel_v4i32
+}
+
+define void @bsel_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+ ; CHECK: bsel_v2i64:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <2 x i64>* %b
+ ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <2 x i64> %1, <i64 6, i64 6>
+ %4 = and <2 x i64> %2, <i64 18446744073709551609, i64 18446744073709551609>
+ %5 = or <2 x i64> %3, %4
+ ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 6
+ ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
+ store <2 x i64> %5, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size bsel_v2i64
+}
+
+define void @binsr_v16i8_i(<16 x i8>* %c, <16 x i8>* %a, <16 x i8>* %b) nounwind {
+ ; CHECK: binsr_v16i8_i:
+
+ %1 = load <16 x i8>* %a
+ ; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <16 x i8>* %b
+ ; CHECK-DAG: ld.b [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <16 x i8> %1, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3,
+ i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
+ %4 = and <16 x i8> %2, <i8 252, i8 252, i8 252, i8 252,
+ i8 252, i8 252, i8 252, i8 252,
+ i8 252, i8 252, i8 252, i8 252,
+ i8 252, i8 252, i8 252, i8 252>
+ %5 = or <16 x i8> %3, %4
+ ; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 3
+ ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
+ store <16 x i8> %5, <16 x i8>* %c
+ ; CHECK-DAG: st.b [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size binsr_v16i8_i
+}
+
+define void @binsr_v8i16_i(<8 x i16>* %c, <8 x i16>* %a, <8 x i16>* %b) nounwind {
+ ; CHECK: binsr_v8i16_i:
+
+ %1 = load <8 x i16>* %a
+ ; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <8 x i16>* %b
+ ; CHECK-DAG: ld.h [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <8 x i16> %1, <i16 3, i16 3, i16 3, i16 3,
+ i16 3, i16 3, i16 3, i16 3>
+ %4 = and <8 x i16> %2, <i16 65532, i16 65532, i16 65532, i16 65532,
+ i16 65532, i16 65532, i16 65532, i16 65532>
+ %5 = or <8 x i16> %3, %4
+ ; CHECK-DAG: ldi.h [[R3:\$w[0-9]+]], 3
+ ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
+ store <8 x i16> %5, <8 x i16>* %c
+ ; CHECK-DAG: st.h [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size binsr_v8i16_i
+}
+
+define void @binsr_v4i32_i(<4 x i32>* %c, <4 x i32>* %a, <4 x i32>* %b) nounwind {
+ ; CHECK: binsr_v4i32_i:
+
+ %1 = load <4 x i32>* %a
+ ; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <4 x i32>* %b
+ ; CHECK-DAG: ld.w [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <4 x i32> %1, <i32 3, i32 3, i32 3, i32 3>
+ %4 = and <4 x i32> %2, <i32 4294967292, i32 4294967292, i32 4294967292, i32 4294967292>
+ %5 = or <4 x i32> %3, %4
+ ; CHECK-DAG: ldi.w [[R3:\$w[0-9]+]], 3
+ ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
+ store <4 x i32> %5, <4 x i32>* %c
+ ; CHECK-DAG: st.w [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size binsr_v4i32_i
+}
+
+define void @binsr_v2i64_i(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
+ ; CHECK: binsr_v2i64_i:
+
+ %1 = load <2 x i64>* %a
+ ; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
+ %2 = load <2 x i64>* %b
+ ; CHECK-DAG: ld.d [[R2:\$w[0-9]+]], 0($6)
+ %3 = and <2 x i64> %1, <i64 3, i64 3>
+ %4 = and <2 x i64> %2, <i64 18446744073709551612, i64 18446744073709551612>
+ %5 = or <2 x i64> %3, %4
+ ; CHECK-DAG: ldi.d [[R3:\$w[0-9]+]], 3
+ ; CHECK-DAG: bsel.v [[R3]], [[R2]], [[R1]]
+ store <2 x i64> %5, <2 x i64>* %c
+ ; CHECK-DAG: st.d [[R3]], 0($4)
+
+ ret void
+ ; CHECK: .size binsr_v2i64_i
+}
+
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %val)
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %val)
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val)
generated by cgit v1.1 at 2025-01-08 17:41:37 +0000