diff options
Diffstat (limited to 'test/CodeGen/PowerPC/vec_shuffle_le.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vec_shuffle_le.ll | 40 |
1 files changed, 29 insertions, 11 deletions
diff --git a/test/CodeGen/PowerPC/vec_shuffle_le.ll b/test/CodeGen/PowerPC/vec_shuffle_le.ll index 635721c..a4b2119 100644 --- a/test/CodeGen/PowerPC/vec_shuffle_le.ll +++ b/test/CodeGen/PowerPC/vec_shuffle_le.ll @@ -6,7 +6,9 @@ entry: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30> -; CHECK: vpkuhum +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vpkuhum [[REG3:[0-9]+]], [[REG2]], [[REG1]] store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -27,7 +29,9 @@ entry: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29> -; CHECK: vpkuwum +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vpkuwum [[REG3:[0-9]+]], [[REG2]], [[REG1]] store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -48,7 +52,9 @@ entry: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23> -; CHECK: vmrglb +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]] store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -69,7 +75,9 @@ entry: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31> -; CHECK: vmrghb +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]] store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -90,7 +98,9 @@ entry: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23> -; CHECK: vmrglh +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]] store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -111,7 +121,9 @@ entry: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31> -; CHECK: vmrghh +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]] store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -132,7 +144,9 @@ entry: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23> -; CHECK: vmrglw +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]] store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -153,7 +167,9 @@ entry: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31> -; CHECK: vmrghw +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]] store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -173,8 +189,10 @@ entry: ; CHECK: VSLDOI_xy: %tmp = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B - %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 19, i32 18, i32 17, i32 16, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4> -; CHECK: vsldoi + %tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27> +; CHECK: lvx [[REG1:[0-9]+]] +; CHECK: lvx [[REG2:[0-9]+]] +; CHECK: vsldoi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 4 store <16 x i8> %tmp3, <16 x i8>* %A ret void } @@ -183,7 +201,7 @@ define void @VSLDOI_xx(<16 x i8>* %A) { entry: ; CHECK: VSLDOI_xx: %tmp = load <16 x i8>* %A - %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4> + %tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11> ; CHECK: vsldoi store <16 x i8> %tmp2, <16 x i8>* %A ret void |