diff options
Diffstat (limited to 'test/CodeGen/PowerPC')
123 files changed, 7323 insertions, 804 deletions
diff --git a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll index 3620b0e..3624b51 100644 --- a/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll +++ b/test/CodeGen/PowerPC/2007-03-24-cntlzd.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=ppc64 -mcpu=g5 | grep cntlzd +; RUN: llc -mcpu=g5 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) nounwind { %tmp19 = load i64* %t @@ -7,6 +9,12 @@ define i32 @_ZNK4llvm5APInt17countLeadingZerosEv(i64 *%t) nounwind { %tmp89 = add i32 %tmp23, -64 ; <i32> [#uses=1] %tmp90 = add i32 %tmp89, 0 ; <i32> [#uses=1] ret i32 %tmp90 + +; CHECK-LABEL: @_ZNK4llvm5APInt17countLeadingZerosEv +; CHECK: ld [[REG1:[0-9]+]], 0(3) +; CHECK-NEXT: cntlzd [[REG2:[0-9]+]], [[REG1]] +; CHECK-NEXT: addi 3, [[REG2]], -64 +; CHECK-NEXT: blr } declare i64 @llvm.ctlz.i64(i64, i1) diff --git a/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll b/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll index 3acd01d..e7bc5bf 100644 --- a/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll +++ b/test/CodeGen/PowerPC/2011-12-05-NoSpillDupCR.ll @@ -183,4 +183,4 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, declare i32 @puts(i8* nocapture) nounwind -!3 = metadata !{metadata !"branch_weights", i32 64, i32 4} +!3 = !{!"branch_weights", i32 64, i32 4} diff --git a/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll b/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll index 4a1a512..a6223d4 100644 --- a/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll +++ b/test/CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll @@ -217,4 +217,4 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, declare i32 @puts(i8* nocapture) nounwind -!3 = metadata !{metadata !"branch_weights", i32 64, i32 4} +!3 = !{!"branch_weights", i32 64, i32 4} diff --git a/test/CodeGen/PowerPC/Frames-large.ll b/test/CodeGen/PowerPC/Frames-large.ll index 0ccea42..5b8aef4 100644 --- a/test/CodeGen/PowerPC/Frames-large.ll +++ b/test/CodeGen/PowerPC/Frames-large.ll @@ -1,9 +1,8 @@ -; RUN: llvm-as < %s > %t.bc -; RUN: llc < %t.bc -march=ppc32 | FileCheck %s -check-prefix=PPC32-NOFP -; RUN: llc < %t.bc -march=ppc32 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-FP +; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=PPC32-NOFP +; RUN: llc < %s -march=ppc32 -disable-fp-elim | FileCheck %s -check-prefix=PPC32-FP -; RUN: llc < %t.bc -march=ppc64 | FileCheck %s -check-prefix=PPC64-NOFP -; RUN: llc < %t.bc -march=ppc64 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-FP +; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=PPC64-NOFP +; RUN: llc < %s -march=ppc64 -disable-fp-elim | FileCheck %s -check-prefix=PPC64-FP target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/aa-tbaa.ll b/test/CodeGen/PowerPC/aa-tbaa.ll index 1939841..0e7ff3d 100644 --- a/test/CodeGen/PowerPC/aa-tbaa.ll +++ b/test/CodeGen/PowerPC/aa-tbaa.ll @@ -35,7 +35,7 @@ next: ; CHECK: blr } -!0 = metadata !{ metadata !"root" } -!1 = metadata !{ metadata !"set1", metadata !0 } -!2 = metadata !{ metadata !"set2", metadata !0 } +!0 = !{ !"root" } +!1 = !{ !"set1", !0 } +!2 = !{ !"set2", !0 } diff --git a/test/CodeGen/PowerPC/add-fi.ll b/test/CodeGen/PowerPC/add-fi.ll new file mode 100644 index 0000000..18892c8 --- /dev/null +++ b/test/CodeGen/PowerPC/add-fi.ll @@ -0,0 +1,24 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32* @test1() { + %X = alloca { i32, i32 } + %Y = getelementptr {i32,i32}* %X, i32 0, i32 1 + ret i32* %Y + +; CHECK-LABEL: @test1 +; CHECK: addi 3, 1, -4 +; CHECK: blr +} + +define i32* @test2() { + %X = alloca { i32, i32, i32, i32 } + %Y = getelementptr {i32,i32,i32,i32}* %X, i32 0, i32 3 + ret i32* %Y + +; CHECK-LABEL: @test2 +; CHECK: addi 3, 1, -4 +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/addi-licm.ll b/test/CodeGen/PowerPC/addi-licm.ll new file mode 100644 index 0000000..070d86f --- /dev/null +++ b/test/CodeGen/PowerPC/addi-licm.ll @@ -0,0 +1,64 @@ +; RUN: llc -mcpu=pwr7 -disable-ppc-preinc-prep < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PIP +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define double @foo() #1 { +entry: + %x = alloca [2048 x float], align 4 + %y = alloca [2048 x float], align 4 + %0 = bitcast [2048 x float]* %x to i8* + call void @llvm.lifetime.start(i64 8192, i8* %0) #2 + %1 = bitcast [2048 x float]* %y to i8* + call void @llvm.lifetime.start(i64 8192, i8* %1) #2 + br label %for.body.i + +; CHECK-LABEL: @foo +; CHECK: addi [[REG1:[0-9]+]], 1, +; CHECK: addi [[REG2:[0-9]+]], 1, +; CHECK: %for.body.i +; CHECK-DAG: lfsx {{[0-9]+}}, [[REG1]], +; CHECK-DAG: lfsx {{[0-9]+}}, [[REG2]], +; CHECK: blr + +; PIP-LABEL: @foo +; PIP: addi [[REG1:[0-9]+]], 1, +; PIP: addi [[REG2:[0-9]+]], 1, +; PIP: %for.body.i +; PIP-DAG: lfsu {{[0-9]+}}, 4([[REG1]]) +; PIP-DAG: lfsu {{[0-9]+}}, 4([[REG2]]) +; PIP: blr + +for.body.i: ; preds = %for.body.i.preheader, %for.body.i + %accumulator.09.i = phi double [ %add.i, %for.body.i ], [ 0.000000e+00, %entry ] + %i.08.i = phi i64 [ %inc.i, %for.body.i ], [ 0, %entry ] + %arrayidx.i = getelementptr inbounds [2048 x float]* %x, i64 0, i64 %i.08.i + %v14 = load float* %arrayidx.i, align 4 + %conv.i = fpext float %v14 to double + %arrayidx1.i = getelementptr inbounds [2048 x float]* %y, i64 0, i64 %i.08.i + %v15 = load float* %arrayidx1.i, align 4 + %conv2.i = fpext float %v15 to double + %mul.i = fmul double %conv.i, %conv2.i + %add.i = fadd double %accumulator.09.i, %mul.i + %inc.i = add nuw nsw i64 %i.08.i, 1 + %exitcond.i = icmp eq i64 %i.08.i, 2047 + br i1 %exitcond.i, label %loop.exit, label %for.body.i + +loop.exit: ; preds = %for.body.i + ret double %accumulator.09.i +} + +; Function Attrs: nounwind +declare void @llvm.lifetime.start(i64, i8* nocapture) #2 + +declare void @bar(float*, float*) + +; Function Attrs: nounwind +declare void @llvm.lifetime.end(i64, i8* nocapture) #2 + +attributes #0 = { nounwind readonly } +attributes #1 = { nounwind } +attributes #2 = { nounwind } + + diff --git a/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll b/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll new file mode 100644 index 0000000..fd430a6 --- /dev/null +++ b/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll @@ -0,0 +1,23 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @bar() #0 { +entry: + tail call void @xxx([2 x i64] [i64 4607182418800017408, i64 4611686018427387904]) #0 + ret void + +; CHECK-LABEL: @bar +; CHECK-DAG: li [[REG1:[0-9]+]], 1023 +; CHECK-DAG: li [[REG2:[0-9]+]], {{1$}} +; CHECK-DAG: sldi 3, [[REG1]], 52 +; CHECK-DAG: sldi 4, [[REG2]], 62 +; CHECK: bl xxx +; CHECK: blr +} + +declare void @xxx([2 x i64]) + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/asm-Zy.ll b/test/CodeGen/PowerPC/asm-Zy.ll index 691165f..6d1ab0e 100644 --- a/test/CodeGen/PowerPC/asm-Zy.ll +++ b/test/CodeGen/PowerPC/asm-Zy.ll @@ -10,5 +10,5 @@ entry: ; CHECK: lwbrx 3, 0, } -!0 = metadata !{i32 101688} +!0 = !{i32 101688} diff --git a/test/CodeGen/PowerPC/asm-constraints.ll b/test/CodeGen/PowerPC/asm-constraints.ll index 998b618..9bf8b75 100644 --- a/test/CodeGen/PowerPC/asm-constraints.ll +++ b/test/CodeGen/PowerPC/asm-constraints.ll @@ -30,15 +30,16 @@ entry: } ; CHECK-LABEL: @foo -; CHECK: ld [[REG:[0-9]+]],0(4) -; CHECK-NEXT: cmpw [[REG]],[[REG]] -; CHECK-NEXT: bne- 1f -; CHECK-NEXT: 1: isync +; CHECK: ld [[REG:[0-9]+]], 0(4) +; CHECK: cmpw 0, [[REG]], [[REG]] +; CHECK: bne- 0, .Ltmp[[TMP:[0-9]+]] +; CHECK: .Ltmp[[TMP]]: +; CHECK: isync attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.ident = !{!0} -!0 = metadata !{metadata !"clang version 3.6.0 (trunk 217557)"} -!1 = metadata !{i32 67, i32 91, i32 110, i32 126} +!0 = !{!"clang version 3.6.0 (trunk 217557)"} +!1 = !{i32 67, i32 91, i32 110, i32 126} diff --git a/test/CodeGen/PowerPC/bperm.ll b/test/CodeGen/PowerPC/bperm.ll new file mode 100644 index 0000000..c489c1f --- /dev/null +++ b/test/CodeGen/PowerPC/bperm.ll @@ -0,0 +1,279 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define zeroext i32 @bs4(i32 zeroext %a) #0 { +entry: + %0 = tail call i32 @llvm.bswap.i32(i32 %a) + ret i32 %0 + +; CHECK-LABEL: @bs4 +; CHECK: rlwinm [[REG1:[0-9]+]], 3, 8, 0, 31 +; CHECK: rlwimi [[REG1]], 3, 24, 16, 23 +; CHECK: rlwimi [[REG1]], 3, 24, 0, 7 +; CHECK: mr 3, [[REG1]] +; CHECK: blr +} + +define i64 @bs8(i64 %x) #0 { +entry: + %0 = tail call i64 @llvm.bswap.i64(i64 %x) + ret i64 %0 + +; CHECK-LABEL: @bs8 +; CHECK-DAG: rldicl [[REG1:[0-9]+]], 3, 16, 0 +; CHECK-DAG: rldicl [[REG2:[0-9]+]], 3, 8, 0 +; CHECK-DAG: rldicl [[REG3:[0-9]+]], 3, 24, 0 +; CHECK-DAG: rldimi [[REG2]], [[REG1]], 8, 48 +; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 32, 0 +; CHECK-DAG: rldimi [[REG2]], [[REG3]], 16, 40 +; CHECK-DAG: rldicl [[REG5:[0-9]+]], 3, 48, 0 +; CHECK-DAG: rldimi [[REG2]], [[REG4]], 24, 32 +; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 56, 0 +; CHECK-DAG: rldimi [[REG2]], [[REG5]], 40, 16 +; CHECK-DAG: rldimi [[REG2]], [[REG6]], 48, 8 +; CHECK-DAG: rldimi [[REG2]], 3, 56, 0 +; CHECK: mr 3, [[REG2]] +; CHECK: blr +} + +define i64 @test1(i64 %i0, i64 %i1) #0 { +entry: + %0 = lshr i64 %i1, 8 + %and = and i64 %0, 5963776000 + ret i64 %and + +; CHECK-LABEL: @test1 +; CHECK-DAG: li [[REG1:[0-9]+]], 11375 +; CHECK-DAG: rldicl [[REG3:[0-9]+]], 4, 56, 0 +; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 19 +; CHECK: and 3, [[REG3]], [[REG2]] +; CHECK: blr +} + +define i64 @test2(i64 %i0, i64 %i1) #0 { +entry: + %0 = lshr i64 %i1, 6 + %and = and i64 %0, 133434808670355456 + ret i64 %and + +; CHECK-LABEL: @test2 +; CHECK-DAG: lis [[REG1:[0-9]+]], 474 +; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 58, 0 +; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 3648 +; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32 +; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464 +; CHECK: and 3, [[REG5]], [[REG4]] +; CHECK: blr +} + +define i64 @test3(i64 %i0, i64 %i1) #0 { +entry: + %0 = shl i64 %i0, 34 + %and = and i64 %0, 191795733152661504 + ret i64 %and + +; CHECK-LABEL: @test3 +; CHECK-DAG: lis [[REG1:[0-9]+]], 170 +; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 34, 0 +; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 22861 +; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 34 +; CHECK: and 3, [[REG4]], [[REG3]] +; CHECK: blr +} + +define i64 @test4(i64 %i0, i64 %i1) #0 { +entry: + %0 = lshr i64 %i1, 15 + %and = and i64 %0, 58195968 + ret i64 %and + +; CHECK-LABEL: @test4 +; CHECK: rldicl [[REG1:[0-9]+]], 4, 49, 0 +; CHECK: andis. 3, [[REG1]], 888 +; CHECK: blr +} + +define i64 @test5(i64 %i0, i64 %i1) #0 { +entry: + %0 = shl i64 %i1, 12 + %and = and i64 %0, 127252959854592 + ret i64 %and + +; CHECK-LABEL: @test5 +; CHECK-DAG: lis [[REG1:[0-9]+]], 3703 +; CHECK-DAG: rldicl [[REG4:[0-9]+]], 4, 12, 0 +; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 35951 +; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19 +; CHECK: and 3, [[REG4]], [[REG3]] +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define zeroext i32 @test6(i32 zeroext %x) #0 { +entry: + %and = lshr i32 %x, 16 + %shr = and i32 %and, 255 + %and1 = shl i32 %x, 16 + %shl = and i32 %and1, 16711680 + %or = or i32 %shr, %shl + ret i32 %or + +; CHECK-LABEL: @test6 +; CHECK: rlwinm [[REG1:[0-9]+]], 3, 16, 24, 31 +; CHECK: rlwimi [[REG1]], 3, 16, 8, 15 +; CHECK: mr 3, [[REG1]] +; CHECK: blr +} + +define i64 @test7(i64 %i0, i64 %i1) #0 { +entry: + %0 = lshr i64 %i0, 5 + %and = and i64 %0, 58195968 + ret i64 %and + +; CHECK-LABEL: @test7 +; CHECK: rlwinm [[REG1:[0-9]+]], 3, 27, 9, 12 +; CHECK: rlwimi [[REG1]], 3, 27, 6, 7 +; CHECK: mr 3, [[REG1]] +; CHECK: blr +} + +define i64 @test8(i64 %i0, i64 %i1) #0 { +entry: + %0 = lshr i64 %i0, 1 + %and = and i64 %0, 169172533248 + ret i64 %and + +; CHECK-LABEL: @test8 +; CHECK-DAG: lis [[REG1:[0-9]+]], 4 +; CHECK-DAG: rldicl [[REG4:[0-9]+]], 3, 63, 0 +; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 60527 +; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 19 +; CHECK: and 3, [[REG4]], [[REG3]] +; CHECK: blr +} + +define i64 @test9(i64 %i0, i64 %i1) #0 { +entry: + %0 = lshr i64 %i1, 14 + %and = and i64 %0, 18848677888 + %1 = shl i64 %i1, 51 + %and3 = and i64 %1, 405323966463344640 + %or4 = or i64 %and, %and3 + ret i64 %or4 + +; CHECK-LABEL: @test9 +; CHECK-DAG: lis [[REG1:[0-9]+]], 1440 +; CHECK-DAG: rldicl [[REG5:[0-9]+]], 4, 62, 0 +; CHECK-DAG: rldicl [[REG6:[0-9]+]], 4, 50, 0 +; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 4 +; CHECK-DAG: rldimi [[REG6]], [[REG5]], 53, 0 +; CHECK-DAG: sldi [[REG3:[0-9]+]], [[REG2]], 32 +; CHECK-DAG: oris [[REG4:[0-9]+]], [[REG3]], 25464 +; CHECK: and 3, [[REG6]], [[REG4]] +; CHECK: blr +} + +define i64 @test10(i64 %i0, i64 %i1) #0 { +entry: + %0 = shl i64 %i0, 37 + %and = and i64 %0, 15881483390550016 + %1 = shl i64 %i0, 25 + %and3 = and i64 %1, 2473599172608 + %or4 = or i64 %and, %and3 + ret i64 %or4 + +; CHECK-LABEL: @test10 +; CHECK-DAG: lis [[REG1:[0-9]+]], 1 +; CHECK-DAG: rldicl [[REG6:[0-9]+]], 3, 25, 0 +; CHECK-DAG: rldicl [[REG7:[0-9]+]], 3, 37, 0 +; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 8183 +; CHECK-DAG: ori [[REG3:[0-9]+]], [[REG1]], 50017 +; CHECK-DAG: sldi [[REG4:[0-9]+]], [[REG2]], 25 +; CHECK-DAG: sldi [[REG5:[0-9]+]], [[REG3]], 37 +; CHECK-DAG: and [[REG8:[0-9]+]], [[REG6]], [[REG4]] +; CHECK-DAG: and [[REG9:[0-9]+]], [[REG7]], [[REG5]] +; CHECK: or 3, [[REG9]], [[REG8]] +; CHECK: blr +} + +define i64 @test11(i64 %x) #0 { +entry: + %and = and i64 %x, 4294967295 + %shl = shl i64 %x, 32 + %or = or i64 %and, %shl + ret i64 %or + +; CHECK-LABEL: @test11 +; CHECK: rlwinm 3, 3, 0, 1, 0 +; CHECK: blr +} + +define i64 @test12(i64 %x) #0 { +entry: + %and = and i64 %x, 4294905855 + %shl = shl i64 %x, 32 + %or = or i64 %and, %shl + ret i64 %or + +; CHECK-LABEL: @test12 +; CHECK: rlwinm 3, 3, 0, 20, 15 +; CHECK: blr +} + +define i64 @test13(i64 %x) #0 { +entry: + %shl = shl i64 %x, 4 + %and = and i64 %shl, 240 + %shr = lshr i64 %x, 28 + %and1 = and i64 %shr, 15 + %or = or i64 %and, %and1 + ret i64 %or + +; CHECK-LABEL: @test13 +; CHECK: rlwinm 3, 3, 4, 24, 31 +; CHECK: blr +} + +define i64 @test14(i64 %x) #0 { +entry: + %shl = shl i64 %x, 4 + %and = and i64 %shl, 240 + %shr = lshr i64 %x, 28 + %and1 = and i64 %shr, 15 + %and2 = and i64 %x, -4294967296 + %or = or i64 %and1, %and2 + %or3 = or i64 %or, %and + ret i64 %or3 + +; CHECK-LABEL: @test14 +; CHECK: rldicr [[REG1:[0-9]+]], 3, 0, 31 +; CHECK: rlwimi [[REG1]], 3, 4, 24, 31 +; CHECK: mr 3, [[REG1]] +; CHECK: blr +} + +define i64 @test15(i64 %x) #0 { +entry: + %shl = shl i64 %x, 4 + %and = and i64 %shl, 240 + %shr = lshr i64 %x, 28 + %and1 = and i64 %shr, 15 + %and2 = and i64 %x, -256 + %or = or i64 %and1, %and2 + %or3 = or i64 %or, %and + ret i64 %or3 + +; CHECK-LABEL: @test15 +; CHECK: rlwimi 3, 3, 4, 24, 31 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.bswap.i32(i32) #0 +declare i64 @llvm.bswap.i64(i64) #0 + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/cc.ll b/test/CodeGen/PowerPC/cc.ll index f92121b..c23ee7c 100644 --- a/test/CodeGen/PowerPC/cc.ll +++ b/test/CodeGen/PowerPC/cc.ll @@ -41,7 +41,7 @@ entry: br label %foo foo: - call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc}" (i64 %a) + call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a) br i1 %c, label %bar, label %end bar: diff --git a/test/CodeGen/PowerPC/cmpb-ppc32.ll b/test/CodeGen/PowerPC/cmpb-ppc32.ll new file mode 100644 index 0000000..639ed88 --- /dev/null +++ b/test/CodeGen/PowerPC/cmpb-ppc32.ll @@ -0,0 +1,50 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-p:32:32-i64:64-n32" +target triple = "powerpc-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 { +entry: + %0 = xor i16 %y, %x + %1 = and i16 %0, 255 + %cmp = icmp eq i16 %1, 0 + %cmp20 = icmp ult i16 %0, 256 + %conv25 = select i1 %cmp, i32 255, i32 0 + %conv27 = select i1 %cmp20, i32 65280, i32 0 + %or = or i32 %conv25, %conv27 + %conv29 = trunc i32 %or to i16 + ret i16 %conv29 + +; CHECK-LABEL: @test16 +; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 +; CHECK: rlwinm 3, [[REG1]], 0, 16, 31 +; CHECK: blr +} + +define i32 @test32(i32 %x, i32 %y) #0 { +entry: + %0 = xor i32 %y, %x + %1 = and i32 %0, 255 + %cmp = icmp eq i32 %1, 0 + %2 = and i32 %0, 65280 + %cmp28 = icmp eq i32 %2, 0 + %3 = and i32 %0, 16711680 + %cmp34 = icmp eq i32 %3, 0 + %cmp40 = icmp ult i32 %0, 16777216 + %conv44 = select i1 %cmp, i32 255, i32 0 + %conv45 = select i1 %cmp28, i32 65280, i32 0 + %conv47 = select i1 %cmp34, i32 16711680, i32 0 + %conv50 = select i1 %cmp40, i32 -16777216, i32 0 + %or = or i32 %conv45, %conv50 + %or49 = or i32 %or, %conv44 + %or52 = or i32 %or49, %conv47 + ret i32 %or52 + +; CHECK-LABEL: @test32 +; CHECK: cmpb 3, 4, 3 +; CHECK-NOT: rlwinm +; CHECK: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/cmpb.ll b/test/CodeGen/PowerPC/cmpb.ll new file mode 100644 index 0000000..7d0c0ab --- /dev/null +++ b/test/CodeGen/PowerPC/cmpb.ll @@ -0,0 +1,204 @@ +; RUN: llc -mcpu pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define zeroext i16 @test16(i16 zeroext %x, i16 zeroext %y) #0 { +entry: + %0 = xor i16 %y, %x + %1 = and i16 %0, 255 + %cmp = icmp eq i16 %1, 0 + %cmp20 = icmp ult i16 %0, 256 + %conv25 = select i1 %cmp, i32 255, i32 0 + %conv27 = select i1 %cmp20, i32 65280, i32 0 + %or = or i32 %conv25, %conv27 + %conv29 = trunc i32 %or to i16 + ret i16 %conv29 + +; CHECK-LABEL: @test16 +; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 +; CHECK: rldicl 3, [[REG1]], 0, 48 +; CHECK: blr +} + +define zeroext i16 @test16p1(i16 zeroext %x, i16 zeroext %y) #0 { +entry: + %0 = xor i16 %y, %x + %1 = and i16 %0, 255 + %cmp = icmp eq i16 %1, 0 + %cmp20 = icmp ult i16 %0, 256 + %conv28 = select i1 %cmp, i32 5, i32 0 + %conv30 = select i1 %cmp20, i32 65280, i32 0 + %or = or i32 %conv28, %conv30 + %conv32 = trunc i32 %or to i16 + ret i16 %conv32 + +; CHECK-LABEL: @test16p1 +; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 +; CHECK: andi. 3, [[REG1]], 65285 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define zeroext i16 @test16p2(i16 zeroext %x, i16 zeroext %y) #0 { +entry: + %0 = xor i16 %y, %x + %1 = and i16 %0, 255 + %cmp = icmp eq i16 %1, 0 + %cmp20 = icmp ult i16 %0, 256 + %conv28 = select i1 %cmp, i32 255, i32 0 + %conv30 = select i1 %cmp20, i32 1280, i32 0 + %or = or i32 %conv28, %conv30 + %conv32 = trunc i32 %or to i16 + ret i16 %conv32 + +; CHECK-LABEL: @test16p2 +; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 +; CHECK: andi. 3, [[REG1]], 1535 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define zeroext i16 @test16p3(i16 zeroext %x, i16 zeroext %y) #0 { +entry: + %0 = xor i16 %y, %x + %1 = and i16 %0, 255 + %cmp = icmp eq i16 %1, 0 + %cmp20 = icmp ult i16 %0, 256 + %conv27 = select i1 %cmp, i32 255, i32 0 + %conv29 = select i1 %cmp20, i32 1024, i32 1280 + %or = or i32 %conv27, %conv29 + %conv31 = trunc i32 %or to i16 + ret i16 %conv31 + +; CHECK-LABEL: @test16p3 +; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 +; CHECK: rldicl [[REG2:[0-9]+]], [[REG1]], 0, 55 +; CHECK: xori 3, [[REG2]], 1280 +; CHECK: blr +} + +define zeroext i32 @test32(i32 zeroext %x, i32 zeroext %y) #0 { +entry: + %0 = xor i32 %y, %x + %1 = and i32 %0, 255 + %cmp = icmp eq i32 %1, 0 + %2 = and i32 %0, 65280 + %cmp28 = icmp eq i32 %2, 0 + %3 = and i32 %0, 16711680 + %cmp34 = icmp eq i32 %3, 0 + %cmp40 = icmp ult i32 %0, 16777216 + %conv44 = select i1 %cmp, i32 255, i32 0 + %conv45 = select i1 %cmp28, i32 65280, i32 0 + %conv47 = select i1 %cmp34, i32 16711680, i32 0 + %conv50 = select i1 %cmp40, i32 -16777216, i32 0 + %or = or i32 %conv45, %conv50 + %or49 = or i32 %or, %conv44 + %or52 = or i32 %or49, %conv47 + ret i32 %or52 + +; CHECK-LABEL: @test32 +; CHECK: cmpb [[REG1:[0-9]+]], 4, 3 +; CHECK: rldicl 3, [[REG1]], 0, 32 +; CHECK: blr +} + +define zeroext i32 @test32p1(i32 zeroext %x, i32 zeroext %y) #0 { +entry: + %0 = xor i32 %y, %x + %1 = and i32 %0, 255 + %cmp = icmp eq i32 %1, 0 + %2 = and i32 %0, 65280 + %cmp28 = icmp eq i32 %2, 0 + %3 = and i32 %0, 16711680 + %cmp34 = icmp eq i32 %3, 0 + %cmp40 = icmp ult i32 %0, 16777216 + %conv47 = select i1 %cmp, i32 255, i32 0 + %conv48 = select i1 %cmp28, i32 65280, i32 0 + %conv50 = select i1 %cmp34, i32 458752, i32 0 + %conv53 = select i1 %cmp40, i32 -16777216, i32 0 + %or = or i32 %conv48, %conv53 + %or52 = or i32 %or, %conv47 + %or55 = or i32 %or52, %conv50 + ret i32 %or55 + +; CHECK-LABEL: @test32p1 +; CHECK: li [[REG1:[0-9]+]], 0 +; CHECK: cmpb [[REG4:[0-9]+]], 4, 3 +; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65287 +; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535 +; CHECK: and 3, [[REG4]], [[REG3]] +; CHECK: blr +} + +define zeroext i32 @test32p2(i32 zeroext %x, i32 zeroext %y) #0 { +entry: + %0 = xor i32 %y, %x + %1 = and i32 %0, 255 + %cmp = icmp eq i32 %1, 0 + %2 = and i32 %0, 65280 + %cmp22 = icmp eq i32 %2, 0 + %cmp28 = icmp ult i32 %0, 16777216 + %conv32 = select i1 %cmp, i32 255, i32 0 + %conv33 = select i1 %cmp22, i32 65280, i32 0 + %conv35 = select i1 %cmp28, i32 -16777216, i32 0 + %or = or i32 %conv33, %conv35 + %or37 = or i32 %or, %conv32 + ret i32 %or37 + +; CHECK-LABEL: @test32p2 +; CHECK: li [[REG1:[0-9]+]], 0 +; CHECK: cmpb [[REG4:[0-9]+]], 4, 3 +; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 65280 +; CHECK: ori [[REG3:[0-9]+]], [[REG2]], 65535 +; CHECK: and 3, [[REG4]], [[REG3]] +; CHECK: blr +} + +define i64 @test64(i64 %x, i64 %y) #0 { +entry: + %shr19 = lshr i64 %x, 56 + %conv21 = trunc i64 %shr19 to i32 + %shr43 = lshr i64 %y, 56 + %conv45 = trunc i64 %shr43 to i32 + %0 = xor i64 %y, %x + %1 = and i64 %0, 255 + %cmp = icmp eq i64 %1, 0 + %2 = and i64 %0, 65280 + %cmp52 = icmp eq i64 %2, 0 + %3 = and i64 %0, 16711680 + %cmp58 = icmp eq i64 %3, 0 + %4 = and i64 %0, 4278190080 + %cmp64 = icmp eq i64 %4, 0 + %5 = and i64 %0, 1095216660480 + %cmp70 = icmp eq i64 %5, 0 + %6 = and i64 %0, 280375465082880 + %cmp76 = icmp eq i64 %6, 0 + %7 = and i64 %0, 71776119061217280 + %cmp82 = icmp eq i64 %7, 0 + %cmp88 = icmp eq i32 %conv21, %conv45 + %conv92 = select i1 %cmp, i64 255, i64 0 + %conv93 = select i1 %cmp52, i64 65280, i64 0 + %or = or i64 %conv92, %conv93 + %conv95 = select i1 %cmp58, i64 16711680, i64 0 + %or97 = or i64 %or, %conv95 + %conv98 = select i1 %cmp64, i64 4278190080, i64 0 + %or100 = or i64 %or97, %conv98 + %conv101 = select i1 %cmp70, i64 1095216660480, i64 0 + %or103 = or i64 %or100, %conv101 + %conv104 = select i1 %cmp76, i64 280375465082880, i64 0 + %or106 = or i64 %or103, %conv104 + %conv107 = select i1 %cmp82, i64 71776119061217280, i64 0 + %or109 = or i64 %or106, %conv107 + %conv110 = select i1 %cmp88, i64 -72057594037927936, i64 0 + %or112 = or i64 %or109, %conv110 + ret i64 %or112 + +; CHECK-LABEL: @test64 +; CHECK: cmpb 3, 3, 4 +; CHECK-NOT: rldicl +; CHECK: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/code-align.ll b/test/CodeGen/PowerPC/code-align.ll new file mode 100644 index 0000000..c6ec37f --- /dev/null +++ b/test/CodeGen/PowerPC/code-align.ll @@ -0,0 +1,110 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s -check-prefix=GENERIC +; RUN: llc -mcpu=970 < %s | FileCheck %s -check-prefix=PWR +; RUN: llc -mcpu=a2 < %s | FileCheck %s -check-prefix=BASIC +; RUN: llc -mcpu=e500mc < %s | FileCheck %s -check-prefix=BASIC +; RUN: llc -mcpu=e5500 < %s | FileCheck %s -check-prefix=BASIC +; RUN: llc -mcpu=pwr4 < %s | FileCheck %s -check-prefix=PWR +; RUN: llc -mcpu=pwr5 < %s | FileCheck %s -check-prefix=PWR +; RUN: llc -mcpu=pwr5x < %s | FileCheck %s -check-prefix=PWR +; RUN: llc -mcpu=pwr6 < %s | FileCheck %s -check-prefix=PWR +; RUN: llc -mcpu=pwr6x < %s | FileCheck %s -check-prefix=PWR +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s -check-prefix=PWR +; RUN: llc -mcpu=pwr8 < %s | FileCheck %s -check-prefix=PWR +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define signext i32 @foo(i32 signext %x) #0 { +entry: + %mul = shl nsw i32 %x, 1 + ret i32 %mul + +; GENERIC-LABEL: .globl foo +; BASIC-LABEL: .globl foo +; PWR-LABEL: .globl foo +; GENERIC: .align 2 +; BASIC: .align 4 +; PWR: .align 4 +; GENERIC: @foo +; BASIC: @foo +; PWR: @foo +} + +; Function Attrs: nounwind +define void @loop(i32 signext %x, i32* nocapture %a) #1 { +entry: + br label %vector.body + +; GENERIC-LABEL: @loop +; BASIC-LABEL: @loop +; PWR-LABEL: @loop +; GENERIC: mtctr +; BASIC: mtctr +; PWR: mtctr +; GENERIC-NOT: .align +; BASIC: .align 4 +; PWR: .align 4 +; GENERIC: lwzu +; BASIC: lwzu +; PWR: lwzu +; GENERIC: bdnz +; BASIC: bdnz +; PWR: bdnz + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %induction45 = or i64 %index, 1 + %0 = getelementptr inbounds i32* %a, i64 %index + %1 = getelementptr inbounds i32* %a, i64 %induction45 + %2 = load i32* %0, align 4 + %3 = load i32* %1, align 4 + %4 = add nsw i32 %2, 4 + %5 = add nsw i32 %3, 4 + %6 = mul nsw i32 %4, 3 + %7 = mul nsw i32 %5, 3 + store i32 %6, i32* %0, align 4 + store i32 %7, i32* %1, align 4 + %index.next = add i64 %index, 2 + %8 = icmp eq i64 %index.next, 2048 + br i1 %8, label %for.end, label %vector.body + +for.end: ; preds = %vector.body + ret void +} + +; Function Attrs: nounwind +define void @sloop(i32 signext %x, i32* nocapture %a) #1 { +entry: + br label %for.body + +; GENERIC-LABEL: @sloop +; BASIC-LABEL: @sloop +; PWR-LABEL: @sloop +; GENERIC: mtctr +; BASIC: mtctr +; PWR: mtctr +; GENERIC-NOT: .align +; BASIC: .align 4 +; PWR: .align 5 +; GENERIC: bdnz +; BASIC: bdnz +; PWR: bdnz + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds i32* %a, i64 %indvars.iv + %0 = load i32* %arrayidx, align 4 + %add = add nsw i32 %0, 4 + %mul = mul nsw i32 %add, 3 + store i32 %mul, i32* %arrayidx, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 2048 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind } + diff --git a/test/CodeGen/PowerPC/constants-i64.ll b/test/CodeGen/PowerPC/constants-i64.ll new file mode 100644 index 0000000..5f2815e --- /dev/null +++ b/test/CodeGen/PowerPC/constants-i64.ll @@ -0,0 +1,84 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define i64 @cn1() #0 { +entry: + ret i64 281474976710655 + +; CHECK-LABEL: @cn1 +; CHECK: lis [[REG1:[0-9]+]], -1 +; CHECK: rldicr 3, [[REG1]], 48, 63 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define i64 @cnb() #0 { +entry: + ret i64 281474976710575 + +; CHECK-LABEL: @cnb +; CHECK: lis [[REG1:[0-9]+]], -81 +; CHECK: rldicr 3, [[REG1]], 48, 63 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define i64 @f2(i64 %x) #0 { +entry: + ret i64 -68719476736 + +; CHECK-LABEL: @f2 +; CHECK: li [[REG1:[0-9]+]], -1 +; CHECK: sldi 3, [[REG1]], 36 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define i64 @f2a(i64 %x) #0 { +entry: + ret i64 -361850994688 + +; CHECK-LABEL: @f2a +; CHECK: li [[REG1:[0-9]+]], -337 +; CHECK: sldi 3, [[REG1]], 30 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define i64 @f2n(i64 %x) #0 { +entry: + ret i64 68719476735 + +; CHECK-LABEL: @f2n +; CHECK: lis [[REG1:[0-9]+]], -4096 +; CHECK: rldicr 3, [[REG1]], 36, 63 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define i64 @f3(i64 %x) #0 { +entry: + ret i64 8589934591 + +; CHECK-LABEL: @f3 +; CHECK: lis [[REG1:[0-9]+]], -32768 +; CHECK: rldicr 3, [[REG1]], 33, 63 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define i64 @cn2n() #0 { +entry: + ret i64 -1407374887747585 + +; CHECK-LABEL: @cn2n +; CHECK: lis [[REG1:[0-9]+]], -5121 +; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 65534 +; CHECK: rldicr 3, [[REG2]], 22, 63 +; CHECK: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/crsave.ll b/test/CodeGen/PowerPC/crsave.ll index a9b4b36..602ba94 100644 --- a/test/CodeGen/PowerPC/crsave.ll +++ b/test/CodeGen/PowerPC/crsave.ll @@ -6,7 +6,7 @@ declare void @foo() define i32 @test_cr2() nounwind uwtable { entry: %ret = alloca i32, align 4 - %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind + %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09mfcr $0", "=r,r,r,r,r,~{cr2}"(i32 1, i32 2, i32 3, i32 0) nounwind store i32 %0, i32* %ret, align 4 call void @foo() %1 = load i32* %ret, align 4 @@ -35,7 +35,7 @@ entry: define i32 @test_cr234() nounwind { entry: %ret = alloca i32, align 4 - %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmp 2,$2,$1\0A\09cmp 3,$2,$2\0A\09cmp 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind + %0 = call i32 asm sideeffect "\0A\09mtcr $4\0A\09cmpw 2,$2,$1\0A\09cmpw 3,$2,$2\0A\09cmpw 4,$2,$3\0A\09mfcr $0", "=r,r,r,r,r,~{cr2},~{cr3},~{cr4}"(i32 1, i32 2, i32 3, i32 0) nounwind store i32 %0, i32* %ret, align 4 call void @foo() %1 = load i32* %ret, align 4 diff --git a/test/CodeGen/PowerPC/ctrloops.ll b/test/CodeGen/PowerPC/ctrloops.ll index ca00f68..ccab7cb 100644 --- a/test/CodeGen/PowerPC/ctrloops.ll +++ b/test/CodeGen/PowerPC/ctrloops.ll @@ -1,6 +1,6 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-freebsd10.0" -; RUN: llc < %s -march=ppc64 | FileCheck %s +; RUN: llc < %s -march=ppc64 -relocation-model=pic | FileCheck %s @a = common global i32 0, align 4 @@ -73,3 +73,26 @@ for.end: ; preds = %for.body, %entry ; CHECK-NOT: cmplwi ; CHECK: bdnz } + +@tls_var = external thread_local global i8 + +define i32 @test4() { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %phi = phi i32 [ %dec, %for.body ], [ undef, %entry ] + %load = ptrtoint i8* @tls_var to i32 + %dec = add i32 %phi, -1 + %cmp = icmp sgt i32 %phi, 1 + br i1 %cmp, label %for.body, label %return + +return: ; preds = %for.body + ret i32 %load +; CHECK-LABEL: @test4 +; CHECK-NOT: mtctr +; CHECK: addi {{[0-9]+}} +; CHECK: cmpwi +; CHECK-NOT: bdnz +; CHECK: bgt +} diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll index 04338a6..bd15367 100644 --- a/test/CodeGen/PowerPC/dbg.ll +++ b/test/CodeGen/PowerPC/dbg.ll @@ -6,8 +6,8 @@ target triple = "powerpc64-unknown-linux-gnu" define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readnone { entry: - tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !15, metadata !{metadata !"0x102"}), !dbg !17 - tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !16, metadata !{metadata !"0x102"}), !dbg !18 + tail call void @llvm.dbg.value(metadata i32 %argc, i64 0, metadata !15, metadata !{!"0x102"}), !dbg !17 + tail call void @llvm.dbg.value(metadata i8** %argv, i64 0, metadata !16, metadata !{!"0x102"}), !dbg !18 %add = add nsw i32 %argc, 1, !dbg !19 ret i32 %add, !dbg !19 } @@ -17,23 +17,23 @@ declare void @llvm.dbg.value(metadata, i64, metadata, metadata) nounwind readnon !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!22} -!0 = metadata !{metadata !"0x11\0012\00clang version 3.1\001\00\000\00\000", metadata !21, metadata !1, metadata !1, metadata !3, metadata !1, metadata !""} ; [ DW_TAG_compile_unit ] -!1 = metadata !{} -!3 = metadata !{metadata !5} -!5 = metadata !{metadata !"0x2e\00main\00main\00\001\000\001\000\006\00256\001\000", metadata !21, null, metadata !7, null, i32 (i32, i8**)* @main, null, null, metadata !13} ; [ DW_TAG_subprogram ] -!6 = metadata !{metadata !"0x29", metadata !21} ; [ DW_TAG_file_type ] -!7 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!8 = metadata !{metadata !9, metadata !9, metadata !10} -!9 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] -!10 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !11} ; [ DW_TAG_pointer_type ] -!11 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !12} ; [ DW_TAG_pointer_type ] -!12 = metadata !{metadata !"0x24\00char\000\008\008\000\000\008", null, null} ; [ DW_TAG_base_type ] -!13 = metadata !{metadata !15, metadata !16} -!15 = metadata !{metadata !"0x101\00argc\0016777217\000", metadata !5, metadata !6, metadata !9} ; [ DW_TAG_arg_variable ] -!16 = metadata !{metadata !"0x101\00argv\0033554433\000", metadata !5, metadata !6, metadata !10} ; [ DW_TAG_arg_variable ] -!17 = metadata !{i32 1, i32 14, metadata !5, null} -!18 = metadata !{i32 1, i32 26, metadata !5, null} -!19 = metadata !{i32 2, i32 3, metadata !20, null} -!20 = metadata !{metadata !"0xb\001\0034\000", metadata !21, metadata !5} ; [ DW_TAG_lexical_block ] -!21 = metadata !{metadata !"dbg.c", metadata !"/src"} -!22 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x11\0012\00clang version 3.1\001\00\000\00\000", !21, !1, !1, !3, !1, !""} ; [ DW_TAG_compile_unit ] +!1 = !{} +!3 = !{!5} +!5 = !{!"0x2e\00main\00main\00\001\000\001\000\006\00256\001\000", !21, null, !7, null, i32 (i32, i8**)* @main, null, null, !13} ; [ DW_TAG_subprogram ] +!6 = !{!"0x29", !21} ; [ DW_TAG_file_type ] +!7 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !8, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!8 = !{!9, !9, !10} +!9 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] +!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] +!11 = !{!"0xf\00\000\0064\0064\000\000", null, null, !12} ; [ DW_TAG_pointer_type ] +!12 = !{!"0x24\00char\000\008\008\000\000\008", null, null} ; [ DW_TAG_base_type ] +!13 = !{!15, !16} +!15 = !{!"0x101\00argc\0016777217\000", !5, !6, !9} ; [ DW_TAG_arg_variable ] +!16 = !{!"0x101\00argv\0033554433\000", !5, !6, !10} ; [ DW_TAG_arg_variable ] +!17 = !MDLocation(line: 1, column: 14, scope: !5) +!18 = !MDLocation(line: 1, column: 26, scope: !5) +!19 = !MDLocation(line: 2, column: 3, scope: !20) +!20 = !{!"0xb\001\0034\000", !21, !5} ; [ DW_TAG_lexical_block ] +!21 = !{!"dbg.c", !"/src"} +!22 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/PowerPC/early-ret2.ll b/test/CodeGen/PowerPC/early-ret2.ll index 1784777..f9758d3 100644 --- a/test/CodeGen/PowerPC/early-ret2.ll +++ b/test/CodeGen/PowerPC/early-ret2.ll @@ -25,5 +25,5 @@ while.end: ; preds = %while.body, %while. attributes #0 = { noinline nounwind } -!0 = metadata !{} +!0 = !{} diff --git a/test/CodeGen/PowerPC/fast-isel-const.ll b/test/CodeGen/PowerPC/fast-isel-const.ll new file mode 100644 index 0000000..1057d0a --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-const.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 + +define zeroext i1 @testi1(i8 %in) nounwind uwtable ssp { +entry: + %c = icmp eq i8 %in, 5 + br i1 %c, label %true, label %false + +; ELF64-LABEL: @testi1 + +true: + br label %end + +; ELF64-NOT: li {{[0-9]+}}, -1 +; ELF64: li {{[0-9]+}}, 1 + +false: + br label %end + +; ELF64: li {{[0-9]+}}, 0 + +end: + %r = phi i1 [ 0, %false], [ 1, %true ] + ret i1 %r + +; ELF64: blr +} + diff --git a/test/CodeGen/PowerPC/fdiv-combine.ll b/test/CodeGen/PowerPC/fdiv-combine.ll new file mode 100644 index 0000000..d3dc3fe --- /dev/null +++ b/test/CodeGen/PowerPC/fdiv-combine.ll @@ -0,0 +1,39 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Following test case checks: +; a / D; b / D; c / D; +; => +; recip = 1.0 / D; a * recip; b * recip; c * recip; + +define void @three_fdiv_double(double %D, double %a, double %b, double %c) #0 { +; CHECK-LABEL: three_fdiv_double: +; CHECK: fdiv +; CHECK-NEXT-NOT: fdiv +; CHECK: fmul +; CHECK: fmul +; CHECK: fmul + %div = fdiv double %a, %D + %div1 = fdiv double %b, %D + %div2 = fdiv double %c, %D + tail call void @foo_3d(double %div, double %div1, double %div2) + ret void +} + +define void @two_fdiv_double(double %D, double %a, double %b) #0 { +; CHECK-LABEL: two_fdiv_double: +; CHECK: fdiv +; CHECK: fdiv +; CHECK-NEXT-NOT: fmul + %div = fdiv double %a, %D + %div1 = fdiv double %b, %D + tail call void @foo_2d(double %div, double %div1) + ret void +} + +declare void @foo_3d(double, double, double) +declare void @foo_3_2xd(<2 x double>, <2 x double>, <2 x double>) +declare void @foo_2d(double, double) + +attributes #0 = { "unsafe-fp-math"="true" } diff --git a/test/CodeGen/PowerPC/flt-preinc.ll b/test/CodeGen/PowerPC/flt-preinc.ll new file mode 100644 index 0000000..dd17031 --- /dev/null +++ b/test/CodeGen/PowerPC/flt-preinc.ll @@ -0,0 +1,40 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readonly +define float @tf(float* nocapture readonly %i, i32 signext %o) #0 { +entry: + %idx.ext = sext i32 %o to i64 + %add.ptr = getelementptr inbounds float* %i, i64 %idx.ext + %0 = load float* %add.ptr, align 4 + %add.ptr.sum = add nsw i64 %idx.ext, 1 + %add.ptr3 = getelementptr inbounds float* %i, i64 %add.ptr.sum + %1 = load float* %add.ptr3, align 4 + %add = fadd float %0, %1 + ret float %add + +; CHECK-LABEL: @tf +; CHECK: lfsux +; CHECK: blr +} + +; Function Attrs: nounwind readonly +define double @td(double* nocapture readonly %i, i32 signext %o) #0 { +entry: + %idx.ext = sext i32 %o to i64 + %add.ptr = getelementptr inbounds double* %i, i64 %idx.ext + %0 = load double* %add.ptr, align 8 + %add.ptr.sum = add nsw i64 %idx.ext, 1 + %add.ptr3 = getelementptr inbounds double* %i, i64 %add.ptr.sum + %1 = load double* %add.ptr3, align 8 + %add = fadd double %0, %1 + ret double %add + +; CHECK-LABEL: @td +; CHECK: lfdux +; CHECK: blr +} + +attributes #0 = { nounwind readonly } + diff --git a/test/CodeGen/PowerPC/fma-assoc.ll b/test/CodeGen/PowerPC/fma-assoc.ll new file mode 100644 index 0000000..dc1316e --- /dev/null +++ b/test/CodeGen/PowerPC/fma-assoc.ll @@ -0,0 +1,79 @@ +; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s + +define double @test_FMADD_ASSOC1(double %A, double %B, double %C, + double %D, double %E) { + %F = fmul double %A, %B ; <double> [#uses=1] + %G = fmul double %C, %D ; <double> [#uses=1] + %H = fadd double %F, %G ; <double> [#uses=1] + %I = fadd double %H, %E ; <double> [#uses=1] + ret double %I +; CHECK-LABEL: test_FMADD_ASSOC1: +; CHECK: fmadd +; CHECK-NEXT: fmadd +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMADD_ASSOC1: +; CHECK-VSX: xsmaddmdp +; CHECK-VSX-NEXT: xsmaddadp +; CHECK-VSX-NEXT: fmr +; CHECK-VSX-NEXT: blr +} + +define double @test_FMADD_ASSOC2(double %A, double %B, double %C, + double %D, double %E) { + %F = fmul double %A, %B ; <double> [#uses=1] + %G = fmul double %C, %D ; <double> [#uses=1] + %H = fadd double %F, %G ; <double> [#uses=1] + %I = fadd double %E, %H ; <double> [#uses=1] + ret double %I +; CHECK-LABEL: test_FMADD_ASSOC2: +; CHECK: fmadd +; CHECK-NEXT: fmadd +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMADD_ASSOC2: +; CHECK-VSX: xsmaddmdp +; CHECK-VSX-NEXT: xsmaddadp +; CHECK-VSX-NEXT: fmr +; CHECK-VSX-NEXT: blr +} + +define double @test_FMSUB_ASSOC1(double %A, double %B, double %C, + double %D, double %E) { + %F = fmul double %A, %B ; <double> [#uses=1] + %G = fmul double %C, %D ; <double> [#uses=1] + %H = fadd double %F, %G ; <double> [#uses=1] + %I = fsub double %H, %E ; <double> [#uses=1] + ret double %I +; CHECK-LABEL: test_FMSUB_ASSOC1: +; CHECK: fmsub +; CHECK-NEXT: fmadd +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMSUB_ASSOC1: +; CHECK-VSX: xsmsubmdp +; CHECK-VSX-NEXT: xsmaddadp +; CHECK-VSX-NEXT: fmr +; CHECK-VSX-NEXT: blr +} + +define double @test_FMSUB_ASSOC2(double %A, double %B, double %C, + double %D, double %E) { + %F = fmul double %A, %B ; <double> [#uses=1] + %G = fmul double %C, %D ; <double> [#uses=1] + %H = fadd double %F, %G ; <double> [#uses=1] + %I = fsub double %E, %H ; <double> [#uses=1] + ret double %I +; CHECK-LABEL: test_FMSUB_ASSOC2: +; CHECK: fnmsub +; CHECK-NEXT: fnmsub +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMSUB_ASSOC2: +; CHECK-VSX: xsnmsubmdp +; CHECK-VSX-NEXT: xsnmsubadp +; CHECK-VSX-NEXT: fmr +; CHECK-VSX-NEXT: blr +} + diff --git a/test/CodeGen/PowerPC/fma-ext.ll b/test/CodeGen/PowerPC/fma-ext.ll new file mode 100644 index 0000000..56825ce --- /dev/null +++ b/test/CodeGen/PowerPC/fma-ext.ll @@ -0,0 +1,93 @@ +; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s + +define double @test_FMADD_EXT1(float %A, float %B, double %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fpext float %D to double ; <double> [#uses=1] + %F = fadd double %E, %C ; <double> [#uses=1] + ret double %F +; CHECK-LABEL: test_FMADD_EXT1: +; CHECK: fmadd +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMADD_EXT1: +; CHECK-VSX: xsmaddmdp +; CHECK-VSX-NEXT: blr +} + +define double @test_FMADD_EXT2(float %A, float %B, double %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fpext float %D to double ; <double> [#uses=1] + %F = fadd double %C, %E ; <double> [#uses=1] + ret double %F +; CHECK-LABEL: test_FMADD_EXT2: +; CHECK: fmadd +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMADD_EXT2: +; CHECK-VSX: xsmaddmdp +; CHECK-VSX-NEXT: blr +} + +define double @test_FMSUB_EXT1(float %A, float %B, double %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fpext float %D to double ; <double> [#uses=1] + %F = fsub double %E, %C ; <double> [#uses=1] + ret double %F +; CHECK-LABEL: test_FMSUB_EXT1: +; CHECK: fmsub +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMSUB_EXT1: +; CHECK-VSX: xsmsubmdp +; CHECK-VSX-NEXT: blr +} + +define double @test_FMSUB_EXT2(float %A, float %B, double %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fpext float %D to double ; <double> [#uses=1] + %F = fsub double %C, %E ; <double> [#uses=1] + ret double %F +; CHECK-LABEL: test_FMSUB_EXT2: +; CHECK: fnmsub +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMSUB_EXT2: +; CHECK-VSX: xsnmsubmdp +; CHECK-VSX-NEXT: fmr +; CHECK-VSX-NEXT: blr +} + +define double @test_FMSUB_EXT3(float %A, float %B, double %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fsub float -0.000000e+00, %D ; <float> [#uses=1] + %F = fpext float %E to double ; <double> [#uses=1] + %G = fsub double %F, %C ; <double> [#uses=1] + ret double %G +; CHECK-LABEL: test_FMSUB_EXT3: +; CHECK: fneg +; CHECK-NEXT: fmsub +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMSUB_EXT3: +; CHECK-VSX: xsnegdp +; CHECK-VSX-NEXT: xsmsubmdp +; CHECK-VSX-NEXT: blr +} + +define double @test_FMSUB_EXT4(float %A, float %B, double %C) { + %D = fmul float %A, %B ; <float> [#uses=1] + %E = fpext float %D to double ; <double> [#uses=1] + %F = fsub double -0.000000e+00, %E ; <double> [#uses=1] + %G = fsub double %F, %C ; <double> [#uses=1] + ret double %G +; CHECK-LABEL: test_FMSUB_EXT4: +; CHECK: fneg +; CHECK-NEXT: fmsub +; CHECK-NEXT: blr + +; CHECK-VSX-LABEL: test_FMSUB_EXT4: +; CHECK-VSX: xsnegdp +; CHECK-VSX-NEXT: xsmsubmdp +; CHECK-VSX-NEXT: blr +}
\ No newline at end of file diff --git a/test/CodeGen/PowerPC/fp-to-int-ext.ll b/test/CodeGen/PowerPC/fp-to-int-ext.ll new file mode 100644 index 0000000..bfacd89 --- /dev/null +++ b/test/CodeGen/PowerPC/fp-to-int-ext.ll @@ -0,0 +1,69 @@ +; RUN: llc -mcpu=a2 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define double @foo1(i32* %x) #0 { +entry: + %0 = load i32* %x, align 4 + %conv = sext i32 %0 to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; CHECK-LABEL: @foo1 +; CHECK: lfiwax [[REG1:[0-9]+]], 0, 3 +; CHECK: fcfid 1, [[REG1]] +; CHECK: blr +} + +define double @foo2(i32* %x) #0 { +entry: + %0 = load i32* %x, align 4 + %conv = zext i32 %0 to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; CHECK-LABEL: @foo2 +; CHECK: lfiwzx [[REG1:[0-9]+]], 0, 3 +; CHECK: fcfid 1, [[REG1]] +; CHECK: blr +} + +define double @foo3(i32* %x) #0 { +entry: + %0 = load i32* %x, align 4 + %1 = add i32 %0, 8 + %conv = zext i32 %1 to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; CHECK-LABEL: @foo3 +; CHECK-DAG: lwz [[REG1:[0-9]+]], 0(3) +; CHECK-DAG: addi [[REG3:[0-9]+]], 1, +; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], 8 +; CHECK-DAG: stw [[REG2]], +; CHECK: lfiwzx [[REG4:[0-9]+]], 0, [[REG3]] +; CHECK: fcfid 1, [[REG4]] +; CHECK: blr +} + +define double @foo4(i32* %x) #0 { +entry: + %0 = load i32* %x, align 4 + %1 = add i32 %0, 8 + %conv = sext i32 %1 to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; CHECK-LABEL: @foo4 +; CHECK-DAG: lwz [[REG1:[0-9]+]], 0(3) +; CHECK-DAG: addi [[REG3:[0-9]+]], 1, +; CHECK-DAG: addi [[REG2:[0-9]+]], [[REG1]], 8 +; CHECK-DAG: stw [[REG2]], +; CHECK: lfiwax [[REG4:[0-9]+]], 0, [[REG3]] +; CHECK: fcfid 1, [[REG4]] +; CHECK: blr +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/fp-to-int-to-fp.ll b/test/CodeGen/PowerPC/fp-to-int-to-fp.ll new file mode 100644 index 0000000..f56b9b3 --- /dev/null +++ b/test/CodeGen/PowerPC/fp-to-int-to-fp.ll @@ -0,0 +1,70 @@ +; RUN: llc -mcpu=a2 < %s | FileCheck %s -check-prefix=FPCVT +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s -check-prefix=PPC64 +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define float @fool(float %X) #0 { +entry: + %conv = fptosi float %X to i64 + %conv1 = sitofp i64 %conv to float + ret float %conv1 + +; FPCVT-LABEL: @fool +; FPCVT: fctidz [[REG1:[0-9]+]], 1 +; FPCVT: fcfids 1, [[REG1]] +; FPCVT: blr + +; PPC64-LABEL: @fool +; PPC64: fctidz [[REG1:[0-9]+]], 1 +; PPC64: fcfid [[REG2:[0-9]+]], [[REG1]] +; PPC64: frsp 1, [[REG2]] +; PPC64: blr +} + +; Function Attrs: nounwind readnone +define double @foodl(double %X) #0 { +entry: + %conv = fptosi double %X to i64 + %conv1 = sitofp i64 %conv to double + ret double %conv1 + +; FPCVT-LABEL: @foodl +; FPCVT: fctidz [[REG1:[0-9]+]], 1 +; FPCVT: fcfid 1, [[REG1]] +; FPCVT: blr + +; PPC64-LABEL: @foodl +; PPC64: fctidz [[REG1:[0-9]+]], 1 +; PPC64: fcfid 1, [[REG1]] +; PPC64: blr +} + +; Function Attrs: nounwind readnone +define float @fooul(float %X) #0 { +entry: + %conv = fptoui float %X to i64 + %conv1 = uitofp i64 %conv to float + ret float %conv1 + +; FPCVT-LABEL: @fooul +; FPCVT: fctiduz [[REG1:[0-9]+]], 1 +; FPCVT: fcfidus 1, [[REG1]] +; FPCVT: blr +} + +; Function Attrs: nounwind readnone +define double @fooudl(double %X) #0 { +entry: + %conv = fptoui double %X to i64 + %conv1 = uitofp i64 %conv to double + ret double %conv1 + +; FPCVT-LABEL: @fooudl +; FPCVT: fctiduz [[REG1:[0-9]+]], 1 +; FPCVT: fcfidu 1, [[REG1]] +; FPCVT: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/glob-comp-aa-crash.ll b/test/CodeGen/PowerPC/glob-comp-aa-crash.ll index f97d0ff..2ea036f 100644 --- a/test/CodeGen/PowerPC/glob-comp-aa-crash.ll +++ b/test/CodeGen/PowerPC/glob-comp-aa-crash.ll @@ -130,10 +130,10 @@ attributes #4 = { optsize } attributes #5 = { nounwind optsize } attributes #6 = { noreturn optsize } -!0 = metadata !{metadata !"any pointer", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA"} -!3 = metadata !{metadata !"bool", metadata !1} -!4 = metadata !{i8 0, i8 2} -!5 = metadata !{metadata !0, metadata !0, i64 0} -!6 = metadata !{metadata !3, metadata !3, i64 0} +!0 = !{!"any pointer", !1} +!1 = !{!"omnipotent char", !2} +!2 = !{!"Simple C/C++ TBAA"} +!3 = !{!"bool", !1} +!4 = !{i8 0, i8 2} +!5 = !{!0, !0, i64 0} +!6 = !{!3, !3, i64 0} diff --git a/test/CodeGen/PowerPC/i1-ext-fold.ll b/test/CodeGen/PowerPC/i1-ext-fold.ll new file mode 100644 index 0000000..19bd8ff --- /dev/null +++ b/test/CodeGen/PowerPC/i1-ext-fold.ll @@ -0,0 +1,54 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define signext i32 @foo(i32 signext %a, i32 signext %b) #0 { +entry: + %cmp = icmp slt i32 %a, %b + %conv = zext i1 %cmp to i32 + %shl = shl nuw nsw i32 %conv, 4 + ret i32 %shl + +; CHECK-LABEL: @foo +; CHECK-DAG: cmpw +; CHECK-DAG: li [[REG1:[0-9]+]], 0 +; CHECK-DAG: li [[REG2:[0-9]+]], 16 +; CHECK: isel 3, [[REG2]], [[REG1]], +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define signext i32 @foo2(i32 signext %a, i32 signext %b) #0 { +entry: + %cmp = icmp slt i32 %a, %b + %conv = zext i1 %cmp to i32 + %shl = shl nuw nsw i32 %conv, 4 + %add1 = or i32 %shl, 5 + ret i32 %add1 + +; CHECK-LABEL: @foo2 +; CHECK-DAG: cmpw +; CHECK-DAG: li [[REG1:[0-9]+]], 5 +; CHECK-DAG: li [[REG2:[0-9]+]], 21 +; CHECK: isel 3, [[REG2]], [[REG1]], +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define signext i32 @foo3(i32 signext %a, i32 signext %b) #0 { +entry: + %cmp = icmp sle i32 %a, %b + %conv = zext i1 %cmp to i32 + %shl = shl nuw nsw i32 %conv, 4 + ret i32 %shl + +; CHECK-LABEL: @foo3 +; CHECK-DAG: cmpw +; CHECK-DAG: li [[REG1:[0-9]+]], 16 +; CHECK: isel 3, 0, [[REG1]], +; CHECK: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/ia-mem-r0.ll b/test/CodeGen/PowerPC/ia-mem-r0.ll new file mode 100644 index 0000000..4ab17ed --- /dev/null +++ b/test/CodeGen/PowerPC/ia-mem-r0.ll @@ -0,0 +1,94 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +; Make sure that we don't generate a std r, 0(0) -- the memory address cannot +; be stored in r0. +; CHECK-LABEL: @test1 +; CHECK-NOT: std {{[0-9]+}}, 0(0) +; CHECK: blr + +define void @test1({ i8*, void (i8*, i8*)* } %fn_arg) { + %fn = alloca { i8*, void (i8*, i8*)* } + %sp = alloca i8*, align 8 + %regs = alloca [18 x i64], align 8 + store { i8*, void (i8*, i8*)* } %fn_arg, { i8*, void (i8*, i8*)* }* %fn + %1 = bitcast [18 x i64]* %regs to i64* + call void asm sideeffect "std 14, $0", "=*m"(i64* %1) + %2 = bitcast [18 x i64]* %regs to i8* + %3 = getelementptr i8* %2, i32 8 + %4 = bitcast i8* %3 to i64* + call void asm sideeffect "std 15, $0", "=*m"(i64* %4) + %5 = bitcast [18 x i64]* %regs to i8* + %6 = getelementptr i8* %5, i32 16 + %7 = bitcast i8* %6 to i64* + call void asm sideeffect "std 16, $0", "=*m"(i64* %7) + %8 = bitcast [18 x i64]* %regs to i8* + %9 = getelementptr i8* %8, i32 24 + %10 = bitcast i8* %9 to i64* + call void asm sideeffect "std 17, $0", "=*m"(i64* %10) + %11 = bitcast [18 x i64]* %regs to i8* + %12 = getelementptr i8* %11, i32 32 + %13 = bitcast i8* %12 to i64* + call void asm sideeffect "std 18, $0", "=*m"(i64* %13) + %14 = bitcast [18 x i64]* %regs to i8* + %15 = getelementptr i8* %14, i32 40 + %16 = bitcast i8* %15 to i64* + call void asm sideeffect "std 19, $0", "=*m"(i64* %16) + %17 = bitcast [18 x i64]* %regs to i8* + %18 = getelementptr i8* %17, i32 48 + %19 = bitcast i8* %18 to i64* + call void asm sideeffect "std 20, $0", "=*m"(i64* %19) + %20 = bitcast [18 x i64]* %regs to i8* + %21 = getelementptr i8* %20, i32 56 + %22 = bitcast i8* %21 to i64* + call void asm sideeffect "std 21, $0", "=*m"(i64* %22) + %23 = bitcast [18 x i64]* %regs to i8* + %24 = getelementptr i8* %23, i32 64 + %25 = bitcast i8* %24 to i64* + call void asm sideeffect "std 22, $0", "=*m"(i64* %25) + %26 = bitcast [18 x i64]* %regs to i8* + %27 = getelementptr i8* %26, i32 72 + %28 = bitcast i8* %27 to i64* + call void asm sideeffect "std 23, $0", "=*m"(i64* %28) + %29 = bitcast [18 x i64]* %regs to i8* + %30 = getelementptr i8* %29, i32 80 + %31 = bitcast i8* %30 to i64* + call void asm sideeffect "std 24, $0", "=*m"(i64* %31) + %32 = bitcast [18 x i64]* %regs to i8* + %33 = getelementptr i8* %32, i32 88 + %34 = bitcast i8* %33 to i64* + call void asm sideeffect "std 25, $0", "=*m"(i64* %34) + %35 = bitcast [18 x i64]* %regs to i8* + %36 = getelementptr i8* %35, i32 96 + %37 = bitcast i8* %36 to i64* + call void asm sideeffect "std 26, $0", "=*m"(i64* %37) + %38 = bitcast [18 x i64]* %regs to i8* + %39 = getelementptr i8* %38, i32 104 + %40 = bitcast i8* %39 to i64* + call void asm sideeffect "std 27, $0", "=*m"(i64* %40) + %41 = bitcast [18 x i64]* %regs to i8* + %42 = getelementptr i8* %41, i32 112 + %43 = bitcast i8* %42 to i64* + call void asm sideeffect "std 28, $0", "=*m"(i64* %43) + %44 = bitcast [18 x i64]* %regs to i8* + %45 = getelementptr i8* %44, i32 120 + %46 = bitcast i8* %45 to i64* + call void asm sideeffect "std 29, $0", "=*m"(i64* %46) + %47 = bitcast [18 x i64]* %regs to i8* + %48 = getelementptr i8* %47, i32 128 + %49 = bitcast i8* %48 to i64* + call void asm sideeffect "std 30, $0", "=*m"(i64* %49) + %50 = bitcast [18 x i64]* %regs to i8* + %51 = getelementptr i8* %50, i32 136 + %52 = bitcast i8* %51 to i64* + call void asm sideeffect "std 31, $0", "=*m"(i64* %52) + %53 = getelementptr { i8*, void (i8*, i8*)* }* %fn, i32 0, i32 1 + %.funcptr = load void (i8*, i8*)** %53 + %54 = getelementptr { i8*, void (i8*, i8*)* }* %fn, i32 0, i32 0 + %.ptr = load i8** %54 + %55 = load i8** %sp + call void %.funcptr(i8* %.ptr, i8* %55) + ret void +} + diff --git a/test/CodeGen/PowerPC/ia-neg-const.ll b/test/CodeGen/PowerPC/ia-neg-const.ll new file mode 100644 index 0000000..556ab80 --- /dev/null +++ b/test/CodeGen/PowerPC/ia-neg-const.ll @@ -0,0 +1,25 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1 + +; Function Attrs: nounwind +define i64 @main() #0 { +entry: + %x = alloca i64, align 8 + store i64 0, i64* %x, align 8 + %0 = call i64 asm sideeffect "ld $0,$1\0A\09add${2:I} $0,$0,$2", "=&r,*m,Ir"(i64* %x, i64 -1) #0 + ret i64 %0 +} + +; CHECK: ld +; CHECK-NOT: addi 3, 3, 4294967295 +; CHECK: addi 3, 3, -1 +; CHECK: blr + +; Function Attrs: nounwind +declare signext i32 @printf(i8* nocapture readonly, ...) #0 + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/in-asm-f64-reg.ll b/test/CodeGen/PowerPC/in-asm-f64-reg.ll index 1321dfc..08b1a2c 100644 --- a/test/CodeGen/PowerPC/in-asm-f64-reg.ll +++ b/test/CodeGen/PowerPC/in-asm-f64-reg.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -no-integrated-as | FileCheck %s define void @f() { ; CHECK: @f diff --git a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll index 5e31cd5..4d8e704 100644 --- a/test/CodeGen/PowerPC/inlineasm-i64-reg.ll +++ b/test/CodeGen/PowerPC/inlineasm-i64-reg.ll @@ -105,4 +105,4 @@ if.end40: attributes #0 = { alwaysinline inlinehint nounwind } attributes #1 = { nounwind } -!0 = metadata !{i32 -2146895770} +!0 = !{i32 -2146895770} diff --git a/test/CodeGen/PowerPC/lbz-from-ld-shift.ll b/test/CodeGen/PowerPC/lbz-from-ld-shift.ll new file mode 100644 index 0000000..3eacd6a --- /dev/null +++ b/test/CodeGen/PowerPC/lbz-from-ld-shift.ll @@ -0,0 +1,18 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readonly +define signext i32 @test(i32* nocapture readonly %P) #0 { +entry: + %0 = load i32* %P, align 4 + %shr = lshr i32 %0, 24 + ret i32 %shr + +; CHECK-LABEL: @test +; CHECK: lbz 3, 0(3) +; CHECK: blr +} + +attributes #0 = { nounwind readonly } + diff --git a/test/CodeGen/PowerPC/ld-st-upd.ll b/test/CodeGen/PowerPC/ld-st-upd.ll new file mode 100644 index 0000000..24f31ac --- /dev/null +++ b/test/CodeGen/PowerPC/ld-st-upd.ll @@ -0,0 +1,19 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc-unknown-linux-gnu" + +; Function Attrs: nounwind +define i32* @test4(i32* readonly %X, i32* nocapture %dest) #0 { + %Y = getelementptr i32* %X, i64 4 + %A = load i32* %Y, align 4 + store i32 %A, i32* %dest, align 4 + ret i32* %Y + +; CHECK-LABEL: @test4 +; CHECK: lwzu [[REG1:[0-9]+]], 16(3) +; CHECK: stw [[REG1]], 0(4) +; CHECK: blr +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/ldtoc-inv.ll b/test/CodeGen/PowerPC/ldtoc-inv.ll new file mode 100644 index 0000000..550747c --- /dev/null +++ b/test/CodeGen/PowerPC/ldtoc-inv.ll @@ -0,0 +1,39 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@phasor = external constant [4096 x i32] + +; Function Attrs: nounwind +define void @test(i32* nocapture %out, i32 zeroext %step_size) #0 { +entry: + %shl = shl i32 %step_size, 2 + %idxprom = zext i32 %shl to i64 + br label %for.body + +; Make sure that the TOC load has been hoisted out of the loop. +; CHECK-LABEL: @test +; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc@l +; CHECK: %for.body +; CHECK: blr + +for.body: ; preds = %entry, %for.body + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %0 = trunc i64 %indvars.iv to i32 + %shl1 = shl i32 %0, %step_size + %idxprom2 = sext i32 %shl1 to i64 + %arrayidx.sum = add nsw i64 %idxprom2, %idxprom + %arrayidx3 = getelementptr inbounds [4096 x i32]* @phasor, i64 0, i64 %arrayidx.sum + %1 = load i32* %arrayidx3, align 4 + %arrayidx5 = getelementptr inbounds i32* %out, i64 %indvars.iv + store i32 %1, i32* %arrayidx5, align 4 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 4 + %cmp = icmp slt i64 %indvars.iv.next, 1020 + br i1 %cmp, label %for.body, label %for.end + +for.end: ; preds = %for.body + ret void +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/loop-data-prefetch.ll b/test/CodeGen/PowerPC/loop-data-prefetch.ll new file mode 100644 index 0000000..8871481 --- /dev/null +++ b/test/CodeGen/PowerPC/loop-data-prefetch.ll @@ -0,0 +1,29 @@ +; RUN: llc -mcpu=a2 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-bgq-linux" + +; Function Attrs: nounwind +define void @foo(double* nocapture %a, double* nocapture readonly %b) #0 { +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] + %arrayidx = getelementptr inbounds double* %b, i64 %indvars.iv + %0 = load double* %arrayidx, align 8 + %add = fadd double %0, 1.000000e+00 + %arrayidx2 = getelementptr inbounds double* %a, i64 %indvars.iv + store double %add, double* %arrayidx2, align 8 + %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 + %exitcond = icmp eq i64 %indvars.iv.next, 1600 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void + +; CHECK-LABEL: @foo +; CHECK: dcbt +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll b/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll index 659cdf7..743cc62 100644 --- a/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll +++ b/test/CodeGen/PowerPC/mult-alt-generic-powerpc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 +; RUN: llc < %s -march=ppc32 -no-integrated-as ; ModuleID = 'mult-alt-generic.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" target triple = "powerpc" diff --git a/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll b/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll index 3da06f6..29a5786 100644 --- a/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll +++ b/test/CodeGen/PowerPC/mult-alt-generic-powerpc64.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 +; RUN: llc < %s -march=ppc64 -no-integrated-as ; ModuleID = 'mult-alt-generic.c' target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64" diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r0.ll b/test/CodeGen/PowerPC/named-reg-alloc-r0.ll index e683f99..b669c35 100644 --- a/test/CodeGen/PowerPC/named-reg-alloc-r0.ll +++ b/test/CodeGen/PowerPC/named-reg-alloc-r0.ll @@ -12,4 +12,4 @@ entry: declare i32 @llvm.read_register.i32(metadata) nounwind -!0 = metadata !{metadata !"r0\00"} +!0 = !{!"r0\00"} diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r1-64.ll b/test/CodeGen/PowerPC/named-reg-alloc-r1-64.ll index b047f9f..419e12c 100644 --- a/test/CodeGen/PowerPC/named-reg-alloc-r1-64.ll +++ b/test/CodeGen/PowerPC/named-reg-alloc-r1-64.ll @@ -15,4 +15,4 @@ entry: declare i64 @llvm.read_register.i64(metadata) nounwind -!0 = metadata !{metadata !"r1\00"} +!0 = !{!"r1\00"} diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r1.ll b/test/CodeGen/PowerPC/named-reg-alloc-r1.ll index 9d0eb34..3ccab8c 100644 --- a/test/CodeGen/PowerPC/named-reg-alloc-r1.ll +++ b/test/CodeGen/PowerPC/named-reg-alloc-r1.ll @@ -17,4 +17,4 @@ entry: declare i32 @llvm.read_register.i32(metadata) nounwind -!0 = metadata !{metadata !"r1\00"} +!0 = !{!"r1\00"} diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r13-64.ll b/test/CodeGen/PowerPC/named-reg-alloc-r13-64.ll index df5085b..74e31fdd 100644 --- a/test/CodeGen/PowerPC/named-reg-alloc-r13-64.ll +++ b/test/CodeGen/PowerPC/named-reg-alloc-r13-64.ll @@ -15,4 +15,4 @@ entry: declare i64 @llvm.read_register.i64(metadata) nounwind -!0 = metadata !{metadata !"r13\00"} +!0 = !{!"r13\00"} diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r13.ll b/test/CodeGen/PowerPC/named-reg-alloc-r13.ll index 900ebb2..314f5d5 100644 --- a/test/CodeGen/PowerPC/named-reg-alloc-r13.ll +++ b/test/CodeGen/PowerPC/named-reg-alloc-r13.ll @@ -15,4 +15,4 @@ entry: declare i32 @llvm.read_register.i32(metadata) nounwind -!0 = metadata !{metadata !"r13\00"} +!0 = !{!"r13\00"} diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll b/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll index 0da33fa..834df8b 100644 --- a/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll +++ b/test/CodeGen/PowerPC/named-reg-alloc-r2-64.ll @@ -1,17 +1,14 @@ -; RUN: not llc < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=powerpc64-apple-darwin 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s define i64 @get_reg() nounwind { entry: ; FIXME: Include an allocatable-specific error message -; CHECK-DARWIN: Invalid register name global variable +; CHECK: Invalid register name global variable %reg = call i64 @llvm.read_register.i64(metadata !0) ret i64 %reg - -; CHECK-LABEL: @get_reg -; CHECK: mr 3, 2 } declare i64 @llvm.read_register.i64(metadata) nounwind -!0 = metadata !{metadata !"r2\00"} +!0 = !{!"r2\00"} diff --git a/test/CodeGen/PowerPC/named-reg-alloc-r2.ll b/test/CodeGen/PowerPC/named-reg-alloc-r2.ll index 51e7e3e..45d9816 100644 --- a/test/CodeGen/PowerPC/named-reg-alloc-r2.ll +++ b/test/CodeGen/PowerPC/named-reg-alloc-r2.ll @@ -1,11 +1,11 @@ -; RUN: not llc < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-DARWIN +; RUN: not llc < %s -mtriple=powerpc-apple-darwin 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32 ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu 2>&1 | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s --check-prefix=CHECK-NOTPPC32 define i32 @get_reg() nounwind { entry: ; FIXME: Include an allocatable-specific error message -; CHECK-DARWIN: Invalid register name global variable +; CHECK-NOTPPC32: Invalid register name global variable %reg = call i32 @llvm.read_register.i32(metadata !0) ret i32 %reg @@ -15,4 +15,4 @@ entry: declare i32 @llvm.read_register.i32(metadata) nounwind -!0 = metadata !{metadata !"r2\00"} +!0 = !{!"r2\00"} diff --git a/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll b/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll new file mode 100644 index 0000000..6beee25 --- /dev/null +++ b/test/CodeGen/PowerPC/no-extra-fp-conv-ldst.ll @@ -0,0 +1,96 @@ +; RUN: llc -mcpu=a2 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readonly +define double @test1(i64* nocapture readonly %x) #0 { +entry: + %0 = load i64* %x, align 8 + %conv = sitofp i64 %0 to double + ret double %conv + +; CHECK-LABEL: @test1 +; CHECK: lfd [[REG1:[0-9]+]], 0(3) +; CHECK: fcfid 1, [[REG1]] +; CHECK: blr +} + +; Function Attrs: nounwind readonly +define double @test2(i32* nocapture readonly %x) #0 { +entry: + %0 = load i32* %x, align 4 + %conv = sitofp i32 %0 to double + ret double %conv + +; CHECK-LABEL: @test2 +; CHECK: lfiwax [[REG1:[0-9]+]], 0, 3 +; CHECK: fcfid 1, [[REG1]] +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define float @foo(float %X) #0 { +entry: + %conv = fptosi float %X to i32 + %conv1 = sitofp i32 %conv to float + ret float %conv1 + +; CHECK-LABEL: @foo +; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1 +; CHECK-DAG: addi [[REG1:[0-9]+]], 1, +; CHECK: stfiwx [[REG2]], 0, [[REG1]] +; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]] +; CHECK: fcfids 1, [[REG3]] +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define double @food(double %X) #0 { +entry: + %conv = fptosi double %X to i32 + %conv1 = sitofp i32 %conv to double + ret double %conv1 + +; CHECK-LABEL: @food +; CHECK-DAG: fctiwz [[REG2:[0-9]+]], 1 +; CHECK-DAG: addi [[REG1:[0-9]+]], 1, +; CHECK: stfiwx [[REG2]], 0, [[REG1]] +; CHECK: lfiwax [[REG3:[0-9]+]], 0, [[REG1]] +; CHECK: fcfid 1, [[REG3]] +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define float @foou(float %X) #0 { +entry: + %conv = fptoui float %X to i32 + %conv1 = uitofp i32 %conv to float + ret float %conv1 + +; CHECK-LABEL: @foou +; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1 +; CHECK-DAG: addi [[REG1:[0-9]+]], 1, +; CHECK: stfiwx [[REG2]], 0, [[REG1]] +; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]] +; CHECK: fcfidus 1, [[REG3]] +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define double @fooud(double %X) #0 { +entry: + %conv = fptoui double %X to i32 + %conv1 = uitofp i32 %conv to double + ret double %conv1 + +; CHECK-LABEL: @fooud +; CHECK-DAG: fctiwuz [[REG2:[0-9]+]], 1 +; CHECK-DAG: addi [[REG1:[0-9]+]], 1, +; CHECK: stfiwx [[REG2]], 0, [[REG1]] +; CHECK: lfiwzx [[REG3:[0-9]+]], 0, [[REG1]] +; CHECK: fcfidu 1, [[REG3]] +; CHECK: blr +} + +attributes #0 = { nounwind readonly } + diff --git a/test/CodeGen/PowerPC/no-pref-jumps.ll b/test/CodeGen/PowerPC/no-pref-jumps.ll new file mode 100644 index 0000000..d9490f1 --- /dev/null +++ b/test/CodeGen/PowerPC/no-pref-jumps.ll @@ -0,0 +1,36 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo(i32 signext %a, i32 signext %b) #0 { +entry: + %cmp = icmp sgt i32 %a, 5 + %cmp1 = icmp slt i32 %b, 3 + %or.cond = or i1 %cmp, %cmp1 + br i1 %or.cond, label %if.then, label %if.else + +; CHECK-LABEL: @foo +; CHECK: cmpwi +; CHECK: cmpwi +; CHECK: cror +; CHECK: blr + +if.then: ; preds = %entry + tail call void bitcast (void (...)* @bar to void ()*)() #0 + br label %if.end + +if.else: ; preds = %entry + tail call void bitcast (void (...)* @car to void ()*)() #0 + br label %if.end + +if.end: ; preds = %if.else, %if.then + ret void +} + +declare void @bar(...) + +declare void @car(...) + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/p8-isel-sched.ll b/test/CodeGen/PowerPC/p8-isel-sched.ll new file mode 100644 index 0000000..034fe3c --- /dev/null +++ b/test/CodeGen/PowerPC/p8-isel-sched.ll @@ -0,0 +1,33 @@ +; RUN: llc -mcpu=pwr8 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @foo(i32* nocapture %r1, i32* nocapture %r2, i32* nocapture %r3, i32* nocapture %r4, i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) #0 { +entry: + %tobool = icmp ne i32 %a, 0 + %cond = select i1 %tobool, i32 %b, i32 %c + store i32 %cond, i32* %r1, align 4 + %cond5 = select i1 %tobool, i32 %b, i32 %d + store i32 %cond5, i32* %r2, align 4 + %add = add nsw i32 %b, 1 + %sub = add nsw i32 %d, -2 + %cond10 = select i1 %tobool, i32 %add, i32 %sub + store i32 %cond10, i32* %r3, align 4 + %add13 = add nsw i32 %b, 3 + %sub15 = add nsw i32 %d, -5 + %cond17 = select i1 %tobool, i32 %add13, i32 %sub15 + store i32 %cond17, i32* %r4, align 4 + ret void +} + +; Make sure that we don't schedule all of the isels together, they should be +; intermixed with the adds because each isel starts a new dispatch group. +; CHECK-LABEL: @foo +; CHECK: isel +; CHECK: addi +; CHECK: isel +; CHECK: blr + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/post-ra-ec.ll b/test/CodeGen/PowerPC/post-ra-ec.ll new file mode 100644 index 0000000..9c61677 --- /dev/null +++ b/test/CodeGen/PowerPC/post-ra-ec.ll @@ -0,0 +1,47 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.inode.0.12.120 = type { i8* } +%struct.kstat2.1.13.121 = type { i32 } +%struct.task_struct.4.16.124 = type { i8*, %struct.atomic_t.2.14.122, %struct.signal_struct.3.15.123* } +%struct.atomic_t.2.14.122 = type { i32 } +%struct.signal_struct.3.15.123 = type { i64 } +%struct.pid.5.17.125 = type { i8* } + +; Function Attrs: nounwind +define signext i32 @proc_task_getattr(%struct.inode.0.12.120* nocapture readonly %inode, %struct.kstat2.1.13.121* nocapture %stat) #0 { +entry: + %call1.i = tail call %struct.task_struct.4.16.124* @get_pid_task(%struct.pid.5.17.125* undef, i32 zeroext 0) #0 + br i1 undef, label %if.end, label %if.then + +if.then: ; preds = %entry + %0 = load i64* undef, align 8 + %conv.i = trunc i64 %0 to i32 + %1 = load i32* null, align 4 + %add = add i32 %1, %conv.i + store i32 %add, i32* null, align 4 + %counter.i.i = getelementptr inbounds %struct.task_struct.4.16.124* %call1.i, i64 0, i32 1, i32 0 + %2 = tail call i32 asm sideeffect "\09lwsync\0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0A\09sync\0A", "=&r,r,~{cr0},~{xer},~{memory}"(i32* %counter.i.i) #0 + %cmp.i = icmp eq i32 %2, 0 + br i1 %cmp.i, label %if.then.i, label %if.end + +; CHECK-LABEL: @proc_task_getattr +; CHECK-NOT: stwcx. [[REG:[0-9]+]],0,[[REG]] +; CHECK: blr + +if.then.i: ; preds = %if.then + %3 = bitcast %struct.task_struct.4.16.124* %call1.i to i8* + tail call void @foo(i8* %3) #0 + unreachable + +if.end: ; preds = %if.then, %entry + ret i32 0 +} + +declare void @foo(i8*) + +declare %struct.task_struct.4.16.124* @get_pid_task(%struct.pid.5.17.125*, i32 zeroext) + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/ppc32-cyclecounter.ll b/test/CodeGen/PowerPC/ppc32-cyclecounter.ll new file mode 100644 index 0000000..9e2cd0b --- /dev/null +++ b/test/CodeGen/PowerPC/ppc32-cyclecounter.ll @@ -0,0 +1,20 @@ +target datalayout = "E-m:e-p:32:32-i64:64-n32" +target triple = "powerpc" +; RUN: llc -mcpu=ppc < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s + +define i64 @test1() nounwind { +entry: + %r = call i64 @llvm.readcyclecounter() + ret i64 %r +} + +; CHECK: @test1 +; CHECK: mfspr 3, 269 +; CHECK: mfspr 4, 268 +; CHECK: mfspr [[REG:[0-9]+]], 269 +; CHECK: cmpw [[CR:[0-9]+]], 3, [[REG]] +; CHECK: bne [[CR]], .LBB + +declare i64 @llvm.readcyclecounter() + diff --git a/test/CodeGen/PowerPC/ppc32-lshrti3.ll b/test/CodeGen/PowerPC/ppc32-lshrti3.ll index 6e76fea..f773cce 100644 --- a/test/CodeGen/PowerPC/ppc32-lshrti3.ll +++ b/test/CodeGen/PowerPC/ppc32-lshrti3.ll @@ -36,4 +36,4 @@ attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "no-frame-pointe !llvm.ident = !{!0} -!0 = metadata !{metadata !"clang version 3.5.0 (213754)"} +!0 = !{!"clang version 3.5.0 (213754)"} diff --git a/test/CodeGen/PowerPC/ppc32-pic-large.ll b/test/CodeGen/PowerPC/ppc32-pic-large.ll index ecc4f10..bb906ec 100644 --- a/test/CodeGen/PowerPC/ppc32-pic-large.ll +++ b/test/CodeGen/PowerPC/ppc32-pic-large.ll @@ -1,23 +1,29 @@ ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=LARGE-BSS %s @bar = common global i32 0, align 4 +declare i32 @call_foo(i32, ...) + define i32 @foo() { entry: %0 = load i32* @bar, align 4 + %call = call i32 (i32, ...)* @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64) ret i32 %0 } !llvm.module.flags = !{!0} -!0 = metadata !{i32 1, metadata !"PIC Level", i32 2} +!0 = !{i32 1, !"PIC Level", i32 2} ; LARGE-BSS: [[POFF:\.L[0-9]+\$poff]]: ; LARGE-BSS-NEXT: .long .LTOC-[[PB:\.L[0-9]+\$pb]] ; LARGE-BSS-NEXT: foo: +; LARGE-BSS: stw 30, -8(1) ; LARGE-BSS: bl [[PB]] ; LARGE-BSS-NEXT: [[PB]]: ; LARGE-BSS: mflr 30 ; LARGE-BSS: lwz [[REG:[0-9]+]], [[POFF]]-[[PB]](30) ; LARGE-BSS-NEXT: add 30, [[REG]], 30 -; LARGE-BSS: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30) -; LARGE-BSS: lwz {{[0-9]+}}, 0([[VREG]]) +; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30) +; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]]) +; LARGE-BSS-DAG: stw {{[0-9]+}}, 8(1) +; LARGE-BSS: lwz 30, -8(1) ; LARGE-BSS: [[VREF]]: ; LARGE-BSS-NEXT: .long bar diff --git a/test/CodeGen/PowerPC/ppc32-pic.ll b/test/CodeGen/PowerPC/ppc32-pic.ll index f9c3467..abc1367 100644 --- a/test/CodeGen/PowerPC/ppc32-pic.ll +++ b/test/CodeGen/PowerPC/ppc32-pic.ll @@ -1,16 +1,24 @@ ; RUN: llc < %s -mtriple=powerpc-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=SMALL-BSS %s @bar = common global i32 0, align 4 +declare i32 @call_foo(i32, ...) + define i32 @foo() { entry: %0 = load i32* @bar, align 4 - ret i32 %0 + %call = call i32 (i32, ...)* @call_foo(i32 %0, i32 0, i32 1, i32 2, i32 4, i32 8, i32 16, i32 32, i32 64) + ret i32 0 } !llvm.module.flags = !{!0} -!0 = metadata !{i32 1, metadata !"PIC Level", i32 1} +!0 = !{i32 1, !"PIC Level", i32 1} ; SMALL-BSS-LABEL:foo: +; SMALL-BSS: stw 30, -8(1) +; SMALL-BSS: stwu 1, -32(1) ; SMALL-BSS: bl _GLOBAL_OFFSET_TABLE_@local-4 ; SMALL-BSS: mflr 30 -; SMALL-BSS: lwz [[VREG:[0-9]+]], bar@GOT(30) -; SMALL-BSS: lwz {{[0-9]+}}, 0([[VREG]]) +; SMALL-BSS-DAG: stw {{[0-9]+}}, 8(1) +; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30) +; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]]) +; SMALL-BSS: bl call_foo@PLT +; SMALL-BSS: lwz 30, -8(1) diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll b/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll new file mode 100644 index 0000000..479c7a7 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-anyregcc-crash.ll @@ -0,0 +1,19 @@ +; RUN: not llc < %s -mtriple=powerpc64-unknown-linux-gnu 2>&1 | FileCheck %s +; +; Check that misuse of anyregcc results in a compile time error. + +; CHECK: LLVM ERROR: ran out of registers during register allocation +define i64 @anyreglimit(i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8, + i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16, + i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24, + i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) { +entry: + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 15, i8* inttoptr (i64 0 to i8*), i32 32, + i64 %v1, i64 %v2, i64 %v3, i64 %v4, i64 %v5, i64 %v6, i64 %v7, i64 %v8, + i64 %v9, i64 %v10, i64 %v11, i64 %v12, i64 %v13, i64 %v14, i64 %v15, i64 %v16, + i64 %v17, i64 %v18, i64 %v19, i64 %v20, i64 %v21, i64 %v22, i64 %v23, i64 %v24, + i64 %v25, i64 %v26, i64 %v27, i64 %v28, i64 %v29, i64 %v30, i64 %v31, i64 %v32) + ret i64 %result +} + +declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) diff --git a/test/CodeGen/PowerPC/ppc64-anyregcc.ll b/test/CodeGen/PowerPC/ppc64-anyregcc.ll new file mode 100644 index 0000000..8b4cec5 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-anyregcc.ll @@ -0,0 +1,367 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Stackmap Header: no constants - 6 callsites +; CHECK-LABEL: .section .llvm_stackmaps +; CHECK-NEXT: __LLVM_StackMaps: +; Header +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 0 +; Num Functions +; CHECK-NEXT: .long 8 +; Num LargeConstants +; CHECK-NEXT: .long 0 +; Num Callsites +; CHECK-NEXT: .long 8 + +; Functions and stack size +; CHECK-NEXT: .quad test +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad property_access1 +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad property_access2 +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad property_access3 +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad anyreg_test1 +; CHECK-NEXT: .quad 144 +; CHECK-NEXT: .quad anyreg_test2 +; CHECK-NEXT: .quad 144 +; CHECK-NEXT: .quad patchpoint_spilldef +; CHECK-NEXT: .quad 256 +; CHECK-NEXT: .quad patchpoint_spillargs +; CHECK-NEXT: .quad 288 + + +; test +; CHECK-LABEL: .long .L{{.*}}-.L.test +; CHECK-NEXT: .short 0 +; 3 locations +; CHECK-NEXT: .short 3 +; Loc 0: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 2: Constant 3 +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 3 +define i64 @test() nounwind ssp uwtable { +entry: + call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 0, i32 24, i8* null, i32 2, i32 1, i32 2, i64 3) + ret i64 0 +} + +; property access 1 - %obj is an anyreg call argument and should therefore be in a register +; CHECK-LABEL: .long .L{{.*}}-.L.property_access1 +; CHECK-NEXT: .short 0 +; 2 locations +; CHECK-NEXT: .short 2 +; Loc 0: Register <-- this is the return register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define i64 @property_access1(i8* %obj) nounwind ssp uwtable { +entry: + %f = inttoptr i64 281474417671919 to i8* + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 1, i32 24, i8* %f, i32 1, i8* %obj) + ret i64 %ret +} + +; property access 2 - %obj is an anyreg call argument and should therefore be in a register +; CHECK-LABEL: .long .L{{.*}}-.L.property_access2 +; CHECK-NEXT: .short 0 +; 2 locations +; CHECK-NEXT: .short 2 +; Loc 0: Register <-- this is the return register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define i64 @property_access2() nounwind ssp uwtable { +entry: + %obj = alloca i64, align 8 + %f = inttoptr i64 281474417671919 to i8* + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %f, i32 1, i64* %obj) + ret i64 %ret +} + +; property access 3 - %obj is a frame index +; CHECK-LABEL: .long .L{{.*}}-.L.property_access3 +; CHECK-NEXT: .short 0 +; 2 locations +; CHECK-NEXT: .short 2 +; Loc 0: Register <-- this is the return register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Direct FP - 8 +; CHECK-NEXT: .byte 2 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 31 +; CHECK-NEXT: .long 112 +define i64 @property_access3() nounwind ssp uwtable { +entry: + %obj = alloca i64, align 8 + %f = inttoptr i64 281474417671919 to i8* + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 24, i8* %f, i32 0, i64* %obj) + ret i64 %ret +} + +; anyreg_test1 +; CHECK-LABEL: .long .L{{.*}}-.L.anyreg_test1 +; CHECK-NEXT: .short 0 +; 14 locations +; CHECK-NEXT: .short 14 +; Loc 0: Register <-- this is the return register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 2: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 3: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 4: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 5: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 6: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 7: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 8: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 9: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 10: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 11: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 12: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 13: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define i64 @anyreg_test1(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { +entry: + %f = inttoptr i64 281474417671919 to i8* + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 4, i32 24, i8* %f, i32 13, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) + ret i64 %ret +} + +; anyreg_test2 +; CHECK-LABEL: .long .L{{.*}}-.L.anyreg_test2 +; CHECK-NEXT: .short 0 +; 14 locations +; CHECK-NEXT: .short 14 +; Loc 0: Register <-- this is the return register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 2: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 3: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 4: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 5: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 6: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 7: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 8: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 9: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 10: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 11: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 12: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 13: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define i64 @anyreg_test2(i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) nounwind ssp uwtable { +entry: + %f = inttoptr i64 281474417671919 to i8* + %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %f, i32 8, i8* %a1, i8* %a2, i8* %a3, i8* %a4, i8* %a5, i8* %a6, i8* %a7, i8* %a8, i8* %a9, i8* %a10, i8* %a11, i8* %a12, i8* %a13) + ret i64 %ret +} + +; Test spilling the return value of an anyregcc call. +; +; <rdar://problem/15432754> [JS] Assertion: "Folded a def to a non-store!" +; +; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spilldef +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 3 +; Loc 0: Register (some register that will be spilled to the stack) +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define i64 @patchpoint_spilldef(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { +entry: + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 12, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2) + tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17 +},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind + ret i64 %result +} + +; Test spilling the arguments of an anyregcc call. +; +; <rdar://problem/15487687> [JS] AnyRegCC argument ends up being spilled +; +; CHECK-LABEL: .long .L{{.*}}-.L.patchpoint_spillargs +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 5 +; Loc 0: Return a register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 1: Arg0 in a Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 2: Arg1 in a Register +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; Loc 3: Arg2 spilled to FP -96 +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 31 +; CHECK-NEXT: .long 128 +; Loc 4: Arg3 spilled to FP - 88 +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 31 +; CHECK-NEXT: .long 136 +define i64 @patchpoint_spillargs(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { +entry: + tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17 +},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind + %result = tail call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 13, i32 24, i8* inttoptr (i64 0 to i8*), i32 2, i64 %p1, i64 %p2, i64 %p3, i64 %p4) + ret i64 %result +} + +declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) +declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) diff --git a/test/CodeGen/PowerPC/ppc64-calls.ll b/test/CodeGen/PowerPC/ppc64-calls.ll index 31794be..707ba95 100644 --- a/test/CodeGen/PowerPC/ppc64-calls.ll +++ b/test/CodeGen/PowerPC/ppc64-calls.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc64 | FileCheck %s +; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -67,3 +67,20 @@ define double @test_external(double %x) nounwind { ; CHECK-NEXT: nop ret double %call } + +; The 'ld 2, 40(1)' really must always come directly after the bctrl to make +; the unwinding code in libgcc happy. +@g = external global void ()* +declare void @h(i64) +define void @test_indir_toc_reload(i64 %x) { + %1 = load void ()** @g + call void %1() + call void @h(i64 %x) + ret void + +; CHECK-LABEL: @test_indir_toc_reload +; CHECK: bctrl +; CHECK-NEXT: ld 2, 40(1) +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/ppc64-elf-abi.ll b/test/CodeGen/PowerPC/ppc64-elf-abi.ll index d82122d..5344337 100644 --- a/test/CodeGen/PowerPC/ppc64-elf-abi.ll +++ b/test/CodeGen/PowerPC/ppc64-elf-abi.ll @@ -1,9 +1,9 @@ ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-ELFv1 -; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mattr=+elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1 -; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mattr=+elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2 +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1 +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -target-abi elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2 ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK-ELFv2 -; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=+elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1 -; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mattr=+elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2 +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv1 < %s | FileCheck %s -check-prefix=CHECK-ELFv1 +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -target-abi elfv2 < %s | FileCheck %s -check-prefix=CHECK-ELFv2 ; CHECK-ELFv2: .abiversion 2 ; CHECK-ELFv1-NOT: .abiversion 2 diff --git a/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll b/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll new file mode 100644 index 0000000..941513f --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll @@ -0,0 +1,56 @@ +; RUN: llc -mcpu=pwr7 -mattr=-vsx -fast-isel -fast-isel-abort < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define fastcc i64 @g1(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { + ret i64 %g1 + +; CHECK-LABEL: @g1 +; CHECK-NOT: mr 3, +; CHECK: blr +} + +define fastcc i64 @g2(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { + ret i64 %g2 + +; CHECK-LABEL: @g2 +; CHECK: mr 3, 4 +; CHECK-NEXT: blr +} + +define fastcc i64 @g3(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { + ret i64 %g3 + +; CHECK-LABEL: @g3 +; CHECK: mr 3, 5 +; CHECK-NEXT: blr +} + +define fastcc double @f2(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { + ret double %f2 + +; CHECK-LABEL: @f2 +; CHECK: fmr 1, 2 +; CHECK-NEXT: blr +} + +define void @cg2(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, i64 %v, double 0.0, i64 0, double 0.0, i64 0, double 0.0) + ret void + +; CHECK-LABEL: @cg2 +; CHECK: mr 4, 3 +; CHECK: blr +} + +define void @cf2(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, i64 0, double %v, i64 0, double 0.0, i64 0, double 0.0) + ret void + +; CHECK-LABEL: @cf2 +; CHECK: mr 2, 1 +; CHECK: blr +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/ppc64-fastcc.ll b/test/CodeGen/PowerPC/ppc64-fastcc.ll new file mode 100644 index 0000000..bb1365a --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-fastcc.ll @@ -0,0 +1,540 @@ +; RUN: llc -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define fastcc i64 @g1(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g1 + +; CHECK-LABEL: @g1 +; CHECK-NOT: mr 3, +; CHECK: blr +} + +define fastcc i64 @g2(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g2 + +; CHECK-LABEL: @g2 +; CHECK: mr 3, 4 +; CHECK-NEXT: blr +} + +define fastcc i64 @g3(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g3 + +; CHECK-LABEL: @g3 +; CHECK: mr 3, 5 +; CHECK-NEXT: blr +} + +define fastcc i64 @g4(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g4 + +; CHECK-LABEL: @g4 +; CHECK: mr 3, 6 +; CHECK-NEXT: blr +} + +define fastcc i64 @g5(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g5 + +; CHECK-LABEL: @g5 +; CHECK: mr 3, 7 +; CHECK-NEXT: blr +} + +define fastcc i64 @g6(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g6 + +; CHECK-LABEL: @g6 +; CHECK: mr 3, 8 +; CHECK-NEXT: blr +} + +define fastcc i64 @g7(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g7 + +; CHECK-LABEL: @g7 +; CHECK: mr 3, 9 +; CHECK-NEXT: blr +} + +define fastcc i64 @g8(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g8 + +; CHECK-LABEL: @g8 +; CHECK: mr 3, 10 +; CHECK-NEXT: blr +} + +define fastcc i64 @g9(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g9 + +; CHECK-LABEL: @g9 +; CHECK: ld 3, 48(1) +; CHECK-NEXT: blr +} + +define fastcc i64 @g10(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g10 + +; CHECK-LABEL: @g10 +; CHECK: ld 3, 56(1) +; CHECK-NEXT: blr +} + +define fastcc i64 @g11(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret i64 %g11 + +; CHECK-LABEL: @g11 +; CHECK: ld 3, 64(1) +; CHECK-NEXT: blr +} + +define fastcc double @f1(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f1 + +; CHECK-LABEL: @f1 +; CHECK-NOT: fmr 1, +; CHECK: blr +} + +define fastcc double @f2(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f2 + +; CHECK-LABEL: @f2 +; CHECK: fmr 1, 2 +; CHECK-NEXT: blr +} + +define fastcc double @f3(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f3 + +; CHECK-LABEL: @f3 +; CHECK: fmr 1, 3 +; CHECK-NEXT: blr +} + +define fastcc double @f4(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f4 + +; CHECK-LABEL: @f4 +; CHECK: fmr 1, 4 +; CHECK-NEXT: blr +} + +define fastcc double @f5(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f5 + +; CHECK-LABEL: @f5 +; CHECK: fmr 1, 5 +; CHECK-NEXT: blr +} + +define fastcc double @f6(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f6 + +; CHECK-LABEL: @f6 +; CHECK: fmr 1, 6 +; CHECK-NEXT: blr +} + +define fastcc double @f7(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f7 + +; CHECK-LABEL: @f7 +; CHECK: fmr 1, 7 +; CHECK-NEXT: blr +} + +define fastcc double @f8(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f8 + +; CHECK-LABEL: @f8 +; CHECK: fmr 1, 8 +; CHECK-NEXT: blr +} + +define fastcc double @f9(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f9 + +; CHECK-LABEL: @f9 +; CHECK: fmr 1, 9 +; CHECK-NEXT: blr +} + +define fastcc double @f10(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f10 + +; CHECK-LABEL: @f10 +; CHECK: fmr 1, 10 +; CHECK-NEXT: blr +} + +define fastcc double @f11(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f11 + +; CHECK-LABEL: @f11 +; CHECK: fmr 1, 11 +; CHECK-NEXT: blr +} + +define fastcc double @f12(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f12 + +; CHECK-LABEL: @f12 +; CHECK: fmr 1, 12 +; CHECK-NEXT: blr +} + +define fastcc double @f13(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f13 + +; CHECK-LABEL: @f13 +; CHECK: fmr 1, 13 +; CHECK-NEXT: blr +} + +define fastcc double @f14(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f14 + +; CHECK-LABEL: @f14 +; CHECK: lfd 1, 120(1) +; CHECK-NEXT: blr +} + +define fastcc double @f15(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret double %f15 + +; CHECK-LABEL: @f15 +; CHECK: lfd 1, 152(1) +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v1(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v1 + +; CHECK-LABEL: @v1 +; CHECK-NOT: vor 2, +; CHECK: blr +} + +define fastcc <4 x i32> @v2(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v2 + +; CHECK-LABEL: @v2 +; CHECK: vor 2, 3, 3 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v3(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v3 + +; CHECK-LABEL: @v3 +; CHECK: vor 2, 4, 4 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v4(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v4 + +; CHECK-LABEL: @v4 +; CHECK: vor 2, 5, 5 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v5(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v5 + +; CHECK-LABEL: @v5 +; CHECK: vor 2, 6, 6 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v6(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v6 + +; CHECK-LABEL: @v6 +; CHECK: vor 2, 7, 7 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v7(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v7 + +; CHECK-LABEL: @v7 +; CHECK: vor 2, 8, 8 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v8(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v8 + +; CHECK-LABEL: @v8 +; CHECK: vor 2, 9, 9 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v9(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v9 + +; CHECK-LABEL: @v9 +; CHECK: vor 2, 10, 10 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v10(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v10 + +; CHECK-LABEL: @v10 +; CHECK: vor 2, 11, 11 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v11(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v11 + +; CHECK-LABEL: @v11 +; CHECK: vor 2, 12, 12 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v12(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v12 + +; CHECK-LABEL: @v12 +; CHECK: vor 2, 13, 13 +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v13(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v13 + +; CHECK-LABEL: @v13 +; CHECK: addi [[REG1:[0-9]+]], 1, 96 +; CHECK-NEXT: lvx 2, 0, [[REG1]] +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v14(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v14 + +; CHECK-LABEL: @v14 +; CHECK: addi [[REG1:[0-9]+]], 1, 128 +; CHECK-NEXT: lvx 2, 0, [[REG1]] +; CHECK-NEXT: blr +} + +define fastcc <4 x i32> @v15(i64 %g1, double %f1, <4 x i32> %v1, i64 %g2, double %f2, <4 x i32> %v2, i64 %g3, double %f3, <4 x i32> %v3, i64 %g4, double %f4, <4 x i32> %v4, i64 %g5, double %f5, <4 x i32> %v5, i64 %g6, double %f6, <4 x i32> %v6, i64 %g7, double %f7, <4 x i32> %v7, i64 %g8, double %f8, <4 x i32> %v8, i64 %g9, double %f9, <4 x i32> %v9, i64 %g10, double %f10, <4 x i32> %v10, i64 %g11, double %f11, <4 x i32> %v11, i64 %g12, double %f12, <4 x i32> %v12, i64 %g13, double %f13, <4 x i32> %v13, i64 %g14, double %f14, <4 x i32> %v14, i64 %g15, double %f15, <4 x i32> %v15, i64 %g16, double %f16, <4 x i32> %v16) #0 { + ret <4 x i32> %v15 + +; CHECK-LABEL: @v15 +; CHECK: addi [[REG1:[0-9]+]], 1, 160 +; CHECK-NEXT: lvx 2, 0, [[REG1]] +; CHECK-NEXT: blr +} + +define void @cg1(i64 %v) #0 { + tail call fastcc i64 @g1(i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg1 +; CHECK-NOT: {{^[ \t]*}}mr 3, +; CHECK: blr +} + +define void @cg2(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg2 +; CHECK: mr 4, 3 +; CHECK: blr +} + +define void @cg3(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg3 +; CHECK: mr 5, 3 +; CHECK: blr +} + +define void @cg4(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg4 +; CHECK: mr 6, 3 +; CHECK: blr +} + +define void @cg5(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg5 +; CHECK: mr 7, 3 +; CHECK: blr +} + +define void @cg6(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg6 +; CHECK: mr 8, 3 +; CHECK: blr +} + +define void @cg7(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg7 +; CHECK: mr 9, 3 +; CHECK: blr +} + +define void @cg8(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg8 +; CHECK: mr 10, 3 +; CHECK: blr +} + +define void @cg9(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg9 +; CHECK: mr [[REG1:[0-9]+]], 3 +; CHECK: std [[REG1]], 48(1) +; CHECK: blr +} + +define void @cg10(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg10 +; CHECK: mr [[REG1:[0-9]+]], 3 +; CHECK: std [[REG1]], 56(1) +; CHECK: blr +} + +define void @cg11(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 %v, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cg11 +; CHECK: mr [[REG1:[0-9]+]], 3 +; CHECK: std [[REG1]], 64(1) +; CHECK: blr +} + +define void @cf1(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cf1 +; CHECK-NOT: fmr 1, +; CHECK: blr +} + +define void @cf2(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cf2 +; CHECK: fmr 2, 1 +; CHECK: blr +} + +define void @cf3(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cf3 +; CHECK: fmr 3, 1 +; CHECK: blr +} + +define void @cf4(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cf4 +; CHECK: fmr 4, 1 +; CHECK: blr +} + +define void @cf5(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cf5 +; CHECK: fmr 5, 1 +; CHECK: blr +} + +define void @cf14(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cf14 +; CHECK: stfd 1, 120(1) +; CHECK: blr +} + +define void @cf15(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double %v, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cf15 +; CHECK: stfd 1, 152(1) +; CHECK: blr +} + +define void @cv2(<4 x i32> %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> %v, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cv2 +; CHECK: vor 3, 2, 2 +; CHECK: blr +} + +define void @cv3(<4 x i32> %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> %v, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cv3 +; CHECK: vor 4, 2, 2 +; CHECK: blr +} + +define void @cv13(<4 x i32> %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> %v, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cv13 +; CHECK: li [[REG1:[0-9]+]], 96 +; CHECK: stvx 2, 1, [[REG1]] +; CHECK: blr +} + +define void @cv14(<4 x i32> %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> %v, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, i64 0, double 0.0, <4 x i32> <i32 0, i32 0, i32 0, i32 0>) + ret void + +; CHECK-LABEL: @cv14 +; CHECK: li [[REG1:[0-9]+]], 128 +; CHECK: stvx 2, 1, [[REG1]] +; CHECK: blr +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll b/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll new file mode 100644 index 0000000..57577f9 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-func-desc-hoist.ll @@ -0,0 +1,47 @@ +; RUN: llc -mcpu=a2 < %s | FileCheck %s -check-prefix=INVFUNCDESC +; RUN: llc -mcpu=a2 -mattr=-invariant-function-descriptors < %s | FileCheck %s -check-prefix=NONINVFUNCDESC +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @bar(void (...)* nocapture %x) #0 { +entry: + %callee.knr.cast = bitcast void (...)* %x to void ()* + br label %for.body + +; INVFUNCDESC-LABEL: @bar +; INVFUNCDESC-DAG: ld [[REG1:[0-9]+]], 8(3) +; INVFUNCDESC-DAG: ld [[REG2:[0-9]+]], 16(3) +; INVFUNCDESC-DAG: ld [[REG3:[0-9]+]], 0(3) + +; INVFUNCDESC: %for.body +; INVFUNCDESC: std 2, 40(1) +; INVFUNCDESC-DAG: mtctr [[REG3]] +; INVFUNCDESC-DAG: mr 11, [[REG2]] +; INVFUNCDESC-DAG: mr 2, [[REG1]] +; INVFUNCDESC: bctrl +; INVFUNCDESC-NEXT: ld 2, 40(1) + +; NONINVFUNCDESC-LABEL: @bar +; NONINVFUNCDESC: %for.body +; NONINVFUNCDESC: std 2, 40(1) +; NONINVFUNCDESC-DAG: ld 3, 0(30) +; NONINVFUNCDESC-DAG: ld 11, 16(30) +; NONINVFUNCDESC-DAG: ld 2, 8(30) +; NONINVFUNCDESC: mtctr 3 +; NONINVFUNCDESC: bctrl +; NONINVFUNCDESC-NEXT: ld 2, 40(1) + +for.body: ; preds = %for.body, %entry + %i.02 = phi i32 [ 0, %entry ], [ %inc, %for.body ] + tail call void %callee.knr.cast() #0 + %inc = add nuw nsw i32 %i.02, 1 + %exitcond = icmp eq i32 %inc, 1600000000 + br i1 %exitcond, label %for.end, label %for.body + +for.end: ; preds = %for.body + ret void +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/ppc64-gep-opt.ll b/test/CodeGen/PowerPC/ppc64-gep-opt.ll new file mode 100644 index 0000000..14cf9a7 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-gep-opt.ll @@ -0,0 +1,157 @@ +; RUN: llc -O3 -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -O3 -print-after=codegenprepare -mcpu=ppc64 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-NoAA <%t %s +; RUN: llc -O3 -print-after=codegenprepare -mcpu=pwr7 < %s >%t 2>&1 && FileCheck --check-prefix=CHECK-UseAA <%t %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Following test cases test enabling SeparateConstOffsetFromGEP pass in the PPC +; backend. If useAA() returns true, it will lower a GEP with multiple indices +; into GEPs with a single index, otherwise it will lower it into a +; "ptrtoint+arithmetics+inttoptr" form. + +%struct = type { i32, i32, i32, i32, [20 x i32] } + +; Check that when two complex GEPs are used in two basic blocks, LLVM can +; elimilate the common subexpression for the second use. +define void @test_GEP_CSE([240 x %struct]* %string, i32* %adj, i32 %lib, i64 %idxprom) { + %liberties = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 3 + %1 = load i32* %liberties, align 4 + %cmp = icmp eq i32 %1, %lib + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + %origin = getelementptr [240 x %struct]* %string, i64 1, i64 %idxprom, i32 2 + %2 = load i32* %origin, align 4 + store i32 %2, i32* %adj, align 4 + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +} + +; CHECK-NoAA-LABEL: @test_GEP_CSE( +; CHECK-NoAA: [[PTR0:%[a-zA-Z0-9]+]] = ptrtoint [240 x %struct]* %string to i64 +; CHECK-NoAA: [[PTR1:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 +; CHECK-NoAA: [[PTR2:%[a-zA-Z0-9]+]] = add i64 [[PTR0]], [[PTR1]] +; CHECK-NoAA: add i64 [[PTR2]], 23052 +; CHECK-NoAA: inttoptr +; CHECK-NoAA: if.then: +; CHECK-NoAA-NOT: ptrtoint +; CHECK-NoAA-NOT: mul +; CHECK-NoAA: add i64 [[PTR2]], 23048 +; CHECK-NoAA: inttoptr + +; CHECK-UseAA-LABEL: @test_GEP_CSE( +; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = bitcast [240 x %struct]* %string to i8* +; CHECK-UseAA: [[IDX:%[a-zA-Z0-9]+]] = mul i64 %idxprom, 96 +; CHECK-UseAA: [[PTR1:%[a-zA-Z0-9]+]] = getelementptr i8* [[PTR0]], i64 [[IDX]] +; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23052 +; CHECK-UseAA: bitcast +; CHECK-UseAA: if.then: +; CHECK-UseAA: getelementptr i8* [[PTR1]], i64 23048 +; CHECK-UseAA: bitcast + +%class.my = type { i32, [128 x i32], i32, [256 x %struct.pt]} +%struct.pt = type { %struct.point*, i32, i32 } +%struct.point = type { i32, i32 } + +; Check when a GEP is used across two basic block, LLVM can sink the address +; calculation and code gen can generate a better addressing mode for the second +; use. +define void @test_GEP_across_BB(%class.my* %this, i64 %idx) { + %1 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 1 + %2 = load i32* %1, align 4 + %3 = getelementptr %class.my* %this, i64 0, i32 3, i64 %idx, i32 2 + %4 = load i32* %3, align 4 + %5 = icmp eq i32 %2, %4 + br i1 %5, label %if.true, label %exit + +if.true: + %6 = shl i32 %4, 1 + store i32 %6, i32* %3, align 4 + br label %exit + +exit: + %7 = add nsw i32 %4, 1 + store i32 %7, i32* %1, align 4 + ret void +} +; CHECK-LABEL: test_GEP_across_BB: +; CHECK-NOT: lwzu +; CHECK: blr + +; CHECK-NoAA-LABEL: test_GEP_across_BB( +; CHECK-NoAA: add i64 [[TMP:%[a-zA-Z0-9]+]], 528 +; CHECK-NoAA: add i64 [[TMP]], 532 +; CHECK-NoAA: if.true: +; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 532 +; CHECK-NoAA: exit: +; CHECK-NoAA: {{%sunk[a-zA-Z0-9]+}} = add i64 [[TMP]], 528 + +; CHECK-UseAA-LABEL: test_GEP_across_BB( +; CHECK-UseAA: [[PTR0:%[a-zA-Z0-9]+]] = getelementptr +; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 528 +; CHECK-UseAA: getelementptr i8* [[PTR0]], i64 532 +; CHECK-UseAA: if.true: +; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 532 +; CHECK-UseAA: exit: +; CHECK-UseAA: {{%sunk[a-zA-Z0-9]+}} = getelementptr i8* [[PTR0]], i64 528 + +%struct.S = type { float, double } +@struct_array = global [1024 x %struct.S] zeroinitializer, align 16 + +; The following two test cases check we can extract constant from indices of +; struct type. +; The constant offsets are from indices "i64 %idxprom" and "i32 1". As the +; alloca size of %struct.S is 16, and "i32 1" is the 2rd element whose field +; offset is 8, the total constant offset is (5 * 16 + 8) = 88. +define double* @test-struct_1(i32 %i) { +entry: + %add = add nsw i32 %i, 5 + %idxprom = sext i32 %add to i64 + %p = getelementptr [1024 x %struct.S]* @struct_array, i64 0, i64 %idxprom, i32 1 + ret double* %p +} +; CHECK-NoAA-LABEL: @test-struct_1( +; CHECK-NoAA-NOT: getelementptr +; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, 88 + +; CHECK-UseAA-LABEL: @test-struct_1( +; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 88 + +%struct3 = type { i64, i32 } +%struct2 = type { %struct3, i32 } +%struct1 = type { i64, %struct2 } +%struct0 = type { i32, i32, i64*, [100 x %struct1] } + +; The constant offsets are from indices "i32 3", "i64 %arrayidx" and "i32 1". +; "i32 3" is the 4th element whose field offset is 16. The alloca size of +; %struct1 is 32. "i32 1" is the 2rd element whose field offset is 8. So the +; total constant offset is 16 + (-2 * 32) + 8 = -40 +define %struct2* @test-struct_2(%struct0* %ptr, i64 %idx) { +entry: + %arrayidx = add nsw i64 %idx, -2 + %ptr2 = getelementptr %struct0* %ptr, i64 0, i32 3, i64 %arrayidx, i32 1 + ret %struct2* %ptr2 +} +; CHECK-NoAA-LABEL: @test-struct_2( +; CHECK-NoAA-NOT: = getelementptr +; CHECK-NoAA: add i64 %{{[a-zA-Z0-9]+}}, -40 + +; CHECK-UseAA-LABEL: @test-struct_2( +; CHECK-UseAA: getelementptr i8* %{{[a-zA-Z0-9]+}}, i64 -40 + +; Test that when a index is added from two constant, SeparateConstOffsetFromGEP +; pass does not generate incorrect result. +define void @test_const_add([3 x i32]* %in) { + %inc = add nsw i32 2, 1 + %idxprom = sext i32 %inc to i64 + %arrayidx = getelementptr [3 x i32]* %in, i64 %idxprom, i64 2 + store i32 0, i32* %arrayidx, align 4 + ret void +} +; CHECK-LABEL: test_const_add: +; CHECK: li [[REG:[0-9]+]], 0 +; CHECK: stw [[REG]], 44(3) +; CHECK: blr + diff --git a/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll b/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll new file mode 100644 index 0000000..e8617cc --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-icbt-pwr7.ll @@ -0,0 +1,19 @@ +; Test the ICBT instruction is not emitted on POWER7 +; Based on the ppc64-prefetch.ll test +; RUN: not llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s 2>&1 | FileCheck %s + +declare void @llvm.prefetch(i8*, i32, i32, i32) + +define void @test(i8* %a, ...) nounwind { +entry: + call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0) + ret void + +; FIXME: Crashing is not really the correct behavior here, we really should just emit nothing +; CHECK: Cannot select: 0x{{[0-9,a-f]+}}: ch = Prefetch +; CHECK: 0x{{[0-9,a-f]+}}: i32 = Constant<0> +; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<3> +; CHECK-NEXT: 0x{{[0-9,a-f]+}}: i32 = Constant<0> + +} + diff --git a/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll b/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll new file mode 100644 index 0000000..a0f084a --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-icbt-pwr8.ll @@ -0,0 +1,16 @@ +; Test the ICBT instruction on POWER8 +; Copied from the ppc64-prefetch.ll test +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s + +declare void @llvm.prefetch(i8*, i32, i32, i32) + +define void @test(i8* %a, ...) nounwind { +entry: + call void @llvm.prefetch(i8* %a, i32 0, i32 3, i32 0) + ret void + +; CHECK-LABEL: @test +; CHECK: icbt +} + + diff --git a/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll b/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll new file mode 100644 index 0000000..b1d3f39 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-nonfunc-calls.ll @@ -0,0 +1,69 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.cd = type { i64, i64, i64 } + +@something = global [33 x i8] c"this is not really code, but...\0A\00", align 1 +@tls_something = thread_local global %struct.cd zeroinitializer, align 8 +@extern_something = external global %struct.cd + +; Function Attrs: nounwind +define void @foo() #0 { +entry: + tail call void bitcast ([33 x i8]* @something to void ()*)() #0 + ret void + +; CHECK-LABEL: @foo +; CHECK-DAG: addis [[REG1:[0-9]+]], 2, something@toc@ha +; CHECK-DAG: std 2, 40(1) +; CHECK-DAG: addi [[REG3:[0-9]+]], [[REG1]], something@toc@l +; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]]) +; CHECK-DAG: ld 11, 16([[REG3]]) +; CHECK-DAG: ld 2, 8([[REG3]]) +; CHECK-DAG: mtctr [[REG2]] +; CHECK: bctrl +; CHECK: ld 2, 40(1) +; CHECK: blr +} + +; Function Attrs: nounwind +define void @bar() #0 { +entry: + tail call void bitcast (%struct.cd* @tls_something to void ()*)() #0 + ret void + +; CHECK-LABEL: @bar +; CHECK-DAG: addis [[REG1:[0-9]+]], 13, tls_something@tprel@ha +; CHECK-DAG: std 2, 40(1) +; CHECK-DAG: addi [[REG3:[0-9]+]], [[REG1]], tls_something@tprel@l +; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]]) +; CHECK-DAG: ld 11, 16([[REG3]]) +; CHECK-DAG: ld 2, 8([[REG3]]) +; CHECK-DAG: mtctr [[REG2]] +; CHECK: bctrl +; CHECK: ld 2, 40(1) +; CHECK: blr +} + +; Function Attrs: nounwind +define void @ext() #0 { +entry: + tail call void bitcast (%struct.cd* @extern_something to void ()*)() #0 + ret void + +; CHECK-LABEL: @ext +; CHECK-DAG: addis [[REG1:[0-9]+]], 2, [[NAME:[._A-Za-z0-9]+]]@toc@ha +; CHECK-DAG: std 2, 40(1) +; CHECK-DAG: ld [[REG3:[0-9]+]], [[NAME]]@toc@l(3) +; CHECK-DAG: ld [[REG2:[0-9]+]], 0([[REG3]]) +; CHECK-DAG: ld 11, 16([[REG3]]) +; CHECK-DAG: ld 2, 8([[REG3]]) +; CHECK-DAG: mtctr [[REG2]] +; CHECK: bctrl +; CHECK: ld 2, 40(1) +; CHECK: blr +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/ppc64-patchpoint.ll b/test/CodeGen/PowerPC/ppc64-patchpoint.ll new file mode 100644 index 0000000..6580eff --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-patchpoint.ll @@ -0,0 +1,97 @@ +; RUN: llc < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE +; RUN: llc -fast-isel -fast-isel-abort < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-BE +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -fast-isel -fast-isel-abort < %s | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK-LE + +target triple = "powerpc64-unknown-linux-gnu" + +; Trivial patchpoint codegen +; +define i64 @trivial_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { +entry: +; CHECK-LABEL: trivial_patchpoint_codegen: + +; CHECK: li 12, -8531 +; CHECK-NEXT: rldic 12, 12, 32, 16 +; CHECK-NEXT: oris 12, 12, 48879 +; CHECK-NEXT: ori 12, 12, 51966 +; CHECK-NEXT: mtctr 12 +; CHECK-NEXT: bctrl + +; CHECK: li 12, -8531 +; CHECK-NEXT: rldic 12, 12, 32, 16 +; CHECK-NEXT: oris 12, 12, 48879 +; CHECK-NEXT: ori 12, 12, 51967 +; CHECK-NEXT: mtctr 12 +; CHECK-NEXT: bctrl + +; CHECK: blr + + %resolveCall2 = inttoptr i64 244837814094590 to i8* + %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 24, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4) + %resolveCall3 = inttoptr i64 244837814094591 to i8* + tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 24, i8* %resolveCall3, i32 2, i64 %p1, i64 %result) + ret i64 %result +} + +; Caller frame metadata with stackmaps. This should not be optimized +; as a leaf function. +; +; CHECK-LABEL: caller_meta_leaf +; CHECK-BE: stdu 1, -80(1) +; CHECK-LE: stdu 1, -64(1) +; CHECK: Ltmp +; CHECK-BE: addi 1, 1, 80 +; CHECK-LE: addi 1, 1, 64 +; CHECK: blr + +define void @caller_meta_leaf() { +entry: + %metadata = alloca i64, i32 3, align 8 + store i64 11, i64* %metadata + store i64 12, i64* %metadata + store i64 13, i64* %metadata + call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 4, i32 0, i64* %metadata) + ret void +} + +; Test patchpoints reusing the same TargetConstant. +; <rdar:15390785> Assertion failed: (CI.getNumArgOperands() >= NumArgs + 4) +; There is no way to verify this, since it depends on memory allocation. +; But I think it's useful to include as a working example. +define i64 @testLowerConstant(i64 %arg, i64 %tmp2, i64 %tmp10, i64* %tmp33, i64 %tmp79) { +entry: + %tmp80 = add i64 %tmp79, -16 + %tmp81 = inttoptr i64 %tmp80 to i64* + %tmp82 = load i64* %tmp81, align 8 + tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 14, i32 8, i64 %arg, i64 %tmp2, i64 %tmp10, i64 %tmp82) + tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 15, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp82) + %tmp83 = load i64* %tmp33, align 8 + %tmp84 = add i64 %tmp83, -24 + %tmp85 = inttoptr i64 %tmp84 to i64* + %tmp86 = load i64* %tmp85, align 8 + tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 17, i32 8, i64 %arg, i64 %tmp10, i64 %tmp86) + tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 18, i32 32, i8* null, i32 3, i64 %arg, i64 %tmp10, i64 %tmp86) + ret i64 10 +} + +; Test small patchpoints that don't emit calls. +define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) { +entry: +; CHECK-LABEL: small_patchpoint_codegen: +; CHECK: Ltmp +; CHECK: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NOT: nop +; CHECK: blr + %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 20, i8* null, i32 2, i64 %p1, i64 %p2) + ret void +} + +declare void @llvm.experimental.stackmap(i64, i32, ...) +declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) +declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) + diff --git a/test/CodeGen/PowerPC/ppc64-r2-alloc.ll b/test/CodeGen/PowerPC/ppc64-r2-alloc.ll new file mode 100644 index 0000000..87292d8 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-r2-alloc.ll @@ -0,0 +1,81 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define signext i32 @foo(i32 signext %a, i32 signext %d) #0 { +entry: + %div = sdiv i32 %a, %d + %div1 = sdiv i32 %div, %d + %div2 = sdiv i32 %div1, %d + %div3 = sdiv i32 %div2, %d + %div4 = sdiv i32 %div3, %d + %div5 = sdiv i32 %div4, %d + %div6 = sdiv i32 %div5, %d + %div7 = sdiv i32 %div6, %d + %div8 = sdiv i32 %div7, %d + %div9 = sdiv i32 %div8, %d + %div10 = sdiv i32 %div9, %d + %div11 = sdiv i32 %div10, %d + %div12 = sdiv i32 %div11, %d + %div13 = sdiv i32 %div12, %d + %div14 = sdiv i32 %div13, %d + %div15 = sdiv i32 %div14, %d + %div16 = sdiv i32 %div15, %d + %div17 = sdiv i32 %div16, %d + %div18 = sdiv i32 %div17, %d + %div19 = sdiv i32 %div18, %d + %div20 = sdiv i32 %div19, %d + %div21 = sdiv i32 %div20, %d + %div22 = sdiv i32 %div21, %d + %div23 = sdiv i32 %div22, %d + %div24 = sdiv i32 %div23, %d + %div25 = sdiv i32 %div24, %d + %div26 = sdiv i32 %div25, %d + %div27 = sdiv i32 %div26, %d + %div28 = sdiv i32 %div27, %d + %div29 = sdiv i32 %div28, %d + %div30 = sdiv i32 %div29, %d + %div31 = sdiv i32 %div30, %d + %div32 = sdiv i32 %div31, %d + %div33 = sdiv i32 %div32, %div31 + %div34 = sdiv i32 %div33, %div30 + %div35 = sdiv i32 %div34, %div29 + %div36 = sdiv i32 %div35, %div28 + %div37 = sdiv i32 %div36, %div27 + %div38 = sdiv i32 %div37, %div26 + %div39 = sdiv i32 %div38, %div25 + %div40 = sdiv i32 %div39, %div24 + %div41 = sdiv i32 %div40, %div23 + %div42 = sdiv i32 %div41, %div22 + %div43 = sdiv i32 %div42, %div21 + %div44 = sdiv i32 %div43, %div20 + %div45 = sdiv i32 %div44, %div19 + %div46 = sdiv i32 %div45, %div18 + %div47 = sdiv i32 %div46, %div17 + %div48 = sdiv i32 %div47, %div16 + %div49 = sdiv i32 %div48, %div15 + %div50 = sdiv i32 %div49, %div14 + %div51 = sdiv i32 %div50, %div13 + %div52 = sdiv i32 %div51, %div12 + %div53 = sdiv i32 %div52, %div11 + %div54 = sdiv i32 %div53, %div10 + %div55 = sdiv i32 %div54, %div9 + %div56 = sdiv i32 %div55, %div8 + %div57 = sdiv i32 %div56, %div7 + %div58 = sdiv i32 %div57, %div6 + %div59 = sdiv i32 %div58, %div5 + %div60 = sdiv i32 %div59, %div4 + %div61 = sdiv i32 %div60, %div3 + %div62 = sdiv i32 %div61, %div2 + %div63 = sdiv i32 %div62, %div1 + %div64 = sdiv i32 %div63, %div + ret i32 %div64 +} + +; This function will need to use all non-reserved GPRs (and then some), make +; sure that r2 is among them. +; CHECK-LABEL: @foo +; CHECK: std 2, +; CHECK: ld 2, +; CHECK: blr + diff --git a/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll b/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll new file mode 100644 index 0000000..368ddc5 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-stackmap-nops.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-gnu-linux | FileCheck %s + +define void @test_shadow_optimization() { +entry: +; Expect 12 bytes worth of nops here rather than 32: With the shadow optimization +; in place, 20 bytes will be consumed by the frame teardown and return instr. +; CHECK-LABEL: test_shadow_optimization: + +; CHECK: nop +; CHECK-NEXT: nop +; CHECK-NEXT: nop +; CHECK-NOT: nop +; CHECK: addi 1, 1, 64 +; CHECK: ld [[REG1:[0-9]+]], 16(1) +; CHECK: ld 31, -8(1) +; CHECK: mtlr [[REG1]] +; CHECK: blr + + tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 0, i32 32) + ret void +} + +declare void @llvm.experimental.stackmap(i64, i32, ...) + diff --git a/test/CodeGen/PowerPC/ppc64-stackmap.ll b/test/CodeGen/PowerPC/ppc64-stackmap.ll new file mode 100644 index 0000000..714d363 --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-stackmap.ll @@ -0,0 +1,289 @@ +; RUN: llc < %s | FileCheck %s +; +; Note: Print verbose stackmaps using -debug-only=stackmaps. + +; We are not getting the correct stack alignment when cross compiling for arm64. +; So specify a datalayout here. +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; CHECK-LABEL: .section .llvm_stackmaps +; CHECK-NEXT: __LLVM_StackMaps: +; Header +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 0 +; CHECK-NEXT: .short 0 +; Num Functions +; CHECK-NEXT: .long 11 +; Num LargeConstants +; CHECK-NEXT: .long 2 +; Num Callsites +; CHECK-NEXT: .long 11 + +; Functions and stack size +; CHECK-NEXT: .quad constantargs +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad osrinline +; CHECK-NEXT: .quad 144 +; CHECK-NEXT: .quad osrcold +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad propertyRead +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad propertyWrite +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad jsVoidCall +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad jsIntCall +; CHECK-NEXT: .quad 128 +; CHECK-NEXT: .quad spilledValue +; CHECK-NEXT: .quad 304 +; CHECK-NEXT: .quad spilledStackMapValue +; CHECK-NEXT: .quad 224 +; CHECK-NEXT: .quad liveConstant +; CHECK-NEXT: .quad 64 +; CHECK-NEXT: .quad clobberLR +; CHECK-NEXT: .quad 208 + +; Num LargeConstants +; CHECK-NEXT: .quad 4294967295 +; CHECK-NEXT: .quad 4294967296 + +; Constant arguments +; +; CHECK-NEXT: .quad 1 +; CHECK-NEXT: .long .L{{.*}}-.L.constantargs +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 4 +; SmallConstant +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 65535 +; SmallConstant +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 65536 +; SmallConstant +; CHECK-NEXT: .byte 5 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 0 +; LargeConstant at index 0 +; CHECK-NEXT: .byte 5 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 1 + +define void @constantargs() { +entry: + %0 = inttoptr i64 244837814094590 to i8* + tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 1, i32 24, i8* %0, i32 0, i64 65535, i64 65536, i64 4294967295, i64 4294967296) + ret void +} + +; Inline OSR Exit +; +; CHECK-LABEL: .long .L{{.*}}-.L.osrinline +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 2 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define void @osrinline(i64 %a, i64 %b) { +entry: + ; Runtime void->void call. + call void inttoptr (i64 244837814094590 to void ()*)() + ; Followed by inline OSR patchpoint with 12-byte shadow and 2 live vars. + call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 3, i32 12, i64 %a, i64 %b) + ret void +} + +; Cold OSR Exit +; +; 2 live variables in register. +; +; CHECK-LABEL: .long .L{{.*}}-.L.osrcold +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 2 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define void @osrcold(i64 %a, i64 %b) { +entry: + %test = icmp slt i64 %a, %b + br i1 %test, label %ret, label %cold +cold: + ; OSR patchpoint with 12-byte nop-slide and 2 live vars. + %thunk = inttoptr i64 244837814094590 to i8* + call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 4, i32 24, i8* %thunk, i32 0, i64 %a, i64 %b) + unreachable +ret: + ret void +} + +; Property Read +; CHECK-LABEL: .long .L{{.*}}-.L.propertyRead +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 0 +; +; FIXME: There are currently no stackmap entries. After moving to +; AnyRegCC, we will have entries for the object and return value. +define i64 @propertyRead(i64* %obj) { +entry: + %resolveRead = inttoptr i64 244837814094590 to i8* + %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 5, i32 24, i8* %resolveRead, i32 1, i64* %obj) + %add = add i64 %result, 3 + ret i64 %add +} + +; Property Write +; CHECK-LABEL: .long .L{{.*}}-.L.propertyWrite +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 2 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define void @propertyWrite(i64 %dummy1, i64* %obj, i64 %dummy2, i64 %a) { +entry: + %resolveWrite = inttoptr i64 244837814094590 to i8* + call anyregcc void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 6, i32 24, i8* %resolveWrite, i32 2, i64* %obj, i64 %a) + ret void +} + +; Void JS Call +; +; 2 live variables in registers. +; +; CHECK-LABEL: .long .L{{.*}}-.L.jsVoidCall +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 2 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define void @jsVoidCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { +entry: + %resolveCall = inttoptr i64 244837814094590 to i8* + call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 7, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) + ret void +} + +; i64 JS Call +; +; 2 live variables in registers. +; +; CHECK-LABEL: .long .L{{.*}}-.L.jsIntCall +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 2 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short {{[0-9]+}} +; CHECK-NEXT: .long 0 +define i64 @jsIntCall(i64 %dummy1, i64* %obj, i64 %arg, i64 %l1, i64 %l2) { +entry: + %resolveCall = inttoptr i64 244837814094590 to i8* + %result = call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 8, i32 24, i8* %resolveCall, i32 2, i64* %obj, i64 %arg, i64 %l1, i64 %l2) + %add = add i64 %result, 3 + ret i64 %add +} + +; Spilled stack map values. +; +; Verify 28 stack map entries. +; +; CHECK-LABEL: .long .L{{.*}}-.L.spilledValue +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 28 +; +; Check that at least one is a spilled entry from r31. +; Location: Indirect FP + ... +; CHECK: .byte 3 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 31 +define void @spilledValue(i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) { +entry: + call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 11, i32 24, i8* null, i32 5, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27) + ret void +} + +; Spilled stack map values. +; +; Verify 30 stack map entries. +; +; CHECK-LABEL: .long .L{{.*}}-.L.spilledStackMapValue +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .short 30 +; +; Check that at least one is a spilled entry from r31. +; Location: Indirect FP + ... +; CHECK: .byte 3 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 31 +define webkit_jscc void @spilledStackMapValue(i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) { +entry: + call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 12, i32 16, i64 %l0, i64 %l1, i64 %l2, i64 %l3, i64 %l4, i64 %l5, i64 %l6, i64 %l7, i64 %l8, i64 %l9, i64 %l10, i64 %l11, i64 %l12, i64 %l13, i64 %l14, i64 %l15, i64 %l16, i64 %l17, i64 %l18, i64 %l19, i64 %l20, i64 %l21, i64 %l22, i64 %l23, i64 %l24, i64 %l25, i64 %l26, i64 %l27, i64 %l28, i64 %l29) + ret void +} + + +; Map a constant value. +; +; CHECK-LABEL: .long .L{{.*}}-.L.liveConstant +; CHECK-NEXT: .short 0 +; 1 location +; CHECK-NEXT: .short 1 +; Loc 0: SmallConstant +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .short 0 +; CHECK-NEXT: .long 33 + +define void @liveConstant() { + tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 15, i32 8, i32 33) + ret void +} + +; Map a value when LR is the only free register. +; +; CHECK-LABEL: .long .L{{.*}}-.L.clobberLR +; CHECK-NEXT: .short 0 +; 1 location +; CHECK-NEXT: .short 1 +; Loc 0: Indirect FP (r31) - offset +; CHECK-NEXT: .byte 3 +; CHECK-NEXT: .byte 4 +; CHECK-NEXT: .short 31 +; CHECK-NEXT: .long {{[0-9]+}} +define void @clobberLR(i32 %a) { + tail call void asm sideeffect "nop", "~{r0},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind + tail call void (i64, i32, ...)* @llvm.experimental.stackmap(i64 16, i32 8, i32 %a) + ret void +} + +declare void @llvm.experimental.stackmap(i64, i32, ...) +declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) +declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...) diff --git a/test/CodeGen/PowerPC/ppc64-vaarg-int.ll b/test/CodeGen/PowerPC/ppc64-vaarg-int.ll index 5a63b01..c9a4f91 100644 --- a/test/CodeGen/PowerPC/ppc64-vaarg-int.ll +++ b/test/CodeGen/PowerPC/ppc64-vaarg-int.ll @@ -16,5 +16,5 @@ declare void @llvm.va_start(i8*) nounwind ; CHECK: @intvaarg ; Make sure that the va pointer is incremented by 8 (not 4). -; CHECK: addi{{.*}}, 8 +; CHECK: addi{{.*}}, 1, 64 diff --git a/test/CodeGen/PowerPC/ppc64le-aggregates.ll b/test/CodeGen/PowerPC/ppc64le-aggregates.ll index 9eed623..3fce36e 100644 --- a/test/CodeGen/PowerPC/ppc64le-aggregates.ll +++ b/test/CodeGen/PowerPC/ppc64le-aggregates.ll @@ -1,4 +1,11 @@ -; RUN: llc < %s -march=ppc64le -mcpu=pwr8 -mattr=+altivec | FileCheck %s +; RUN: llc < %s -march=ppc64le -mcpu=pwr8 -mattr=+altivec -mattr=-vsx | FileCheck %s +; RUN: llc < %s -march=ppc64le -mattr=+altivec -mattr=-vsx | FileCheck %s + +; Currently VSX support is disabled for this test because we generate lxsdx +; instead of lfd, and stxsdx instead of stfd. That is a poor choice when we +; have reg+imm addressing, and is on the list of things to be fixed. +; The second run step is to ensure that -march=ppc64le is adequate to select +; the same feature set as with -mcpu=pwr8 since that is the baseline for ppc64le. target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" @@ -257,26 +264,26 @@ entry: ret void } ; CHECK-LABEL: @caller2 -; CHECK: ld [[REG:[0-9]+]], .LC -; CHECK-DAG: lfs 1, 0([[REG]]) -; CHECK-DAG: lfs 2, 4([[REG]]) -; CHECK-DAG: lfs 3, 8([[REG]]) -; CHECK-DAG: lfs 4, 12([[REG]]) -; CHECK-DAG: lfs 5, 16([[REG]]) -; CHECK-DAG: lfs 6, 20([[REG]]) -; CHECK-DAG: lfs 7, 24([[REG]]) -; CHECK-DAG: lfs 8, 28([[REG]]) -; CHECK: ld [[REG:[0-9]+]], .LC -; CHECK-DAG: lfs 9, 0([[REG]]) -; CHECK-DAG: lfs 10, 4([[REG]]) -; CHECK-DAG: lfs 11, 8([[REG]]) -; CHECK-DAG: lfs 12, 12([[REG]]) -; CHECK-DAG: lfs 13, 16([[REG]]) -; CHECK: ld [[REG:[0-9]+]], .LC -; CHECK-DAG: lwz [[REG0:[0-9]+]], 0([[REG]]) -; CHECK-DAG: lwz [[REG1:[0-9]+]], 4([[REG]]) -; CHECK-DAG: sldi [[REG1]], [[REG1]], 32 -; CHECK-DAG: or 10, [[REG0]], [[REG1]] +; CHECK: ld {{[0-9]+}}, .LC +; CHECK-DAG: lfs 1, 0({{[0-9]+}}) +; CHECK-DAG: lfs 2, 4({{[0-9]+}}) +; CHECK-DAG: lfs 3, 8({{[0-9]+}}) +; CHECK-DAG: lfs 4, 12({{[0-9]+}}) +; CHECK-DAG: lfs 5, 16({{[0-9]+}}) +; CHECK-DAG: lfs 6, 20({{[0-9]+}}) +; CHECK-DAG: lfs 7, 24({{[0-9]+}}) +; CHECK-DAG: lfs 8, 28({{[0-9]+}}) + +; CHECK-DAG: lfs 9, 0({{[0-9]+}}) +; CHECK-DAG: lfs 10, 4({{[0-9]+}}) +; CHECK-DAG: lfs 11, 8({{[0-9]+}}) +; CHECK-DAG: lfs 12, 12({{[0-9]+}}) +; CHECK-DAG: lfs 13, 16({{[0-9]+}}) + +; CHECK-DAG: lwz [[REG0:[0-9]+]], 0({{[0-9]+}}) +; CHECK-DAG: lwz [[REG1:[0-9]+]], 4({{[0-9]+}}) +; CHECK-DAG: sldi [[REG2:[0-9]+]], [[REG1]], 32 +; CHECK-DAG: or 10, [[REG0]], [[REG2]] ; CHECK: bl test2 declare void @test2([8 x float], [5 x float], [2 x float]) diff --git a/test/CodeGen/PowerPC/ppc64le-calls.ll b/test/CodeGen/PowerPC/ppc64le-calls.ll index 0d667dd..b65b954 100644 --- a/test/CodeGen/PowerPC/ppc64le-calls.ll +++ b/test/CodeGen/PowerPC/ppc64le-calls.ll @@ -1,4 +1,8 @@ ; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -march=ppc64le < %s | FileCheck %s + +; The second run of the test case is to ensure the behaviour is the same +; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ppc64le-localentry.ll b/test/CodeGen/PowerPC/ppc64le-localentry.ll index 4676ce8..d9995de 100644 --- a/test/CodeGen/PowerPC/ppc64le-localentry.ll +++ b/test/CodeGen/PowerPC/ppc64le-localentry.ll @@ -1,5 +1,10 @@ ; RUN: llc -march=ppc64le -mcpu=pwr8 < %s | FileCheck %s ; RUN: llc -march=ppc64le -mcpu=pwr8 -O0 < %s | FileCheck %s +; RUN: llc -march=ppc64le < %s | FileCheck %s +; RUN: llc -march=ppc64le -O0 < %s | FileCheck %s + +; The second run of the test case is to ensure the behaviour is the same +; without specifying -mcpu=pwr8 as that is now the baseline for ppc64le. target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/ppcf128-endian.ll b/test/CodeGen/PowerPC/ppcf128-endian.ll index 2a5f13a..180fedf 100644 --- a/test/CodeGen/PowerPC/ppcf128-endian.ll +++ b/test/CodeGen/PowerPC/ppcf128-endian.ll @@ -1,4 +1,4 @@ -; RUN: llc -mcpu=pwr7 -mattr=+altivec < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s target datalayout = "e-m:e-i64:64-n32:64" target triple = "powerpc64le-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/pr17168.ll b/test/CodeGen/PowerPC/pr17168.ll index c3f0162..62a9ede 100644 --- a/test/CodeGen/PowerPC/pr17168.ll +++ b/test/CodeGen/PowerPC/pr17168.ll @@ -25,7 +25,7 @@ for.cond968.preheader: ; preds = %for.cond968.prehead for.end1042: ; preds = %for.cond968.preheader, %for.cond964.preheader, %entry %0 = phi i32 [ undef, %for.cond964.preheader ], [ undef, %for.cond968.preheader ], [ undef, %entry ] %1 = load i32* getelementptr inbounds ([3 x i32]* @grid_points, i64 0, i64 0), align 4, !dbg !443, !tbaa !444 - tail call void @llvm.dbg.value(metadata !447, i64 0, metadata !119, metadata !{metadata !"0x102"}), !dbg !448 + tail call void @llvm.dbg.value(metadata i32 1, i64 0, metadata !119, metadata !{!"0x102"}), !dbg !448 %sub10454270 = add nsw i32 %0, -1, !dbg !448 %cmp10464271 = icmp sgt i32 %sub10454270, 1, !dbg !448 %sub11134263 = add nsw i32 %1, -1, !dbg !450 @@ -54,468 +54,468 @@ attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!438, !464} -!0 = metadata !{metadata !"0x11\0012\00clang version 3.4 (trunk 190311)\001\00\000\00\000", metadata !1, metadata !2, metadata !2, metadata !3, metadata !298, metadata !2} ; [ DW_TAG_compile_unit ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] [DW_LANG_C99] -!1 = metadata !{metadata !"bt.c", metadata !"/home/hfinkel/src/NPB2.3-omp-C/BT"} -!2 = metadata !{} -!3 = metadata !{metadata !4, metadata !82, metadata !102, metadata !114, metadata !132, metadata !145, metadata !154, metadata !155, metadata !162, metadata !183, metadata !200, metadata !201, metadata !207, metadata !208, metadata !215, metadata !221, metadata !230, metadata !238, metadata !246, metadata !255, metadata !260, metadata !261, metadata !268, metadata !274, metadata !279, metadata !280, metadata !287, metadata !293} -!4 = metadata !{metadata !"0x2e\00main\00main\00\0074\000\001\000\006\00256\001\0074", metadata !1, metadata !5, metadata !6, null, null, null, null, metadata !12} ; [ DW_TAG_subprogram ] [line 74] [def] [main] -!5 = metadata !{metadata !"0x29", metadata !1} ; [ DW_TAG_file_type ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!6 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!7 = metadata !{metadata !8, metadata !8, metadata !9} -!8 = metadata !{metadata !"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] -!9 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] -!10 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char] -!11 = metadata !{metadata !"0x24\00char\000\008\008\000\000\008", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_unsigned_char] -!12 = metadata !{metadata !13, metadata !14, metadata !15, metadata !16, metadata !17, metadata !18, metadata !19, metadata !21, metadata !22, metadata !23, metadata !25, metadata !26} -!13 = metadata !{metadata !"0x101\00argc\0016777290\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [argc] [line 74] -!14 = metadata !{metadata !"0x101\00argv\0033554506\000", metadata !4, metadata !5, metadata !9} ; [ DW_TAG_arg_variable ] [argv] [line 74] -!15 = metadata !{metadata !"0x100\00niter\0076\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [niter] [line 76] -!16 = metadata !{metadata !"0x100\00step\0076\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [step] [line 76] -!17 = metadata !{metadata !"0x100\00n3\0076\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [n3] [line 76] -!18 = metadata !{metadata !"0x100\00nthreads\0077\000", metadata !4, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [nthreads] [line 77] -!19 = metadata !{metadata !"0x100\00navg\0078\000", metadata !4, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [navg] [line 78] -!20 = metadata !{metadata !"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float] -!21 = metadata !{metadata !"0x100\00mflops\0078\000", metadata !4, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [mflops] [line 78] -!22 = metadata !{metadata !"0x100\00tmax\0080\000", metadata !4, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [tmax] [line 80] -!23 = metadata !{metadata !"0x100\00verified\0081\000", metadata !4, metadata !5, metadata !24} ; [ DW_TAG_auto_variable ] [verified] [line 81] -!24 = metadata !{metadata !"0x16\00boolean\0012\000\000\000\000", metadata !1, null, metadata !8} ; [ DW_TAG_typedef ] [boolean] [line 12, size 0, align 0, offset 0] [from int] -!25 = metadata !{metadata !"0x100\00class\0082\000", metadata !4, metadata !5, metadata !11} ; [ DW_TAG_auto_variable ] [class] [line 82] -!26 = metadata !{metadata !"0x100\00fp\0083\000", metadata !4, metadata !5, metadata !27} ; [ DW_TAG_auto_variable ] [fp] [line 83] -!27 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !28} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from FILE] -!28 = metadata !{metadata !"0x16\00FILE\0049\000\000\000\000", metadata !1, null, metadata !29} ; [ DW_TAG_typedef ] [FILE] [line 49, size 0, align 0, offset 0] [from _IO_FILE] -!29 = metadata !{metadata !"0x13\00_IO_FILE\00271\001728\0064\000\000\000", metadata !30, null, null, metadata !31, null, null, null} ; [ DW_TAG_structure_type ] [_IO_FILE] [line 271, size 1728, align 64, offset 0] [def] [from ] -!30 = metadata !{metadata !"/usr/include/libio.h", metadata !"/home/hfinkel/src/NPB2.3-omp-C/BT"} -!31 = metadata !{metadata !32, metadata !33, metadata !34, metadata !35, metadata !36, metadata !37, metadata !38, metadata !39, metadata !40, metadata !41, metadata !42, metadata !43, metadata !44, metadata !52, metadata !53, metadata !54, metadata !55, metadata !58, metadata !60, metadata !62, metadata !66, metadata !68, metadata !70, metadata !71, metadata !72, metadata !73, metadata !74, metadata !77, metadata !78} -!32 = metadata !{metadata !"0xd\00_flags\00272\0032\0032\000\000", metadata !30, metadata !29, metadata !8} ; [ DW_TAG_member ] [_flags] [line 272, size 32, align 32, offset 0] [from int] -!33 = metadata !{metadata !"0xd\00_IO_read_ptr\00277\0064\0064\0064\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_read_ptr] [line 277, size 64, align 64, offset 64] [from ] -!34 = metadata !{metadata !"0xd\00_IO_read_end\00278\0064\0064\00128\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_read_end] [line 278, size 64, align 64, offset 128] [from ] -!35 = metadata !{metadata !"0xd\00_IO_read_base\00279\0064\0064\00192\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_read_base] [line 279, size 64, align 64, offset 192] [from ] -!36 = metadata !{metadata !"0xd\00_IO_write_base\00280\0064\0064\00256\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_write_base] [line 280, size 64, align 64, offset 256] [from ] -!37 = metadata !{metadata !"0xd\00_IO_write_ptr\00281\0064\0064\00320\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_write_ptr] [line 281, size 64, align 64, offset 320] [from ] -!38 = metadata !{metadata !"0xd\00_IO_write_end\00282\0064\0064\00384\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_write_end] [line 282, size 64, align 64, offset 384] [from ] -!39 = metadata !{metadata !"0xd\00_IO_buf_base\00283\0064\0064\00448\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_buf_base] [line 283, size 64, align 64, offset 448] [from ] -!40 = metadata !{metadata !"0xd\00_IO_buf_end\00284\0064\0064\00512\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_buf_end] [line 284, size 64, align 64, offset 512] [from ] -!41 = metadata !{metadata !"0xd\00_IO_save_base\00286\0064\0064\00576\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_save_base] [line 286, size 64, align 64, offset 576] [from ] -!42 = metadata !{metadata !"0xd\00_IO_backup_base\00287\0064\0064\00640\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_backup_base] [line 287, size 64, align 64, offset 640] [from ] -!43 = metadata !{metadata !"0xd\00_IO_save_end\00288\0064\0064\00704\000", metadata !30, metadata !29, metadata !10} ; [ DW_TAG_member ] [_IO_save_end] [line 288, size 64, align 64, offset 704] [from ] -!44 = metadata !{metadata !"0xd\00_markers\00290\0064\0064\00768\000", metadata !30, metadata !29, metadata !45} ; [ DW_TAG_member ] [_markers] [line 290, size 64, align 64, offset 768] [from ] -!45 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !46} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _IO_marker] -!46 = metadata !{metadata !"0x13\00_IO_marker\00186\00192\0064\000\000\000", metadata !30, null, null, metadata !47, null, null, null} ; [ DW_TAG_structure_type ] [_IO_marker] [line 186, size 192, align 64, offset 0] [def] [from ] -!47 = metadata !{metadata !48, metadata !49, metadata !51} -!48 = metadata !{metadata !"0xd\00_next\00187\0064\0064\000\000", metadata !30, metadata !46, metadata !45} ; [ DW_TAG_member ] [_next] [line 187, size 64, align 64, offset 0] [from ] -!49 = metadata !{metadata !"0xd\00_sbuf\00188\0064\0064\0064\000", metadata !30, metadata !46, metadata !50} ; [ DW_TAG_member ] [_sbuf] [line 188, size 64, align 64, offset 64] [from ] -!50 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !29} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _IO_FILE] -!51 = metadata !{metadata !"0xd\00_pos\00192\0032\0032\00128\000", metadata !30, metadata !46, metadata !8} ; [ DW_TAG_member ] [_pos] [line 192, size 32, align 32, offset 128] [from int] -!52 = metadata !{metadata !"0xd\00_chain\00292\0064\0064\00832\000", metadata !30, metadata !29, metadata !50} ; [ DW_TAG_member ] [_chain] [line 292, size 64, align 64, offset 832] [from ] -!53 = metadata !{metadata !"0xd\00_fileno\00294\0032\0032\00896\000", metadata !30, metadata !29, metadata !8} ; [ DW_TAG_member ] [_fileno] [line 294, size 32, align 32, offset 896] [from int] -!54 = metadata !{metadata !"0xd\00_flags2\00298\0032\0032\00928\000", metadata !30, metadata !29, metadata !8} ; [ DW_TAG_member ] [_flags2] [line 298, size 32, align 32, offset 928] [from int] -!55 = metadata !{metadata !"0xd\00_old_offset\00300\0064\0064\00960\000", metadata !30, metadata !29, metadata !56} ; [ DW_TAG_member ] [_old_offset] [line 300, size 64, align 64, offset 960] [from __off_t] -!56 = metadata !{metadata !"0x16\00__off_t\00141\000\000\000\000", metadata !30, null, metadata !57} ; [ DW_TAG_typedef ] [__off_t] [line 141, size 0, align 0, offset 0] [from long int] -!57 = metadata !{metadata !"0x24\00long int\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed] -!58 = metadata !{metadata !"0xd\00_cur_column\00304\0016\0016\001024\000", metadata !30, metadata !29, metadata !59} ; [ DW_TAG_member ] [_cur_column] [line 304, size 16, align 16, offset 1024] [from unsigned short] -!59 = metadata !{metadata !"0x24\00unsigned short\000\0016\0016\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned short] [line 0, size 16, align 16, offset 0, enc DW_ATE_unsigned] -!60 = metadata !{metadata !"0xd\00_vtable_offset\00305\008\008\001040\000", metadata !30, metadata !29, metadata !61} ; [ DW_TAG_member ] [_vtable_offset] [line 305, size 8, align 8, offset 1040] [from signed char] -!61 = metadata !{metadata !"0x24\00signed char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [signed char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char] -!62 = metadata !{metadata !"0xd\00_shortbuf\00306\008\008\001048\000", metadata !30, metadata !29, metadata !63} ; [ DW_TAG_member ] [_shortbuf] [line 306, size 8, align 8, offset 1048] [from ] -!63 = metadata !{metadata !"0x1\00\000\008\008\000\000", null, null, metadata !11, metadata !64, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 8, align 8, offset 0] [from char] -!64 = metadata !{metadata !65} -!65 = metadata !{metadata !"0x21\000\001"} ; [ DW_TAG_subrange_type ] [0, 0] -!66 = metadata !{metadata !"0xd\00_lock\00310\0064\0064\001088\000", metadata !30, metadata !29, metadata !67} ; [ DW_TAG_member ] [_lock] [line 310, size 64, align 64, offset 1088] [from ] -!67 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] -!68 = metadata !{metadata !"0xd\00_offset\00319\0064\0064\001152\000", metadata !30, metadata !29, metadata !69} ; [ DW_TAG_member ] [_offset] [line 319, size 64, align 64, offset 1152] [from __off64_t] -!69 = metadata !{metadata !"0x16\00__off64_t\00142\000\000\000\000", metadata !30, null, metadata !57} ; [ DW_TAG_typedef ] [__off64_t] [line 142, size 0, align 0, offset 0] [from long int] -!70 = metadata !{metadata !"0xd\00__pad1\00328\0064\0064\001216\000", metadata !30, metadata !29, metadata !67} ; [ DW_TAG_member ] [__pad1] [line 328, size 64, align 64, offset 1216] [from ] -!71 = metadata !{metadata !"0xd\00__pad2\00329\0064\0064\001280\000", metadata !30, metadata !29, metadata !67} ; [ DW_TAG_member ] [__pad2] [line 329, size 64, align 64, offset 1280] [from ] -!72 = metadata !{metadata !"0xd\00__pad3\00330\0064\0064\001344\000", metadata !30, metadata !29, metadata !67} ; [ DW_TAG_member ] [__pad3] [line 330, size 64, align 64, offset 1344] [from ] -!73 = metadata !{metadata !"0xd\00__pad4\00331\0064\0064\001408\000", metadata !30, metadata !29, metadata !67} ; [ DW_TAG_member ] [__pad4] [line 331, size 64, align 64, offset 1408] [from ] -!74 = metadata !{metadata !"0xd\00__pad5\00332\0064\0064\001472\000", metadata !30, metadata !29, metadata !75} ; [ DW_TAG_member ] [__pad5] [line 332, size 64, align 64, offset 1472] [from size_t] -!75 = metadata !{metadata !"0x16\00size_t\0042\000\000\000\000", metadata !30, null, metadata !76} ; [ DW_TAG_typedef ] [size_t] [line 42, size 0, align 0, offset 0] [from long unsigned int] -!76 = metadata !{metadata !"0x24\00long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned] -!77 = metadata !{metadata !"0xd\00_mode\00334\0032\0032\001536\000", metadata !30, metadata !29, metadata !8} ; [ DW_TAG_member ] [_mode] [line 334, size 32, align 32, offset 1536] [from int] -!78 = metadata !{metadata !"0xd\00_unused2\00336\00160\008\001568\000", metadata !30, metadata !29, metadata !79} ; [ DW_TAG_member ] [_unused2] [line 336, size 160, align 8, offset 1568] [from ] -!79 = metadata !{metadata !"0x1\00\000\00160\008\000\000", null, null, metadata !11, metadata !80, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 160, align 8, offset 0] [from char] -!80 = metadata !{metadata !81} -!81 = metadata !{metadata !"0x21\000\0020"} ; [ DW_TAG_subrange_type ] [0, 19] -!82 = metadata !{metadata !"0x2e\00verify\00verify\00\002388\001\001\000\006\00256\001\002388", metadata !1, metadata !5, metadata !83, null, null, null, null, metadata !86} ; [ DW_TAG_subprogram ] [line 2388] [local] [def] [verify] -!83 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !84, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!84 = metadata !{null, metadata !8, metadata !10, metadata !85} -!85 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !24} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from boolean] -!86 = metadata !{metadata !87, metadata !88, metadata !89, metadata !90, metadata !94, metadata !95, metadata !96, metadata !97, metadata !98, metadata !99, metadata !100, metadata !101} -!87 = metadata !{metadata !"0x101\00no_time_steps\0016779604\000", metadata !82, metadata !5, metadata !8} ; [ DW_TAG_arg_variable ] [no_time_steps] [line 2388] -!88 = metadata !{metadata !"0x101\00class\0033556820\000", metadata !82, metadata !5, metadata !10} ; [ DW_TAG_arg_variable ] [class] [line 2388] -!89 = metadata !{metadata !"0x101\00verified\0050334036\000", metadata !82, metadata !5, metadata !85} ; [ DW_TAG_arg_variable ] [verified] [line 2388] -!90 = metadata !{metadata !"0x100\00xcrref\002397\000", metadata !82, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [xcrref] [line 2397] -!91 = metadata !{metadata !"0x1\00\000\00320\0064\000\000", null, null, metadata !20, metadata !92, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 320, align 64, offset 0] [from double] -!92 = metadata !{metadata !93} -!93 = metadata !{metadata !"0x21\000\005"} ; [ DW_TAG_subrange_type ] [0, 4] -!94 = metadata !{metadata !"0x100\00xceref\002397\000", metadata !82, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [xceref] [line 2397] -!95 = metadata !{metadata !"0x100\00xcrdif\002397\000", metadata !82, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [xcrdif] [line 2397] -!96 = metadata !{metadata !"0x100\00xcedif\002397\000", metadata !82, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [xcedif] [line 2397] -!97 = metadata !{metadata !"0x100\00epsilon\002398\000", metadata !82, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [epsilon] [line 2398] -!98 = metadata !{metadata !"0x100\00xce\002398\000", metadata !82, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [xce] [line 2398] -!99 = metadata !{metadata !"0x100\00xcr\002398\000", metadata !82, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [xcr] [line 2398] -!100 = metadata !{metadata !"0x100\00dtref\002398\000", metadata !82, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [dtref] [line 2398] -!101 = metadata !{metadata !"0x100\00m\002399\000", metadata !82, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 2399] -!102 = metadata !{metadata !"0x2e\00rhs_norm\00rhs_norm\00\00266\001\001\000\006\00256\001\00266", metadata !1, metadata !5, metadata !103, null, null, null, null, metadata !106} ; [ DW_TAG_subprogram ] [line 266] [local] [def] [rhs_norm] -!103 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !104, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!104 = metadata !{null, metadata !105} -!105 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !20} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from double] -!106 = metadata !{metadata !107, metadata !108, metadata !109, metadata !110, metadata !111, metadata !112, metadata !113} -!107 = metadata !{metadata !"0x101\00rms\0016777482\000", metadata !102, metadata !5, metadata !105} ; [ DW_TAG_arg_variable ] [rms] [line 266] -!108 = metadata !{metadata !"0x100\00i\00271\000", metadata !102, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 271] -!109 = metadata !{metadata !"0x100\00j\00271\000", metadata !102, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 271] -!110 = metadata !{metadata !"0x100\00k\00271\000", metadata !102, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 271] -!111 = metadata !{metadata !"0x100\00d\00271\000", metadata !102, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [d] [line 271] -!112 = metadata !{metadata !"0x100\00m\00271\000", metadata !102, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 271] -!113 = metadata !{metadata !"0x100\00add\00272\000", metadata !102, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [add] [line 272] -!114 = metadata !{metadata !"0x2e\00compute_rhs\00compute_rhs\00\001767\001\001\000\006\00256\001\001767", metadata !1, metadata !5, metadata !115, null, void ()* @compute_rhs, null, null, metadata !117} ; [ DW_TAG_subprogram ] [line 1767] [local] [def] [compute_rhs] -!115 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !116, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!116 = metadata !{null} -!117 = metadata !{metadata !118, metadata !119, metadata !120, metadata !121, metadata !122, metadata !123, metadata !124, metadata !125, metadata !126, metadata !127, metadata !128, metadata !129, metadata !130, metadata !131} -!118 = metadata !{metadata !"0x100\00i\001769\000", metadata !114, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 1769] -!119 = metadata !{metadata !"0x100\00j\001769\000", metadata !114, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 1769] -!120 = metadata !{metadata !"0x100\00k\001769\000", metadata !114, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 1769] -!121 = metadata !{metadata !"0x100\00m\001769\000", metadata !114, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 1769] -!122 = metadata !{metadata !"0x100\00rho_inv\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [rho_inv] [line 1770] -!123 = metadata !{metadata !"0x100\00uijk\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [uijk] [line 1770] -!124 = metadata !{metadata !"0x100\00up1\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [up1] [line 1770] -!125 = metadata !{metadata !"0x100\00um1\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [um1] [line 1770] -!126 = metadata !{metadata !"0x100\00vijk\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [vijk] [line 1770] -!127 = metadata !{metadata !"0x100\00vp1\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [vp1] [line 1770] -!128 = metadata !{metadata !"0x100\00vm1\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [vm1] [line 1770] -!129 = metadata !{metadata !"0x100\00wijk\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [wijk] [line 1770] -!130 = metadata !{metadata !"0x100\00wp1\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [wp1] [line 1770] -!131 = metadata !{metadata !"0x100\00wm1\001770\000", metadata !114, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [wm1] [line 1770] -!132 = metadata !{metadata !"0x2e\00error_norm\00error_norm\00\00225\001\001\000\006\00256\001\00225", metadata !1, metadata !5, metadata !103, null, null, null, null, metadata !133} ; [ DW_TAG_subprogram ] [line 225] [local] [def] [error_norm] -!133 = metadata !{metadata !134, metadata !135, metadata !136, metadata !137, metadata !138, metadata !139, metadata !140, metadata !141, metadata !142, metadata !143, metadata !144} -!134 = metadata !{metadata !"0x101\00rms\0016777441\000", metadata !132, metadata !5, metadata !105} ; [ DW_TAG_arg_variable ] [rms] [line 225] -!135 = metadata !{metadata !"0x100\00i\00232\000", metadata !132, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 232] -!136 = metadata !{metadata !"0x100\00j\00232\000", metadata !132, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 232] -!137 = metadata !{metadata !"0x100\00k\00232\000", metadata !132, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 232] -!138 = metadata !{metadata !"0x100\00m\00232\000", metadata !132, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 232] -!139 = metadata !{metadata !"0x100\00d\00232\000", metadata !132, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [d] [line 232] -!140 = metadata !{metadata !"0x100\00xi\00233\000", metadata !132, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [xi] [line 233] -!141 = metadata !{metadata !"0x100\00eta\00233\000", metadata !132, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [eta] [line 233] -!142 = metadata !{metadata !"0x100\00zeta\00233\000", metadata !132, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [zeta] [line 233] -!143 = metadata !{metadata !"0x100\00u_exact\00233\000", metadata !132, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [u_exact] [line 233] -!144 = metadata !{metadata !"0x100\00add\00233\000", metadata !132, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [add] [line 233] -!145 = metadata !{metadata !"0x2e\00exact_solution\00exact_solution\00\00643\001\001\000\006\00256\001\00644", metadata !1, metadata !5, metadata !146, null, null, null, null, metadata !148} ; [ DW_TAG_subprogram ] [line 643] [local] [def] [scope 644] [exact_solution] -!146 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !147, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!147 = metadata !{null, metadata !20, metadata !20, metadata !20, metadata !105} -!148 = metadata !{metadata !149, metadata !150, metadata !151, metadata !152, metadata !153} -!149 = metadata !{metadata !"0x101\00xi\0016777859\000", metadata !145, metadata !5, metadata !20} ; [ DW_TAG_arg_variable ] [xi] [line 643] -!150 = metadata !{metadata !"0x101\00eta\0033555075\000", metadata !145, metadata !5, metadata !20} ; [ DW_TAG_arg_variable ] [eta] [line 643] -!151 = metadata !{metadata !"0x101\00zeta\0050332291\000", metadata !145, metadata !5, metadata !20} ; [ DW_TAG_arg_variable ] [zeta] [line 643] -!152 = metadata !{metadata !"0x101\00dtemp\0067109508\000", metadata !145, metadata !5, metadata !105} ; [ DW_TAG_arg_variable ] [dtemp] [line 644] -!153 = metadata !{metadata !"0x100\00m\00653\000", metadata !145, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 653] -!154 = metadata !{metadata !"0x2e\00set_constants\00set_constants\00\002191\001\001\000\006\00256\001\002191", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 2191] [local] [def] [set_constants] -!155 = metadata !{metadata !"0x2e\00lhsinit\00lhsinit\00\00855\001\001\000\006\00256\001\00855", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !156} ; [ DW_TAG_subprogram ] [line 855] [local] [def] [lhsinit] -!156 = metadata !{metadata !157, metadata !158, metadata !159, metadata !160, metadata !161} -!157 = metadata !{metadata !"0x100\00i\00857\000", metadata !155, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 857] -!158 = metadata !{metadata !"0x100\00j\00857\000", metadata !155, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 857] -!159 = metadata !{metadata !"0x100\00k\00857\000", metadata !155, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 857] -!160 = metadata !{metadata !"0x100\00m\00857\000", metadata !155, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 857] -!161 = metadata !{metadata !"0x100\00n\00857\000", metadata !155, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [n] [line 857] -!162 = metadata !{metadata !"0x2e\00initialize\00initialize\00\00669\001\001\000\006\00256\001\00669", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !163} ; [ DW_TAG_subprogram ] [line 669] [local] [def] [initialize] -!163 = metadata !{metadata !164, metadata !165, metadata !166, metadata !167, metadata !168, metadata !169, metadata !170, metadata !171, metadata !172, metadata !173, metadata !174, metadata !179, metadata !180, metadata !181, metadata !182} -!164 = metadata !{metadata !"0x100\00i\00679\000", metadata !162, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 679] -!165 = metadata !{metadata !"0x100\00j\00679\000", metadata !162, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 679] -!166 = metadata !{metadata !"0x100\00k\00679\000", metadata !162, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 679] -!167 = metadata !{metadata !"0x100\00m\00679\000", metadata !162, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 679] -!168 = metadata !{metadata !"0x100\00ix\00679\000", metadata !162, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [ix] [line 679] -!169 = metadata !{metadata !"0x100\00iy\00679\000", metadata !162, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [iy] [line 679] -!170 = metadata !{metadata !"0x100\00iz\00679\000", metadata !162, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [iz] [line 679] -!171 = metadata !{metadata !"0x100\00xi\00680\000", metadata !162, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [xi] [line 680] -!172 = metadata !{metadata !"0x100\00eta\00680\000", metadata !162, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [eta] [line 680] -!173 = metadata !{metadata !"0x100\00zeta\00680\000", metadata !162, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [zeta] [line 680] -!174 = metadata !{metadata !"0x100\00Pface\00680\000", metadata !162, metadata !5, metadata !175} ; [ DW_TAG_auto_variable ] [Pface] [line 680] -!175 = metadata !{metadata !"0x1\00\000\001920\0064\000\000", null, null, metadata !20, metadata !176, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1920, align 64, offset 0] [from double] -!176 = metadata !{metadata !177, metadata !178, metadata !93} -!177 = metadata !{metadata !"0x21\000\002"} ; [ DW_TAG_subrange_type ] [0, 1] -!178 = metadata !{metadata !"0x21\000\003"} ; [ DW_TAG_subrange_type ] [0, 2] -!179 = metadata !{metadata !"0x100\00Pxi\00680\000", metadata !162, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [Pxi] [line 680] -!180 = metadata !{metadata !"0x100\00Peta\00680\000", metadata !162, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [Peta] [line 680] -!181 = metadata !{metadata !"0x100\00Pzeta\00680\000", metadata !162, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [Pzeta] [line 680] -!182 = metadata !{metadata !"0x100\00temp\00680\000", metadata !162, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [temp] [line 680] -!183 = metadata !{metadata !"0x2e\00exact_rhs\00exact_rhs\00\00301\001\001\000\006\00256\001\00301", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !184} ; [ DW_TAG_subprogram ] [line 301] [local] [def] [exact_rhs] -!184 = metadata !{metadata !185, metadata !186, metadata !187, metadata !188, metadata !189, metadata !190, metadata !191, metadata !192, metadata !193, metadata !194, metadata !195, metadata !196, metadata !197, metadata !198, metadata !199} -!185 = metadata !{metadata !"0x100\00dtemp\00310\000", metadata !183, metadata !5, metadata !91} ; [ DW_TAG_auto_variable ] [dtemp] [line 310] -!186 = metadata !{metadata !"0x100\00xi\00310\000", metadata !183, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [xi] [line 310] -!187 = metadata !{metadata !"0x100\00eta\00310\000", metadata !183, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [eta] [line 310] -!188 = metadata !{metadata !"0x100\00zeta\00310\000", metadata !183, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [zeta] [line 310] -!189 = metadata !{metadata !"0x100\00dtpp\00310\000", metadata !183, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [dtpp] [line 310] -!190 = metadata !{metadata !"0x100\00m\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 311] -!191 = metadata !{metadata !"0x100\00i\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 311] -!192 = metadata !{metadata !"0x100\00j\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 311] -!193 = metadata !{metadata !"0x100\00k\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 311] -!194 = metadata !{metadata !"0x100\00ip1\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [ip1] [line 311] -!195 = metadata !{metadata !"0x100\00im1\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [im1] [line 311] -!196 = metadata !{metadata !"0x100\00jp1\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [jp1] [line 311] -!197 = metadata !{metadata !"0x100\00jm1\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [jm1] [line 311] -!198 = metadata !{metadata !"0x100\00km1\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [km1] [line 311] -!199 = metadata !{metadata !"0x100\00kp1\00311\000", metadata !183, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [kp1] [line 311] -!200 = metadata !{metadata !"0x2e\00adi\00adi\00\00210\001\001\000\006\00256\001\00210", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 210] [local] [def] [adi] -!201 = metadata !{metadata !"0x2e\00add\00add\00\00187\001\001\000\006\00256\001\00187", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !202} ; [ DW_TAG_subprogram ] [line 187] [local] [def] [add] -!202 = metadata !{metadata !203, metadata !204, metadata !205, metadata !206} -!203 = metadata !{metadata !"0x100\00i\00193\000", metadata !201, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 193] -!204 = metadata !{metadata !"0x100\00j\00193\000", metadata !201, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 193] -!205 = metadata !{metadata !"0x100\00k\00193\000", metadata !201, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 193] -!206 = metadata !{metadata !"0x100\00m\00193\000", metadata !201, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 193] -!207 = metadata !{metadata !"0x2e\00z_solve\00z_solve\00\003457\001\001\000\006\00256\001\003457", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 3457] [local] [def] [z_solve] -!208 = metadata !{metadata !"0x2e\00z_backsubstitute\00z_backsubstitute\00\003480\001\001\000\006\00256\001\003480", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !209} ; [ DW_TAG_subprogram ] [line 3480] [local] [def] [z_backsubstitute] -!209 = metadata !{metadata !210, metadata !211, metadata !212, metadata !213, metadata !214} -!210 = metadata !{metadata !"0x100\00i\003492\000", metadata !208, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 3492] -!211 = metadata !{metadata !"0x100\00j\003492\000", metadata !208, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 3492] -!212 = metadata !{metadata !"0x100\00k\003492\000", metadata !208, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 3492] -!213 = metadata !{metadata !"0x100\00m\003492\000", metadata !208, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 3492] -!214 = metadata !{metadata !"0x100\00n\003492\000", metadata !208, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [n] [line 3492] -!215 = metadata !{metadata !"0x2e\00z_solve_cell\00z_solve_cell\00\003512\001\001\000\006\00256\001\003512", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !216} ; [ DW_TAG_subprogram ] [line 3512] [local] [def] [z_solve_cell] -!216 = metadata !{metadata !217, metadata !218, metadata !219, metadata !220} -!217 = metadata !{metadata !"0x100\00i\003527\000", metadata !215, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 3527] -!218 = metadata !{metadata !"0x100\00j\003527\000", metadata !215, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 3527] -!219 = metadata !{metadata !"0x100\00k\003527\000", metadata !215, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 3527] -!220 = metadata !{metadata !"0x100\00ksize\003527\000", metadata !215, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [ksize] [line 3527] -!221 = metadata !{metadata !"0x2e\00binvrhs\00binvrhs\00\003154\001\001\000\006\00256\001\003154", metadata !1, metadata !5, metadata !222, null, null, null, null, metadata !225} ; [ DW_TAG_subprogram ] [line 3154] [local] [def] [binvrhs] -!222 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !223, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!223 = metadata !{null, metadata !224, metadata !105} -!224 = metadata !{metadata !"0xf\00\000\0064\0064\000\000", null, null, metadata !91} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] -!225 = metadata !{metadata !226, metadata !227, metadata !228, metadata !229} -!226 = metadata !{metadata !"0x101\00lhs\0016780370\000", metadata !221, metadata !5, metadata !224} ; [ DW_TAG_arg_variable ] [lhs] [line 3154] -!227 = metadata !{metadata !"0x101\00r\0033557586\000", metadata !221, metadata !5, metadata !105} ; [ DW_TAG_arg_variable ] [r] [line 3154] -!228 = metadata !{metadata !"0x100\00pivot\003159\000", metadata !221, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [pivot] [line 3159] -!229 = metadata !{metadata !"0x100\00coeff\003159\000", metadata !221, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [coeff] [line 3159] -!230 = metadata !{metadata !"0x2e\00matmul_sub\00matmul_sub\00\002841\001\001\000\006\00256\001\002842", metadata !1, metadata !5, metadata !231, null, null, null, null, metadata !233} ; [ DW_TAG_subprogram ] [line 2841] [local] [def] [scope 2842] [matmul_sub] -!231 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !232, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!232 = metadata !{null, metadata !224, metadata !224, metadata !224} -!233 = metadata !{metadata !234, metadata !235, metadata !236, metadata !237} -!234 = metadata !{metadata !"0x101\00ablock\0016780057\000", metadata !230, metadata !5, metadata !224} ; [ DW_TAG_arg_variable ] [ablock] [line 2841] -!235 = metadata !{metadata !"0x101\00bblock\0033557273\000", metadata !230, metadata !5, metadata !224} ; [ DW_TAG_arg_variable ] [bblock] [line 2841] -!236 = metadata !{metadata !"0x101\00cblock\0050334490\000", metadata !230, metadata !5, metadata !224} ; [ DW_TAG_arg_variable ] [cblock] [line 2842] -!237 = metadata !{metadata !"0x100\00j\002851\000", metadata !230, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 2851] -!238 = metadata !{metadata !"0x2e\00matvec_sub\00matvec_sub\00\002814\001\001\000\006\00256\001\002814", metadata !1, metadata !5, metadata !239, null, null, null, null, metadata !241} ; [ DW_TAG_subprogram ] [line 2814] [local] [def] [matvec_sub] -!239 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !240, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!240 = metadata !{null, metadata !224, metadata !105, metadata !105} -!241 = metadata !{metadata !242, metadata !243, metadata !244, metadata !245} -!242 = metadata !{metadata !"0x101\00ablock\0016780030\000", metadata !238, metadata !5, metadata !224} ; [ DW_TAG_arg_variable ] [ablock] [line 2814] -!243 = metadata !{metadata !"0x101\00avec\0033557246\000", metadata !238, metadata !5, metadata !105} ; [ DW_TAG_arg_variable ] [avec] [line 2814] -!244 = metadata !{metadata !"0x101\00bvec\0050334462\000", metadata !238, metadata !5, metadata !105} ; [ DW_TAG_arg_variable ] [bvec] [line 2814] -!245 = metadata !{metadata !"0x100\00i\002823\000", metadata !238, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 2823] -!246 = metadata !{metadata !"0x2e\00binvcrhs\00binvcrhs\00\002885\001\001\000\006\00256\001\002885", metadata !1, metadata !5, metadata !247, null, null, null, null, metadata !249} ; [ DW_TAG_subprogram ] [line 2885] [local] [def] [binvcrhs] -!247 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !248, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!248 = metadata !{null, metadata !224, metadata !224, metadata !105} -!249 = metadata !{metadata !250, metadata !251, metadata !252, metadata !253, metadata !254} -!250 = metadata !{metadata !"0x101\00lhs\0016780101\000", metadata !246, metadata !5, metadata !224} ; [ DW_TAG_arg_variable ] [lhs] [line 2885] -!251 = metadata !{metadata !"0x101\00c\0033557317\000", metadata !246, metadata !5, metadata !224} ; [ DW_TAG_arg_variable ] [c] [line 2885] -!252 = metadata !{metadata !"0x101\00r\0050334533\000", metadata !246, metadata !5, metadata !105} ; [ DW_TAG_arg_variable ] [r] [line 2885] -!253 = metadata !{metadata !"0x100\00pivot\002890\000", metadata !246, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [pivot] [line 2890] -!254 = metadata !{metadata !"0x100\00coeff\002890\000", metadata !246, metadata !5, metadata !20} ; [ DW_TAG_auto_variable ] [coeff] [line 2890] -!255 = metadata !{metadata !"0x2e\00lhsz\00lhsz\00\001475\001\001\000\006\00256\001\001475", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !256} ; [ DW_TAG_subprogram ] [line 1475] [local] [def] [lhsz] -!256 = metadata !{metadata !257, metadata !258, metadata !259} -!257 = metadata !{metadata !"0x100\00i\001484\000", metadata !255, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 1484] -!258 = metadata !{metadata !"0x100\00j\001484\000", metadata !255, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 1484] -!259 = metadata !{metadata !"0x100\00k\001484\000", metadata !255, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 1484] -!260 = metadata !{metadata !"0x2e\00y_solve\00y_solve\00\003299\001\001\000\006\00256\001\003299", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 3299] [local] [def] [y_solve] -!261 = metadata !{metadata !"0x2e\00y_backsubstitute\00y_backsubstitute\00\003323\001\001\000\006\00256\001\003323", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !262} ; [ DW_TAG_subprogram ] [line 3323] [local] [def] [y_backsubstitute] -!262 = metadata !{metadata !263, metadata !264, metadata !265, metadata !266, metadata !267} -!263 = metadata !{metadata !"0x100\00i\003335\000", metadata !261, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 3335] -!264 = metadata !{metadata !"0x100\00j\003335\000", metadata !261, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 3335] -!265 = metadata !{metadata !"0x100\00k\003335\000", metadata !261, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 3335] -!266 = metadata !{metadata !"0x100\00m\003335\000", metadata !261, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 3335] -!267 = metadata !{metadata !"0x100\00n\003335\000", metadata !261, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [n] [line 3335] -!268 = metadata !{metadata !"0x2e\00y_solve_cell\00y_solve_cell\00\003355\001\001\000\006\00256\001\003355", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !269} ; [ DW_TAG_subprogram ] [line 3355] [local] [def] [y_solve_cell] -!269 = metadata !{metadata !270, metadata !271, metadata !272, metadata !273} -!270 = metadata !{metadata !"0x100\00i\003370\000", metadata !268, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 3370] -!271 = metadata !{metadata !"0x100\00j\003370\000", metadata !268, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 3370] -!272 = metadata !{metadata !"0x100\00k\003370\000", metadata !268, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 3370] -!273 = metadata !{metadata !"0x100\00jsize\003370\000", metadata !268, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [jsize] [line 3370] -!274 = metadata !{metadata !"0x2e\00lhsy\00lhsy\00\001181\001\001\000\006\00256\001\001181", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !275} ; [ DW_TAG_subprogram ] [line 1181] [local] [def] [lhsy] -!275 = metadata !{metadata !276, metadata !277, metadata !278} -!276 = metadata !{metadata !"0x100\00i\001190\000", metadata !274, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 1190] -!277 = metadata !{metadata !"0x100\00j\001190\000", metadata !274, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 1190] -!278 = metadata !{metadata !"0x100\00k\001190\000", metadata !274, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 1190] -!279 = metadata !{metadata !"0x2e\00x_solve\00x_solve\00\002658\001\001\000\006\00256\001\002658", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 2658] [local] [def] [x_solve] -!280 = metadata !{metadata !"0x2e\00x_backsubstitute\00x_backsubstitute\00\002684\001\001\000\006\00256\001\002684", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !281} ; [ DW_TAG_subprogram ] [line 2684] [local] [def] [x_backsubstitute] -!281 = metadata !{metadata !282, metadata !283, metadata !284, metadata !285, metadata !286} -!282 = metadata !{metadata !"0x100\00i\002696\000", metadata !280, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 2696] -!283 = metadata !{metadata !"0x100\00j\002696\000", metadata !280, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 2696] -!284 = metadata !{metadata !"0x100\00k\002696\000", metadata !280, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 2696] -!285 = metadata !{metadata !"0x100\00m\002696\000", metadata !280, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [m] [line 2696] -!286 = metadata !{metadata !"0x100\00n\002696\000", metadata !280, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [n] [line 2696] -!287 = metadata !{metadata !"0x2e\00x_solve_cell\00x_solve_cell\00\002716\001\001\000\006\00256\001\002716", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !288} ; [ DW_TAG_subprogram ] [line 2716] [local] [def] [x_solve_cell] -!288 = metadata !{metadata !289, metadata !290, metadata !291, metadata !292} -!289 = metadata !{metadata !"0x100\00i\002728\000", metadata !287, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 2728] -!290 = metadata !{metadata !"0x100\00j\002728\000", metadata !287, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 2728] -!291 = metadata !{metadata !"0x100\00k\002728\000", metadata !287, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 2728] -!292 = metadata !{metadata !"0x100\00isize\002728\000", metadata !287, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [isize] [line 2728] -!293 = metadata !{metadata !"0x2e\00lhsx\00lhsx\00\00898\001\001\000\006\00256\001\00898", metadata !1, metadata !5, metadata !115, null, null, null, null, metadata !294} ; [ DW_TAG_subprogram ] [line 898] [local] [def] [lhsx] -!294 = metadata !{metadata !295, metadata !296, metadata !297} -!295 = metadata !{metadata !"0x100\00i\00907\000", metadata !293, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [i] [line 907] -!296 = metadata !{metadata !"0x100\00j\00907\000", metadata !293, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [j] [line 907] -!297 = metadata !{metadata !"0x100\00k\00907\000", metadata !293, metadata !5, metadata !8} ; [ DW_TAG_auto_variable ] [k] [line 907] -!298 = metadata !{metadata !299, metadata !304, metadata !305, metadata !309, metadata !310, metadata !311, metadata !312, metadata !313, metadata !314, metadata !315, metadata !316, metadata !317, metadata !318, metadata !319, metadata !320, metadata !321, metadata !322, metadata !323, metadata !324, metadata !325, metadata !326, metadata !327, metadata !328, metadata !329, metadata !330, metadata !331, metadata !332, metadata !333, metadata !334, metadata !335, metadata !336, metadata !337, metadata !338, metadata !339, metadata !340, metadata !341, metadata !342, metadata !343, metadata !347, metadata !350, metadata !351, metadata !352, metadata !353, metadata !354, metadata !355, metadata !356, metadata !360, metadata !361, metadata !362, metadata !363, metadata !364, metadata !365, metadata !366, metadata !367, metadata !368, metadata !369, metadata !370, metadata !371, metadata !372, metadata !373, metadata !374, metadata !375, metadata !376, metadata !377, metadata !378, metadata !379, metadata !380, metadata !381, metadata !382, metadata !383, metadata !384, metadata !385, metadata !386, metadata !387, metadata !388, metadata !389, metadata !390, metadata !391, metadata !392, metadata !393, metadata !394, metadata !395, metadata !396, metadata !397, metadata !398, metadata !399, metadata !400, metadata !401, metadata !402, metadata !403, metadata !404, metadata !405, metadata !406, metadata !407, metadata !408, metadata !409, metadata !410, metadata !411, metadata !412, metadata !413, metadata !414, metadata !415, metadata !416, metadata !417, metadata !418, metadata !419, metadata !422, metadata !426, metadata !427, metadata !430, metadata !431, metadata !434, metadata !435, metadata !436, metadata !437} -!299 = metadata !{metadata !"0x34\00grid_points\00grid_points\00\0028\001\001", null, metadata !300, metadata !302, [3 x i32]* @grid_points, null} ; [ DW_TAG_variable ] [grid_points] [line 28] [local] [def] -!300 = metadata !{metadata !"0x29", metadata !301} ; [ DW_TAG_file_type ] [/home/hfinkel/src/NPB2.3-omp-C/BT/./header.h] -!301 = metadata !{metadata !"./header.h", metadata !"/home/hfinkel/src/NPB2.3-omp-C/BT"} -!302 = metadata !{metadata !"0x1\00\000\0096\0032\000\000", null, null, metadata !8, metadata !303, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 96, align 32, offset 0] [from int] -!303 = metadata !{metadata !178} -!304 = metadata !{metadata !"0x34\00dt\00dt\00\0035\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dt] [line 35] [local] [def] -!305 = metadata !{metadata !"0x34\00rhs\00rhs\00\0068\001\001", null, metadata !300, metadata !306, null, null} ; [ DW_TAG_variable ] [rhs] [line 68] [local] [def] -!306 = metadata !{metadata !"0x1\00\000\001385839040\0064\000\000", null, null, metadata !20, metadata !307, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1385839040, align 64, offset 0] [from double] -!307 = metadata !{metadata !308, metadata !308, metadata !308, metadata !93} -!308 = metadata !{metadata !"0x21\000\00163"} ; [ DW_TAG_subrange_type ] [0, 162] -!309 = metadata !{metadata !"0x34\00zzcon5\00zzcon5\00\0042\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [zzcon5] [line 42] [local] [def] -!310 = metadata !{metadata !"0x34\00zzcon4\00zzcon4\00\0042\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [zzcon4] [line 42] [local] [def] -!311 = metadata !{metadata !"0x34\00zzcon3\00zzcon3\00\0042\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [zzcon3] [line 42] [local] [def] -!312 = metadata !{metadata !"0x34\00dz5tz1\00dz5tz1\00\0043\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz5tz1] [line 43] [local] [def] -!313 = metadata !{metadata !"0x34\00dz4tz1\00dz4tz1\00\0043\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz4tz1] [line 43] [local] [def] -!314 = metadata !{metadata !"0x34\00dz3tz1\00dz3tz1\00\0043\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz3tz1] [line 43] [local] [def] -!315 = metadata !{metadata !"0x34\00zzcon2\00zzcon2\00\0042\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [zzcon2] [line 42] [local] [def] -!316 = metadata !{metadata !"0x34\00dz2tz1\00dz2tz1\00\0043\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz2tz1] [line 43] [local] [def] -!317 = metadata !{metadata !"0x34\00tz2\00tz2\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tz2] [line 31] [local] [def] -!318 = metadata !{metadata !"0x34\00dz1tz1\00dz1tz1\00\0043\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz1tz1] [line 43] [local] [def] -!319 = metadata !{metadata !"0x34\00yycon5\00yycon5\00\0040\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [yycon5] [line 40] [local] [def] -!320 = metadata !{metadata !"0x34\00yycon4\00yycon4\00\0040\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [yycon4] [line 40] [local] [def] -!321 = metadata !{metadata !"0x34\00yycon3\00yycon3\00\0040\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [yycon3] [line 40] [local] [def] -!322 = metadata !{metadata !"0x34\00dy5ty1\00dy5ty1\00\0041\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy5ty1] [line 41] [local] [def] -!323 = metadata !{metadata !"0x34\00dy4ty1\00dy4ty1\00\0041\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy4ty1] [line 41] [local] [def] -!324 = metadata !{metadata !"0x34\00dy3ty1\00dy3ty1\00\0041\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy3ty1] [line 41] [local] [def] -!325 = metadata !{metadata !"0x34\00yycon2\00yycon2\00\0040\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [yycon2] [line 40] [local] [def] -!326 = metadata !{metadata !"0x34\00dy2ty1\00dy2ty1\00\0041\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy2ty1] [line 41] [local] [def] -!327 = metadata !{metadata !"0x34\00ty2\00ty2\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [ty2] [line 31] [local] [def] -!328 = metadata !{metadata !"0x34\00dy1ty1\00dy1ty1\00\0041\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy1ty1] [line 41] [local] [def] -!329 = metadata !{metadata !"0x34\00dssp\00dssp\00\0035\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dssp] [line 35] [local] [def] -!330 = metadata !{metadata !"0x34\00c1\00c1\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c1] [line 45] [local] [def] -!331 = metadata !{metadata !"0x34\00xxcon5\00xxcon5\00\0038\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [xxcon5] [line 38] [local] [def] -!332 = metadata !{metadata !"0x34\00xxcon4\00xxcon4\00\0038\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [xxcon4] [line 38] [local] [def] -!333 = metadata !{metadata !"0x34\00xxcon3\00xxcon3\00\0038\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [xxcon3] [line 38] [local] [def] -!334 = metadata !{metadata !"0x34\00dx5tx1\00dx5tx1\00\0039\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx5tx1] [line 39] [local] [def] -!335 = metadata !{metadata !"0x34\00dx4tx1\00dx4tx1\00\0039\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx4tx1] [line 39] [local] [def] -!336 = metadata !{metadata !"0x34\00dx3tx1\00dx3tx1\00\0039\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx3tx1] [line 39] [local] [def] -!337 = metadata !{metadata !"0x34\00c2\00c2\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c2] [line 45] [local] [def] -!338 = metadata !{metadata !"0x34\00con43\00con43\00\0048\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [con43] [line 48] [local] [def] -!339 = metadata !{metadata !"0x34\00xxcon2\00xxcon2\00\0038\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [xxcon2] [line 38] [local] [def] -!340 = metadata !{metadata !"0x34\00dx2tx1\00dx2tx1\00\0039\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx2tx1] [line 39] [local] [def] -!341 = metadata !{metadata !"0x34\00tx2\00tx2\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tx2] [line 31] [local] [def] -!342 = metadata !{metadata !"0x34\00dx1tx1\00dx1tx1\00\0039\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx1tx1] [line 39] [local] [def] -!343 = metadata !{metadata !"0x34\00forcing\00forcing\00\0066\001\001", null, metadata !300, metadata !344, null, null} ; [ DW_TAG_variable ] [forcing] [line 66] [local] [def] -!344 = metadata !{metadata !"0x1\00\000\001663006848\0064\000\000", null, null, metadata !20, metadata !345, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1663006848, align 64, offset 0] [from double] -!345 = metadata !{metadata !308, metadata !308, metadata !308, metadata !346} -!346 = metadata !{metadata !"0x21\000\006"} ; [ DW_TAG_subrange_type ] [0, 5] -!347 = metadata !{metadata !"0x34\00qs\00qs\00\0063\001\001", null, metadata !300, metadata !348, null, null} ; [ DW_TAG_variable ] [qs] [line 63] [local] [def] -!348 = metadata !{metadata !"0x1\00\000\00277167808\0064\000\000", null, null, metadata !20, metadata !349, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 277167808, align 64, offset 0] [from double] -!349 = metadata !{metadata !308, metadata !308, metadata !308} -!350 = metadata !{metadata !"0x34\00square\00square\00\0065\001\001", null, metadata !300, metadata !348, null, null} ; [ DW_TAG_variable ] [square] [line 65] [local] [def] -!351 = metadata !{metadata !"0x34\00ws\00ws\00\0062\001\001", null, metadata !300, metadata !348, null, null} ; [ DW_TAG_variable ] [ws] [line 62] [local] [def] -!352 = metadata !{metadata !"0x34\00vs\00vs\00\0061\001\001", null, metadata !300, metadata !348, null, null} ; [ DW_TAG_variable ] [vs] [line 61] [local] [def] -!353 = metadata !{metadata !"0x34\00us\00us\00\0060\001\001", null, metadata !300, metadata !348, null, null} ; [ DW_TAG_variable ] [us] [line 60] [local] [def] -!354 = metadata !{metadata !"0x34\00rho_i\00rho_i\00\0064\001\001", null, metadata !300, metadata !348, null, null} ; [ DW_TAG_variable ] [rho_i] [line 64] [local] [def] -!355 = metadata !{metadata !"0x34\00u\00u\00\0067\001\001", null, metadata !300, metadata !306, null, null} ; [ DW_TAG_variable ] [u] [line 67] [local] [def] -!356 = metadata !{metadata !"0x34\00ce\00ce\00\0036\001\001", null, metadata !300, metadata !357, null, null} ; [ DW_TAG_variable ] [ce] [line 36] [local] [def] -!357 = metadata !{metadata !"0x1\00\000\004160\0064\000\000", null, null, metadata !20, metadata !358, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 4160, align 64, offset 0] [from double] -!358 = metadata !{metadata !93, metadata !359} -!359 = metadata !{metadata !"0x21\000\0013"} ; [ DW_TAG_subrange_type ] [0, 12] -!360 = metadata !{metadata !"0x34\00dnzm1\00dnzm1\00\0044\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dnzm1] [line 44] [local] [def] -!361 = metadata !{metadata !"0x34\00dnym1\00dnym1\00\0044\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dnym1] [line 44] [local] [def] -!362 = metadata !{metadata !"0x34\00dnxm1\00dnxm1\00\0044\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dnxm1] [line 44] [local] [def] -!363 = metadata !{metadata !"0x34\00zzcon1\00zzcon1\00\0042\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [zzcon1] [line 42] [local] [def] -!364 = metadata !{metadata !"0x34\00yycon1\00yycon1\00\0040\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [yycon1] [line 40] [local] [def] -!365 = metadata !{metadata !"0x34\00xxcon1\00xxcon1\00\0038\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [xxcon1] [line 38] [local] [def] -!366 = metadata !{metadata !"0x34\00con16\00con16\00\0048\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [con16] [line 48] [local] [def] -!367 = metadata !{metadata !"0x34\00c2iv\00c2iv\00\0048\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c2iv] [line 48] [local] [def] -!368 = metadata !{metadata !"0x34\00c3c4tz3\00c3c4tz3\00\0048\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c3c4tz3] [line 48] [local] [def] -!369 = metadata !{metadata !"0x34\00c3c4ty3\00c3c4ty3\00\0048\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c3c4ty3] [line 48] [local] [def] -!370 = metadata !{metadata !"0x34\00c3c4tx3\00c3c4tx3\00\0048\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c3c4tx3] [line 48] [local] [def] -!371 = metadata !{metadata !"0x34\00comz6\00comz6\00\0047\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [comz6] [line 47] [local] [def] -!372 = metadata !{metadata !"0x34\00comz5\00comz5\00\0047\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [comz5] [line 47] [local] [def] -!373 = metadata !{metadata !"0x34\00comz4\00comz4\00\0047\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [comz4] [line 47] [local] [def] -!374 = metadata !{metadata !"0x34\00comz1\00comz1\00\0047\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [comz1] [line 47] [local] [def] -!375 = metadata !{metadata !"0x34\00dtdssp\00dtdssp\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dtdssp] [line 45] [local] [def] -!376 = metadata !{metadata !"0x34\00c2dttz1\00c2dttz1\00\0047\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c2dttz1] [line 47] [local] [def] -!377 = metadata !{metadata !"0x34\00c2dtty1\00c2dtty1\00\0047\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c2dtty1] [line 47] [local] [def] -!378 = metadata !{metadata !"0x34\00c2dttx1\00c2dttx1\00\0047\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c2dttx1] [line 47] [local] [def] -!379 = metadata !{metadata !"0x34\00dttz2\00dttz2\00\0046\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dttz2] [line 46] [local] [def] -!380 = metadata !{metadata !"0x34\00dttz1\00dttz1\00\0046\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dttz1] [line 46] [local] [def] -!381 = metadata !{metadata !"0x34\00dtty2\00dtty2\00\0046\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dtty2] [line 46] [local] [def] -!382 = metadata !{metadata !"0x34\00dtty1\00dtty1\00\0046\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dtty1] [line 46] [local] [def] -!383 = metadata !{metadata !"0x34\00dttx2\00dttx2\00\0046\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dttx2] [line 46] [local] [def] -!384 = metadata !{metadata !"0x34\00dttx1\00dttx1\00\0046\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dttx1] [line 46] [local] [def] -!385 = metadata !{metadata !"0x34\00c5dssp\00c5dssp\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c5dssp] [line 45] [local] [def] -!386 = metadata !{metadata !"0x34\00c4dssp\00c4dssp\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c4dssp] [line 45] [local] [def] -!387 = metadata !{metadata !"0x34\00dzmax\00dzmax\00\0037\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dzmax] [line 37] [local] [def] -!388 = metadata !{metadata !"0x34\00dymax\00dymax\00\0037\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dymax] [line 37] [local] [def] -!389 = metadata !{metadata !"0x34\00dxmax\00dxmax\00\0037\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dxmax] [line 37] [local] [def] -!390 = metadata !{metadata !"0x34\00dz5\00dz5\00\0034\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz5] [line 34] [local] [def] -!391 = metadata !{metadata !"0x34\00dz4\00dz4\00\0034\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz4] [line 34] [local] [def] -!392 = metadata !{metadata !"0x34\00dz3\00dz3\00\0034\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz3] [line 34] [local] [def] -!393 = metadata !{metadata !"0x34\00dz2\00dz2\00\0034\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz2] [line 34] [local] [def] -!394 = metadata !{metadata !"0x34\00dz1\00dz1\00\0034\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dz1] [line 34] [local] [def] -!395 = metadata !{metadata !"0x34\00dy5\00dy5\00\0033\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy5] [line 33] [local] [def] -!396 = metadata !{metadata !"0x34\00dy4\00dy4\00\0033\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy4] [line 33] [local] [def] -!397 = metadata !{metadata !"0x34\00dy3\00dy3\00\0033\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy3] [line 33] [local] [def] -!398 = metadata !{metadata !"0x34\00dy2\00dy2\00\0033\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy2] [line 33] [local] [def] -!399 = metadata !{metadata !"0x34\00dy1\00dy1\00\0033\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dy1] [line 33] [local] [def] -!400 = metadata !{metadata !"0x34\00dx5\00dx5\00\0032\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx5] [line 32] [local] [def] -!401 = metadata !{metadata !"0x34\00dx4\00dx4\00\0032\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx4] [line 32] [local] [def] -!402 = metadata !{metadata !"0x34\00dx3\00dx3\00\0032\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx3] [line 32] [local] [def] -!403 = metadata !{metadata !"0x34\00dx2\00dx2\00\0032\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx2] [line 32] [local] [def] -!404 = metadata !{metadata !"0x34\00dx1\00dx1\00\0032\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [dx1] [line 32] [local] [def] -!405 = metadata !{metadata !"0x34\00tz3\00tz3\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tz3] [line 31] [local] [def] -!406 = metadata !{metadata !"0x34\00tz1\00tz1\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tz1] [line 31] [local] [def] -!407 = metadata !{metadata !"0x34\00ty3\00ty3\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [ty3] [line 31] [local] [def] -!408 = metadata !{metadata !"0x34\00ty1\00ty1\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [ty1] [line 31] [local] [def] -!409 = metadata !{metadata !"0x34\00tx3\00tx3\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tx3] [line 31] [local] [def] -!410 = metadata !{metadata !"0x34\00tx1\00tx1\00\0031\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tx1] [line 31] [local] [def] -!411 = metadata !{metadata !"0x34\00conz1\00conz1\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [conz1] [line 45] [local] [def] -!412 = metadata !{metadata !"0x34\00c1345\00c1345\00\0044\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c1345] [line 44] [local] [def] -!413 = metadata !{metadata !"0x34\00c3c4\00c3c4\00\0044\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c3c4] [line 44] [local] [def] -!414 = metadata !{metadata !"0x34\00c1c5\00c1c5\00\0044\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c1c5] [line 44] [local] [def] -!415 = metadata !{metadata !"0x34\00c1c2\00c1c2\00\0044\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c1c2] [line 44] [local] [def] -!416 = metadata !{metadata !"0x34\00c5\00c5\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c5] [line 45] [local] [def] -!417 = metadata !{metadata !"0x34\00c4\00c4\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c4] [line 45] [local] [def] -!418 = metadata !{metadata !"0x34\00c3\00c3\00\0045\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [c3] [line 45] [local] [def] -!419 = metadata !{metadata !"0x34\00lhs\00lhs\00\0069\001\001", null, metadata !300, metadata !420, null, null} ; [ DW_TAG_variable ] [lhs] [line 69] [local] [def] -!420 = metadata !{metadata !"0x1\00\000\0020787585600\0064\000\000", null, null, metadata !20, metadata !421, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 20787585600, align 64, offset 0] [from double] -!421 = metadata !{metadata !308, metadata !308, metadata !308, metadata !178, metadata !93, metadata !93} -!422 = metadata !{metadata !"0x34\00q\00q\00\0073\001\001", null, metadata !300, metadata !423, null, null} ; [ DW_TAG_variable ] [q] [line 73] [local] [def] -!423 = metadata !{metadata !"0x1\00\000\0010368\0064\000\000", null, null, metadata !20, metadata !424, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 10368, align 64, offset 0] [from double] -!424 = metadata !{metadata !425} -!425 = metadata !{metadata !"0x21\000\00162"} ; [ DW_TAG_subrange_type ] [0, 161] -!426 = metadata !{metadata !"0x34\00cuf\00cuf\00\0072\001\001", null, metadata !300, metadata !423, null, null} ; [ DW_TAG_variable ] [cuf] [line 72] [local] [def] -!427 = metadata !{metadata !"0x34\00buf\00buf\00\0075\001\001", null, metadata !300, metadata !428, null, null} ; [ DW_TAG_variable ] [buf] [line 75] [local] [def] -!428 = metadata !{metadata !"0x1\00\000\0051840\0064\000\000", null, null, metadata !20, metadata !429, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 51840, align 64, offset 0] [from double] -!429 = metadata !{metadata !425, metadata !93} -!430 = metadata !{metadata !"0x34\00ue\00ue\00\0074\001\001", null, metadata !300, metadata !428, null, null} ; [ DW_TAG_variable ] [ue] [line 74] [local] [def] -!431 = metadata !{metadata !"0x34\00njac\00njac\00\0086\001\001", null, metadata !300, metadata !432, null, null} ; [ DW_TAG_variable ] [njac] [line 86] [local] [def] -!432 = metadata !{metadata !"0x1\00\000\006886684800\0064\000\000", null, null, metadata !20, metadata !433, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 6886684800, align 64, offset 0] [from double] -!433 = metadata !{metadata !308, metadata !308, metadata !425, metadata !93, metadata !93} -!434 = metadata !{metadata !"0x34\00fjac\00fjac\00\0084\001\001", null, metadata !300, metadata !432, null, null} ; [ DW_TAG_variable ] [fjac] [line 84] [local] [def] -!435 = metadata !{metadata !"0x34\00tmp3\00tmp3\00\0088\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tmp3] [line 88] [local] [def] -!436 = metadata !{metadata !"0x34\00tmp2\00tmp2\00\0088\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tmp2] [line 88] [local] [def] -!437 = metadata !{metadata !"0x34\00tmp1\00tmp1\00\0088\001\001", null, metadata !300, metadata !20, null, null} ; [ DW_TAG_variable ] [tmp1] [line 88] [local] [def] -!438 = metadata !{i32 2, metadata !"Dwarf Version", i32 4} -!439 = metadata !{i32 1898, i32 0, metadata !440, null} -!440 = metadata !{metadata !"0xb\001898\000\00107", metadata !1, metadata !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!441 = metadata !{i32 1913, i32 0, metadata !442, null} -!442 = metadata !{metadata !"0xb\001913\000\00115", metadata !1, metadata !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!443 = metadata !{i32 1923, i32 0, metadata !114, null} -!444 = metadata !{metadata !"int", metadata !445} -!445 = metadata !{metadata !"omnipotent char", metadata !446} -!446 = metadata !{metadata !"Simple C/C++ TBAA"} -!447 = metadata !{i32 1} -!448 = metadata !{i32 1925, i32 0, metadata !449, null} -!449 = metadata !{metadata !"0xb\001925\000\00121", metadata !1, metadata !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!450 = metadata !{i32 1939, i32 0, metadata !451, null} -!451 = metadata !{metadata !"0xb\001939\000\00127", metadata !1, metadata !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!452 = metadata !{i32 1940, i32 0, metadata !453, null} -!453 = metadata !{metadata !"0xb\001940\000\00129", metadata !1, metadata !454} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!454 = metadata !{metadata !"0xb\001939\000\00128", metadata !1, metadata !451} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!455 = metadata !{i32 1941, i32 0, metadata !456, null} -!456 = metadata !{metadata !"0xb\001941\000\00131", metadata !1, metadata !457} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!457 = metadata !{metadata !"0xb\001940\000\00130", metadata !1, metadata !453} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!458 = metadata !{i32 2020, i32 0, metadata !459, null} -!459 = metadata !{metadata !"0xb\002020\000\00149", metadata !1, metadata !460} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!460 = metadata !{metadata !"0xb\002019\000\00148", metadata !1, metadata !461} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!461 = metadata !{metadata !"0xb\002019\000\00147", metadata !1, metadata !462} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!462 = metadata !{metadata !"0xb\002018\000\00146", metadata !1, metadata !463} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!463 = metadata !{metadata !"0xb\002018\000\00145", metadata !1, metadata !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] -!464 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x11\0012\00clang version 3.4 (trunk 190311)\001\00\000\00\000", !1, !2, !2, !3, !298, !2} ; [ DW_TAG_compile_unit ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] [DW_LANG_C99] +!1 = !{!"bt.c", !"/home/hfinkel/src/NPB2.3-omp-C/BT"} +!2 = !{} +!3 = !{!4, !82, !102, !114, !132, !145, !154, !155, !162, !183, !200, !201, !207, !208, !215, !221, !230, !238, !246, !255, !260, !261, !268, !274, !279, !280, !287, !293} +!4 = !{!"0x2e\00main\00main\00\0074\000\001\000\006\00256\001\0074", !1, !5, !6, null, null, null, null, !12} ; [ DW_TAG_subprogram ] [line 74] [def] [main] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = !{!8, !8, !9} +!8 = !{!"0x24\00int\000\0032\0032\000\000\005", null, null} ; [ DW_TAG_base_type ] [int] [line 0, size 32, align 32, offset 0, enc DW_ATE_signed] +!9 = !{!"0xf\00\000\0064\0064\000\000", null, null, !10} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] +!10 = !{!"0xf\00\000\0064\0064\000\000", null, null, !11} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from char] +!11 = !{!"0x24\00char\000\008\008\000\000\008", null, null} ; [ DW_TAG_base_type ] [char] [line 0, size 8, align 8, offset 0, enc DW_ATE_unsigned_char] +!12 = !{!13, !14, !15, !16, !17, !18, !19, !21, !22, !23, !25, !26} +!13 = !{!"0x101\00argc\0016777290\000", !4, !5, !8} ; [ DW_TAG_arg_variable ] [argc] [line 74] +!14 = !{!"0x101\00argv\0033554506\000", !4, !5, !9} ; [ DW_TAG_arg_variable ] [argv] [line 74] +!15 = !{!"0x100\00niter\0076\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [niter] [line 76] +!16 = !{!"0x100\00step\0076\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [step] [line 76] +!17 = !{!"0x100\00n3\0076\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [n3] [line 76] +!18 = !{!"0x100\00nthreads\0077\000", !4, !5, !8} ; [ DW_TAG_auto_variable ] [nthreads] [line 77] +!19 = !{!"0x100\00navg\0078\000", !4, !5, !20} ; [ DW_TAG_auto_variable ] [navg] [line 78] +!20 = !{!"0x24\00double\000\0064\0064\000\000\004", null, null} ; [ DW_TAG_base_type ] [double] [line 0, size 64, align 64, offset 0, enc DW_ATE_float] +!21 = !{!"0x100\00mflops\0078\000", !4, !5, !20} ; [ DW_TAG_auto_variable ] [mflops] [line 78] +!22 = !{!"0x100\00tmax\0080\000", !4, !5, !20} ; [ DW_TAG_auto_variable ] [tmax] [line 80] +!23 = !{!"0x100\00verified\0081\000", !4, !5, !24} ; [ DW_TAG_auto_variable ] [verified] [line 81] +!24 = !{!"0x16\00boolean\0012\000\000\000\000", !1, null, !8} ; [ DW_TAG_typedef ] [boolean] [line 12, size 0, align 0, offset 0] [from int] +!25 = !{!"0x100\00class\0082\000", !4, !5, !11} ; [ DW_TAG_auto_variable ] [class] [line 82] +!26 = !{!"0x100\00fp\0083\000", !4, !5, !27} ; [ DW_TAG_auto_variable ] [fp] [line 83] +!27 = !{!"0xf\00\000\0064\0064\000\000", null, null, !28} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from FILE] +!28 = !{!"0x16\00FILE\0049\000\000\000\000", !1, null, !29} ; [ DW_TAG_typedef ] [FILE] [line 49, size 0, align 0, offset 0] [from _IO_FILE] +!29 = !{!"0x13\00_IO_FILE\00271\001728\0064\000\000\000", !30, null, null, !31, null, null, null} ; [ DW_TAG_structure_type ] [_IO_FILE] [line 271, size 1728, align 64, offset 0] [def] [from ] +!30 = !{!"/usr/include/libio.h", !"/home/hfinkel/src/NPB2.3-omp-C/BT"} +!31 = !{!32, !33, !34, !35, !36, !37, !38, !39, !40, !41, !42, !43, !44, !52, !53, !54, !55, !58, !60, !62, !66, !68, !70, !71, !72, !73, !74, !77, !78} +!32 = !{!"0xd\00_flags\00272\0032\0032\000\000", !30, !29, !8} ; [ DW_TAG_member ] [_flags] [line 272, size 32, align 32, offset 0] [from int] +!33 = !{!"0xd\00_IO_read_ptr\00277\0064\0064\0064\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_read_ptr] [line 277, size 64, align 64, offset 64] [from ] +!34 = !{!"0xd\00_IO_read_end\00278\0064\0064\00128\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_read_end] [line 278, size 64, align 64, offset 128] [from ] +!35 = !{!"0xd\00_IO_read_base\00279\0064\0064\00192\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_read_base] [line 279, size 64, align 64, offset 192] [from ] +!36 = !{!"0xd\00_IO_write_base\00280\0064\0064\00256\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_write_base] [line 280, size 64, align 64, offset 256] [from ] +!37 = !{!"0xd\00_IO_write_ptr\00281\0064\0064\00320\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_write_ptr] [line 281, size 64, align 64, offset 320] [from ] +!38 = !{!"0xd\00_IO_write_end\00282\0064\0064\00384\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_write_end] [line 282, size 64, align 64, offset 384] [from ] +!39 = !{!"0xd\00_IO_buf_base\00283\0064\0064\00448\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_buf_base] [line 283, size 64, align 64, offset 448] [from ] +!40 = !{!"0xd\00_IO_buf_end\00284\0064\0064\00512\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_buf_end] [line 284, size 64, align 64, offset 512] [from ] +!41 = !{!"0xd\00_IO_save_base\00286\0064\0064\00576\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_save_base] [line 286, size 64, align 64, offset 576] [from ] +!42 = !{!"0xd\00_IO_backup_base\00287\0064\0064\00640\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_backup_base] [line 287, size 64, align 64, offset 640] [from ] +!43 = !{!"0xd\00_IO_save_end\00288\0064\0064\00704\000", !30, !29, !10} ; [ DW_TAG_member ] [_IO_save_end] [line 288, size 64, align 64, offset 704] [from ] +!44 = !{!"0xd\00_markers\00290\0064\0064\00768\000", !30, !29, !45} ; [ DW_TAG_member ] [_markers] [line 290, size 64, align 64, offset 768] [from ] +!45 = !{!"0xf\00\000\0064\0064\000\000", null, null, !46} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _IO_marker] +!46 = !{!"0x13\00_IO_marker\00186\00192\0064\000\000\000", !30, null, null, !47, null, null, null} ; [ DW_TAG_structure_type ] [_IO_marker] [line 186, size 192, align 64, offset 0] [def] [from ] +!47 = !{!48, !49, !51} +!48 = !{!"0xd\00_next\00187\0064\0064\000\000", !30, !46, !45} ; [ DW_TAG_member ] [_next] [line 187, size 64, align 64, offset 0] [from ] +!49 = !{!"0xd\00_sbuf\00188\0064\0064\0064\000", !30, !46, !50} ; [ DW_TAG_member ] [_sbuf] [line 188, size 64, align 64, offset 64] [from ] +!50 = !{!"0xf\00\000\0064\0064\000\000", null, null, !29} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from _IO_FILE] +!51 = !{!"0xd\00_pos\00192\0032\0032\00128\000", !30, !46, !8} ; [ DW_TAG_member ] [_pos] [line 192, size 32, align 32, offset 128] [from int] +!52 = !{!"0xd\00_chain\00292\0064\0064\00832\000", !30, !29, !50} ; [ DW_TAG_member ] [_chain] [line 292, size 64, align 64, offset 832] [from ] +!53 = !{!"0xd\00_fileno\00294\0032\0032\00896\000", !30, !29, !8} ; [ DW_TAG_member ] [_fileno] [line 294, size 32, align 32, offset 896] [from int] +!54 = !{!"0xd\00_flags2\00298\0032\0032\00928\000", !30, !29, !8} ; [ DW_TAG_member ] [_flags2] [line 298, size 32, align 32, offset 928] [from int] +!55 = !{!"0xd\00_old_offset\00300\0064\0064\00960\000", !30, !29, !56} ; [ DW_TAG_member ] [_old_offset] [line 300, size 64, align 64, offset 960] [from __off_t] +!56 = !{!"0x16\00__off_t\00141\000\000\000\000", !30, null, !57} ; [ DW_TAG_typedef ] [__off_t] [line 141, size 0, align 0, offset 0] [from long int] +!57 = !{!"0x24\00long int\000\0064\0064\000\000\005", null, null} ; [ DW_TAG_base_type ] [long int] [line 0, size 64, align 64, offset 0, enc DW_ATE_signed] +!58 = !{!"0xd\00_cur_column\00304\0016\0016\001024\000", !30, !29, !59} ; [ DW_TAG_member ] [_cur_column] [line 304, size 16, align 16, offset 1024] [from unsigned short] +!59 = !{!"0x24\00unsigned short\000\0016\0016\000\000\007", null, null} ; [ DW_TAG_base_type ] [unsigned short] [line 0, size 16, align 16, offset 0, enc DW_ATE_unsigned] +!60 = !{!"0xd\00_vtable_offset\00305\008\008\001040\000", !30, !29, !61} ; [ DW_TAG_member ] [_vtable_offset] [line 305, size 8, align 8, offset 1040] [from signed char] +!61 = !{!"0x24\00signed char\000\008\008\000\000\006", null, null} ; [ DW_TAG_base_type ] [signed char] [line 0, size 8, align 8, offset 0, enc DW_ATE_signed_char] +!62 = !{!"0xd\00_shortbuf\00306\008\008\001048\000", !30, !29, !63} ; [ DW_TAG_member ] [_shortbuf] [line 306, size 8, align 8, offset 1048] [from ] +!63 = !{!"0x1\00\000\008\008\000\000", null, null, !11, !64, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 8, align 8, offset 0] [from char] +!64 = !{!65} +!65 = !{!"0x21\000\001"} ; [ DW_TAG_subrange_type ] [0, 0] +!66 = !{!"0xd\00_lock\00310\0064\0064\001088\000", !30, !29, !67} ; [ DW_TAG_member ] [_lock] [line 310, size 64, align 64, offset 1088] [from ] +!67 = !{!"0xf\00\000\0064\0064\000\000", null, null, null} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] +!68 = !{!"0xd\00_offset\00319\0064\0064\001152\000", !30, !29, !69} ; [ DW_TAG_member ] [_offset] [line 319, size 64, align 64, offset 1152] [from __off64_t] +!69 = !{!"0x16\00__off64_t\00142\000\000\000\000", !30, null, !57} ; [ DW_TAG_typedef ] [__off64_t] [line 142, size 0, align 0, offset 0] [from long int] +!70 = !{!"0xd\00__pad1\00328\0064\0064\001216\000", !30, !29, !67} ; [ DW_TAG_member ] [__pad1] [line 328, size 64, align 64, offset 1216] [from ] +!71 = !{!"0xd\00__pad2\00329\0064\0064\001280\000", !30, !29, !67} ; [ DW_TAG_member ] [__pad2] [line 329, size 64, align 64, offset 1280] [from ] +!72 = !{!"0xd\00__pad3\00330\0064\0064\001344\000", !30, !29, !67} ; [ DW_TAG_member ] [__pad3] [line 330, size 64, align 64, offset 1344] [from ] +!73 = !{!"0xd\00__pad4\00331\0064\0064\001408\000", !30, !29, !67} ; [ DW_TAG_member ] [__pad4] [line 331, size 64, align 64, offset 1408] [from ] +!74 = !{!"0xd\00__pad5\00332\0064\0064\001472\000", !30, !29, !75} ; [ DW_TAG_member ] [__pad5] [line 332, size 64, align 64, offset 1472] [from size_t] +!75 = !{!"0x16\00size_t\0042\000\000\000\000", !30, null, !76} ; [ DW_TAG_typedef ] [size_t] [line 42, size 0, align 0, offset 0] [from long unsigned int] +!76 = !{!"0x24\00long unsigned int\000\0064\0064\000\000\007", null, null} ; [ DW_TAG_base_type ] [long unsigned int] [line 0, size 64, align 64, offset 0, enc DW_ATE_unsigned] +!77 = !{!"0xd\00_mode\00334\0032\0032\001536\000", !30, !29, !8} ; [ DW_TAG_member ] [_mode] [line 334, size 32, align 32, offset 1536] [from int] +!78 = !{!"0xd\00_unused2\00336\00160\008\001568\000", !30, !29, !79} ; [ DW_TAG_member ] [_unused2] [line 336, size 160, align 8, offset 1568] [from ] +!79 = !{!"0x1\00\000\00160\008\000\000", null, null, !11, !80, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 160, align 8, offset 0] [from char] +!80 = !{!81} +!81 = !{!"0x21\000\0020"} ; [ DW_TAG_subrange_type ] [0, 19] +!82 = !{!"0x2e\00verify\00verify\00\002388\001\001\000\006\00256\001\002388", !1, !5, !83, null, null, null, null, !86} ; [ DW_TAG_subprogram ] [line 2388] [local] [def] [verify] +!83 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !84, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!84 = !{null, !8, !10, !85} +!85 = !{!"0xf\00\000\0064\0064\000\000", null, null, !24} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from boolean] +!86 = !{!87, !88, !89, !90, !94, !95, !96, !97, !98, !99, !100, !101} +!87 = !{!"0x101\00no_time_steps\0016779604\000", !82, !5, !8} ; [ DW_TAG_arg_variable ] [no_time_steps] [line 2388] +!88 = !{!"0x101\00class\0033556820\000", !82, !5, !10} ; [ DW_TAG_arg_variable ] [class] [line 2388] +!89 = !{!"0x101\00verified\0050334036\000", !82, !5, !85} ; [ DW_TAG_arg_variable ] [verified] [line 2388] +!90 = !{!"0x100\00xcrref\002397\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xcrref] [line 2397] +!91 = !{!"0x1\00\000\00320\0064\000\000", null, null, !20, !92, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 320, align 64, offset 0] [from double] +!92 = !{!93} +!93 = !{!"0x21\000\005"} ; [ DW_TAG_subrange_type ] [0, 4] +!94 = !{!"0x100\00xceref\002397\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xceref] [line 2397] +!95 = !{!"0x100\00xcrdif\002397\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xcrdif] [line 2397] +!96 = !{!"0x100\00xcedif\002397\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xcedif] [line 2397] +!97 = !{!"0x100\00epsilon\002398\000", !82, !5, !20} ; [ DW_TAG_auto_variable ] [epsilon] [line 2398] +!98 = !{!"0x100\00xce\002398\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xce] [line 2398] +!99 = !{!"0x100\00xcr\002398\000", !82, !5, !91} ; [ DW_TAG_auto_variable ] [xcr] [line 2398] +!100 = !{!"0x100\00dtref\002398\000", !82, !5, !20} ; [ DW_TAG_auto_variable ] [dtref] [line 2398] +!101 = !{!"0x100\00m\002399\000", !82, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 2399] +!102 = !{!"0x2e\00rhs_norm\00rhs_norm\00\00266\001\001\000\006\00256\001\00266", !1, !5, !103, null, null, null, null, !106} ; [ DW_TAG_subprogram ] [line 266] [local] [def] [rhs_norm] +!103 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !104, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!104 = !{null, !105} +!105 = !{!"0xf\00\000\0064\0064\000\000", null, null, !20} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from double] +!106 = !{!107, !108, !109, !110, !111, !112, !113} +!107 = !{!"0x101\00rms\0016777482\000", !102, !5, !105} ; [ DW_TAG_arg_variable ] [rms] [line 266] +!108 = !{!"0x100\00i\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 271] +!109 = !{!"0x100\00j\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 271] +!110 = !{!"0x100\00k\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 271] +!111 = !{!"0x100\00d\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [d] [line 271] +!112 = !{!"0x100\00m\00271\000", !102, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 271] +!113 = !{!"0x100\00add\00272\000", !102, !5, !20} ; [ DW_TAG_auto_variable ] [add] [line 272] +!114 = !{!"0x2e\00compute_rhs\00compute_rhs\00\001767\001\001\000\006\00256\001\001767", !1, !5, !115, null, void ()* @compute_rhs, null, null, !117} ; [ DW_TAG_subprogram ] [line 1767] [local] [def] [compute_rhs] +!115 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !116, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!116 = !{null} +!117 = !{!118, !119, !120, !121, !122, !123, !124, !125, !126, !127, !128, !129, !130, !131} +!118 = !{!"0x100\00i\001769\000", !114, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 1769] +!119 = !{!"0x100\00j\001769\000", !114, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 1769] +!120 = !{!"0x100\00k\001769\000", !114, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 1769] +!121 = !{!"0x100\00m\001769\000", !114, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 1769] +!122 = !{!"0x100\00rho_inv\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [rho_inv] [line 1770] +!123 = !{!"0x100\00uijk\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [uijk] [line 1770] +!124 = !{!"0x100\00up1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [up1] [line 1770] +!125 = !{!"0x100\00um1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [um1] [line 1770] +!126 = !{!"0x100\00vijk\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [vijk] [line 1770] +!127 = !{!"0x100\00vp1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [vp1] [line 1770] +!128 = !{!"0x100\00vm1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [vm1] [line 1770] +!129 = !{!"0x100\00wijk\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [wijk] [line 1770] +!130 = !{!"0x100\00wp1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [wp1] [line 1770] +!131 = !{!"0x100\00wm1\001770\000", !114, !5, !20} ; [ DW_TAG_auto_variable ] [wm1] [line 1770] +!132 = !{!"0x2e\00error_norm\00error_norm\00\00225\001\001\000\006\00256\001\00225", !1, !5, !103, null, null, null, null, !133} ; [ DW_TAG_subprogram ] [line 225] [local] [def] [error_norm] +!133 = !{!134, !135, !136, !137, !138, !139, !140, !141, !142, !143, !144} +!134 = !{!"0x101\00rms\0016777441\000", !132, !5, !105} ; [ DW_TAG_arg_variable ] [rms] [line 225] +!135 = !{!"0x100\00i\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 232] +!136 = !{!"0x100\00j\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 232] +!137 = !{!"0x100\00k\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 232] +!138 = !{!"0x100\00m\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 232] +!139 = !{!"0x100\00d\00232\000", !132, !5, !8} ; [ DW_TAG_auto_variable ] [d] [line 232] +!140 = !{!"0x100\00xi\00233\000", !132, !5, !20} ; [ DW_TAG_auto_variable ] [xi] [line 233] +!141 = !{!"0x100\00eta\00233\000", !132, !5, !20} ; [ DW_TAG_auto_variable ] [eta] [line 233] +!142 = !{!"0x100\00zeta\00233\000", !132, !5, !20} ; [ DW_TAG_auto_variable ] [zeta] [line 233] +!143 = !{!"0x100\00u_exact\00233\000", !132, !5, !91} ; [ DW_TAG_auto_variable ] [u_exact] [line 233] +!144 = !{!"0x100\00add\00233\000", !132, !5, !20} ; [ DW_TAG_auto_variable ] [add] [line 233] +!145 = !{!"0x2e\00exact_solution\00exact_solution\00\00643\001\001\000\006\00256\001\00644", !1, !5, !146, null, null, null, null, !148} ; [ DW_TAG_subprogram ] [line 643] [local] [def] [scope 644] [exact_solution] +!146 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !147, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!147 = !{null, !20, !20, !20, !105} +!148 = !{!149, !150, !151, !152, !153} +!149 = !{!"0x101\00xi\0016777859\000", !145, !5, !20} ; [ DW_TAG_arg_variable ] [xi] [line 643] +!150 = !{!"0x101\00eta\0033555075\000", !145, !5, !20} ; [ DW_TAG_arg_variable ] [eta] [line 643] +!151 = !{!"0x101\00zeta\0050332291\000", !145, !5, !20} ; [ DW_TAG_arg_variable ] [zeta] [line 643] +!152 = !{!"0x101\00dtemp\0067109508\000", !145, !5, !105} ; [ DW_TAG_arg_variable ] [dtemp] [line 644] +!153 = !{!"0x100\00m\00653\000", !145, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 653] +!154 = !{!"0x2e\00set_constants\00set_constants\00\002191\001\001\000\006\00256\001\002191", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 2191] [local] [def] [set_constants] +!155 = !{!"0x2e\00lhsinit\00lhsinit\00\00855\001\001\000\006\00256\001\00855", !1, !5, !115, null, null, null, null, !156} ; [ DW_TAG_subprogram ] [line 855] [local] [def] [lhsinit] +!156 = !{!157, !158, !159, !160, !161} +!157 = !{!"0x100\00i\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 857] +!158 = !{!"0x100\00j\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 857] +!159 = !{!"0x100\00k\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 857] +!160 = !{!"0x100\00m\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 857] +!161 = !{!"0x100\00n\00857\000", !155, !5, !8} ; [ DW_TAG_auto_variable ] [n] [line 857] +!162 = !{!"0x2e\00initialize\00initialize\00\00669\001\001\000\006\00256\001\00669", !1, !5, !115, null, null, null, null, !163} ; [ DW_TAG_subprogram ] [line 669] [local] [def] [initialize] +!163 = !{!164, !165, !166, !167, !168, !169, !170, !171, !172, !173, !174, !179, !180, !181, !182} +!164 = !{!"0x100\00i\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 679] +!165 = !{!"0x100\00j\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 679] +!166 = !{!"0x100\00k\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 679] +!167 = !{!"0x100\00m\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 679] +!168 = !{!"0x100\00ix\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [ix] [line 679] +!169 = !{!"0x100\00iy\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [iy] [line 679] +!170 = !{!"0x100\00iz\00679\000", !162, !5, !8} ; [ DW_TAG_auto_variable ] [iz] [line 679] +!171 = !{!"0x100\00xi\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [xi] [line 680] +!172 = !{!"0x100\00eta\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [eta] [line 680] +!173 = !{!"0x100\00zeta\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [zeta] [line 680] +!174 = !{!"0x100\00Pface\00680\000", !162, !5, !175} ; [ DW_TAG_auto_variable ] [Pface] [line 680] +!175 = !{!"0x1\00\000\001920\0064\000\000", null, null, !20, !176, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1920, align 64, offset 0] [from double] +!176 = !{!177, !178, !93} +!177 = !{!"0x21\000\002"} ; [ DW_TAG_subrange_type ] [0, 1] +!178 = !{!"0x21\000\003"} ; [ DW_TAG_subrange_type ] [0, 2] +!179 = !{!"0x100\00Pxi\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [Pxi] [line 680] +!180 = !{!"0x100\00Peta\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [Peta] [line 680] +!181 = !{!"0x100\00Pzeta\00680\000", !162, !5, !20} ; [ DW_TAG_auto_variable ] [Pzeta] [line 680] +!182 = !{!"0x100\00temp\00680\000", !162, !5, !91} ; [ DW_TAG_auto_variable ] [temp] [line 680] +!183 = !{!"0x2e\00exact_rhs\00exact_rhs\00\00301\001\001\000\006\00256\001\00301", !1, !5, !115, null, null, null, null, !184} ; [ DW_TAG_subprogram ] [line 301] [local] [def] [exact_rhs] +!184 = !{!185, !186, !187, !188, !189, !190, !191, !192, !193, !194, !195, !196, !197, !198, !199} +!185 = !{!"0x100\00dtemp\00310\000", !183, !5, !91} ; [ DW_TAG_auto_variable ] [dtemp] [line 310] +!186 = !{!"0x100\00xi\00310\000", !183, !5, !20} ; [ DW_TAG_auto_variable ] [xi] [line 310] +!187 = !{!"0x100\00eta\00310\000", !183, !5, !20} ; [ DW_TAG_auto_variable ] [eta] [line 310] +!188 = !{!"0x100\00zeta\00310\000", !183, !5, !20} ; [ DW_TAG_auto_variable ] [zeta] [line 310] +!189 = !{!"0x100\00dtpp\00310\000", !183, !5, !20} ; [ DW_TAG_auto_variable ] [dtpp] [line 310] +!190 = !{!"0x100\00m\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 311] +!191 = !{!"0x100\00i\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 311] +!192 = !{!"0x100\00j\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 311] +!193 = !{!"0x100\00k\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 311] +!194 = !{!"0x100\00ip1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [ip1] [line 311] +!195 = !{!"0x100\00im1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [im1] [line 311] +!196 = !{!"0x100\00jp1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [jp1] [line 311] +!197 = !{!"0x100\00jm1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [jm1] [line 311] +!198 = !{!"0x100\00km1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [km1] [line 311] +!199 = !{!"0x100\00kp1\00311\000", !183, !5, !8} ; [ DW_TAG_auto_variable ] [kp1] [line 311] +!200 = !{!"0x2e\00adi\00adi\00\00210\001\001\000\006\00256\001\00210", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 210] [local] [def] [adi] +!201 = !{!"0x2e\00add\00add\00\00187\001\001\000\006\00256\001\00187", !1, !5, !115, null, null, null, null, !202} ; [ DW_TAG_subprogram ] [line 187] [local] [def] [add] +!202 = !{!203, !204, !205, !206} +!203 = !{!"0x100\00i\00193\000", !201, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 193] +!204 = !{!"0x100\00j\00193\000", !201, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 193] +!205 = !{!"0x100\00k\00193\000", !201, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 193] +!206 = !{!"0x100\00m\00193\000", !201, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 193] +!207 = !{!"0x2e\00z_solve\00z_solve\00\003457\001\001\000\006\00256\001\003457", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 3457] [local] [def] [z_solve] +!208 = !{!"0x2e\00z_backsubstitute\00z_backsubstitute\00\003480\001\001\000\006\00256\001\003480", !1, !5, !115, null, null, null, null, !209} ; [ DW_TAG_subprogram ] [line 3480] [local] [def] [z_backsubstitute] +!209 = !{!210, !211, !212, !213, !214} +!210 = !{!"0x100\00i\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3492] +!211 = !{!"0x100\00j\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 3492] +!212 = !{!"0x100\00k\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 3492] +!213 = !{!"0x100\00m\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 3492] +!214 = !{!"0x100\00n\003492\000", !208, !5, !8} ; [ DW_TAG_auto_variable ] [n] [line 3492] +!215 = !{!"0x2e\00z_solve_cell\00z_solve_cell\00\003512\001\001\000\006\00256\001\003512", !1, !5, !115, null, null, null, null, !216} ; [ DW_TAG_subprogram ] [line 3512] [local] [def] [z_solve_cell] +!216 = !{!217, !218, !219, !220} +!217 = !{!"0x100\00i\003527\000", !215, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3527] +!218 = !{!"0x100\00j\003527\000", !215, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 3527] +!219 = !{!"0x100\00k\003527\000", !215, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 3527] +!220 = !{!"0x100\00ksize\003527\000", !215, !5, !8} ; [ DW_TAG_auto_variable ] [ksize] [line 3527] +!221 = !{!"0x2e\00binvrhs\00binvrhs\00\003154\001\001\000\006\00256\001\003154", !1, !5, !222, null, null, null, null, !225} ; [ DW_TAG_subprogram ] [line 3154] [local] [def] [binvrhs] +!222 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !223, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!223 = !{null, !224, !105} +!224 = !{!"0xf\00\000\0064\0064\000\000", null, null, !91} ; [ DW_TAG_pointer_type ] [line 0, size 64, align 64, offset 0] [from ] +!225 = !{!226, !227, !228, !229} +!226 = !{!"0x101\00lhs\0016780370\000", !221, !5, !224} ; [ DW_TAG_arg_variable ] [lhs] [line 3154] +!227 = !{!"0x101\00r\0033557586\000", !221, !5, !105} ; [ DW_TAG_arg_variable ] [r] [line 3154] +!228 = !{!"0x100\00pivot\003159\000", !221, !5, !20} ; [ DW_TAG_auto_variable ] [pivot] [line 3159] +!229 = !{!"0x100\00coeff\003159\000", !221, !5, !20} ; [ DW_TAG_auto_variable ] [coeff] [line 3159] +!230 = !{!"0x2e\00matmul_sub\00matmul_sub\00\002841\001\001\000\006\00256\001\002842", !1, !5, !231, null, null, null, null, !233} ; [ DW_TAG_subprogram ] [line 2841] [local] [def] [scope 2842] [matmul_sub] +!231 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !232, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!232 = !{null, !224, !224, !224} +!233 = !{!234, !235, !236, !237} +!234 = !{!"0x101\00ablock\0016780057\000", !230, !5, !224} ; [ DW_TAG_arg_variable ] [ablock] [line 2841] +!235 = !{!"0x101\00bblock\0033557273\000", !230, !5, !224} ; [ DW_TAG_arg_variable ] [bblock] [line 2841] +!236 = !{!"0x101\00cblock\0050334490\000", !230, !5, !224} ; [ DW_TAG_arg_variable ] [cblock] [line 2842] +!237 = !{!"0x100\00j\002851\000", !230, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 2851] +!238 = !{!"0x2e\00matvec_sub\00matvec_sub\00\002814\001\001\000\006\00256\001\002814", !1, !5, !239, null, null, null, null, !241} ; [ DW_TAG_subprogram ] [line 2814] [local] [def] [matvec_sub] +!239 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !240, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!240 = !{null, !224, !105, !105} +!241 = !{!242, !243, !244, !245} +!242 = !{!"0x101\00ablock\0016780030\000", !238, !5, !224} ; [ DW_TAG_arg_variable ] [ablock] [line 2814] +!243 = !{!"0x101\00avec\0033557246\000", !238, !5, !105} ; [ DW_TAG_arg_variable ] [avec] [line 2814] +!244 = !{!"0x101\00bvec\0050334462\000", !238, !5, !105} ; [ DW_TAG_arg_variable ] [bvec] [line 2814] +!245 = !{!"0x100\00i\002823\000", !238, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 2823] +!246 = !{!"0x2e\00binvcrhs\00binvcrhs\00\002885\001\001\000\006\00256\001\002885", !1, !5, !247, null, null, null, null, !249} ; [ DW_TAG_subprogram ] [line 2885] [local] [def] [binvcrhs] +!247 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !248, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!248 = !{null, !224, !224, !105} +!249 = !{!250, !251, !252, !253, !254} +!250 = !{!"0x101\00lhs\0016780101\000", !246, !5, !224} ; [ DW_TAG_arg_variable ] [lhs] [line 2885] +!251 = !{!"0x101\00c\0033557317\000", !246, !5, !224} ; [ DW_TAG_arg_variable ] [c] [line 2885] +!252 = !{!"0x101\00r\0050334533\000", !246, !5, !105} ; [ DW_TAG_arg_variable ] [r] [line 2885] +!253 = !{!"0x100\00pivot\002890\000", !246, !5, !20} ; [ DW_TAG_auto_variable ] [pivot] [line 2890] +!254 = !{!"0x100\00coeff\002890\000", !246, !5, !20} ; [ DW_TAG_auto_variable ] [coeff] [line 2890] +!255 = !{!"0x2e\00lhsz\00lhsz\00\001475\001\001\000\006\00256\001\001475", !1, !5, !115, null, null, null, null, !256} ; [ DW_TAG_subprogram ] [line 1475] [local] [def] [lhsz] +!256 = !{!257, !258, !259} +!257 = !{!"0x100\00i\001484\000", !255, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 1484] +!258 = !{!"0x100\00j\001484\000", !255, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 1484] +!259 = !{!"0x100\00k\001484\000", !255, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 1484] +!260 = !{!"0x2e\00y_solve\00y_solve\00\003299\001\001\000\006\00256\001\003299", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 3299] [local] [def] [y_solve] +!261 = !{!"0x2e\00y_backsubstitute\00y_backsubstitute\00\003323\001\001\000\006\00256\001\003323", !1, !5, !115, null, null, null, null, !262} ; [ DW_TAG_subprogram ] [line 3323] [local] [def] [y_backsubstitute] +!262 = !{!263, !264, !265, !266, !267} +!263 = !{!"0x100\00i\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3335] +!264 = !{!"0x100\00j\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 3335] +!265 = !{!"0x100\00k\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 3335] +!266 = !{!"0x100\00m\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 3335] +!267 = !{!"0x100\00n\003335\000", !261, !5, !8} ; [ DW_TAG_auto_variable ] [n] [line 3335] +!268 = !{!"0x2e\00y_solve_cell\00y_solve_cell\00\003355\001\001\000\006\00256\001\003355", !1, !5, !115, null, null, null, null, !269} ; [ DW_TAG_subprogram ] [line 3355] [local] [def] [y_solve_cell] +!269 = !{!270, !271, !272, !273} +!270 = !{!"0x100\00i\003370\000", !268, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 3370] +!271 = !{!"0x100\00j\003370\000", !268, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 3370] +!272 = !{!"0x100\00k\003370\000", !268, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 3370] +!273 = !{!"0x100\00jsize\003370\000", !268, !5, !8} ; [ DW_TAG_auto_variable ] [jsize] [line 3370] +!274 = !{!"0x2e\00lhsy\00lhsy\00\001181\001\001\000\006\00256\001\001181", !1, !5, !115, null, null, null, null, !275} ; [ DW_TAG_subprogram ] [line 1181] [local] [def] [lhsy] +!275 = !{!276, !277, !278} +!276 = !{!"0x100\00i\001190\000", !274, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 1190] +!277 = !{!"0x100\00j\001190\000", !274, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 1190] +!278 = !{!"0x100\00k\001190\000", !274, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 1190] +!279 = !{!"0x2e\00x_solve\00x_solve\00\002658\001\001\000\006\00256\001\002658", !1, !5, !115, null, null, null, null, !2} ; [ DW_TAG_subprogram ] [line 2658] [local] [def] [x_solve] +!280 = !{!"0x2e\00x_backsubstitute\00x_backsubstitute\00\002684\001\001\000\006\00256\001\002684", !1, !5, !115, null, null, null, null, !281} ; [ DW_TAG_subprogram ] [line 2684] [local] [def] [x_backsubstitute] +!281 = !{!282, !283, !284, !285, !286} +!282 = !{!"0x100\00i\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 2696] +!283 = !{!"0x100\00j\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 2696] +!284 = !{!"0x100\00k\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 2696] +!285 = !{!"0x100\00m\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [m] [line 2696] +!286 = !{!"0x100\00n\002696\000", !280, !5, !8} ; [ DW_TAG_auto_variable ] [n] [line 2696] +!287 = !{!"0x2e\00x_solve_cell\00x_solve_cell\00\002716\001\001\000\006\00256\001\002716", !1, !5, !115, null, null, null, null, !288} ; [ DW_TAG_subprogram ] [line 2716] [local] [def] [x_solve_cell] +!288 = !{!289, !290, !291, !292} +!289 = !{!"0x100\00i\002728\000", !287, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 2728] +!290 = !{!"0x100\00j\002728\000", !287, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 2728] +!291 = !{!"0x100\00k\002728\000", !287, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 2728] +!292 = !{!"0x100\00isize\002728\000", !287, !5, !8} ; [ DW_TAG_auto_variable ] [isize] [line 2728] +!293 = !{!"0x2e\00lhsx\00lhsx\00\00898\001\001\000\006\00256\001\00898", !1, !5, !115, null, null, null, null, !294} ; [ DW_TAG_subprogram ] [line 898] [local] [def] [lhsx] +!294 = !{!295, !296, !297} +!295 = !{!"0x100\00i\00907\000", !293, !5, !8} ; [ DW_TAG_auto_variable ] [i] [line 907] +!296 = !{!"0x100\00j\00907\000", !293, !5, !8} ; [ DW_TAG_auto_variable ] [j] [line 907] +!297 = !{!"0x100\00k\00907\000", !293, !5, !8} ; [ DW_TAG_auto_variable ] [k] [line 907] +!298 = !{!299, !304, !305, !309, !310, !311, !312, !313, !314, !315, !316, !317, !318, !319, !320, !321, !322, !323, !324, !325, !326, !327, !328, !329, !330, !331, !332, !333, !334, !335, !336, !337, !338, !339, !340, !341, !342, !343, !347, !350, !351, !352, !353, !354, !355, !356, !360, !361, !362, !363, !364, !365, !366, !367, !368, !369, !370, !371, !372, !373, !374, !375, !376, !377, !378, !379, !380, !381, !382, !383, !384, !385, !386, !387, !388, !389, !390, !391, !392, !393, !394, !395, !396, !397, !398, !399, !400, !401, !402, !403, !404, !405, !406, !407, !408, !409, !410, !411, !412, !413, !414, !415, !416, !417, !418, !419, !422, !426, !427, !430, !431, !434, !435, !436, !437} +!299 = !{!"0x34\00grid_points\00grid_points\00\0028\001\001", null, !300, !302, [3 x i32]* @grid_points, null} ; [ DW_TAG_variable ] [grid_points] [line 28] [local] [def] +!300 = !{!"0x29", !301} ; [ DW_TAG_file_type ] [/home/hfinkel/src/NPB2.3-omp-C/BT/./header.h] +!301 = !{!"./header.h", !"/home/hfinkel/src/NPB2.3-omp-C/BT"} +!302 = !{!"0x1\00\000\0096\0032\000\000", null, null, !8, !303, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 96, align 32, offset 0] [from int] +!303 = !{!178} +!304 = !{!"0x34\00dt\00dt\00\0035\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dt] [line 35] [local] [def] +!305 = !{!"0x34\00rhs\00rhs\00\0068\001\001", null, !300, !306, null, null} ; [ DW_TAG_variable ] [rhs] [line 68] [local] [def] +!306 = !{!"0x1\00\000\001385839040\0064\000\000", null, null, !20, !307, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1385839040, align 64, offset 0] [from double] +!307 = !{!308, !308, !308, !93} +!308 = !{!"0x21\000\00163"} ; [ DW_TAG_subrange_type ] [0, 162] +!309 = !{!"0x34\00zzcon5\00zzcon5\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon5] [line 42] [local] [def] +!310 = !{!"0x34\00zzcon4\00zzcon4\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon4] [line 42] [local] [def] +!311 = !{!"0x34\00zzcon3\00zzcon3\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon3] [line 42] [local] [def] +!312 = !{!"0x34\00dz5tz1\00dz5tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz5tz1] [line 43] [local] [def] +!313 = !{!"0x34\00dz4tz1\00dz4tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz4tz1] [line 43] [local] [def] +!314 = !{!"0x34\00dz3tz1\00dz3tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz3tz1] [line 43] [local] [def] +!315 = !{!"0x34\00zzcon2\00zzcon2\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon2] [line 42] [local] [def] +!316 = !{!"0x34\00dz2tz1\00dz2tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz2tz1] [line 43] [local] [def] +!317 = !{!"0x34\00tz2\00tz2\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tz2] [line 31] [local] [def] +!318 = !{!"0x34\00dz1tz1\00dz1tz1\00\0043\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz1tz1] [line 43] [local] [def] +!319 = !{!"0x34\00yycon5\00yycon5\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon5] [line 40] [local] [def] +!320 = !{!"0x34\00yycon4\00yycon4\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon4] [line 40] [local] [def] +!321 = !{!"0x34\00yycon3\00yycon3\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon3] [line 40] [local] [def] +!322 = !{!"0x34\00dy5ty1\00dy5ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy5ty1] [line 41] [local] [def] +!323 = !{!"0x34\00dy4ty1\00dy4ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy4ty1] [line 41] [local] [def] +!324 = !{!"0x34\00dy3ty1\00dy3ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy3ty1] [line 41] [local] [def] +!325 = !{!"0x34\00yycon2\00yycon2\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon2] [line 40] [local] [def] +!326 = !{!"0x34\00dy2ty1\00dy2ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy2ty1] [line 41] [local] [def] +!327 = !{!"0x34\00ty2\00ty2\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [ty2] [line 31] [local] [def] +!328 = !{!"0x34\00dy1ty1\00dy1ty1\00\0041\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy1ty1] [line 41] [local] [def] +!329 = !{!"0x34\00dssp\00dssp\00\0035\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dssp] [line 35] [local] [def] +!330 = !{!"0x34\00c1\00c1\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c1] [line 45] [local] [def] +!331 = !{!"0x34\00xxcon5\00xxcon5\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon5] [line 38] [local] [def] +!332 = !{!"0x34\00xxcon4\00xxcon4\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon4] [line 38] [local] [def] +!333 = !{!"0x34\00xxcon3\00xxcon3\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon3] [line 38] [local] [def] +!334 = !{!"0x34\00dx5tx1\00dx5tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx5tx1] [line 39] [local] [def] +!335 = !{!"0x34\00dx4tx1\00dx4tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx4tx1] [line 39] [local] [def] +!336 = !{!"0x34\00dx3tx1\00dx3tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx3tx1] [line 39] [local] [def] +!337 = !{!"0x34\00c2\00c2\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2] [line 45] [local] [def] +!338 = !{!"0x34\00con43\00con43\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [con43] [line 48] [local] [def] +!339 = !{!"0x34\00xxcon2\00xxcon2\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon2] [line 38] [local] [def] +!340 = !{!"0x34\00dx2tx1\00dx2tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx2tx1] [line 39] [local] [def] +!341 = !{!"0x34\00tx2\00tx2\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tx2] [line 31] [local] [def] +!342 = !{!"0x34\00dx1tx1\00dx1tx1\00\0039\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx1tx1] [line 39] [local] [def] +!343 = !{!"0x34\00forcing\00forcing\00\0066\001\001", null, !300, !344, null, null} ; [ DW_TAG_variable ] [forcing] [line 66] [local] [def] +!344 = !{!"0x1\00\000\001663006848\0064\000\000", null, null, !20, !345, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 1663006848, align 64, offset 0] [from double] +!345 = !{!308, !308, !308, !346} +!346 = !{!"0x21\000\006"} ; [ DW_TAG_subrange_type ] [0, 5] +!347 = !{!"0x34\00qs\00qs\00\0063\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [qs] [line 63] [local] [def] +!348 = !{!"0x1\00\000\00277167808\0064\000\000", null, null, !20, !349, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 277167808, align 64, offset 0] [from double] +!349 = !{!308, !308, !308} +!350 = !{!"0x34\00square\00square\00\0065\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [square] [line 65] [local] [def] +!351 = !{!"0x34\00ws\00ws\00\0062\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [ws] [line 62] [local] [def] +!352 = !{!"0x34\00vs\00vs\00\0061\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [vs] [line 61] [local] [def] +!353 = !{!"0x34\00us\00us\00\0060\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [us] [line 60] [local] [def] +!354 = !{!"0x34\00rho_i\00rho_i\00\0064\001\001", null, !300, !348, null, null} ; [ DW_TAG_variable ] [rho_i] [line 64] [local] [def] +!355 = !{!"0x34\00u\00u\00\0067\001\001", null, !300, !306, null, null} ; [ DW_TAG_variable ] [u] [line 67] [local] [def] +!356 = !{!"0x34\00ce\00ce\00\0036\001\001", null, !300, !357, null, null} ; [ DW_TAG_variable ] [ce] [line 36] [local] [def] +!357 = !{!"0x1\00\000\004160\0064\000\000", null, null, !20, !358, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 4160, align 64, offset 0] [from double] +!358 = !{!93, !359} +!359 = !{!"0x21\000\0013"} ; [ DW_TAG_subrange_type ] [0, 12] +!360 = !{!"0x34\00dnzm1\00dnzm1\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dnzm1] [line 44] [local] [def] +!361 = !{!"0x34\00dnym1\00dnym1\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dnym1] [line 44] [local] [def] +!362 = !{!"0x34\00dnxm1\00dnxm1\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dnxm1] [line 44] [local] [def] +!363 = !{!"0x34\00zzcon1\00zzcon1\00\0042\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [zzcon1] [line 42] [local] [def] +!364 = !{!"0x34\00yycon1\00yycon1\00\0040\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [yycon1] [line 40] [local] [def] +!365 = !{!"0x34\00xxcon1\00xxcon1\00\0038\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [xxcon1] [line 38] [local] [def] +!366 = !{!"0x34\00con16\00con16\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [con16] [line 48] [local] [def] +!367 = !{!"0x34\00c2iv\00c2iv\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2iv] [line 48] [local] [def] +!368 = !{!"0x34\00c3c4tz3\00c3c4tz3\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3c4tz3] [line 48] [local] [def] +!369 = !{!"0x34\00c3c4ty3\00c3c4ty3\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3c4ty3] [line 48] [local] [def] +!370 = !{!"0x34\00c3c4tx3\00c3c4tx3\00\0048\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3c4tx3] [line 48] [local] [def] +!371 = !{!"0x34\00comz6\00comz6\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [comz6] [line 47] [local] [def] +!372 = !{!"0x34\00comz5\00comz5\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [comz5] [line 47] [local] [def] +!373 = !{!"0x34\00comz4\00comz4\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [comz4] [line 47] [local] [def] +!374 = !{!"0x34\00comz1\00comz1\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [comz1] [line 47] [local] [def] +!375 = !{!"0x34\00dtdssp\00dtdssp\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dtdssp] [line 45] [local] [def] +!376 = !{!"0x34\00c2dttz1\00c2dttz1\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2dttz1] [line 47] [local] [def] +!377 = !{!"0x34\00c2dtty1\00c2dtty1\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2dtty1] [line 47] [local] [def] +!378 = !{!"0x34\00c2dttx1\00c2dttx1\00\0047\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c2dttx1] [line 47] [local] [def] +!379 = !{!"0x34\00dttz2\00dttz2\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dttz2] [line 46] [local] [def] +!380 = !{!"0x34\00dttz1\00dttz1\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dttz1] [line 46] [local] [def] +!381 = !{!"0x34\00dtty2\00dtty2\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dtty2] [line 46] [local] [def] +!382 = !{!"0x34\00dtty1\00dtty1\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dtty1] [line 46] [local] [def] +!383 = !{!"0x34\00dttx2\00dttx2\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dttx2] [line 46] [local] [def] +!384 = !{!"0x34\00dttx1\00dttx1\00\0046\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dttx1] [line 46] [local] [def] +!385 = !{!"0x34\00c5dssp\00c5dssp\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c5dssp] [line 45] [local] [def] +!386 = !{!"0x34\00c4dssp\00c4dssp\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c4dssp] [line 45] [local] [def] +!387 = !{!"0x34\00dzmax\00dzmax\00\0037\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dzmax] [line 37] [local] [def] +!388 = !{!"0x34\00dymax\00dymax\00\0037\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dymax] [line 37] [local] [def] +!389 = !{!"0x34\00dxmax\00dxmax\00\0037\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dxmax] [line 37] [local] [def] +!390 = !{!"0x34\00dz5\00dz5\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz5] [line 34] [local] [def] +!391 = !{!"0x34\00dz4\00dz4\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz4] [line 34] [local] [def] +!392 = !{!"0x34\00dz3\00dz3\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz3] [line 34] [local] [def] +!393 = !{!"0x34\00dz2\00dz2\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz2] [line 34] [local] [def] +!394 = !{!"0x34\00dz1\00dz1\00\0034\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dz1] [line 34] [local] [def] +!395 = !{!"0x34\00dy5\00dy5\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy5] [line 33] [local] [def] +!396 = !{!"0x34\00dy4\00dy4\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy4] [line 33] [local] [def] +!397 = !{!"0x34\00dy3\00dy3\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy3] [line 33] [local] [def] +!398 = !{!"0x34\00dy2\00dy2\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy2] [line 33] [local] [def] +!399 = !{!"0x34\00dy1\00dy1\00\0033\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dy1] [line 33] [local] [def] +!400 = !{!"0x34\00dx5\00dx5\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx5] [line 32] [local] [def] +!401 = !{!"0x34\00dx4\00dx4\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx4] [line 32] [local] [def] +!402 = !{!"0x34\00dx3\00dx3\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx3] [line 32] [local] [def] +!403 = !{!"0x34\00dx2\00dx2\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx2] [line 32] [local] [def] +!404 = !{!"0x34\00dx1\00dx1\00\0032\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [dx1] [line 32] [local] [def] +!405 = !{!"0x34\00tz3\00tz3\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tz3] [line 31] [local] [def] +!406 = !{!"0x34\00tz1\00tz1\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tz1] [line 31] [local] [def] +!407 = !{!"0x34\00ty3\00ty3\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [ty3] [line 31] [local] [def] +!408 = !{!"0x34\00ty1\00ty1\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [ty1] [line 31] [local] [def] +!409 = !{!"0x34\00tx3\00tx3\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tx3] [line 31] [local] [def] +!410 = !{!"0x34\00tx1\00tx1\00\0031\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tx1] [line 31] [local] [def] +!411 = !{!"0x34\00conz1\00conz1\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [conz1] [line 45] [local] [def] +!412 = !{!"0x34\00c1345\00c1345\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c1345] [line 44] [local] [def] +!413 = !{!"0x34\00c3c4\00c3c4\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3c4] [line 44] [local] [def] +!414 = !{!"0x34\00c1c5\00c1c5\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c1c5] [line 44] [local] [def] +!415 = !{!"0x34\00c1c2\00c1c2\00\0044\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c1c2] [line 44] [local] [def] +!416 = !{!"0x34\00c5\00c5\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c5] [line 45] [local] [def] +!417 = !{!"0x34\00c4\00c4\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c4] [line 45] [local] [def] +!418 = !{!"0x34\00c3\00c3\00\0045\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [c3] [line 45] [local] [def] +!419 = !{!"0x34\00lhs\00lhs\00\0069\001\001", null, !300, !420, null, null} ; [ DW_TAG_variable ] [lhs] [line 69] [local] [def] +!420 = !{!"0x1\00\000\0020787585600\0064\000\000", null, null, !20, !421, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 20787585600, align 64, offset 0] [from double] +!421 = !{!308, !308, !308, !178, !93, !93} +!422 = !{!"0x34\00q\00q\00\0073\001\001", null, !300, !423, null, null} ; [ DW_TAG_variable ] [q] [line 73] [local] [def] +!423 = !{!"0x1\00\000\0010368\0064\000\000", null, null, !20, !424, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 10368, align 64, offset 0] [from double] +!424 = !{!425} +!425 = !{!"0x21\000\00162"} ; [ DW_TAG_subrange_type ] [0, 161] +!426 = !{!"0x34\00cuf\00cuf\00\0072\001\001", null, !300, !423, null, null} ; [ DW_TAG_variable ] [cuf] [line 72] [local] [def] +!427 = !{!"0x34\00buf\00buf\00\0075\001\001", null, !300, !428, null, null} ; [ DW_TAG_variable ] [buf] [line 75] [local] [def] +!428 = !{!"0x1\00\000\0051840\0064\000\000", null, null, !20, !429, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 51840, align 64, offset 0] [from double] +!429 = !{!425, !93} +!430 = !{!"0x34\00ue\00ue\00\0074\001\001", null, !300, !428, null, null} ; [ DW_TAG_variable ] [ue] [line 74] [local] [def] +!431 = !{!"0x34\00njac\00njac\00\0086\001\001", null, !300, !432, null, null} ; [ DW_TAG_variable ] [njac] [line 86] [local] [def] +!432 = !{!"0x1\00\000\006886684800\0064\000\000", null, null, !20, !433, i32 0, null, null, null} ; [ DW_TAG_array_type ] [line 0, size 6886684800, align 64, offset 0] [from double] +!433 = !{!308, !308, !425, !93, !93} +!434 = !{!"0x34\00fjac\00fjac\00\0084\001\001", null, !300, !432, null, null} ; [ DW_TAG_variable ] [fjac] [line 84] [local] [def] +!435 = !{!"0x34\00tmp3\00tmp3\00\0088\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tmp3] [line 88] [local] [def] +!436 = !{!"0x34\00tmp2\00tmp2\00\0088\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tmp2] [line 88] [local] [def] +!437 = !{!"0x34\00tmp1\00tmp1\00\0088\001\001", null, !300, !20, null, null} ; [ DW_TAG_variable ] [tmp1] [line 88] [local] [def] +!438 = !{i32 2, !"Dwarf Version", i32 4} +!439 = !MDLocation(line: 1898, scope: !440) +!440 = !{!"0xb\001898\000\00107", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!441 = !MDLocation(line: 1913, scope: !442) +!442 = !{!"0xb\001913\000\00115", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!443 = !MDLocation(line: 1923, scope: !114) +!444 = !{!"int", !445} +!445 = !{!"omnipotent char", !446} +!446 = !{!"Simple C/C++ TBAA"} +!447 = !{i32 1} +!448 = !MDLocation(line: 1925, scope: !449) +!449 = !{!"0xb\001925\000\00121", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!450 = !MDLocation(line: 1939, scope: !451) +!451 = !{!"0xb\001939\000\00127", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!452 = !MDLocation(line: 1940, scope: !453) +!453 = !{!"0xb\001940\000\00129", !1, !454} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!454 = !{!"0xb\001939\000\00128", !1, !451} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!455 = !MDLocation(line: 1941, scope: !456) +!456 = !{!"0xb\001941\000\00131", !1, !457} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!457 = !{!"0xb\001940\000\00130", !1, !453} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!458 = !MDLocation(line: 2020, scope: !459) +!459 = !{!"0xb\002020\000\00149", !1, !460} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!460 = !{!"0xb\002019\000\00148", !1, !461} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!461 = !{!"0xb\002019\000\00147", !1, !462} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!462 = !{!"0xb\002018\000\00146", !1, !463} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!463 = !{!"0xb\002018\000\00145", !1, !114} ; [ DW_TAG_lexical_block ] [/home/hfinkel/src/NPB2.3-omp-C/BT/bt.c] +!464 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/PowerPC/preincprep-invoke.ll b/test/CodeGen/PowerPC/preincprep-invoke.ll new file mode 100644 index 0000000..473b7d0 --- /dev/null +++ b/test/CodeGen/PowerPC/preincprep-invoke.ll @@ -0,0 +1,50 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@.str1 = external unnamed_addr constant [1 x i8], align 1 +@.str2 = external unnamed_addr constant [39 x i8], align 1 + +declare void @_ZN13CStdOutStreamlsEPKc() + +declare void @_ZN13CStdOutStream5FlushEv() + +declare i32 @__gxx_personality_v0(...) + +define void @_Z11GetPasswordP13CStdOutStreamb() { +entry: + br label %for.cond.i.i + +for.cond.i.i: ; preds = %for.cond.i.i, %entry + br i1 undef, label %_ZN11CStringBaseIcEC2EPKc.exit.critedge, label %for.cond.i.i + +_ZN11CStringBaseIcEC2EPKc.exit.critedge: ; preds = %for.cond.i.i + invoke void @_ZN13CStdOutStreamlsEPKc() + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %_ZN11CStringBaseIcEC2EPKc.exit.critedge + invoke void @_ZN13CStdOutStream5FlushEv() + to label %invoke.cont4 unwind label %lpad + +invoke.cont4: ; preds = %invoke.cont + %call7 = invoke i8* @getpass() + to label %for.cond.i.i30 unwind label %lpad + +; CHECK-LABEL: @_Z11GetPasswordP13CStdOutStreamb +; CHECK: addi {{[0-9]+}}, 3, -1 + +for.cond.i.i30: ; preds = %for.cond.i.i30, %invoke.cont4 + %indvars.iv.i.i26 = phi i64 [ %indvars.iv.next.i.i29, %for.cond.i.i30 ], [ 0, %invoke.cont4 ] + %arrayidx.i.i27 = getelementptr inbounds i8* %call7, i64 %indvars.iv.i.i26 + %0 = load i8* %arrayidx.i.i27, align 1 + %indvars.iv.next.i.i29 = add nuw nsw i64 %indvars.iv.i.i26, 1 + br label %for.cond.i.i30 + +lpad: ; preds = %invoke.cont4, %invoke.cont, %_ZN11CStringBaseIcEC2EPKc.exit.critedge + %1 = landingpad { i8*, i32 } personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) + cleanup + resume { i8*, i32 } undef +} + +declare i8* @getpass() + diff --git a/test/CodeGen/PowerPC/qpx-bv-sint.ll b/test/CodeGen/PowerPC/qpx-bv-sint.ll new file mode 100644 index 0000000..0bc14ed --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-bv-sint.ll @@ -0,0 +1,33 @@ +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" +; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s + +define void @s452() nounwind { +entry: + br label %for.body4 + +for.body4: ; preds = %for.body4, %entry + %conv.4 = sitofp i32 undef to double + %conv.5 = sitofp i32 undef to double + %mul.4.v.i0.1 = insertelement <2 x double> undef, double %conv.4, i32 0 + %mul.4.v.i0.2 = insertelement <2 x double> %mul.4.v.i0.1, double %conv.5, i32 1 + %mul.4 = fmul <2 x double> %mul.4.v.i0.2, undef + %add7.4 = fadd <2 x double> undef, %mul.4 + store <2 x double> %add7.4, <2 x double>* undef, align 16 + br i1 undef, label %for.end, label %for.body4 + +for.end: ; preds = %for.body4 + unreachable +; CHECK-LABEL: @s452 +; CHECK: lfiwax [[REG1:[0-9]+]], +; CHECK: fcfid [[REG2:[0-9]+]], [[REG1]] +; FIXME: We could 'promote' this to a vector earlier and remove this splat. +; CHECK: qvesplati {{[0-9]+}}, [[REG2]], 0 +; CHECK: qvfmul +; CHECK: qvfadd +; CHECK: qvesplati {{[0-9]+}}, +; FIXME: We can use qvstfcdx here instead of two stores. +; CHECK: stfd +; CHECK: stfd +} + diff --git a/test/CodeGen/PowerPC/qpx-bv.ll b/test/CodeGen/PowerPC/qpx-bv.ll new file mode 100644 index 0000000..ae181de --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-bv.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -mcpu=a2q | FileCheck %s + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +define <4 x double> @foo(double %f1, double %f2, double %f3, double %f4) { + %v1 = insertelement <4 x double> undef, double %f1, i32 0 + %v2 = insertelement <4 x double> %v1, double %f2, i32 1 + %v3 = insertelement <4 x double> %v2, double %f3, i32 2 + %v4 = insertelement <4 x double> %v3, double %f4, i32 3 + ret <4 x double> %v4 + +; CHECK-LABEL: @foo +; CHECK: qvgpci [[REG1:[0-9]+]], 275 +; CHECK-DAG: qvgpci [[REG2:[0-9]+]], 101 +; CHECK-DAG: qvfperm [[REG3:[0-9]+]], 3, 4, [[REG1]] +; CHECK-DAG: qvfperm [[REG4:[0-9]+]], 1, 2, [[REG1]] +; CHECK-DAG: qvfperm 1, [[REG4]], [[REG3]], [[REG2]] +; CHECK: blr +} + +define <4 x float> @goo(float %f1, float %f2, float %f3, float %f4) { + %v1 = insertelement <4 x float> undef, float %f1, i32 0 + %v2 = insertelement <4 x float> %v1, float %f2, i32 1 + %v3 = insertelement <4 x float> %v2, float %f3, i32 2 + %v4 = insertelement <4 x float> %v3, float %f4, i32 3 + ret <4 x float> %v4 + +; CHECK-LABEL: @goo +; CHECK: qvgpci [[REG1:[0-9]+]], 275 +; CHECK-DAG: qvgpci [[REG2:[0-9]+]], 101 +; CHECK-DAG: qvfperm [[REG3:[0-9]+]], 3, 4, [[REG1]] +; CHECK-DAG: qvfperm [[REG4:[0-9]+]], 1, 2, [[REG1]] +; CHECK-DAG: qvfperm 1, [[REG4]], [[REG3]], [[REG2]] +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/qpx-func-clobber.ll b/test/CodeGen/PowerPC/qpx-func-clobber.ll new file mode 100644 index 0000000..511fa38 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-func-clobber.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s +target triple = "powerpc64-bgq-linux" + +declare <4 x double> @foo(<4 x double> %p) + +define <4 x double> @bar(<4 x double> %p, <4 x double> %q) { +entry: + %v = call <4 x double> @foo(<4 x double> %p) + %w = call <4 x double> @foo(<4 x double> %q) + %x = fadd <4 x double> %v, %w + ret <4 x double> %x + +; CHECK-LABEL: @bar +; CHECK: qvstfdx 2, +; CHECK: bl foo +; CHECK: qvstfdx 1, +; CHECK: qvlfdx 1, +; CHECK: bl foo +; CHECK: qvlfdx [[REG:[0-9]+]], +; CHECK: qvfadd 1, [[REG]], 1 +} + diff --git a/test/CodeGen/PowerPC/qpx-load.ll b/test/CodeGen/PowerPC/qpx-load.ll new file mode 100644 index 0000000..bea3477 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-load.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s +target triple = "powerpc64-bgq-linux" + +define <4 x double> @foo(<4 x double>* %p) { +entry: + %v = load <4 x double>* %p, align 8 + ret <4 x double> %v +} + +; CHECK: @foo +; CHECK-DAG: li [[REG1:[0-9]+]], 31 +; CHECK-DAG: qvlfdx [[REG4:[0-9]+]], 0, 3 +; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: qvlpcldx [[REG3:[0-9]+]], 0, 3 +; CHECK-DAG: qvfperm 1, [[REG4]], [[REG2]], [[REG3]] +; CHECK: blr + +define <4 x double> @bar(<4 x double>* %p) { +entry: + %v = load <4 x double>* %p, align 32 + ret <4 x double> %v +} + +; CHECK: @bar +; CHECK: qvlfdx + diff --git a/test/CodeGen/PowerPC/qpx-recipest.ll b/test/CodeGen/PowerPC/qpx-recipest.ll new file mode 100644 index 0000000..0e01358 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-recipest.ll @@ -0,0 +1,194 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q -enable-unsafe-fp-math | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q | FileCheck -check-prefix=CHECK-SAFE %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +declare <4 x double> @llvm.sqrt.v4f64(<4 x double>) +declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) + +define <4 x double> @foo(<4 x double> %a, <4 x double> %b) nounwind { +entry: + %x = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %b) + %r = fdiv <4 x double> %a, %x + ret <4 x double> %r + +; CHECK-LABEL: @foo +; CHECK: qvfrsqrte +; CHECK: qvfmul +; FIXME: We're currently loading two constants here (1.5 and -1.5), and using +; an qvfmadd instead of a qvfnmsub +; CHECK: qvfmadd +; CHECK: qvfmadd +; CHECK: qvfmul +; CHECK: qvfmul +; CHECK: qvfmadd +; CHECK: qvfmul +; CHECK: qvfmul +; CHECK: blr + +; CHECK-SAFE-LABEL: @foo +; CHECK-SAFE: fsqrt +; CHECK-SAFE: fdiv +; CHECK-SAFE: blr +} + +define <4 x double> @foof(<4 x double> %a, <4 x float> %b) nounwind { +entry: + %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b) + %y = fpext <4 x float> %x to <4 x double> + %r = fdiv <4 x double> %a, %y + ret <4 x double> %r + +; CHECK-LABEL: @foof +; CHECK: qvfrsqrtes +; CHECK: qvfmuls +; FIXME: We're currently loading two constants here (1.5 and -1.5), and using +; an qvfmadd instead of a qvfnmsubs +; CHECK: qvfmadds +; CHECK: qvfmadds +; CHECK: qvfmuls +; CHECK: qvfmul +; CHECK: blr + +; CHECK-SAFE-LABEL: @foof +; CHECK-SAFE: fsqrts +; CHECK-SAFE: fdiv +; CHECK-SAFE: blr +} + +define <4 x float> @food(<4 x float> %a, <4 x double> %b) nounwind { +entry: + %x = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %b) + %y = fptrunc <4 x double> %x to <4 x float> + %r = fdiv <4 x float> %a, %y + ret <4 x float> %r + +; CHECK-LABEL: @food +; CHECK: qvfrsqrte +; CHECK: qvfmul +; FIXME: We're currently loading two constants here (1.5 and -1.5), and using +; an qvfmadd instead of a qvfnmsub +; CHECK: qvfmadd +; CHECK: qvfmadd +; CHECK: qvfmul +; CHECK: qvfmul +; CHECK: qvfmadd +; CHECK: qvfmul +; CHECK: qvfrsp +; CHECK: qvfmuls +; CHECK: blr + +; CHECK-SAFE-LABEL: @food +; CHECK-SAFE: fsqrt +; CHECK-SAFE: fdivs +; CHECK-SAFE: blr +} + +define <4 x float> @goo(<4 x float> %a, <4 x float> %b) nounwind { +entry: + %x = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %b) + %r = fdiv <4 x float> %a, %x + ret <4 x float> %r + +; CHECK-LABEL: @goo +; CHECK: qvfrsqrtes +; CHECK: qvfmuls +; FIXME: We're currently loading two constants here (1.5 and -1.5), and using +; an qvfmadd instead of a qvfnmsubs +; CHECK: qvfmadds +; CHECK: qvfmadds +; CHECK: qvfmuls +; CHECK: qvfmuls +; CHECK: blr + +; CHECK-SAFE-LABEL: @goo +; CHECK-SAFE: fsqrts +; CHECK-SAFE: fdivs +; CHECK-SAFE: blr +} + +define <4 x double> @foo2(<4 x double> %a, <4 x double> %b) nounwind { +entry: + %r = fdiv <4 x double> %a, %b + ret <4 x double> %r + +; CHECK-LABEL: @foo2 +; CHECK: qvfre +; CHECK: qvfnmsub +; CHECK: qvfmadd +; CHECK: qvfnmsub +; CHECK: qvfmadd +; CHECK: qvfmul +; CHECK: blr + +; CHECK-SAFE-LABEL: @foo2 +; CHECK-SAFE: fdiv +; CHECK-SAFE: blr +} + +define <4 x float> @goo2(<4 x float> %a, <4 x float> %b) nounwind { +entry: + %r = fdiv <4 x float> %a, %b + ret <4 x float> %r + +; CHECK-LABEL: @goo2 +; CHECK: qvfres +; CHECK: qvfnmsubs +; CHECK: qvfmadds +; CHECK: qvfmuls +; CHECK: blr + +; CHECK-SAFE-LABEL: @goo2 +; CHECK-SAFE: fdivs +; CHECK-SAFE: blr +} + +define <4 x double> @foo3(<4 x double> %a) nounwind { +entry: + %r = call <4 x double> @llvm.sqrt.v4f64(<4 x double> %a) + ret <4 x double> %r + +; CHECK-LABEL: @foo3 +; CHECK: qvfrsqrte +; CHECK: qvfmul +; FIXME: We're currently loading two constants here (1.5 and -1.5), and using +; an qvfmadd instead of a qvfnmsub +; CHECK-DAG: qvfmadd +; CHECK-DAG: qvfcmpeq +; CHECK-DAG: qvfmadd +; CHECK-DAG: qvfmul +; CHECK-DAG: qvfmul +; CHECK-DAG: qvfmadd +; CHECK-DAG: qvfmul +; CHECK-DAG: qvfmul +; CHECK: qvfsel +; CHECK: blr + +; CHECK-SAFE-LABEL: @foo3 +; CHECK-SAFE: fsqrt +; CHECK-SAFE: blr +} + +define <4 x float> @goo3(<4 x float> %a) nounwind { +entry: + %r = call <4 x float> @llvm.sqrt.v4f32(<4 x float> %a) + ret <4 x float> %r + +; CHECK-LABEL: @goo3 +; CHECK: qvfrsqrtes +; CHECK: qvfmuls +; FIXME: We're currently loading two constants here (1.5 and -1.5), and using +; an qvfmadds instead of a qvfnmsubs +; CHECK-DAG: qvfmadds +; CHECK-DAG: qvfcmpeq +; CHECK-DAG: qvfmadds +; CHECK-DAG: qvfmuls +; CHECK-DAG: qvfmuls +; CHECK: qvfsel +; CHECK: blr + +; CHECK-SAFE-LABEL: @goo3 +; CHECK-SAFE: fsqrts +; CHECK-SAFE: blr +} + diff --git a/test/CodeGen/PowerPC/qpx-rounding-ops.ll b/test/CodeGen/PowerPC/qpx-rounding-ops.ll new file mode 100644 index 0000000..6fdd8e6 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-rounding-ops.ll @@ -0,0 +1,109 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2q -enable-unsafe-fp-math | FileCheck -check-prefix=CHECK-FM %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define <4 x float> @test1(<4 x float> %x) nounwind { + %call = tail call <4 x float> @llvm.floor.v4f32(<4 x float> %x) nounwind readnone + ret <4 x float> %call + +; CHECK: test1: +; CHECK: qvfrim 1, 1 + +; CHECK-FM: test1: +; CHECK-FM: qvfrim 1, 1 +} + +declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readnone + +define <4 x double> @test2(<4 x double> %x) nounwind { + %call = tail call <4 x double> @llvm.floor.v4f64(<4 x double> %x) nounwind readnone + ret <4 x double> %call + +; CHECK: test2: +; CHECK: qvfrim 1, 1 + +; CHECK-FM: test2: +; CHECK-FM: qvfrim 1, 1 +} + +declare <4 x double> @llvm.floor.v4f64(<4 x double>) nounwind readnone + +define <4 x float> @test3(<4 x float> %x) nounwind { + %call = tail call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %x) nounwind readnone + ret <4 x float> %call + +; CHECK: test3: +; CHECK-NOT: qvfrin + +; CHECK-FM: test3: +; CHECK-FM-NOT: qvfrin +} + +declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone + +define <4 x double> @test4(<4 x double> %x) nounwind { + %call = tail call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %x) nounwind readnone + ret <4 x double> %call + +; CHECK: test4: +; CHECK-NOT: qvfrin + +; CHECK-FM: test4: +; CHECK-FM-NOT: qvfrin +} + +declare <4 x double> @llvm.nearbyint.v4f64(<4 x double>) nounwind readnone + +define <4 x float> @test5(<4 x float> %x) nounwind { + %call = tail call <4 x float> @llvm.ceil.v4f32(<4 x float> %x) nounwind readnone + ret <4 x float> %call + +; CHECK: test5: +; CHECK: qvfrip 1, 1 + +; CHECK-FM: test5: +; CHECK-FM: qvfrip 1, 1 +} + +declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone + +define <4 x double> @test6(<4 x double> %x) nounwind { + %call = tail call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone + ret <4 x double> %call + +; CHECK: test6: +; CHECK: qvfrip 1, 1 + +; CHECK-FM: test6: +; CHECK-FM: qvfrip 1, 1 +} + +declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone + +define <4 x float> @test9(<4 x float> %x) nounwind { + %call = tail call <4 x float> @llvm.trunc.v4f32(<4 x float> %x) nounwind readnone + ret <4 x float> %call + +; CHECK: test9: +; CHECK: qvfriz 1, 1 + +; CHECK-FM: test9: +; CHECK-FM: qvfriz 1, 1 +} + +declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone + +define <4 x double> @test10(<4 x double> %x) nounwind { + %call = tail call <4 x double> @llvm.trunc.v4f64(<4 x double> %x) nounwind readnone + ret <4 x double> %call + +; CHECK: test10: +; CHECK: qvfriz 1, 1 + +; CHECK-FM: test10: +; CHECK-FM: qvfriz 1, 1 +} + +declare <4 x double> @llvm.trunc.v4f64(<4 x double>) nounwind readnone + diff --git a/test/CodeGen/PowerPC/qpx-s-load.ll b/test/CodeGen/PowerPC/qpx-s-load.ll new file mode 100644 index 0000000..1ca0ae6 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-s-load.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s +target triple = "powerpc64-bgq-linux" + +define <4 x float> @foo(<4 x float>* %p) { +entry: + %v = load <4 x float>* %p, align 4 + ret <4 x float> %v +} + +; CHECK: @foo +; CHECK-DAG: li [[REG1:[0-9]+]], 15 +; CHECK-DAG: qvlfsx [[REG4:[0-9]+]], 0, 3 +; CHECK-DAG: qvlfsx [[REG2:[0-9]+]], 3, [[REG1]] +; CHECK-DAG: qvlpclsx [[REG3:[0-9]+]], 0, 3 +; CHECK-DAG: qvfperm 1, [[REG4]], [[REG2]], [[REG3]] +; CHECK: blr + +define <4 x float> @bar(<4 x float>* %p) { +entry: + %v = load <4 x float>* %p, align 16 + ret <4 x float> %v +} + +; CHECK: @bar +; CHECK: qvlfsx + diff --git a/test/CodeGen/PowerPC/qpx-s-sel.ll b/test/CodeGen/PowerPC/qpx-s-sel.ll new file mode 100644 index 0000000..e3a2dd9 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-s-sel.ll @@ -0,0 +1,144 @@ +; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s +target triple = "powerpc64-bgq-linux" + +@Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16 +@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 + +define <4 x float> @test1(<4 x float> %a, <4 x float> %b, <4 x i1> %c) nounwind readnone { +entry: + %r = select <4 x i1> %c, <4 x float> %a, <4 x float> %b + ret <4 x float> %r + +; CHECK-LABEL: @test1 +; CHECK: qvfsel 1, 3, 1, 2 +; CHECK: blr +} + +define <4 x float> @test2(<4 x float> %a, <4 x float> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone { +entry: + %v = insertelement <4 x i1> undef, i1 %c1, i32 0 + %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1 + %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2 + %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3 + %r = select <4 x i1> %v4, <4 x float> %a, <4 x float> %b + ret <4 x float> %r + +; CHECK-LABEL: @test2 +; CHECK: stw +; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], +; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], +; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] +; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] +; CHECK: qvfsel 1, [[REG4]], 1, 2 +; CHECK: blr +} + +define <4 x i1> @test3(<4 x i1> %a) nounwind readnone { +entry: + %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1> + ret <4 x i1> %v + +; CHECK-LABEL: @test3 +; CHECK: qvlfsx [[REG:[0-9]+]], +; qvflogical 1, 1, [[REG]], 1 +; blr +} + +define <4 x i1> @test4(<4 x i1> %a) nounwind { +entry: + %q = load <4 x i1>* @Q, align 16 + %v = and <4 x i1> %a, %q + ret <4 x i1> %v + +; CHECK-LABEL: @test4 +; CHECK-DAG: lbz +; CHECK-DAG: qvlfdx [[REG1:[0-9]+]], +; CHECK-DAG: stw +; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]], +; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]] +; CHECK: qvflogical 1, 1, [[REG4]], 1 +; CHECK: blr +} + +define void @test5(<4 x i1> %a) nounwind { +entry: + store <4 x i1> %a, <4 x i1>* @R + ret void + +; CHECK-LABEL: @test5 +; CHECK: qvlfdx [[REG1:[0-9]+]], +; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] +; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvstfiwx [[REG3]], +; CHECK: lwz +; CHECK: stb +; CHECK: blr +} + +define i1 @test6(<4 x i1> %a) nounwind { +entry: + %r = extractelement <4 x i1> %a, i32 2 + ret i1 %r + +; CHECK-LABEL: @test6 +; CHECK: qvlfdx [[REG1:[0-9]+]], +; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] +; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvstfiwx [[REG3]], +; CHECK: lwz +; CHECK: blr +} + +define i1 @test7(<4 x i1> %a) nounwind { +entry: + %r = extractelement <4 x i1> %a, i32 2 + %s = extractelement <4 x i1> %a, i32 3 + %q = and i1 %r, %s + ret i1 %q + +; CHECK-LABEL: @test7 +; CHECK: qvlfdx [[REG1:[0-9]+]], +; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] +; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvstfiwx [[REG3]], +; CHECK-DAG: lwz [[REG4:[0-9]+]], +; FIXME: We're storing the vector twice, and that's silly. +; CHECK-DAG: qvstfiwx [[REG3]], +; CHECK: lwz [[REG5:[0-9]+]], +; CHECK: and 3, +; CHECK: blr +} + +define i1 @test8(<3 x i1> %a) nounwind { +entry: + %r = extractelement <3 x i1> %a, i32 2 + ret i1 %r + +; CHECK-LABEL: @test8 +; CHECK: qvlfdx [[REG1:[0-9]+]], +; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] +; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvstfiwx [[REG3]], +; CHECK: lwz +; CHECK: blr +} + +define <3 x float> @test9(<3 x float> %a, <3 x float> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone { +entry: + %v = insertelement <3 x i1> undef, i1 %c1, i32 0 + %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1 + %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2 + %r = select <3 x i1> %v3, <3 x float> %a, <3 x float> %b + ret <3 x float> %r + +; CHECK-LABEL: @test9 +; CHECK: stw +; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], +; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], +; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] +; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] +; CHECK: qvfsel 1, [[REG4]], 1, 2 +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/qpx-s-store.ll b/test/CodeGen/PowerPC/qpx-s-store.ll new file mode 100644 index 0000000..0bd6201 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-s-store.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s +target triple = "powerpc64-bgq-linux" + +define void @foo(<4 x float> %v, <4 x float>* %p) { +entry: + store <4 x float> %v, <4 x float>* %p, align 4 + ret void +} + +; CHECK: @foo +; CHECK: stfs +; CHECK: stfs +; CHECK: stfs +; CHECK: stfs +; CHECK: blr + +define void @bar(<4 x float> %v, <4 x float>* %p) { +entry: + store <4 x float> %v, <4 x float>* %p, align 16 + ret void +} + +; CHECK: @bar +; CHECK: qvstfsx + diff --git a/test/CodeGen/PowerPC/qpx-sel.ll b/test/CodeGen/PowerPC/qpx-sel.ll new file mode 100644 index 0000000..6822735 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-sel.ll @@ -0,0 +1,152 @@ +; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s +target triple = "powerpc64-bgq-linux" + +@Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16 +@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 + +define <4 x double> @test1(<4 x double> %a, <4 x double> %b, <4 x i1> %c) nounwind readnone { +entry: + %r = select <4 x i1> %c, <4 x double> %a, <4 x double> %b + ret <4 x double> %r + +; CHECK-LABEL: @test1 +; CHECK: qvfsel 1, 3, 1, 2 +; CHECK: blr +} + +define <4 x double> @test2(<4 x double> %a, <4 x double> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone { +entry: + %v = insertelement <4 x i1> undef, i1 %c1, i32 0 + %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1 + %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2 + %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3 + %r = select <4 x i1> %v4, <4 x double> %a, <4 x double> %b + ret <4 x double> %r + +; CHECK-LABEL: @test2 + +; FIXME: This load/store sequence is unnecessary. +; CHECK-DAG: lbz +; CHECK-DAG: stw + +; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], +; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], +; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] +; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] +; CHECK: qvfsel 1, [[REG4]], 1, 2 +; CHECK: blr +} + +define <4 x i1> @test3(<4 x i1> %a) nounwind readnone { +entry: + %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1> + ret <4 x i1> %v + +; CHECK-LABEL: @test3 +; CHECK: qvlfsx [[REG:[0-9]+]], +; qvflogical 1, 1, [[REG]], 1 +; blr +} + +define <4 x i1> @test4(<4 x i1> %a) nounwind { +entry: + %q = load <4 x i1>* @Q, align 16 + %v = and <4 x i1> %a, %q + ret <4 x i1> %v + +; CHECK-LABEL: @test4 +; CHECK-DAG: lbz +; CHECK-DAG: qvlfdx [[REG1:[0-9]+]], +; CHECK-DAG: stw +; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]], +; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]] +; CHECK: qvflogical 1, 1, [[REG4]], 1 +; CHECK: blr +} + +define void @test5(<4 x i1> %a) nounwind { +entry: + store <4 x i1> %a, <4 x i1>* @R + ret void + +; CHECK-LABEL: @test5 +; CHECK: qvlfdx [[REG1:[0-9]+]], +; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] +; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvstfiwx [[REG3]], +; CHECK: lwz +; CHECK: stb +; CHECK: blr +} + +define i1 @test6(<4 x i1> %a) nounwind { +entry: + %r = extractelement <4 x i1> %a, i32 2 + ret i1 %r + +; CHECK-LABEL: @test6 +; CHECK: qvlfdx [[REG1:[0-9]+]], +; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] +; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvstfiwx [[REG3]], +; CHECK: lwz +; CHECK: blr +} + +define i1 @test7(<4 x i1> %a) nounwind { +entry: + %r = extractelement <4 x i1> %a, i32 2 + %s = extractelement <4 x i1> %a, i32 3 + %q = and i1 %r, %s + ret i1 %q + +; CHECK-LABEL: @test7 +; CHECK: qvlfdx [[REG1:[0-9]+]], +; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] +; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvstfiwx [[REG3]], +; CHECK-DAG: lwz [[REG4:[0-9]+]], +; FIXME: We're storing the vector twice, and that's silly. +; CHECK-DAG: qvstfiwx [[REG3]], +; CHECK-DAG: lwz [[REG5:[0-9]+]], +; CHECK: and 3, +; CHECK: blr +} + +define i1 @test8(<3 x i1> %a) nounwind { +entry: + %r = extractelement <3 x i1> %a, i32 2 + ret i1 %r + +; CHECK-LABEL: @test8 +; CHECK: qvlfdx [[REG1:[0-9]+]], +; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] +; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] +; CHECK: qvstfiwx [[REG3]], +; CHECK: lwz +; CHECK: blr +} + +define <3 x double> @test9(<3 x double> %a, <3 x double> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone { +entry: + %v = insertelement <3 x i1> undef, i1 %c1, i32 0 + %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1 + %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2 + %r = select <3 x i1> %v3, <3 x double> %a, <3 x double> %b + ret <3 x double> %r + +; CHECK-LABEL: @test9 + +; FIXME: This load/store sequence is unnecessary. +; CHECK-DAG: lbz +; CHECK-DAG: stw + +; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], +; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], +; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] +; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] +; CHECK: qvfsel 1, [[REG4]], 1, 2 +; CHECK: blr +} + diff --git a/test/CodeGen/PowerPC/qpx-store.ll b/test/CodeGen/PowerPC/qpx-store.ll new file mode 100644 index 0000000..2579d2c --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-store.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s +target triple = "powerpc64-bgq-linux" + +define void @foo(<4 x double> %v, <4 x double>* %p) { +entry: + store <4 x double> %v, <4 x double>* %p, align 8 + ret void +} + +; CHECK: @foo +; CHECK: stfd +; CHECK: stfd +; CHECK: stfd +; CHECK: stfd +; CHECK: blr + +define void @bar(<4 x double> %v, <4 x double>* %p) { +entry: + store <4 x double> %v, <4 x double>* %p, align 32 + ret void +} + +; CHECK: @bar +; CHECK: qvstfdx + diff --git a/test/CodeGen/PowerPC/qpx-unalperm.ll b/test/CodeGen/PowerPC/qpx-unalperm.ll new file mode 100644 index 0000000..e765b46 --- /dev/null +++ b/test/CodeGen/PowerPC/qpx-unalperm.ll @@ -0,0 +1,64 @@ +; RUN: llc < %s -mcpu=a2q | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-bgq-linux" + +define <4 x double> @foo(<4 x double>* %a) { +entry: + %r = load <4 x double>* %a, align 32 + ret <4 x double> %r +; CHECK: qvlfdx +; CHECK: blr +} + +define <4 x double> @bar(<4 x double>* %a) { +entry: + %r = load <4 x double>* %a, align 8 + %b = getelementptr <4 x double>* %a, i32 16 + %s = load <4 x double>* %b, align 32 + %t = fadd <4 x double> %r, %s + ret <4 x double> %t +; CHECK: qvlpcldx +; CHECK: qvlfdx +; CHECK: qvfperm +; CHECK: blr +} + +define <4 x double> @bar1(<4 x double>* %a) { +entry: + %r = load <4 x double>* %a, align 8 + %b = getelementptr <4 x double>* %a, i32 16 + %s = load <4 x double>* %b, align 8 + %t = fadd <4 x double> %r, %s + ret <4 x double> %t +} + +define <4 x double> @bar2(<4 x double>* %a) { +entry: + %r = load <4 x double>* %a, align 8 + %b = getelementptr <4 x double>* %a, i32 1 + %s = load <4 x double>* %b, align 32 + %t = fadd <4 x double> %r, %s + ret <4 x double> %t +} + +define <4 x double> @bar3(<4 x double>* %a) { +entry: + %r = load <4 x double>* %a, align 8 + %b = getelementptr <4 x double>* %a, i32 1 + %s = load <4 x double>* %b, align 8 + %t = fadd <4 x double> %r, %s + ret <4 x double> %t +} + +define <4 x double> @bar4(<4 x double>* %a) { +entry: + %r = load <4 x double>* %a, align 8 + %b = getelementptr <4 x double>* %a, i32 1 + %s = load <4 x double>* %b, align 8 + %c = getelementptr <4 x double>* %b, i32 1 + %t = load <4 x double>* %c, align 8 + %u = fadd <4 x double> %r, %s + %v = fadd <4 x double> %u, %t + ret <4 x double> %v +} + diff --git a/test/CodeGen/PowerPC/retaddr2.ll b/test/CodeGen/PowerPC/retaddr2.ll new file mode 100644 index 0000000..8581f6c --- /dev/null +++ b/test/CodeGen/PowerPC/retaddr2.ll @@ -0,0 +1,24 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define i8* @test1() #0 { +entry: + %0 = tail call i8* @llvm.returnaddress(i32 0) + ret i8* %0 +} + +; CHECK-LABEL: @test1 +; CHECK: mflr 0 +; CHECK: std 0, 16(1) +; CHECK-DAG: ld 3, 64(1) +; CHECK-DAG: ld 0, 16(1) +; CHECK: mtlr 0 +; CHECK: blr + +; Function Attrs: nounwind readnone +declare i8* @llvm.returnaddress(i32) #0 + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/rlwimi-and.ll b/test/CodeGen/PowerPC/rlwimi-and.ll index 213363e..9433f8e 100644 --- a/test/CodeGen/PowerPC/rlwimi-and.ll +++ b/test/CodeGen/PowerPC/rlwimi-and.ll @@ -28,11 +28,9 @@ codeRepl17: ; preds = %codeRepl4 store i16 %rvml38.sroa.0.0.insert.insert, i16* undef, align 2 unreachable -; FIXME: the SLWI could be folded into the RLWIMI to give a rotate of 8. ; CHECK: @test -; CHECK-DAG: slwi [[R1:[0-9]+]], {{[0-9]+}}, 31 -; CHECK-DAG: rlwinm [[R2:[0-9]+]], {{[0-9]+}}, 0, 31, 31 -; CHECK: rlwimi [[R2]], [[R1]], 9, 23, 23 +; CHECK: rlwinm [[R1:[0-9]+]], {{[0-9]+}}, 0, 31, 31 +; CHECK: rlwimi [[R1]], {{[0-9]+}}, 8, 23, 23 codeRepl29: ; preds = %codeRepl1 unreachable diff --git a/test/CodeGen/PowerPC/rlwimi2.ll b/test/CodeGen/PowerPC/rlwimi2.ll index 1bee4e0..7978718 100644 --- a/test/CodeGen/PowerPC/rlwimi2.ll +++ b/test/CodeGen/PowerPC/rlwimi2.ll @@ -1,7 +1,7 @@ ; All of these ands and shifts should be folded into rlwimi's ; RUN: llc < %s -march=ppc32 -o %t -; RUN: grep rlwimi %t | count 3 -; RUN: grep srwi %t | count 1 +; RUN: grep rlwimi %t | count 4 +; RUN: not grep srwi %t ; RUN: not grep slwi %t define i16 @test1(i32 %srcA, i32 %srcB, i32 %alpha) nounwind { diff --git a/test/CodeGen/PowerPC/rm-zext.ll b/test/CodeGen/PowerPC/rm-zext.ll new file mode 100644 index 0000000..33995e1 --- /dev/null +++ b/test/CodeGen/PowerPC/rm-zext.ll @@ -0,0 +1,89 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define signext i32 @foo(i32 signext %a) #0 { +entry: + %mul = mul nsw i32 %a, %a + %shr2 = lshr i32 %mul, 5 + ret i32 %shr2 + +; CHECK-LABEL @foo +; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 +; CHECK: blr +} + +define zeroext i32 @test6(i32 zeroext %x) #0 { +entry: + %and = lshr i32 %x, 16 + %shr = and i32 %and, 255 + %and1 = shl i32 %x, 16 + %shl = and i32 %and1, 16711680 + %or = or i32 %shr, %shl + ret i32 %or + +; CHECK-LABEL @test6 +; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 +; CHECK: blr +} + +define zeroext i32 @min(i32 zeroext %a, i32 zeroext %b) #0 { +entry: + %cmp = icmp ule i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond + +; CHECK-LABEL @min +; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.bswap.i32(i32) #0 + +; Function Attrs: nounwind readonly +define zeroext i32 @bs32(i32* nocapture readonly %x) #1 { +entry: + %0 = load i32* %x, align 4 + %1 = tail call i32 @llvm.bswap.i32(i32 %0) + ret i32 %1 + +; CHECK-LABEL: @bs32 +; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 +; CHECK: blr +} + +; Function Attrs: nounwind readonly +define zeroext i16 @bs16(i16* nocapture readonly %x) #1 { +entry: + %0 = load i16* %x, align 2 + %1 = tail call i16 @llvm.bswap.i16(i16 %0) + ret i16 %1 + +; CHECK-LABEL: @bs16 +; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +declare i16 @llvm.bswap.i16(i16) #0 + +; Function Attrs: nounwind readnone +define zeroext i32 @ctlz32(i32 zeroext %x) #0 { +entry: + %0 = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) + ret i32 %0 + +; CHECK-LABEL: @ctlz32 +; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 +; CHECK: blr +} + +; Function Attrs: nounwind readnone +declare i32 @llvm.ctlz.i32(i32, i1) #0 + + +attributes #0 = { nounwind readnone } +attributes #1 = { nounwind readonly } + diff --git a/test/CodeGen/PowerPC/sdiv-pow2.ll b/test/CodeGen/PowerPC/sdiv-pow2.ll new file mode 100644 index 0000000..5ec019d --- /dev/null +++ b/test/CodeGen/PowerPC/sdiv-pow2.ll @@ -0,0 +1,67 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc-unknown-linux-gnu -mcpu=ppc < %s | FileCheck -check-prefix=CHECK-32 %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind readnone +define signext i32 @foo4(i32 signext %a) #0 { +entry: + %div = sdiv i32 %a, 8 + ret i32 %div + +; CHECK-LABEL @foo4 +; CHECK: srawi [[REG1:[0-9]+]], 3, 3 +; CHECK: addze [[REG2:[0-9]+]], [[REG1]] +; CHECK: extsw 3, [[REG2]] +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define i64 @foo8(i64 %a) #0 { +entry: + %div = sdiv i64 %a, 8 + ret i64 %div + +; CHECK-LABEL @foo8 +; CHECK: sradi [[REG1:[0-9]+]], 3, 3 +; CHECK: addze 3, [[REG1]] +; CHECK: blr + +; CHECK-32-LABEL @foo8 +; CHECK-32-NOT: sradi +; CHECK-32: blr +} + +; Function Attrs: nounwind readnone +define signext i32 @foo4n(i32 signext %a) #0 { +entry: + %div = sdiv i32 %a, -8 + ret i32 %div + +; CHECK-LABEL: @foo4n +; CHECK: srawi [[REG1:[0-9]+]], 3, 3 +; CHECK: addze [[REG2:[0-9]+]], [[REG1]] +; CHECK: neg [[REG3:[0-9]+]], [[REG2]] +; CHECK: extsw 3, [[REG3]] +; CHECK: blr +} + +; Function Attrs: nounwind readnone +define i64 @foo8n(i64 %a) #0 { +entry: + %div = sdiv i64 %a, -8 + ret i64 %div + +; CHECK-LABEL: @foo8n +; CHECK: sradi [[REG1:[0-9]+]], 3, 3 +; CHECK: addze [[REG2:[0-9]+]], [[REG1]] +; CHECK: neg 3, [[REG2]] +; CHECK: blr + +; CHECK-32-LABEL @foo8n +; CHECK-32-NOT: sradi +; CHECK-32: blr +} + +attributes #0 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/stack-realign.ll b/test/CodeGen/PowerPC/stack-realign.ll index a59fceb..762f50a 100644 --- a/test/CodeGen/PowerPC/stack-realign.ll +++ b/test/CodeGen/PowerPC/stack-realign.ll @@ -37,6 +37,7 @@ entry: ; CHECK-DAG: subfic 0, [[REG]], -160 ; CHECK: stdux 1, 1, 0 +; CHECK: .cfi_def_cfa_register r30 ; CHECK: .cfi_offset r30, -16 ; CHECK: .cfi_offset lr, 16 @@ -59,6 +60,7 @@ entry: ; CHECK-FP-DAG: subfic 0, [[REG]], -160 ; CHECK-FP: stdux 1, 1, 0 +; CHECK-FP: .cfi_def_cfa_register r30 ; CHECK-FP: .cfi_offset r31, -8 ; CHECK-FP: .cfi_offset r30, -16 ; CHECK-FP: .cfi_offset lr, 16 @@ -120,6 +122,8 @@ entry: ; CHECK-DAG: subfc 0, [[REG3]], [[REG2]] ; CHECK: stdux 1, 1, 0 +; CHECK: .cfi_def_cfa_register r30 + ; CHECK: blr ; CHECK-32-LABEL: @hoo @@ -178,6 +182,8 @@ entry: ; CHECK-DAG: subfic 0, [[REG]], -192 ; CHECK: stdux 1, 1, 0 +; CHECK: .cfi_def_cfa_register r30 + ; CHECK: stfd 30, -16(30) ; CHECK: blr @@ -193,6 +199,8 @@ entry: ; CHECK-FP-DAG: subfic 0, [[REG]], -192 ; CHECK-FP: stdux 1, 1, 0 +; CHECK-FP: .cfi_def_cfa_register r30 + ; CHECK-FP: stfd 30, -16(30) ; CHECK-FP: blr diff --git a/test/CodeGen/PowerPC/subreg-postra-2.ll b/test/CodeGen/PowerPC/subreg-postra-2.ll new file mode 100644 index 0000000..2faaa61 --- /dev/null +++ b/test/CodeGen/PowerPC/subreg-postra-2.ll @@ -0,0 +1,175 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @jbd2_journal_commit_transaction() #0 { +entry: + br i1 undef, label %do.body, label %if.then5 + +if.then5: ; preds = %entry + unreachable + +do.body: ; preds = %entry + br i1 undef, label %do.body.i, label %trace_jbd2_start_commit.exit + +do.body.i: ; preds = %do.body + unreachable + +trace_jbd2_start_commit.exit: ; preds = %do.body + br i1 undef, label %do.body.i1116, label %trace_jbd2_commit_locking.exit + +do.body.i1116: ; preds = %trace_jbd2_start_commit.exit + unreachable + +trace_jbd2_commit_locking.exit: ; preds = %trace_jbd2_start_commit.exit + br i1 undef, label %while.end, label %while.body.lr.ph + +while.body.lr.ph: ; preds = %trace_jbd2_commit_locking.exit + unreachable + +while.end: ; preds = %trace_jbd2_commit_locking.exit + br i1 undef, label %spin_unlock.exit1146, label %if.then.i.i.i.i1144 + +if.then.i.i.i.i1144: ; preds = %while.end + unreachable + +spin_unlock.exit1146: ; preds = %while.end + br i1 undef, label %spin_unlock.exit1154, label %if.then.i.i.i.i1152 + +if.then.i.i.i.i1152: ; preds = %spin_unlock.exit1146 + unreachable + +spin_unlock.exit1154: ; preds = %spin_unlock.exit1146 + br i1 undef, label %do.body.i1159, label %trace_jbd2_commit_flushing.exit + +do.body.i1159: ; preds = %spin_unlock.exit1154 + br i1 undef, label %if.end.i1166, label %do.body5.i1165 + +do.body5.i1165: ; preds = %do.body.i1159 + unreachable + +if.end.i1166: ; preds = %do.body.i1159 + unreachable + +trace_jbd2_commit_flushing.exit: ; preds = %spin_unlock.exit1154 + br i1 undef, label %for.end.i, label %for.body.lr.ph.i + +for.body.lr.ph.i: ; preds = %trace_jbd2_commit_flushing.exit + unreachable + +for.end.i: ; preds = %trace_jbd2_commit_flushing.exit + br i1 undef, label %journal_submit_data_buffers.exit, label %if.then.i.i.i.i31.i + +if.then.i.i.i.i31.i: ; preds = %for.end.i + br label %journal_submit_data_buffers.exit + +journal_submit_data_buffers.exit: ; preds = %if.then.i.i.i.i31.i, %for.end.i + br i1 undef, label %if.end103, label %if.then102 + +if.then102: ; preds = %journal_submit_data_buffers.exit + unreachable + +if.end103: ; preds = %journal_submit_data_buffers.exit + br i1 undef, label %do.body.i1182, label %trace_jbd2_commit_logging.exit + +do.body.i1182: ; preds = %if.end103 + br i1 undef, label %if.end.i1189, label %do.body5.i1188 + +do.body5.i1188: ; preds = %do.body5.i1188, %do.body.i1182 + br i1 undef, label %if.end.i1189, label %do.body5.i1188 + +if.end.i1189: ; preds = %do.body5.i1188, %do.body.i1182 + unreachable + +trace_jbd2_commit_logging.exit: ; preds = %if.end103 + br label %while.cond129.outer1451 + +while.cond129.outer1451: ; preds = %start_journal_io, %trace_jbd2_commit_logging.exit + br label %while.cond129 + +while.cond129: ; preds = %if.then135, %while.cond129.outer1451 + br i1 undef, label %while.end246, label %if.then135 + +if.then135: ; preds = %while.cond129 + br i1 undef, label %start_journal_io, label %while.cond129 + +start_journal_io: ; preds = %if.then135 + br label %while.cond129.outer1451 + +while.end246: ; preds = %while.cond129 + br i1 undef, label %for.end.i1287, label %for.body.i1277 + +for.body.i1277: ; preds = %while.end246 + unreachable + +for.end.i1287: ; preds = %while.end246 + br i1 undef, label %journal_finish_inode_data_buffers.exit, label %if.then.i.i.i.i84.i + +if.then.i.i.i.i84.i: ; preds = %for.end.i1287 + unreachable + +journal_finish_inode_data_buffers.exit: ; preds = %for.end.i1287 + br i1 undef, label %if.end256, label %if.then249 + +if.then249: ; preds = %journal_finish_inode_data_buffers.exit + unreachable + +if.end256: ; preds = %journal_finish_inode_data_buffers.exit + br label %while.body318 + +while.body318: ; preds = %wait_on_buffer.exit, %if.end256 + br i1 undef, label %wait_on_buffer.exit, label %if.then.i1296 + +if.then.i1296: ; preds = %while.body318 + br label %wait_on_buffer.exit + +wait_on_buffer.exit: ; preds = %if.then.i1296, %while.body318 + br i1 undef, label %do.body378, label %while.body318 + +do.body378: ; preds = %wait_on_buffer.exit + br i1 undef, label %while.end418, label %while.body392.lr.ph + +while.body392.lr.ph: ; preds = %do.body378 + br label %while.body392 + +while.body392: ; preds = %wait_on_buffer.exit1319, %while.body392.lr.ph + %0 = load i8** undef, align 8 + %add.ptr399 = getelementptr inbounds i8* %0, i64 -72 + %b_state.i.i1314 = bitcast i8* %add.ptr399 to i64* + %tobool.i1316 = icmp eq i64 undef, 0 + br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %if.then.i1317 + +if.then.i1317: ; preds = %while.body392 + unreachable + +wait_on_buffer.exit1319: ; preds = %while.body392 + %1 = load volatile i64* %b_state.i.i1314, align 8 + %conv.i.i1322 = and i64 %1, 1 + %lnot404 = icmp eq i64 %conv.i.i1322, 0 + %.err.4 = select i1 %lnot404, i32 -5, i32 undef + %2 = call i64 asm sideeffect "1:.long 0x7c0000a8 $| ((($0) & 0x1f) << 21) $| (((0) & 0x1f) << 16) $| ((($3) & 0x1f) << 11) $| (((0) & 0x1) << 0) \0Aandc $0,$0,$2\0Astdcx. $0,0,$3\0Abne- 1b\0A", "=&r,=*m,r,r,*m,~{cc},~{memory}"(i64* %b_state.i.i1314, i64 262144, i64* %b_state.i.i1314, i64* %b_state.i.i1314) #0 + store i8* %0, i8** undef, align 8 + %cmp.i1312 = icmp eq i32* undef, undef + br i1 %cmp.i1312, label %while.end418, label %while.body392 + +while.end418: ; preds = %wait_on_buffer.exit1319, %do.body378 + %err.4.lcssa = phi i32 [ undef, %do.body378 ], [ %.err.4, %wait_on_buffer.exit1319 ] + %tobool419 = icmp eq i32 %err.4.lcssa, 0 + br i1 %tobool419, label %if.end421, label %if.then420 + +; CHECK-LABEL: @jbd2_journal_commit_transaction +; CHECK: andi. +; CHECK: cror [[REG:[0-9]+]], 1, 1 +; CHECK: stdcx. +; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]] + +if.then420: ; preds = %while.end418 + unreachable + +if.end421: ; preds = %while.end418 + unreachable +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/subreg-postra.ll b/test/CodeGen/PowerPC/subreg-postra.ll new file mode 100644 index 0000000..b10fa66 --- /dev/null +++ b/test/CodeGen/PowerPC/subreg-postra.ll @@ -0,0 +1,168 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @jbd2_journal_commit_transaction(i32* %journal) #0 { +entry: + br i1 undef, label %do.body, label %if.then5 + +if.then5: ; preds = %entry + unreachable + +do.body: ; preds = %entry + br i1 undef, label %do.body.i, label %trace_jbd2_start_commit.exit + +do.body.i: ; preds = %do.body + unreachable + +trace_jbd2_start_commit.exit: ; preds = %do.body + br i1 undef, label %do.body.i1116, label %trace_jbd2_commit_locking.exit + +do.body.i1116: ; preds = %trace_jbd2_start_commit.exit + br i1 undef, label %if.end.i1123, label %do.body5.i1122 + +do.body5.i1122: ; preds = %do.body.i1116 + unreachable + +if.end.i1123: ; preds = %do.body.i1116 + br label %trace_jbd2_commit_locking.exit + +trace_jbd2_commit_locking.exit: ; preds = %if.end.i1123, %trace_jbd2_start_commit.exit + br i1 undef, label %spin_unlock.exit1146, label %if.then.i.i.i.i1144 + +if.then.i.i.i.i1144: ; preds = %trace_jbd2_commit_locking.exit + unreachable + +spin_unlock.exit1146: ; preds = %trace_jbd2_commit_locking.exit + br i1 undef, label %spin_unlock.exit1154, label %if.then.i.i.i.i1152 + +if.then.i.i.i.i1152: ; preds = %spin_unlock.exit1146 + br label %spin_unlock.exit1154 + +spin_unlock.exit1154: ; preds = %if.then.i.i.i.i1152, %spin_unlock.exit1146 + br i1 undef, label %do.body.i1159, label %trace_jbd2_commit_flushing.exit + +do.body.i1159: ; preds = %spin_unlock.exit1154 + unreachable + +trace_jbd2_commit_flushing.exit: ; preds = %spin_unlock.exit1154 + br i1 undef, label %for.end.i, label %for.body.lr.ph.i + +for.body.lr.ph.i: ; preds = %trace_jbd2_commit_flushing.exit + br i1 undef, label %spin_unlock.exit.i, label %if.then.i.i.i.i.i + +if.then.i.i.i.i.i: ; preds = %for.body.lr.ph.i + unreachable + +spin_unlock.exit.i: ; preds = %for.body.lr.ph.i + unreachable + +for.end.i: ; preds = %trace_jbd2_commit_flushing.exit + br i1 undef, label %journal_submit_data_buffers.exit, label %if.then.i.i.i.i31.i + +if.then.i.i.i.i31.i: ; preds = %for.end.i + unreachable + +journal_submit_data_buffers.exit: ; preds = %for.end.i + br i1 undef, label %if.end103, label %if.then102 + +if.then102: ; preds = %journal_submit_data_buffers.exit + unreachable + +if.end103: ; preds = %journal_submit_data_buffers.exit + br i1 undef, label %do.body.i1182, label %trace_jbd2_commit_logging.exit + +do.body.i1182: ; preds = %if.end103 + unreachable + +trace_jbd2_commit_logging.exit: ; preds = %if.end103 + br i1 undef, label %for.end.i1287, label %for.body.i1277 + +for.body.i1277: ; preds = %trace_jbd2_commit_logging.exit + unreachable + +for.end.i1287: ; preds = %trace_jbd2_commit_logging.exit + br i1 undef, label %journal_finish_inode_data_buffers.exit, label %if.then.i.i.i.i84.i + +if.then.i.i.i.i84.i: ; preds = %for.end.i1287 + unreachable + +journal_finish_inode_data_buffers.exit: ; preds = %for.end.i1287 + br i1 undef, label %if.end256, label %if.then249 + +if.then249: ; preds = %journal_finish_inode_data_buffers.exit + unreachable + +if.end256: ; preds = %journal_finish_inode_data_buffers.exit + br i1 undef, label %do.body277, label %if.then260 + +if.then260: ; preds = %if.end256 + br label %do.body277 + +do.body277: ; preds = %if.then260, %if.end256 + br label %while.body318 + +while.body318: ; preds = %wait_on_buffer.exit, %do.body277 + %tobool.i1295 = icmp eq i64 undef, 0 + br i1 %tobool.i1295, label %wait_on_buffer.exit, label %if.then.i1296 + +if.then.i1296: ; preds = %while.body318 + unreachable + +wait_on_buffer.exit: ; preds = %while.body318 + br i1 undef, label %do.body378, label %while.body318 + +do.body378: ; preds = %wait_on_buffer.exit + br i1 undef, label %while.end418, label %while.body392.lr.ph + +while.body392.lr.ph: ; preds = %do.body378 + br label %while.body392 + +while.body392: ; preds = %wait_on_buffer.exit1319, %while.body392.lr.ph + %0 = load i8** undef, align 8 + %add.ptr399 = getelementptr inbounds i8* %0, i64 -72 + %b_state.i.i1314 = bitcast i8* %add.ptr399 to i64* + %tobool.i1316 = icmp eq i64 undef, 0 + br i1 %tobool.i1316, label %wait_on_buffer.exit1319, label %if.then.i1317 + +if.then.i1317: ; preds = %while.body392 + unreachable + +wait_on_buffer.exit1319: ; preds = %while.body392 + %1 = load volatile i64* %b_state.i.i1314, align 8 + %conv.i.i1322 = and i64 %1, 1 + %lnot404 = icmp eq i64 %conv.i.i1322, 0 + %.err.4 = select i1 %lnot404, i32 -5, i32 undef + %2 = call i64 asm sideeffect "1:.long 0x7c0000a8 $| ((($0) & 0x1f) << 21) $| (((0) & 0x1f) << 16) $| ((($3) & 0x1f) << 11) $| (((0) & 0x1) << 0) \0Aandc $0,$0,$2\0Astdcx. $0,0,$3\0Abne- 1b\0A", "=&r,=*m,r,r,*m,~{cc},~{memory}"(i64* %b_state.i.i1314, i64 262144, i64* %b_state.i.i1314, i64* %b_state.i.i1314) #1 + %prev.i.i.i1325 = getelementptr inbounds i8* %0, i64 8 + %3 = load i32** null, align 8 + store i32* %3, i32** undef, align 8 + call void @__brelse(i32* undef) #1 + br i1 undef, label %while.end418, label %while.body392 + +; CHECK-LABEL: @jbd2_journal_commit_transaction +; CHECK: andi. +; CHECK: cror [[REG:[0-9]+]], 1, 1 +; CHECK: stdcx. +; CHECK: isel {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}, [[REG]] + +while.end418: ; preds = %wait_on_buffer.exit1319, %do.body378 + %err.4.lcssa = phi i32 [ undef, %do.body378 ], [ %.err.4, %wait_on_buffer.exit1319 ] + br i1 undef, label %if.end421, label %if.then420 + +if.then420: ; preds = %while.end418 + call void @jbd2_journal_abort(i32* %journal, i32 signext %err.4.lcssa) #1 + br label %if.end421 + +if.end421: ; preds = %if.then420, %while.end418 + unreachable +} + +declare void @jbd2_journal_abort(i32*, i32 signext) + +declare void @__brelse(i32*) + +attributes #0 = { nounwind } +attributes #1 = { nounwind } + diff --git a/test/CodeGen/PowerPC/tls-cse.ll b/test/CodeGen/PowerPC/tls-cse.ll new file mode 100644 index 0000000..2aa75f9 --- /dev/null +++ b/test/CodeGen/PowerPC/tls-cse.ll @@ -0,0 +1,52 @@ +; RUN: llc -march=ppc64 -mcpu=pwr7 -O2 -relocation-model=pic < %s | FileCheck %s +; RUN: llc -march=ppc64 -mcpu=pwr7 -O2 -relocation-model=pic < %s | grep "__tls_get_addr" | count 1 + +; This test was derived from LLVM's own +; PrettyStackTraceEntry::~PrettyStackTraceEntry(). It demonstrates an +; opportunity for CSE of calls to __tls_get_addr(). + +target datalayout = "e-m:e-i64:64-n32:64" +target triple = "powerpc64le-unknown-linux-gnu" + +%"class.llvm::PrettyStackTraceEntry" = type { i32 (...)**, %"class.llvm::PrettyStackTraceEntry"* } + +@_ZTVN4llvm21PrettyStackTraceEntryE = unnamed_addr constant [5 x i8*] [i8* null, i8* null, i8* bitcast (void (%"class.llvm::PrettyStackTraceEntry"*)* @_ZN4llvm21PrettyStackTraceEntryD2Ev to i8*), i8* bitcast (void (%"class.llvm::PrettyStackTraceEntry"*)* @_ZN4llvm21PrettyStackTraceEntryD0Ev to i8*), i8* bitcast (void ()* @__cxa_pure_virtual to i8*)], align 8 +@_ZL20PrettyStackTraceHead = internal thread_local unnamed_addr global %"class.llvm::PrettyStackTraceEntry"* null, align 8 +@.str = private unnamed_addr constant [87 x i8] c"PrettyStackTraceHead == this && \22Pretty stack trace entry destruction is out of order\22\00", align 1 +@.str1 = private unnamed_addr constant [64 x i8] c"/home/wschmidt/llvm/llvm-test2/lib/Support/PrettyStackTrace.cpp\00", align 1 +@__PRETTY_FUNCTION__._ZN4llvm21PrettyStackTraceEntryD2Ev = private unnamed_addr constant [62 x i8] c"virtual llvm::PrettyStackTraceEntry::~PrettyStackTraceEntry()\00", align 1 + +declare void @_ZN4llvm21PrettyStackTraceEntryD2Ev(%"class.llvm::PrettyStackTraceEntry"* %this) unnamed_addr +declare void @__cxa_pure_virtual() +declare void @__assert_fail(i8*, i8*, i32 zeroext, i8*) +declare void @_ZdlPv(i8*) + +define void @_ZN4llvm21PrettyStackTraceEntryD0Ev(%"class.llvm::PrettyStackTraceEntry"* %this) unnamed_addr align 2 { +entry: + %0 = getelementptr inbounds %"class.llvm::PrettyStackTraceEntry"* %this, i64 0, i32 0 + store i32 (...)** bitcast (i8** getelementptr inbounds ([5 x i8*]* @_ZTVN4llvm21PrettyStackTraceEntryE, i64 0, i64 2) to i32 (...)**), i32 (...)*** %0, align 8 + %1 = load %"class.llvm::PrettyStackTraceEntry"** @_ZL20PrettyStackTraceHead, align 8 + %cmp.i = icmp eq %"class.llvm::PrettyStackTraceEntry"* %1, %this + br i1 %cmp.i, label %_ZN4llvm21PrettyStackTraceEntryD2Ev.exit, label %cond.false.i + +cond.false.i: ; preds = %entry + tail call void @__assert_fail(i8* getelementptr inbounds ([87 x i8]* @.str, i64 0, i64 0), i8* getelementptr inbounds ([64 x i8]* @.str1, i64 0, i64 0), i32 zeroext 119, i8* getelementptr inbounds ([62 x i8]* @__PRETTY_FUNCTION__._ZN4llvm21PrettyStackTraceEntryD2Ev, i64 0, i64 0)) + unreachable + +_ZN4llvm21PrettyStackTraceEntryD2Ev.exit: ; preds = %entry + %NextEntry.i.i = getelementptr inbounds %"class.llvm::PrettyStackTraceEntry"* %this, i64 0, i32 1 + %2 = bitcast %"class.llvm::PrettyStackTraceEntry"** %NextEntry.i.i to i64* + %3 = load i64* %2, align 8 + store i64 %3, i64* bitcast (%"class.llvm::PrettyStackTraceEntry"** @_ZL20PrettyStackTraceHead to i64*), align 8 + %4 = bitcast %"class.llvm::PrettyStackTraceEntry"* %this to i8* + tail call void @_ZdlPv(i8* %4) + ret void +} + +; CHECK-LABEL: _ZN4llvm21PrettyStackTraceEntryD0Ev: +; CHECK: addis [[REG1:[0-9]+]], 2, _ZL20PrettyStackTraceHead@got@tlsld@ha +; CHECK: addi 3, [[REG1]], _ZL20PrettyStackTraceHead@got@tlsld@l +; CHECK: bl __tls_get_addr(_ZL20PrettyStackTraceHead@tlsld) +; CHECK: addis 3, 3, _ZL20PrettyStackTraceHead@dtprel@ha +; CHECK: ld {{[0-9]+}}, _ZL20PrettyStackTraceHead@dtprel@l(3) +; CHECK: std {{[0-9]+}}, _ZL20PrettyStackTraceHead@dtprel@l(3) diff --git a/test/CodeGen/PowerPC/tls-pic.ll b/test/CodeGen/PowerPC/tls-pic.ll index 9ba3725..6c671b0 100644 --- a/test/CodeGen/PowerPC/tls-pic.ll +++ b/test/CodeGen/PowerPC/tls-pic.ll @@ -19,32 +19,32 @@ entry: ; OPT0-LABEL: main: ; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha -; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l +; OPT0: addi 3, [[REG]], a@got@tlsld@l ; OPT0: bl __tls_get_addr(a@tlsld) ; OPT0-NEXT: nop ; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha -; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l +; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l ; OPT0-32-LABEL: main ; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld ; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha -; OPT0-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l +; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l ; OPT1-32-LABEL: main ; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld ; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha -; OPT1-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l +; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l ; Test peephole optimization for thread-local storage using the ; local dynamic model. ; OPT1-LABEL: main: ; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha -; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l +; OPT1: addi 3, [[REG]], a@got@tlsld@l ; OPT1: bl __tls_get_addr(a@tlsld) ; OPT1-NEXT: nop ; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha -; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) +; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) ; Test correct assembly code generation for thread-local storage using ; the general dynamic model. @@ -60,8 +60,8 @@ entry: } ; OPT1-LABEL: main2 -; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha -; OPT1-NEXT: addi 3, [[REG]], a2@got@tlsgd@l +; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha +; OPT1: addi 3, [[REG]], a2@got@tlsgd@l ; OPT1: bl __tls_get_addr(a2@tlsgd) ; OPT1-NEXT: nop ; OPT1-32-LABEL: main2 diff --git a/test/CodeGen/PowerPC/tls-store2.ll b/test/CodeGen/PowerPC/tls-store2.ll index f884dd8..e9aa17e 100644 --- a/test/CodeGen/PowerPC/tls-store2.ll +++ b/test/CodeGen/PowerPC/tls-store2.ll @@ -19,13 +19,14 @@ entry: } ; CHECK-LABEL: call_once: -; CHECK: addis 3, 2, __once_callable@got@tlsgd@ha -; CHECK: addi 3, 3, __once_callable@got@tlsgd@l +; CHECK: addi 3, {{[0-9]+}}, __once_callable@got@tlsgd@l ; CHECK: bl __tls_get_addr(__once_callable@tlsgd) ; CHECK-NEXT: nop -; CHECK: std {{[0-9]+}}, 0(3) -; CHECK: addis 3, 2, __once_call@got@tlsgd@ha -; CHECK: addi 3, 3, __once_call@got@tlsgd@l +; FIXME: We could check here for 'std {{[0-9]+}}, 0(3)', but that no longer +; works because, with new scheduling freedom, we create a copy of R3 based on the +; initial scheduling, but don't coalesce it again after we move the instructions +; so that the copy is no longer necessary. +; CHECK: addi 3, {{[0-9]+}}, __once_call@got@tlsgd@l ; CHECK: bl __tls_get_addr(__once_call@tlsgd) ; CHECK-NEXT: nop ; CHECK: std {{[0-9]+}}, 0(3) diff --git a/test/CodeGen/PowerPC/toc-load-sched-bug.ll b/test/CodeGen/PowerPC/toc-load-sched-bug.ll index d437915..e92c4f4 100644 --- a/test/CodeGen/PowerPC/toc-load-sched-bug.ll +++ b/test/CodeGen/PowerPC/toc-load-sched-bug.ll @@ -484,51 +484,51 @@ attributes #7 = { noreturn nounwind } !llvm.ident = !{!0} -!0 = metadata !{metadata !"clang version 3.6.0 (trunk 215115) (llvm/trunk 215117)"} -!1 = metadata !{metadata !2, metadata !4, i64 0} -!2 = metadata !{metadata !"_ZTSSs", metadata !3, i64 0} -!3 = metadata !{metadata !"_ZTSNSs12_Alloc_hiderE", metadata !4, i64 0} -!4 = metadata !{metadata !"any pointer", metadata !5, i64 0} -!5 = metadata !{metadata !"omnipotent char", metadata !6, i64 0} -!6 = metadata !{metadata !"Simple C/C++ TBAA"} -!7 = metadata !{metadata !8, metadata !9, i64 0} -!8 = metadata !{metadata !"_ZTSNSs9_Rep_baseE", metadata !9, i64 0, metadata !9, i64 8, metadata !10, i64 16} -!9 = metadata !{metadata !"long", metadata !5, i64 0} -!10 = metadata !{metadata !"int", metadata !5, i64 0} -!11 = metadata !{metadata !12, metadata !12, i64 0} -!12 = metadata !{metadata !"vtable pointer", metadata !6, i64 0} -!13 = metadata !{metadata !3, metadata !4, i64 0} -!14 = metadata !{metadata !15, metadata !10, i64 24} -!15 = metadata !{metadata !"_ZTSN4llvm12SMDiagnosticE", metadata !4, i64 0, metadata !16, i64 8, metadata !2, i64 16, metadata !10, i64 24, metadata !10, i64 28, metadata !17, i64 32, metadata !2, i64 40, metadata !2, i64 48, metadata !18, i64 56, metadata !19, i64 80} -!16 = metadata !{metadata !"_ZTSN4llvm5SMLocE", metadata !4, i64 0} -!17 = metadata !{metadata !"_ZTSN4llvm9SourceMgr8DiagKindE", metadata !5, i64 0} -!18 = metadata !{metadata !"_ZTSSt6vectorISt4pairIjjESaIS1_EE"} -!19 = metadata !{metadata !"_ZTSN4llvm11SmallVectorINS_7SMFixItELj4EEE", metadata !20, i64 48} -!20 = metadata !{metadata !"_ZTSN4llvm18SmallVectorStorageINS_7SMFixItELj4EEE", metadata !5, i64 0} -!21 = metadata !{metadata !15, metadata !10, i64 28} -!22 = metadata !{metadata !15, metadata !17, i64 32} -!23 = metadata !{metadata !24, metadata !4, i64 0} -!24 = metadata !{metadata !"_ZTSN4llvm15SmallVectorBaseE", metadata !4, i64 0, metadata !4, i64 8, metadata !4, i64 16} -!25 = metadata !{metadata !24, metadata !4, i64 8} -!26 = metadata !{metadata !24, metadata !4, i64 16} -!27 = metadata !{metadata !4, metadata !4, i64 0} -!28 = metadata !{metadata !"branch_weights", i32 64, i32 4} -!29 = metadata !{metadata !10, metadata !10, i64 0} -!30 = metadata !{metadata !31, metadata !4, i64 8} -!31 = metadata !{metadata !"_ZTSN4llvm12MemoryBufferE", metadata !4, i64 8, metadata !4, i64 16} -!32 = metadata !{metadata !31, metadata !4, i64 16} -!33 = metadata !{metadata !5, metadata !5, i64 0} -!34 = metadata !{metadata !35, metadata !4, i64 0} -!35 = metadata !{metadata !"_ZTSSt12_Vector_baseISt4pairIjjESaIS1_EE", metadata !36, i64 0} -!36 = metadata !{metadata !"_ZTSNSt12_Vector_baseISt4pairIjjESaIS1_EE12_Vector_implE", metadata !4, i64 0, metadata !4, i64 8, metadata !4, i64 16} -!37 = metadata !{metadata !38, metadata !38, i64 0} -!38 = metadata !{metadata !"bool", metadata !5, i64 0} -!39 = metadata !{i8 0, i8 2} -!40 = metadata !{metadata !41, metadata !4, i64 0} -!41 = metadata !{metadata !"_ZTSN4llvm10TimeRegionE", metadata !4, i64 0} -!42 = metadata !{metadata !43, metadata !44, i64 32} -!43 = metadata !{metadata !"_ZTSN4llvm11raw_ostreamE", metadata !4, i64 8, metadata !4, i64 16, metadata !4, i64 24, metadata !44, i64 32} -!44 = metadata !{metadata !"_ZTSN4llvm11raw_ostream10BufferKindE", metadata !5, i64 0} -!45 = metadata !{metadata !43, metadata !4, i64 24} -!46 = metadata !{metadata !43, metadata !4, i64 8} -!47 = metadata !{i64 0, i64 8, metadata !27, i64 8, i64 8, metadata !27} +!0 = !{!"clang version 3.6.0 (trunk 215115) (llvm/trunk 215117)"} +!1 = !{!2, !4, i64 0} +!2 = !{!"_ZTSSs", !3, i64 0} +!3 = !{!"_ZTSNSs12_Alloc_hiderE", !4, i64 0} +!4 = !{!"any pointer", !5, i64 0} +!5 = !{!"omnipotent char", !6, i64 0} +!6 = !{!"Simple C/C++ TBAA"} +!7 = !{!8, !9, i64 0} +!8 = !{!"_ZTSNSs9_Rep_baseE", !9, i64 0, !9, i64 8, !10, i64 16} +!9 = !{!"long", !5, i64 0} +!10 = !{!"int", !5, i64 0} +!11 = !{!12, !12, i64 0} +!12 = !{!"vtable pointer", !6, i64 0} +!13 = !{!3, !4, i64 0} +!14 = !{!15, !10, i64 24} +!15 = !{!"_ZTSN4llvm12SMDiagnosticE", !4, i64 0, !16, i64 8, !2, i64 16, !10, i64 24, !10, i64 28, !17, i64 32, !2, i64 40, !2, i64 48, !18, i64 56, !19, i64 80} +!16 = !{!"_ZTSN4llvm5SMLocE", !4, i64 0} +!17 = !{!"_ZTSN4llvm9SourceMgr8DiagKindE", !5, i64 0} +!18 = !{!"_ZTSSt6vectorISt4pairIjjESaIS1_EE"} +!19 = !{!"_ZTSN4llvm11SmallVectorINS_7SMFixItELj4EEE", !20, i64 48} +!20 = !{!"_ZTSN4llvm18SmallVectorStorageINS_7SMFixItELj4EEE", !5, i64 0} +!21 = !{!15, !10, i64 28} +!22 = !{!15, !17, i64 32} +!23 = !{!24, !4, i64 0} +!24 = !{!"_ZTSN4llvm15SmallVectorBaseE", !4, i64 0, !4, i64 8, !4, i64 16} +!25 = !{!24, !4, i64 8} +!26 = !{!24, !4, i64 16} +!27 = !{!4, !4, i64 0} +!28 = !{!"branch_weights", i32 64, i32 4} +!29 = !{!10, !10, i64 0} +!30 = !{!31, !4, i64 8} +!31 = !{!"_ZTSN4llvm12MemoryBufferE", !4, i64 8, !4, i64 16} +!32 = !{!31, !4, i64 16} +!33 = !{!5, !5, i64 0} +!34 = !{!35, !4, i64 0} +!35 = !{!"_ZTSSt12_Vector_baseISt4pairIjjESaIS1_EE", !36, i64 0} +!36 = !{!"_ZTSNSt12_Vector_baseISt4pairIjjESaIS1_EE12_Vector_implE", !4, i64 0, !4, i64 8, !4, i64 16} +!37 = !{!38, !38, i64 0} +!38 = !{!"bool", !5, i64 0} +!39 = !{i8 0, i8 2} +!40 = !{!41, !4, i64 0} +!41 = !{!"_ZTSN4llvm10TimeRegionE", !4, i64 0} +!42 = !{!43, !44, i64 32} +!43 = !{!"_ZTSN4llvm11raw_ostreamE", !4, i64 8, !4, i64 16, !4, i64 24, !44, i64 32} +!44 = !{!"_ZTSN4llvm11raw_ostream10BufferKindE", !5, i64 0} +!45 = !{!43, !4, i64 24} +!46 = !{!43, !4, i64 8} +!47 = !{i64 0, i64 8, !27, i64 8, i64 8, !27} diff --git a/test/CodeGen/PowerPC/unwind-dw2-g.ll b/test/CodeGen/PowerPC/unwind-dw2-g.ll index 54d3189..4ae6ff2 100644 --- a/test/CodeGen/PowerPC/unwind-dw2-g.ll +++ b/test/CodeGen/PowerPC/unwind-dw2-g.ll @@ -21,15 +21,15 @@ attributes #0 = { nounwind } !llvm.dbg.cu = !{!0} !llvm.module.flags = !{!8, !11} -!0 = metadata !{metadata !"0x11\0012\00clang version 3.4\000\00\000\00\000", metadata !1, metadata !2, metadata !2, metadata !3, metadata !2, metadata !2} ; [ DW_TAG_compile_unit ] [/tmp/unwind-dw2.c] [DW_LANG_C99] -!1 = metadata !{metadata !"/tmp/unwind-dw2.c", metadata !"/tmp"} -!2 = metadata !{} -!3 = metadata !{metadata !4} -!4 = metadata !{metadata !"0x2e\00foo\00foo\00\001\000\001\000\006\000\000\001", metadata !1, metadata !5, metadata !6, null, void ()* @foo, null, null, metadata !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] -!5 = metadata !{metadata !"0x29", metadata !1} ; [ DW_TAG_file_type ] [/tmp/unwind-dw2.c] -!6 = metadata !{metadata !"0x15\00\000\000\000\000\000\000", i32 0, null, null, metadata !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] -!7 = metadata !{null} -!8 = metadata !{i32 2, metadata !"Dwarf Version", i32 3} -!9 = metadata !{i32 2, i32 0, metadata !4, null} -!10 = metadata !{i32 3, i32 0, metadata !4, null} -!11 = metadata !{i32 1, metadata !"Debug Info Version", i32 2} +!0 = !{!"0x11\0012\00clang version 3.4\000\00\000\00\000", !1, !2, !2, !3, !2, !2} ; [ DW_TAG_compile_unit ] [/tmp/unwind-dw2.c] [DW_LANG_C99] +!1 = !{!"/tmp/unwind-dw2.c", !"/tmp"} +!2 = !{} +!3 = !{!4} +!4 = !{!"0x2e\00foo\00foo\00\001\000\001\000\006\000\000\001", !1, !5, !6, null, void ()* @foo, null, null, !2} ; [ DW_TAG_subprogram ] [line 1] [def] [foo] +!5 = !{!"0x29", !1} ; [ DW_TAG_file_type ] [/tmp/unwind-dw2.c] +!6 = !{!"0x15\00\000\000\000\000\000\000", i32 0, null, null, !7, null, null, null} ; [ DW_TAG_subroutine_type ] [line 0, size 0, align 0, offset 0] [from ] +!7 = !{null} +!8 = !{i32 2, !"Dwarf Version", i32 3} +!9 = !MDLocation(line: 2, scope: !4) +!10 = !MDLocation(line: 3, scope: !4) +!11 = !{i32 1, !"Debug Info Version", i32 2} diff --git a/test/CodeGen/PowerPC/vec-abi-align.ll b/test/CodeGen/PowerPC/vec-abi-align.ll index 5075ff2..2ec57af 100644 --- a/test/CodeGen/PowerPC/vec-abi-align.ll +++ b/test/CodeGen/PowerPC/vec-abi-align.ll @@ -35,17 +35,17 @@ entry: ret void ; CHECK-LABEL: @test2 -; CHECK: ld {{[0-9]+}}, 112(1) -; CHECK: li [[REG16:[0-9]+]], 16 -; CHECK: addi [[REGB:[0-9]+]], 1, 112 -; CHECK: lvx 2, [[REGB]], [[REG16]] +; CHECK-DAG: ld {{[0-9]+}}, 112(1) +; CHECK-DAG: li [[REG16:[0-9]+]], 16 +; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 112 +; CHECK-DAG: lvx 2, [[REGB]], [[REG16]] ; CHECK: blr ; CHECK-VSX-LABEL: @test2 -; CHECK-VSX: ld {{[0-9]+}}, 112(1) -; CHECK-VSX: li [[REG16:[0-9]+]], 16 -; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 112 -; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] +; CHECK-VSX-DAG: ld {{[0-9]+}}, 112(1) +; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16 +; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 112 +; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] ; CHECK-VSX: blr } @@ -61,17 +61,17 @@ entry: ret void ; CHECK-LABEL: @test3 -; CHECK: ld {{[0-9]+}}, 128(1) -; CHECK: li [[REG16:[0-9]+]], 16 -; CHECK: addi [[REGB:[0-9]+]], 1, 128 -; CHECK: lvx 2, [[REGB]], [[REG16]] +; CHECK-DAG: ld {{[0-9]+}}, 128(1) +; CHECK-DAG: li [[REG16:[0-9]+]], 16 +; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 128 +; CHECK-DAG: lvx 2, [[REGB]], [[REG16]] ; CHECK: blr ; CHECK-VSX-LABEL: @test3 -; CHECK-VSX: ld {{[0-9]+}}, 128(1) -; CHECK-VSX: li [[REG16:[0-9]+]], 16 -; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 128 -; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] +; CHECK-VSX-DAG: ld {{[0-9]+}}, 128(1) +; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16 +; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 128 +; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] ; CHECK-VSX: blr } diff --git a/test/CodeGen/PowerPC/vec_clz.ll b/test/CodeGen/PowerPC/vec_clz.ll new file mode 100644 index 0000000..01cdecd --- /dev/null +++ b/test/CodeGen/PowerPC/vec_clz.ll @@ -0,0 +1,40 @@ +; Check the vctlz* instructions that were added in P8 +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s + +declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8>) nounwind readnone +declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>) nounwind readnone +declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>) nounwind readnone +declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>) nounwind readnone + +define <16 x i8> @test_v16i8(<16 x i8> %x) nounwind readnone { + %vcnt = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %x) + ret <16 x i8> %vcnt +; CHECK: @test_v16i8 +; CHECK: vclzb 2, 2 +; CHECK: blr +} + +define <8 x i16> @test_v8i16(<8 x i16> %x) nounwind readnone { + %vcnt = tail call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %x) + ret <8 x i16> %vcnt +; CHECK: @test_v8i16 +; CHECK: vclzh 2, 2 +; CHECK: blr +} + +define <4 x i32> @test_v4i32(<4 x i32> %x) nounwind readnone { + %vcnt = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %x) + ret <4 x i32> %vcnt +; CHECK: @test_v4i32 +; CHECK: vclzw 2, 2 +; CHECK: blr +} + +define <2 x i64> @test_v2i64(<2 x i64> %x) nounwind readnone { + %vcnt = tail call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %x) + ret <2 x i64> %vcnt +; CHECK: @test_v2i64 +; CHECK: vclzd 2, 2 +; CHECK: blr +} diff --git a/test/CodeGen/PowerPC/vec_misaligned.ll b/test/CodeGen/PowerPC/vec_misaligned.ll index 73a4a4d..49f11e4 100644 --- a/test/CodeGen/PowerPC/vec_misaligned.ll +++ b/test/CodeGen/PowerPC/vec_misaligned.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-vector | FileCheck %s -; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s -check-prefix=CHECK-LE +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mattr=-power8-vector | FileCheck %s -check-prefix=CHECK-LE target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin8" diff --git a/test/CodeGen/PowerPC/vec_popcnt.ll b/test/CodeGen/PowerPC/vec_popcnt.ll new file mode 100644 index 0000000..0ce9dfa --- /dev/null +++ b/test/CodeGen/PowerPC/vec_popcnt.ll @@ -0,0 +1,72 @@ +; Check the vecpopcnt* instructions that were added in P8 +; In addition, check the conversions to/from the v2i64 VMX register that was also added in P8. +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s + +declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone +declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16>) nounwind readnone +declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone +declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone + +define <16 x i8> @test_v16i8_v2i64(<2 x i64> %x) nounwind readnone { + %tmp = bitcast <2 x i64> %x to <16 x i8>; + %vcnt = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp) + ret <16 x i8> %vcnt +; CHECK: @test_v16i8_v2i64 +; CHECK: vpopcntb 2, 2 +; CHECK: blr +} + +define <8 x i16> @test_v8i16_v2i64(<2 x i64> %x) nounwind readnone { + %tmp = bitcast <2 x i64> %x to <8 x i16> + %vcnt = tail call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %tmp) + ret <8 x i16> %vcnt +; CHECK: @test_v8i16_v2i64 +; CHECK: vpopcnth 2, 2 +; CHECK: blr +} + +define <4 x i32> @test_v4i32_v2i64(<2 x i64> %x) nounwind readnone { + %tmp = bitcast <2 x i64> %x to <4 x i32> + %vcnt = tail call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %tmp) + ret <4 x i32> %vcnt +; CHECK: @test_v4i32_v2i64 +; CHECK: vpopcntw 2, 2 +; CHECK: blr +} + +define <2 x i64> @test_v2i64_v2i64(<2 x i64> %x) nounwind readnone { + %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %x) + ret <2 x i64> %vcnt +; CHECK: @test_v2i64_v2i64 +; CHECK: vpopcntd 2, 2 +; CHECK: blr +} + +define <2 x i64> @test_v2i64_v4i32(<4 x i32> %x) nounwind readnone { + %tmp = bitcast <4 x i32> %x to <2 x i64> + %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp) + ret <2 x i64> %vcnt +; CHECK: @test_v2i64_v4i32 +; CHECK: vpopcntd 2, 2 +; CHECK: blr +} + + +define <2 x i64> @test_v2i64_v8i16(<8 x i16> %x) nounwind readnone { + %tmp = bitcast <8 x i16> %x to <2 x i64> + %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp) + ret <2 x i64> %vcnt +; CHECK: @test_v2i64_v8i16 +; CHECK: vpopcntd 2, 2 +; CHECK: blr +} + +define <2 x i64> @test_v2i64_v16i8(<16 x i8> %x) nounwind readnone { + %tmp = bitcast <16 x i8> %x to <2 x i64> + %vcnt = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %tmp) + ret <2 x i64> %vcnt +; CHECK: @test_v2i64_v16i8 +; CHECK: vpopcntd 2, 2 +; CHECK: blr +} diff --git a/test/CodeGen/PowerPC/vec_shuffle_le.ll b/test/CodeGen/PowerPC/vec_shuffle_le.ll index a4b2119..c7fc1c6 100644 --- a/test/CodeGen/PowerPC/vec_shuffle_le.ll +++ b/test/CodeGen/PowerPC/vec_shuffle_le.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) { entry: diff --git a/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll b/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll new file mode 100644 index 0000000..f7d5a51 --- /dev/null +++ b/test/CodeGen/PowerPC/vec_veqv_vnand_vorc.ll @@ -0,0 +1,29 @@ +; Check the miscellaneous logical vector operations added in P8 +; +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s +; Test x eqv y +define <4 x i32> @test_veqv(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp = xor <4 x i32> %x, %y + %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %ret_val +; CHECK: veqv 2, 2, 3 +} + +; Test x vnand y +define <4 x i32> @test_vnand(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp = and <4 x i32> %x, %y + %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %ret_val +; CHECK: vnand 2, 2, 3 +} + +; Test x vorc y and variants +define <4 x i32> @test_vorc(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp1 = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1> + %tmp2 = or <4 x i32> %x, %tmp1 +; CHECK: vorc 3, 2, 3 + %tmp3 = xor <4 x i32> %tmp2, <i32 -1, i32 -1, i32 -1, i32 -1> + %tmp4 = or <4 x i32> %tmp3, %x +; CHECK: vorc 2, 2, 3 + ret <4 x i32> %tmp4 +} diff --git a/test/CodeGen/PowerPC/vsel-prom.ll b/test/CodeGen/PowerPC/vsel-prom.ll new file mode 100644 index 0000000..dd219ec --- /dev/null +++ b/test/CodeGen/PowerPC/vsel-prom.ll @@ -0,0 +1,23 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @Compute_Lateral() #0 { +entry: + br i1 undef, label %if.then, label %if.end + +if.then: ; preds = %entry + unreachable + +if.end: ; preds = %entry + %0 = select i1 undef, <2 x double> undef, <2 x double> zeroinitializer + %1 = extractelement <2 x double> %0, i32 1 + store double %1, double* undef, align 8 + ret void + +; CHECK-LABEL: @Compute_Lateral +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/vsx-args.ll b/test/CodeGen/PowerPC/vsx-args.ll index 520aeb5..2b53c0a 100644 --- a/test/CodeGen/PowerPC/vsx-args.ll +++ b/test/CodeGen/PowerPC/vsx-args.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s +; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/vsx-fma-m.ll b/test/CodeGen/PowerPC/vsx-fma-m.ll index 9dff9a7..ab36072 100644 --- a/test/CodeGen/PowerPC/vsx-fma-m.ll +++ b/test/CodeGen/PowerPC/vsx-fma-m.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx | FileCheck %s +; RUN: llc < %s -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 | FileCheck -check-prefix=CHECK-FISL %s ; Also run with -schedule-ppc-vsx-fma-mutation-early as a stress test for the ; live-interval-updating logic. @@ -22,6 +23,15 @@ entry: ; CHECK-DAG: stxsdx 3, 0, 7 ; CHECK-DAG: stxsdx 1, 7, [[C1]] ; CHECK: blr + +; CHECK-FISL-LABEL: @test1 +; CHECK-FISL-DAG: fmr 0, 1 +; CHECK-FISL-DAG: xsmaddadp 0, 2, 3 +; CHECK-FISL-DAG: stxsdx 0, 0, 7 +; CHECK-FISL-DAG: xsmaddadp 1, 2, 4 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8 +; CHECK-FISL-DAG: stxsdx 1, 7, [[C1]] +; CHECK-FISL: blr } define void @test2(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 { @@ -46,6 +56,19 @@ entry: ; CHECK-DAG: stxsdx 4, 8, [[C1]] ; CHECK-DAG: stxsdx 1, 8, [[C2]] ; CHECK: blr + +; CHECK-FISL-LABEL: @test2 +; CHECK-FISL-DAG: fmr 0, 1 +; CHECK-FISL-DAG: xsmaddadp 0, 2, 3 +; CHECK-FISL-DAG: stxsdx 0, 0, 8 +; CHECK-FISL-DAG: fmr 0, 1 +; CHECK-FISL-DAG: xsmaddadp 0, 2, 4 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 8 +; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]] +; CHECK-FISL-DAG: xsmaddadp 1, 2, 5 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16 +; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]] +; CHECK-FISL: blr } define void @test3(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 { @@ -81,6 +104,20 @@ entry: ; CHECK-DAG: stxsdx 1, 8, [[C2]] ; CHECK-DAG: stxsdx 4, 8, [[C3]] ; CHECK: blr + +; CHECK-FISL-LABEL: @test3 +; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1 +; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4 +; CHECK-FISL-DAG: fmr 4, [[F1]] +; CHECK-FISL-DAG: xsmaddadp 4, 2, 3 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24 +; CHECK-FISL-DAG: stxsdx 4, 8, [[C1]] +; CHECK-FISL-DAG: xsmaddadp 1, 2, 5 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16 +; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]] +; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8 +; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]] +; CHECK-FISL: blr } define void @test4(double %a, double %b, double %c, double %e, double %f, double* nocapture %d) #0 { @@ -116,6 +153,22 @@ entry: ; CHECK-DAG: stxsdx 4, 8, [[C3]] ; CHECK-DAG: stxsdx 1, 8, [[C2]] ; CHECK: blr + +; CHECK-FISL-LABEL: @test4 +; CHECK-FISL-DAG: fmr [[F1:[0-9]+]], 1 +; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 3 +; CHECK-FISL-DAG: stxsdx 0, 0, 8 +; CHECK-FISL-DAG: fmr [[F1]], 1 +; CHECK-FISL-DAG: xsmaddadp [[F1]], 2, 4 +; CHECK-FISL-DAG: li [[C3:[0-9]+]], 8 +; CHECK-FISL-DAG: stxsdx 0, 8, [[C3]] +; CHECK-FISL-DAG: xsmaddadp 0, 2, 3 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 24 +; CHECK-FISL-DAG: stxsdx 0, 8, [[C1]] +; CHECK-FISL-DAG: xsmaddadp 1, 2, 5 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 16 +; CHECK-FISL-DAG: stxsdx 1, 8, [[C2]] +; CHECK-FISL: blr } declare double @llvm.fma.f64(double, double, double) #0 @@ -136,6 +189,15 @@ entry: ; CHECK-DAG: stxvd2x 36, 0, 3 ; CHECK-DAG: stxvd2x 34, 3, [[C1:[0-9]+]] ; CHECK: blr + +; CHECK-FISL-LABEL: @testv1 +; CHECK-FISL-DAG: xxlor 0, 34, 34 +; CHECK-FISL-DAG: xvmaddadp 0, 35, 36 +; CHECK-FISL-DAG: stxvd2x 0, 0, 3 +; CHECK-FISL-DAG: xvmaddadp 34, 35, 37 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16 +; CHECK-FISL-DAG: stxvd2x 34, 3, [[C1:[0-9]+]] +; CHECK-FISL: blr } define void @testv2(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 { @@ -160,6 +222,19 @@ entry: ; CHECK-DAG: stxvd2x 37, 3, [[C1:[0-9]+]] ; CHECK-DAG: stxvd2x 34, 3, [[C2:[0-9]+]] ; CHECK: blr + +; CHECK-FISL-LABEL: @testv2 +; CHECK-FISL-DAG: xxlor 0, 34, 34 +; CHECK-FISL-DAG: xvmaddadp 0, 35, 36 +; CHECK-FISL-DAG: stxvd2x 0, 0, 3 +; CHECK-FISL-DAG: xxlor 0, 34, 34 +; CHECK-FISL-DAG: xvmaddadp 0, 35, 37 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16 +; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1:[0-9]+]] +; CHECK-FISL-DAG: xvmaddadp 34, 35, 38 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32 +; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2:[0-9]+]] +; CHECK-FISL: blr } define void @testv3(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 { @@ -194,13 +269,30 @@ entry: ; re-ordering the instructions. ; CHECK-DAG: xvmaddadp [[V1]], 35, 36 -; CHECK-DAG: xvmaddmdp 36, 35, 37 +; CHECK-DAG: xvmaddmdp 35, 36, 37 ; CHECK-DAG: xvmaddadp 34, 35, 38 ; CHECK-DAG: stxvd2x 32, 0, 3 -; CHECK-DAG: stxvd2x 36, 3, [[C1]] +; CHECK-DAG: stxvd2x 35, 3, [[C1]] ; CHECK-DAG: stxvd2x 34, 3, [[C2]] ; CHECK-DAG: stxvd2x 37, 3, [[C3]] ; CHECK: blr + +; CHECK-FISL-LABEL: @testv3 +; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34 +; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36 +; CHECK-FISL-DAG: stxvd2x [[V1]], 0, 3 +; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34 +; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37 +; CHECK-FISL-DAG: xxlor [[V3:[0-9]+]], 0, 0 +; CHECK-FISL-DAG: xvmaddadp [[V3]], 35, 36 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 48 +; CHECK-FISL-DAG: stxvd2x [[V3]], 3, [[C1]] +; CHECK-FISL-DAG: xvmaddadp 34, 35, 38 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32 +; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]] +; CHECK-FISL-DAG: li [[C3:[0-9]+]], 16 +; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]] +; CHECK-FISL: blr } define void @testv4(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %e, <2 x double> %f, <2 x double>* nocapture %d) #0 { @@ -236,6 +328,22 @@ entry: ; CHECK-DAG: stxvd2x 37, 3, [[C3]] ; CHECK-DAG: stxvd2x 34, 3, [[C2]] ; CHECK: blr + +; CHECK-FISL-LABEL: @testv4 +; CHECK-FISL-DAG: xxlor [[V1:[0-9]+]], 34, 34 +; CHECK-FISL-DAG: xvmaddadp [[V1]], 35, 36 +; CHECK-FISL-DAG: stxvd2x 0, 0, 3 +; CHECK-FISL-DAG: xxlor [[V2:[0-9]+]], 34, 34 +; CHECK-FISL-DAG: xvmaddadp [[V2]], 35, 37 +; CHECK-FISL-DAG: li [[C1:[0-9]+]], 16 +; CHECK-FISL-DAG: stxvd2x 0, 3, [[C1]] +; CHECK-FISL-DAG: xvmaddadp 0, 35, 37 +; CHECK-FISL-DAG: li [[C3:[0-9]+]], 48 +; CHECK-FISL-DAG: stxvd2x 0, 3, [[C3]] +; CHECK-FISL-DAG: xvmaddadp 0, 35, 36 +; CHECK-FISL-DAG: li [[C2:[0-9]+]], 32 +; CHECK-FISL-DAG: stxvd2x 34, 3, [[C2]] +; CHECK-FISL: blr } declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) #0 diff --git a/test/CodeGen/PowerPC/vsx-infl-copy1.ll b/test/CodeGen/PowerPC/vsx-infl-copy1.ll new file mode 100644 index 0000000..cff7f8f --- /dev/null +++ b/test/CodeGen/PowerPC/vsx-infl-copy1.ll @@ -0,0 +1,133 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@ub = external global [1024 x i32], align 4 +@uc = external global [1024 x i32], align 4 + +; Function Attrs: noinline nounwind +define void @_Z8example9Pj() #0 { +entry: + br label %vector.body + +; CHECK-LABEL: @_Z8example9Pj +; CHECK: xxlor + +vector.body: ; preds = %vector.body, %entry + %index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ] + %vec.phi = phi <4 x i32> [ zeroinitializer, %entry ], [ %43, %vector.body ] + %vec.phi20 = phi <4 x i32> [ zeroinitializer, %entry ], [ %44, %vector.body ] + %vec.phi21 = phi <4 x i32> [ zeroinitializer, %entry ], [ %45, %vector.body ] + %vec.phi23 = phi <4 x i32> [ zeroinitializer, %entry ], [ %46, %vector.body ] + %vec.phi24 = phi <4 x i32> [ zeroinitializer, %entry ], [ %47, %vector.body ] + %vec.phi25 = phi <4 x i32> [ zeroinitializer, %entry ], [ %48, %vector.body ] + %vec.phi26 = phi <4 x i32> [ zeroinitializer, %entry ], [ %49, %vector.body ] + %vec.phi27 = phi <4 x i32> [ zeroinitializer, %entry ], [ %50, %vector.body ] + %vec.phi28 = phi <4 x i32> [ zeroinitializer, %entry ], [ %51, %vector.body ] + %vec.phi29 = phi <4 x i32> [ zeroinitializer, %entry ], [ %52, %vector.body ] + %vec.phi30 = phi <4 x i32> [ zeroinitializer, %entry ], [ %53, %vector.body ] + %wide.load32 = load <4 x i32>* null, align 4 + %.sum82 = add i64 %index, 24 + %0 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum82 + %1 = bitcast i32* %0 to <4 x i32>* + %wide.load36 = load <4 x i32>* %1, align 4 + %wide.load37 = load <4 x i32>* undef, align 4 + %.sum84 = add i64 %index, 32 + %2 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum84 + %3 = bitcast i32* %2 to <4 x i32>* + %wide.load38 = load <4 x i32>* %3, align 4 + %.sum85 = add i64 %index, 36 + %4 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum85 + %5 = bitcast i32* %4 to <4 x i32>* + %wide.load39 = load <4 x i32>* %5, align 4 + %6 = getelementptr [1024 x i32]* @ub, i64 0, i64 undef + %7 = bitcast i32* %6 to <4 x i32>* + %wide.load40 = load <4 x i32>* %7, align 4 + %.sum87 = add i64 %index, 44 + %8 = getelementptr [1024 x i32]* @ub, i64 0, i64 %.sum87 + %9 = bitcast i32* %8 to <4 x i32>* + %wide.load41 = load <4 x i32>* %9, align 4 + %10 = getelementptr inbounds [1024 x i32]* @uc, i64 0, i64 %index + %11 = bitcast i32* %10 to <4 x i32>* + %wide.load42 = load <4 x i32>* %11, align 4 + %.sum8889 = or i64 %index, 4 + %12 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum8889 + %13 = bitcast i32* %12 to <4 x i32>* + %wide.load43 = load <4 x i32>* %13, align 4 + %.sum9091 = or i64 %index, 8 + %14 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum9091 + %15 = bitcast i32* %14 to <4 x i32>* + %wide.load44 = load <4 x i32>* %15, align 4 + %.sum94 = add i64 %index, 16 + %16 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum94 + %17 = bitcast i32* %16 to <4 x i32>* + %wide.load46 = load <4 x i32>* %17, align 4 + %.sum95 = add i64 %index, 20 + %18 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum95 + %19 = bitcast i32* %18 to <4 x i32>* + %wide.load47 = load <4 x i32>* %19, align 4 + %20 = getelementptr [1024 x i32]* @uc, i64 0, i64 undef + %21 = bitcast i32* %20 to <4 x i32>* + %wide.load48 = load <4 x i32>* %21, align 4 + %.sum97 = add i64 %index, 28 + %22 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum97 + %23 = bitcast i32* %22 to <4 x i32>* + %wide.load49 = load <4 x i32>* %23, align 4 + %.sum98 = add i64 %index, 32 + %24 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum98 + %25 = bitcast i32* %24 to <4 x i32>* + %wide.load50 = load <4 x i32>* %25, align 4 + %.sum99 = add i64 %index, 36 + %26 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum99 + %27 = bitcast i32* %26 to <4 x i32>* + %wide.load51 = load <4 x i32>* %27, align 4 + %.sum100 = add i64 %index, 40 + %28 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum100 + %29 = bitcast i32* %28 to <4 x i32>* + %wide.load52 = load <4 x i32>* %29, align 4 + %.sum101 = add i64 %index, 44 + %30 = getelementptr [1024 x i32]* @uc, i64 0, i64 %.sum101 + %31 = bitcast i32* %30 to <4 x i32>* + %wide.load53 = load <4 x i32>* %31, align 4 + %32 = add <4 x i32> zeroinitializer, %vec.phi + %33 = add <4 x i32> zeroinitializer, %vec.phi20 + %34 = add <4 x i32> %wide.load32, %vec.phi21 + %35 = add <4 x i32> zeroinitializer, %vec.phi23 + %36 = add <4 x i32> zeroinitializer, %vec.phi24 + %37 = add <4 x i32> %wide.load36, %vec.phi25 + %38 = add <4 x i32> %wide.load37, %vec.phi26 + %39 = add <4 x i32> %wide.load38, %vec.phi27 + %40 = add <4 x i32> %wide.load39, %vec.phi28 + %41 = add <4 x i32> %wide.load40, %vec.phi29 + %42 = add <4 x i32> %wide.load41, %vec.phi30 + %43 = sub <4 x i32> %32, %wide.load42 + %44 = sub <4 x i32> %33, %wide.load43 + %45 = sub <4 x i32> %34, %wide.load44 + %46 = sub <4 x i32> %35, %wide.load46 + %47 = sub <4 x i32> %36, %wide.load47 + %48 = sub <4 x i32> %37, %wide.load48 + %49 = sub <4 x i32> %38, %wide.load49 + %50 = sub <4 x i32> %39, %wide.load50 + %51 = sub <4 x i32> %40, %wide.load51 + %52 = sub <4 x i32> %41, %wide.load52 + %53 = sub <4 x i32> %42, %wide.load53 + %index.next = add i64 %index, 48 + br i1 false, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body + %.lcssa112 = phi <4 x i32> [ %53, %vector.body ] + %.lcssa111 = phi <4 x i32> [ %52, %vector.body ] + %.lcssa110 = phi <4 x i32> [ %51, %vector.body ] + %.lcssa109 = phi <4 x i32> [ %50, %vector.body ] + %.lcssa108 = phi <4 x i32> [ %49, %vector.body ] + %.lcssa107 = phi <4 x i32> [ %48, %vector.body ] + %.lcssa106 = phi <4 x i32> [ %47, %vector.body ] + %.lcssa105 = phi <4 x i32> [ %46, %vector.body ] + %.lcssa103 = phi <4 x i32> [ %45, %vector.body ] + %.lcssa102 = phi <4 x i32> [ %44, %vector.body ] + %.lcssa = phi <4 x i32> [ %43, %vector.body ] + ret void +} + +attributes #0 = { noinline nounwind } + diff --git a/test/CodeGen/PowerPC/vsx-infl-copy2.ll b/test/CodeGen/PowerPC/vsx-infl-copy2.ll new file mode 100644 index 0000000..0f27906 --- /dev/null +++ b/test/CodeGen/PowerPC/vsx-infl-copy2.ll @@ -0,0 +1,114 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: nounwind +define void @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc(i32* nocapture readonly %first) #0 { +entry: + br i1 false, label %loop2_start, label %if.end5 + +; CHECK-LABEL: @_Z28test_goto_loop_unroll_factorILi22EiEvPKT0_iPKc + +loop2_start: ; preds = %loop2_start, %entry + br i1 undef, label %loop2_start, label %if.then.i31 + +if.end5: ; preds = %entry + br i1 undef, label %loop_start.preheader, label %if.then.i31 + +loop_start.preheader: ; preds = %if.end5 + br i1 false, label %middle.block, label %vector.body + +vector.body: ; preds = %vector.body, %loop_start.preheader + %vec.phi61 = phi <4 x i32> [ %34, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %vec.phi62 = phi <4 x i32> [ %35, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %vec.phi63 = phi <4 x i32> [ %36, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %vec.phi65 = phi <4 x i32> [ %37, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %vec.phi67 = phi <4 x i32> [ %38, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %vec.phi68 = phi <4 x i32> [ %39, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %vec.phi69 = phi <4 x i32> [ %40, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %vec.phi70 = phi <4 x i32> [ %41, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %vec.phi71 = phi <4 x i32> [ %42, %vector.body ], [ zeroinitializer, %loop_start.preheader ] + %.sum = add i64 0, 4 + %wide.load72 = load <4 x i32>* null, align 4 + %.sum109 = add i64 0, 8 + %0 = getelementptr i32* %first, i64 %.sum109 + %1 = bitcast i32* %0 to <4 x i32>* + %wide.load73 = load <4 x i32>* %1, align 4 + %.sum110 = add i64 0, 12 + %2 = getelementptr i32* %first, i64 %.sum110 + %3 = bitcast i32* %2 to <4 x i32>* + %wide.load74 = load <4 x i32>* %3, align 4 + %.sum112 = add i64 0, 20 + %4 = getelementptr i32* %first, i64 %.sum112 + %5 = bitcast i32* %4 to <4 x i32>* + %wide.load76 = load <4 x i32>* %5, align 4 + %.sum114 = add i64 0, 28 + %6 = getelementptr i32* %first, i64 %.sum114 + %7 = bitcast i32* %6 to <4 x i32>* + %wide.load78 = load <4 x i32>* %7, align 4 + %.sum115 = add i64 0, 32 + %8 = getelementptr i32* %first, i64 %.sum115 + %9 = bitcast i32* %8 to <4 x i32>* + %wide.load79 = load <4 x i32>* %9, align 4 + %.sum116 = add i64 0, 36 + %10 = getelementptr i32* %first, i64 %.sum116 + %11 = bitcast i32* %10 to <4 x i32>* + %wide.load80 = load <4 x i32>* %11, align 4 + %.sum117 = add i64 0, 40 + %12 = getelementptr i32* %first, i64 %.sum117 + %13 = bitcast i32* %12 to <4 x i32>* + %wide.load81 = load <4 x i32>* %13, align 4 + %.sum118 = add i64 0, 44 + %14 = getelementptr i32* %first, i64 %.sum118 + %15 = bitcast i32* %14 to <4 x i32>* + %wide.load82 = load <4 x i32>* %15, align 4 + %16 = mul <4 x i32> %wide.load72, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %17 = mul <4 x i32> %wide.load73, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %18 = mul <4 x i32> %wide.load74, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %19 = mul <4 x i32> %wide.load76, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %20 = mul <4 x i32> %wide.load78, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %21 = mul <4 x i32> %wide.load79, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %22 = mul <4 x i32> %wide.load80, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %23 = mul <4 x i32> %wide.load81, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %24 = mul <4 x i32> %wide.load82, <i32 269850533, i32 269850533, i32 269850533, i32 269850533> + %25 = add <4 x i32> %16, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %26 = add <4 x i32> %17, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %27 = add <4 x i32> %18, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %28 = add <4 x i32> %19, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %29 = add <4 x i32> %20, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %30 = add <4 x i32> %21, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %31 = add <4 x i32> %22, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %32 = add <4 x i32> %23, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %33 = add <4 x i32> %24, <i32 -1138325064, i32 -1138325064, i32 -1138325064, i32 -1138325064> + %34 = add nsw <4 x i32> %25, %vec.phi61 + %35 = add nsw <4 x i32> %26, %vec.phi62 + %36 = add nsw <4 x i32> %27, %vec.phi63 + %37 = add nsw <4 x i32> %28, %vec.phi65 + %38 = add nsw <4 x i32> %29, %vec.phi67 + %39 = add nsw <4 x i32> %30, %vec.phi68 + %40 = add nsw <4 x i32> %31, %vec.phi69 + %41 = add nsw <4 x i32> %32, %vec.phi70 + %42 = add nsw <4 x i32> %33, %vec.phi71 + br i1 false, label %middle.block, label %vector.body + +middle.block: ; preds = %vector.body, %loop_start.preheader + %rdx.vec.exit.phi85 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %34, %vector.body ] + %rdx.vec.exit.phi86 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %35, %vector.body ] + %rdx.vec.exit.phi87 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %36, %vector.body ] + %rdx.vec.exit.phi89 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %37, %vector.body ] + %rdx.vec.exit.phi91 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %38, %vector.body ] + %rdx.vec.exit.phi92 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %39, %vector.body ] + %rdx.vec.exit.phi93 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %40, %vector.body ] + %rdx.vec.exit.phi94 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %41, %vector.body ] + %rdx.vec.exit.phi95 = phi <4 x i32> [ zeroinitializer, %loop_start.preheader ], [ %42, %vector.body ] + br i1 false, label %if.then.i31, label %loop_start.prol + +loop_start.prol: ; preds = %loop_start.prol, %middle.block + br label %loop_start.prol + +if.then.i31: ; preds = %middle.block, %if.end5, %loop2_start + unreachable +} + +attributes #0 = { nounwind } + diff --git a/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll b/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll new file mode 100644 index 0000000..7367672 --- /dev/null +++ b/test/CodeGen/PowerPC/vsx-ldst-builtin-le.ll @@ -0,0 +1,172 @@ +; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t +; RUN: grep lxvd2x < %t | count 18 +; RUN: grep stxvd2x < %t | count 18 +; RUN: grep xxpermdi < %t | count 36 + +@vf = global <4 x float> <float -1.500000e+00, float 2.500000e+00, float -3.500000e+00, float 4.500000e+00>, align 16 +@vd = global <2 x double> <double 3.500000e+00, double -7.500000e+00>, align 16 +@vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16 +@vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 +@vsll = global <2 x i64> <i64 255, i64 -937>, align 16 +@vull = global <2 x i64> <i64 1447, i64 2894>, align 16 +@res_vsi = common global <4 x i32> zeroinitializer, align 16 +@res_vui = common global <4 x i32> zeroinitializer, align 16 +@res_vf = common global <4 x float> zeroinitializer, align 16 +@res_vsll = common global <2 x i64> zeroinitializer, align 16 +@res_vull = common global <2 x i64> zeroinitializer, align 16 +@res_vd = common global <2 x double> zeroinitializer, align 16 + +define void @test1() { +entry: +; CHECK-LABEL: test1 + %__a.addr.i31 = alloca i32, align 4 + %__b.addr.i32 = alloca <4 x i32>*, align 8 + %__a.addr.i29 = alloca i32, align 4 + %__b.addr.i30 = alloca <4 x float>*, align 8 + %__a.addr.i27 = alloca i32, align 4 + %__b.addr.i28 = alloca <2 x i64>*, align 8 + %__a.addr.i25 = alloca i32, align 4 + %__b.addr.i26 = alloca <2 x i64>*, align 8 + %__a.addr.i23 = alloca i32, align 4 + %__b.addr.i24 = alloca <2 x double>*, align 8 + %__a.addr.i20 = alloca <4 x i32>, align 16 + %__b.addr.i21 = alloca i32, align 4 + %__c.addr.i22 = alloca <4 x i32>*, align 8 + %__a.addr.i17 = alloca <4 x i32>, align 16 + %__b.addr.i18 = alloca i32, align 4 + %__c.addr.i19 = alloca <4 x i32>*, align 8 + %__a.addr.i14 = alloca <4 x float>, align 16 + %__b.addr.i15 = alloca i32, align 4 + %__c.addr.i16 = alloca <4 x float>*, align 8 + %__a.addr.i11 = alloca <2 x i64>, align 16 + %__b.addr.i12 = alloca i32, align 4 + %__c.addr.i13 = alloca <2 x i64>*, align 8 + %__a.addr.i8 = alloca <2 x i64>, align 16 + %__b.addr.i9 = alloca i32, align 4 + %__c.addr.i10 = alloca <2 x i64>*, align 8 + %__a.addr.i6 = alloca <2 x double>, align 16 + %__b.addr.i7 = alloca i32, align 4 + %__c.addr.i = alloca <2 x double>*, align 8 + %__a.addr.i = alloca i32, align 4 + %__b.addr.i = alloca <4 x i32>*, align 8 + store i32 0, i32* %__a.addr.i, align 4 + store <4 x i32>* @vsi, <4 x i32>** %__b.addr.i, align 8 + %0 = load i32* %__a.addr.i, align 4 + %1 = load <4 x i32>** %__b.addr.i, align 8 + %2 = bitcast <4 x i32>* %1 to i8* + %3 = getelementptr i8* %2, i32 %0 + %4 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %3) + store <4 x i32> %4, <4 x i32>* @res_vsi, align 16 + store i32 0, i32* %__a.addr.i31, align 4 + store <4 x i32>* @vui, <4 x i32>** %__b.addr.i32, align 8 + %5 = load i32* %__a.addr.i31, align 4 + %6 = load <4 x i32>** %__b.addr.i32, align 8 + %7 = bitcast <4 x i32>* %6 to i8* + %8 = getelementptr i8* %7, i32 %5 + %9 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %8) + store <4 x i32> %9, <4 x i32>* @res_vui, align 16 + store i32 0, i32* %__a.addr.i29, align 4 + store <4 x float>* @vf, <4 x float>** %__b.addr.i30, align 8 + %10 = load i32* %__a.addr.i29, align 4 + %11 = load <4 x float>** %__b.addr.i30, align 8 + %12 = bitcast <4 x float>* %11 to i8* + %13 = getelementptr i8* %12, i32 %10 + %14 = call <4 x i32> @llvm.ppc.vsx.lxvw4x(i8* %13) + %15 = bitcast <4 x i32> %14 to <4 x float> + store <4 x float> %15, <4 x float>* @res_vf, align 16 + store i32 0, i32* %__a.addr.i27, align 4 + store <2 x i64>* @vsll, <2 x i64>** %__b.addr.i28, align 8 + %16 = load i32* %__a.addr.i27, align 4 + %17 = load <2 x i64>** %__b.addr.i28, align 8 + %18 = bitcast <2 x i64>* %17 to i8* + %19 = getelementptr i8* %18, i32 %16 + %20 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %19) + %21 = bitcast <2 x double> %20 to <2 x i64> + store <2 x i64> %21, <2 x i64>* @res_vsll, align 16 + store i32 0, i32* %__a.addr.i25, align 4 + store <2 x i64>* @vull, <2 x i64>** %__b.addr.i26, align 8 + %22 = load i32* %__a.addr.i25, align 4 + %23 = load <2 x i64>** %__b.addr.i26, align 8 + %24 = bitcast <2 x i64>* %23 to i8* + %25 = getelementptr i8* %24, i32 %22 + %26 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %25) + %27 = bitcast <2 x double> %26 to <2 x i64> + store <2 x i64> %27, <2 x i64>* @res_vull, align 16 + store i32 0, i32* %__a.addr.i23, align 4 + store <2 x double>* @vd, <2 x double>** %__b.addr.i24, align 8 + %28 = load i32* %__a.addr.i23, align 4 + %29 = load <2 x double>** %__b.addr.i24, align 8 + %30 = bitcast <2 x double>* %29 to i8* + %31 = getelementptr i8* %30, i32 %28 + %32 = call <2 x double> @llvm.ppc.vsx.lxvd2x(i8* %31) + store <2 x double> %32, <2 x double>* @res_vd, align 16 + %33 = load <4 x i32>* @vsi, align 16 + store <4 x i32> %33, <4 x i32>* %__a.addr.i20, align 16 + store i32 0, i32* %__b.addr.i21, align 4 + store <4 x i32>* @res_vsi, <4 x i32>** %__c.addr.i22, align 8 + %34 = load <4 x i32>* %__a.addr.i20, align 16 + %35 = load i32* %__b.addr.i21, align 4 + %36 = load <4 x i32>** %__c.addr.i22, align 8 + %37 = bitcast <4 x i32>* %36 to i8* + %38 = getelementptr i8* %37, i32 %35 + call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %34, i8* %38) + %39 = load <4 x i32>* @vui, align 16 + store <4 x i32> %39, <4 x i32>* %__a.addr.i17, align 16 + store i32 0, i32* %__b.addr.i18, align 4 + store <4 x i32>* @res_vui, <4 x i32>** %__c.addr.i19, align 8 + %40 = load <4 x i32>* %__a.addr.i17, align 16 + %41 = load i32* %__b.addr.i18, align 4 + %42 = load <4 x i32>** %__c.addr.i19, align 8 + %43 = bitcast <4 x i32>* %42 to i8* + %44 = getelementptr i8* %43, i32 %41 + call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %40, i8* %44) + %45 = load <4 x float>* @vf, align 16 + store <4 x float> %45, <4 x float>* %__a.addr.i14, align 16 + store i32 0, i32* %__b.addr.i15, align 4 + store <4 x float>* @res_vf, <4 x float>** %__c.addr.i16, align 8 + %46 = load <4 x float>* %__a.addr.i14, align 16 + %47 = bitcast <4 x float> %46 to <4 x i32> + %48 = load i32* %__b.addr.i15, align 4 + %49 = load <4 x float>** %__c.addr.i16, align 8 + %50 = bitcast <4 x float>* %49 to i8* + %51 = getelementptr i8* %50, i32 %48 + call void @llvm.ppc.vsx.stxvw4x(<4 x i32> %47, i8* %51) #1 + %52 = load <2 x i64>* @vsll, align 16 + store <2 x i64> %52, <2 x i64>* %__a.addr.i11, align 16 + store i32 0, i32* %__b.addr.i12, align 4 + store <2 x i64>* @res_vsll, <2 x i64>** %__c.addr.i13, align 8 + %53 = load <2 x i64>* %__a.addr.i11, align 16 + %54 = bitcast <2 x i64> %53 to <2 x double> + %55 = load i32* %__b.addr.i12, align 4 + %56 = load <2 x i64>** %__c.addr.i13, align 8 + %57 = bitcast <2 x i64>* %56 to i8* + %58 = getelementptr i8* %57, i32 %55 + call void @llvm.ppc.vsx.stxvd2x(<2 x double> %54, i8* %58) + %59 = load <2 x i64>* @vull, align 16 + store <2 x i64> %59, <2 x i64>* %__a.addr.i8, align 16 + store i32 0, i32* %__b.addr.i9, align 4 + store <2 x i64>* @res_vull, <2 x i64>** %__c.addr.i10, align 8 + %60 = load <2 x i64>* %__a.addr.i8, align 16 + %61 = bitcast <2 x i64> %60 to <2 x double> + %62 = load i32* %__b.addr.i9, align 4 + %63 = load <2 x i64>** %__c.addr.i10, align 8 + %64 = bitcast <2 x i64>* %63 to i8* + %65 = getelementptr i8* %64, i32 %62 + call void @llvm.ppc.vsx.stxvd2x(<2 x double> %61, i8* %65) + %66 = load <2 x double>* @vd, align 16 + store <2 x double> %66, <2 x double>* %__a.addr.i6, align 16 + store i32 0, i32* %__b.addr.i7, align 4 + store <2 x double>* @res_vd, <2 x double>** %__c.addr.i, align 8 + %67 = load <2 x double>* %__a.addr.i6, align 16 + %68 = load i32* %__b.addr.i7, align 4 + %69 = load <2 x double>** %__c.addr.i, align 8 + %70 = bitcast <2 x double>* %69 to i8* + %71 = getelementptr i8* %70, i32 %68 + call void @llvm.ppc.vsx.stxvd2x(<2 x double> %67, i8* %71) + ret void +} + +declare void @llvm.ppc.vsx.stxvd2x(<2 x double>, i8*) +declare void @llvm.ppc.vsx.stxvw4x(<4 x i32>, i8*) +declare <2 x double> @llvm.ppc.vsx.lxvd2x(i8*) +declare <4 x i32> @llvm.ppc.vsx.lxvw4x(i8*) diff --git a/test/CodeGen/PowerPC/vsx-ldst.ll b/test/CodeGen/PowerPC/vsx-ldst.ll index 0c9ebef..688187d 100644 --- a/test/CodeGen/PowerPC/vsx-ldst.ll +++ b/test/CodeGen/PowerPC/vsx-ldst.ll @@ -3,6 +3,16 @@ ; RUN: grep lxvd2x < %t | count 3 ; RUN: grep stxvw4x < %t | count 3 ; RUN: grep stxvd2x < %t | count 3 +; RUN: llc -mcpu=pwr8 -mattr=+vsx -O0 -fast-isel=1 -mtriple=powerpc64-unknown-linux-gnu < %s > %t +; RUN: grep lxvw4x < %t | count 3 +; RUN: grep lxvd2x < %t | count 3 +; RUN: grep stxvw4x < %t | count 3 +; RUN: grep stxvd2x < %t | count 3 + +; RUN: llc -mcpu=pwr8 -mattr=+vsx -O2 -mtriple=powerpc64le-unknown-linux-gnu < %s > %t +; RUN: grep lxvd2x < %t | count 6 +; RUN: grep stxvd2x < %t | count 6 +; RUN: grep xxpermdi < %t | count 12 @vsi = global <4 x i32> <i32 -1, i32 2, i32 -3, i32 4>, align 16 @vui = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16 diff --git a/test/CodeGen/PowerPC/vsx-p8.ll b/test/CodeGen/PowerPC/vsx-p8.ll index 81406b6..d5a1905 100644 --- a/test/CodeGen/PowerPC/vsx-p8.ll +++ b/test/CodeGen/PowerPC/vsx-p8.ll @@ -1,4 +1,7 @@ ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s +; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -26,17 +29,27 @@ define <4 x float> @test32u(<4 x float>* %a) { %v = load <4 x float>* %a, align 8 ret <4 x float> %v -; CHECK-LABEL: @test32u -; CHECK: lxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test32u +; CHECK-REG: lxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test32u +; CHECK-FISL: lxvw4x 0, 0, 3 +; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: blr } define void @test33u(<4 x float>* %a, <4 x float> %b) { store <4 x float> %b, <4 x float>* %a, align 8 ret void -; CHECK-LABEL: @test33u -; CHECK: stxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test33u +; CHECK-REG: stxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test33u +; CHECK-FISL: vor 3, 2, 2 +; CHECK-FISL: stxvw4x 35, 0, 3 +; CHECK-FISL: blr } diff --git a/test/CodeGen/PowerPC/vsx-self-copy.ll b/test/CodeGen/PowerPC/vsx-self-copy.ll index 23615ca..787ac4b 100644 --- a/test/CodeGen/PowerPC/vsx-self-copy.ll +++ b/test/CodeGen/PowerPC/vsx-self-copy.ll @@ -1,4 +1,5 @@ ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" diff --git a/test/CodeGen/PowerPC/vsx-spill-norwstore.ll b/test/CodeGen/PowerPC/vsx-spill-norwstore.ll new file mode 100644 index 0000000..a3c4aa5 --- /dev/null +++ b/test/CodeGen/PowerPC/vsx-spill-norwstore.ll @@ -0,0 +1,63 @@ +; RUN: llc -mcpu=pwr7 -verify-machineinstrs < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +@.str1 = external unnamed_addr constant [5 x i8], align 1 +@.str10 = external unnamed_addr constant [9 x i8], align 1 + +; Function Attrs: nounwind +define void @main() #0 { +; CHECK-LABEL: @main +; Make sure that the stxvd2x passes -verify-machineinstrs +; CHECK: stxvd2x + +entry: + %0 = tail call <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0 + %1 = tail call <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8> <i8 0, i8 -1, i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 -1, i8 0, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1>) #0 + br i1 false, label %if.then.i68.i, label %check.exit69.i + +if.then.i68.i: ; preds = %entry + unreachable + +check.exit69.i: ; preds = %entry + br i1 undef, label %if.then.i63.i, label %check.exit64.i + +if.then.i63.i: ; preds = %check.exit69.i + tail call void (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str10, i64 0, i64 0), i8* getelementptr inbounds ([5 x i8]* @.str1, i64 0, i64 0)) #0 + br label %check.exit64.i + +check.exit64.i: ; preds = %if.then.i63.i, %check.exit69.i + %2 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %0, <8 x i16> <i16 0, i16 -1, i16 -1, i16 0, i16 0, i16 0, i16 -1, i16 0>) #0 + %tobool.i55.i = icmp eq i32 %2, 0 + br i1 %tobool.i55.i, label %if.then.i58.i, label %check.exit59.i + +if.then.i58.i: ; preds = %check.exit64.i + unreachable + +check.exit59.i: ; preds = %check.exit64.i + %3 = tail call i32 @llvm.ppc.altivec.vcmpequh.p(i32 2, <8 x i16> %1, <8 x i16> <i16 -1, i16 0, i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1>) #0 + %tobool.i50.i = icmp eq i32 %3, 0 + br i1 %tobool.i50.i, label %if.then.i53.i, label %check.exit54.i + +if.then.i53.i: ; preds = %check.exit59.i + unreachable + +check.exit54.i: ; preds = %check.exit59.i + unreachable +} + +; Function Attrs: nounwind readnone +declare <8 x i16> @llvm.ppc.altivec.vupkhsb(<16 x i8>) #1 + +; Function Attrs: nounwind readnone +declare <8 x i16> @llvm.ppc.altivec.vupklsb(<16 x i8>) #1 + +; Function Attrs: nounwind +declare void @printf(i8* nocapture readonly, ...) #0 + +; Function Attrs: nounwind readnone +declare i32 @llvm.ppc.altivec.vcmpequh.p(i32, <8 x i16>, <8 x i16>) #1 + +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } + diff --git a/test/CodeGen/PowerPC/vsx-spill.ll b/test/CodeGen/PowerPC/vsx-spill.ll index 29bc6fc..032bcf6 100644 --- a/test/CodeGen/PowerPC/vsx-spill.ll +++ b/test/CodeGen/PowerPC/vsx-spill.ll @@ -1,4 +1,7 @@ ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -7,10 +10,16 @@ entry: call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind br label %return -; CHECK: @foo1 -; CHECK: xxlor [[R1:[0-9]+]], 1, 1 -; CHECK: xxlor 1, [[R1]], [[R1]] -; CHECK: blr +; CHECK-REG: @foo1 +; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1 +; CHECK-REG: xxlor 1, [[R1]], [[R1]] +; CHECK-REG: blr + +; CHECK-FISL: @foo1 +; CHECK-FISL: lis 0, -1 +; CHECK-FISL: ori 0, 0, 65384 +; CHECK-FISL: stxsdx 1, 1, 0 +; CHECK-FISL: blr return: ; preds = %entry ret double %a @@ -22,10 +31,16 @@ entry: call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind br label %return -; CHECK: @foo2 -; CHECK: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1 -; CHECK: {{xxlor|xsadddp}} 1, [[R1]], [[R1]] -; CHECK: blr +; CHECK-REG: @foo2 +; CHECK-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1 +; CHECK-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]] +; CHECK-REG: blr + +; CHECK-FISL: @foo2 +; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1 +; CHECK-FISL: stxsdx [[R1]], [[R1]], 0 +; CHECK-FISL: lxsdx [[R1]], [[R1]], 0 +; CHECK-FISL: blr return: ; preds = %entry ret double %b diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll index 333b75a..f91ffdb 100644 --- a/test/CodeGen/PowerPC/vsx.ll +++ b/test/CodeGen/PowerPC/vsx.ll @@ -1,4 +1,7 @@ ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -47,9 +50,16 @@ entry: %v = xor <4 x i32> %a, %b ret <4 x i32> %v -; CHECK-LABEL: @test5 -; CHECK: xxlxor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test5 +; CHECK-REG: xxlxor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test5 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlxor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) { @@ -57,9 +67,16 @@ entry: %v = xor <8 x i16> %a, %b ret <8 x i16> %v -; CHECK-LABEL: @test6 -; CHECK: xxlxor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test6 +; CHECK-REG: xxlxor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test6 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlxor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <16 x i8> @test7(<16 x i8> %a, <16 x i8> %b) { @@ -67,9 +84,16 @@ entry: %v = xor <16 x i8> %a, %b ret <16 x i8> %v -; CHECK-LABEL: @test7 -; CHECK: xxlxor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test7 +; CHECK-REG: xxlxor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test7 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlxor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <4 x i32> @test8(<4 x i32> %a, <4 x i32> %b) { @@ -77,9 +101,16 @@ entry: %v = or <4 x i32> %a, %b ret <4 x i32> %v -; CHECK-LABEL: @test8 -; CHECK: xxlor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test8 +; CHECK-REG: xxlor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test8 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) { @@ -87,9 +118,16 @@ entry: %v = or <8 x i16> %a, %b ret <8 x i16> %v -; CHECK-LABEL: @test9 -; CHECK: xxlor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test9 +; CHECK-REG: xxlor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test9 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <16 x i8> @test10(<16 x i8> %a, <16 x i8> %b) { @@ -97,9 +135,16 @@ entry: %v = or <16 x i8> %a, %b ret <16 x i8> %v -; CHECK-LABEL: @test10 -; CHECK: xxlor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test10 +; CHECK-REG: xxlor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test10 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) { @@ -107,9 +152,16 @@ entry: %v = and <4 x i32> %a, %b ret <4 x i32> %v -; CHECK-LABEL: @test11 -; CHECK: xxland 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test11 +; CHECK-REG: xxland 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test11 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxland 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) { @@ -117,9 +169,16 @@ entry: %v = and <8 x i16> %a, %b ret <8 x i16> %v -; CHECK-LABEL: @test12 -; CHECK: xxland 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test12 +; CHECK-REG: xxland 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test12 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxland 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <16 x i8> @test13(<16 x i8> %a, <16 x i8> %b) { @@ -127,9 +186,16 @@ entry: %v = and <16 x i8> %a, %b ret <16 x i8> %v -; CHECK-LABEL: @test13 -; CHECK: xxland 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test13 +; CHECK-REG: xxland 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test13 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxland 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <4 x i32> @test14(<4 x i32> %a, <4 x i32> %b) { @@ -138,9 +204,23 @@ entry: %w = xor <4 x i32> %v, <i32 -1, i32 -1, i32 -1, i32 -1> ret <4 x i32> %w -; CHECK-LABEL: @test14 -; CHECK: xxlnor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test14 +; CHECK-REG: xxlnor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test14 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlor 36, 36, 37 +; CHECK-FISL: vor 0, 4, 4 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlnor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: lis 0, -1 +; CHECK-FISL: ori 0, 0, 65520 +; CHECK-FISL: stvx 0, 1, 0 +; CHECK-FISL: blr } define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) { @@ -149,9 +229,23 @@ entry: %w = xor <8 x i16> %v, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> ret <8 x i16> %w -; CHECK-LABEL: @test15 -; CHECK: xxlnor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test15 +; CHECK-REG: xxlnor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test15 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlor 36, 36, 37 +; CHECK-FISL: vor 0, 4, 4 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlnor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: lis 0, -1 +; CHECK-FISL: ori 0, 0, 65520 +; CHECK-FISL: stvx 0, 1, 0 +; CHECK-FISL: blr } define <16 x i8> @test16(<16 x i8> %a, <16 x i8> %b) { @@ -160,9 +254,23 @@ entry: %w = xor <16 x i8> %v, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> ret <16 x i8> %w -; CHECK-LABEL: @test16 -; CHECK: xxlnor 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test16 +; CHECK-REG: xxlnor 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test16 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlor 36, 36, 37 +; CHECK-FISL: vor 0, 4, 4 +; CHECK-FISL: vor 4, 2, 2 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: xxlnor 36, 36, 37 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: lis 0, -1 +; CHECK-FISL: ori 0, 0, 65520 +; CHECK-FISL: stvx 0, 1, 0 +; CHECK-FISL: blr } define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) { @@ -171,9 +279,21 @@ entry: %v = and <4 x i32> %a, %w ret <4 x i32> %v -; CHECK-LABEL: @test17 -; CHECK: xxlandc 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test17 +; CHECK-REG: xxlandc 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test17 +; CHECK-FISL: vspltisb 4, -1 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: vor 0, 4, 4 +; CHECK-FISL: xxlxor 37, 37, 32 +; CHECK-FISL: vor 3, 5, 5 +; CHECK-FISL: vor 5, 2, 2 +; CHECK-FISL: vor 0, 3, 3 +; CHECK-FISL: xxland 37, 37, 32 +; CHECK-FISL: vor 2, 5, 5 +; CHECK-FISL: blr } define <8 x i16> @test18(<8 x i16> %a, <8 x i16> %b) { @@ -182,9 +302,24 @@ entry: %v = and <8 x i16> %a, %w ret <8 x i16> %v -; CHECK-LABEL: @test18 -; CHECK: xxlandc 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test18 +; CHECK-REG: xxlandc 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test18 +; CHECK-FISL: vspltisb 4, -1 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: vor 0, 4, 4 +; CHECK-FISL: xxlxor 37, 37, 32 +; CHECK-FISL: vor 4, 5, 5 +; CHECK-FISL: vor 5, 2, 2 +; CHECK-FISL: vor 0, 3, 3 +; CHECK-FISL: xxlandc 37, 37, 32 +; CHECK-FISL: vor 2, 5, 5 +; CHECK-FISL: lis 0, -1 +; CHECK-FISL: ori 0, 0, 65520 +; CHECK-FISL: stvx 4, 1, 0 +; CHECK-FISL: blr } define <16 x i8> @test19(<16 x i8> %a, <16 x i8> %b) { @@ -193,9 +328,24 @@ entry: %v = and <16 x i8> %a, %w ret <16 x i8> %v -; CHECK-LABEL: @test19 -; CHECK: xxlandc 34, 34, 35 -; CHECK: blr +; CHECK-REG-LABEL: @test19 +; CHECK-REG: xxlandc 34, 34, 35 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test19 +; CHECK-FISL: vspltisb 4, -1 +; CHECK-FISL: vor 5, 3, 3 +; CHECK-FISL: vor 0, 4, 4 +; CHECK-FISL: xxlxor 37, 37, 32 +; CHECK-FISL: vor 4, 5, 5 +; CHECK-FISL: vor 5, 2, 2 +; CHECK-FISL: vor 0, 3, 3 +; CHECK-FISL: xxlandc 37, 37, 32 +; CHECK-FISL: vor 2, 5, 5 +; CHECK-FISL: lis 0, -1 +; CHECK-FISL: ori 0, 0, 65520 +; CHECK-FISL: stvx 4, 1, 0 +; CHECK-FISL: blr } define <4 x i32> @test20(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { @@ -204,10 +354,19 @@ entry: %v = select <4 x i1> %m, <4 x i32> %a, <4 x i32> %b ret <4 x i32> %v -; CHECK-LABEL: @test20 -; CHECK: vcmpequw {{[0-9]+}}, 4, 5 -; CHECK: xxsel 34, 35, 34, {{[0-9]+}} -; CHECK: blr +; CHECK-REG-LABEL: @test20 +; CHECK-REG: vcmpequw {{[0-9]+}}, 4, 5 +; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test20 +; CHECK-FISL: vcmpequw 4, 4, 5 +; CHECK-FISL: vor 0, 3, 3 +; CHECK-FISL: vor 1, 2, 2 +; CHECK-FISL: vor 6, 4, 4 +; CHECK-FISL: xxsel 32, 32, 33, 38 +; CHECK-FISL: vor 2, 0, 0 +; CHECK-FISL: blr } define <4 x float> @test21(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { @@ -216,10 +375,20 @@ entry: %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b ret <4 x float> %v -; CHECK-LABEL: @test21 -; CHECK: xvcmpeqsp [[V1:[0-9]+]], 36, 37 -; CHECK: xxsel 34, 35, 34, [[V1]] -; CHECK: blr +; CHECK-REG-LABEL: @test21 +; CHECK-REG: xvcmpeqsp [[V1:[0-9]+]], 36, 37 +; CHECK-REG: xxsel 34, 35, 34, [[V1]] +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test21 +; CHECK-FISL: vor 0, 5, 5 +; CHECK-FISL: vor 1, 4, 4 +; CHECK-FISL: vor 6, 3, 3 +; CHECK-FISL: vor 7, 2, 2 +; CHECK-FISL: xvcmpeqsp 32, 33, 32 +; CHECK-FISL: xxsel 32, 38, 39, 32 +; CHECK-FISL: vor 2, 0, 0 +; CHECK-FISL: blr } define <4 x float> @test22(<4 x float> %a, <4 x float> %b, <4 x float> %c, <4 x float> %d) { @@ -228,16 +397,27 @@ entry: %v = select <4 x i1> %m, <4 x float> %a, <4 x float> %b ret <4 x float> %v -; CHECK-LABEL: @test22 -; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 -; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 -; CHECK-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 -; CHECK-DAG: xxlnor -; CHECK-DAG: xxlnor -; CHECK-DAG: xxlor -; CHECK-DAG: xxlor -; CHECK: xxsel 34, 35, 34, {{[0-9]+}} -; CHECK: blr +; CHECK-REG-LABEL: @test22 +; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 37, 37 +; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 36 +; CHECK-REG-DAG: xvcmpeqsp {{[0-9]+}}, 36, 37 +; CHECK-REG-DAG: xxlnor +; CHECK-REG-DAG: xxlnor +; CHECK-REG-DAG: xxlor +; CHECK-REG-DAG: xxlor +; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test22 +; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 32 +; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 32, 32 +; CHECK-FISL-DAG: xvcmpeqsp {{[0-9]+}}, 33, 33 +; CHECK-FISL-DAG: xxlnor +; CHECK-FISL-DAG: xxlnor +; CHECK-FISL-DAG: xxlor +; CHECK-FISL-DAG: xxlor +; CHECK-FISL: xxsel 0, 38, 39, {{[0-9]+}} +; CHECK-FISL: blr } define <8 x i16> @test23(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c, <8 x i16> %d) { @@ -246,10 +426,19 @@ entry: %v = select <8 x i1> %m, <8 x i16> %a, <8 x i16> %b ret <8 x i16> %v -; CHECK-LABEL: @test23 -; CHECK: vcmpequh {{[0-9]+}}, 4, 5 -; CHECK: xxsel 34, 35, 34, {{[0-9]+}} -; CHECK: blr +; CHECK-REG-LABEL: @test23 +; CHECK-REG: vcmpequh {{[0-9]+}}, 4, 5 +; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test23 +; CHECK-FISL: vcmpequh 4, 4, 5 +; CHECK-FISL: vor 0, 3, 3 +; CHECK-FISL: vor 1, 2, 2 +; CHECK-FISL: vor 6, 4, 4 +; CHECK-FISL: xxsel 32, 32, 33, 38 +; CHECK-FISL: vor 2, 0, +; CHECK-FISL: blr } define <16 x i8> @test24(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, <16 x i8> %d) { @@ -258,10 +447,19 @@ entry: %v = select <16 x i1> %m, <16 x i8> %a, <16 x i8> %b ret <16 x i8> %v -; CHECK-LABEL: @test24 -; CHECK: vcmpequb {{[0-9]+}}, 4, 5 -; CHECK: xxsel 34, 35, 34, {{[0-9]+}} -; CHECK: blr +; CHECK-REG-LABEL: @test24 +; CHECK-REG: vcmpequb {{[0-9]+}}, 4, 5 +; CHECK-REG: xxsel 34, 35, 34, {{[0-9]+}} +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test24 +; CHECK-FISL: vcmpequb 4, 4, 5 +; CHECK-FISL: vor 0, 3, 3 +; CHECK-FISL: vor 1, 2, 2 +; CHECK-FISL: vor 6, 4, 4 +; CHECK-FISL: xxsel 32, 32, 33, 38 +; CHECK-FISL: vor 2, 0, 0 +; CHECK-FISL: blr } define <2 x double> @test25(<2 x double> %a, <2 x double> %b, <2 x double> %c, <2 x double> %d) { @@ -342,9 +540,16 @@ define <2 x i64> @test30(<2 x i64>* %a) { %v = load <2 x i64>* %a, align 16 ret <2 x i64> %v -; CHECK-LABEL: @test30 -; CHECK: lxvd2x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test30 +; CHECK-REG: lxvd2x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test30 +; CHECK-FISL: lxvd2x 0, 0, 3 +; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: vor 3, 2, 2 +; CHECK-FISL: vor 2, 3, 3 +; CHECK-FISL: blr } define void @test31(<2 x i64>* %a, <2 x i64> %b) { @@ -360,18 +565,28 @@ define <4 x float> @test32(<4 x float>* %a) { %v = load <4 x float>* %a, align 16 ret <4 x float> %v -; CHECK-LABEL: @test32 -; CHECK: lxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test32 +; CHECK-REG: lxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test32 +; CHECK-FISL: lxvw4x 0, 0, 3 +; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: blr } define void @test33(<4 x float>* %a, <4 x float> %b) { store <4 x float> %b, <4 x float>* %a, align 16 ret void -; CHECK-LABEL: @test33 -; CHECK: stxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test33 +; CHECK-REG: stxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test33 +; CHECK-FISL: vor 3, 2, 2 +; CHECK-FISL: stxvw4x 35, 0, 3 +; CHECK-FISL: blr } define <4 x float> @test32u(<4 x float>* %a) { @@ -390,27 +605,44 @@ define void @test33u(<4 x float>* %a, <4 x float> %b) { store <4 x float> %b, <4 x float>* %a, align 8 ret void -; CHECK-LABEL: @test33u -; CHECK: stxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test33u +; CHECK-REG: stxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test33u +; CHECK-FISL: vor 3, 2, 2 +; CHECK-FISL: stxvw4x 35, 0, 3 +; CHECK-FISL: blr } define <4 x i32> @test34(<4 x i32>* %a) { %v = load <4 x i32>* %a, align 16 ret <4 x i32> %v -; CHECK-LABEL: @test34 -; CHECK: lxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test34 +; CHECK-REG: lxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test34 +; CHECK-FISL: lxvw4x 0, 0, 3 +; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: vor 3, 2, 2 +; CHECK-FISL: vor 2, 3, 3 +; CHECK-FISL: blr } define void @test35(<4 x i32>* %a, <4 x i32> %b) { store <4 x i32> %b, <4 x i32>* %a, align 16 ret void -; CHECK-LABEL: @test35 -; CHECK: stxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test35 +; CHECK-REG: stxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test35 +; CHECK-FISL: vor 3, 2, 2 +; CHECK-FISL: stxvw4x 35, 0, 3 +; CHECK-FISL: blr } define <2 x double> @test40(<2 x i64> %a) { @@ -596,37 +828,60 @@ define double @test63(<2 x double> %a) { %v = extractelement <2 x double> %a, i32 0 ret double %v -; CHECK-LABEL: @test63 -; CHECK: xxlor 1, 34, 34 -; CHECK: blr +; CHECK-REG-LABEL: @test63 +; CHECK-REG: xxlor 1, 34, 34 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test63 +; CHECK-FISL: xxlor 0, 34, 34 +; CHECK-FISL: fmr 1, 0 +; CHECK-FISL: blr } define double @test64(<2 x double> %a) { %v = extractelement <2 x double> %a, i32 1 ret double %v -; CHECK-LABEL: @test64 -; CHECK: xxpermdi 1, 34, 34, 2 -; CHECK: blr +; CHECK-REG-LABEL: @test64 +; CHECK-REG: xxpermdi 1, 34, 34, 2 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test64 +; CHECK-FISL: xxpermdi 34, 34, 34, 2 +; CHECK-FISL: xxlor 0, 34, 34 +; CHECK-FISL: fmr 1, 0 +; CHECK-FISL: blr } define <2 x i1> @test65(<2 x i64> %a, <2 x i64> %b) { %w = icmp eq <2 x i64> %a, %b ret <2 x i1> %w -; CHECK-LABEL: @test65 -; CHECK: vcmpequw 2, 2, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test65 +; CHECK-REG: vcmpequw 2, 2, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test65 +; CHECK-FISL: vor 4, 3, 3 +; CHECK-FISL: vor 5, 2, 2 +; CHECK-FISL: vcmpequw 4, 5, 4 +; CHECK-FISL: vor 2, 4, 4 +; CHECK-FISL: blr } define <2 x i1> @test66(<2 x i64> %a, <2 x i64> %b) { %w = icmp ne <2 x i64> %a, %b ret <2 x i1> %w -; CHECK-LABEL: @test66 -; CHECK: vcmpequw {{[0-9]+}}, 2, 3 -; CHECK: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} -; CHECK: blr +; CHECK-REG-LABEL: @test66 +; CHECK-REG: vcmpequw {{[0-9]+}}, 2, 3 +; CHECK-REG: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test66 +; CHECK-FISL: vcmpequw {{[0-9]+}}, 5, 4 +; CHECK-FISL: xxlnor 34, {{[0-9]+}}, {{[0-9]+}} +; CHECK-FISL: blr } define <2 x i1> @test67(<2 x i64> %a, <2 x i64> %b) { @@ -660,7 +915,7 @@ define <2 x double> @test69(<2 x i16> %a) { ; CHECK-LABEL: @test69 ; CHECK: vspltisw [[V1:[0-9]+]], 8 ; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]] -; CHECK: vslw [[V3:[0-9]+]], 2, [[V2]] +; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]] ; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]] ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 ; CHECK: xvcvsxwdp 34, [[V4]] @@ -674,7 +929,7 @@ define <2 x double> @test70(<2 x i8> %a) { ; CHECK-LABEL: @test70 ; CHECK: vspltisw [[V1:[0-9]+]], 12 ; CHECK: vadduwm [[V2:[0-9]+]], [[V1]], [[V1]] -; CHECK: vslw [[V3:[0-9]+]], 2, [[V2]] +; CHECK: vslw [[V3:[0-9]+]], {{[0-9]+}}, [[V2]] ; CHECK: vsraw {{[0-9]+}}, [[V3]], [[V2]] ; CHECK: xxsldwi [[V4:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, 1 ; CHECK: xvcvsxwdp 34, [[V4]] @@ -687,15 +942,24 @@ define <2 x i32> @test80(i32 %v) { %i = add <2 x i32> %b2, <i32 2, i32 3> ret <2 x i32> %i -; CHECK-LABEL: @test80 -; CHECK-DAG: addi [[R1:[0-9]+]], 3, 3 -; CHECK-DAG: addi [[R2:[0-9]+]], 1, -16 -; CHECK-DAG: addi [[R3:[0-9]+]], 3, 2 -; CHECK: std [[R1]], -8(1) -; CHECK: std [[R3]], -16(1) -; CHECK: lxvd2x 34, 0, [[R2]] -; CHECK-NOT: stxvd2x -; CHECK: blr +; CHECK-REG-LABEL: @test80 +; CHECK-REG-DAG: addi [[R1:[0-9]+]], 3, 3 +; CHECK-REG-DAG: addi [[R2:[0-9]+]], 1, -16 +; CHECK-REG-DAG: addi [[R3:[0-9]+]], 3, 2 +; CHECK-REG: std [[R1]], -8(1) +; CHECK-REG: std [[R3]], -16(1) +; CHECK-REG: lxvd2x 34, 0, [[R2]] +; CHECK-REG-NOT: stxvd2x +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test80 +; CHECK-FISL-DAG: addi [[R1:[0-9]+]], 3, 3 +; CHECK-FISL-DAG: addi [[R2:[0-9]+]], 1, -16 +; CHECK-FISL-DAG: addi [[R3:[0-9]+]], 3, 2 +; CHECK-FISL-DAG: std [[R1]], -8(1) +; CHECK-FISL-DAG: std [[R3]], -16(1) +; CHECK-FISL-DAG: lxvd2x 0, 0, [[R2]] +; CHECK-FISL: blr } define <2 x double> @test81(<4 x float> %b) { @@ -712,8 +976,11 @@ entry: %v = select i1 %m, double %a, double %b ret double %v -; CHECK-LABEL: @test82 -; CHECK: xscmpudp [[REG:[0-9]+]], 3, 4 -; CHECK: beqlr [[REG]] -} +; CHECK-REG-LABEL: @test82 +; CHECK-REG: xscmpudp [[REG:[0-9]+]], 3, 4 +; CHECK-REG: beqlr [[REG]] +; CHECK-FISL-LABEL: @test82 +; CHECK-FISL: xscmpudp [[REG:[0-9]+]], 3, 4 +; CHECK-FISL: beq [[REG]], {{.*}} +} diff --git a/test/CodeGen/PowerPC/vsx_insert_extract_le.ll b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll new file mode 100644 index 0000000..0a9df37 --- /dev/null +++ b/test/CodeGen/PowerPC/vsx_insert_extract_le.ll @@ -0,0 +1,52 @@ +; RUN: llc -mcpu=pwr8 -mattr=+vsx -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +define <2 x double> @testi0(<2 x double>* %p1, double* %p2) { + %v = load <2 x double>* %p1 + %s = load double* %p2 + %r = insertelement <2 x double> %v, double %s, i32 0 + ret <2 x double> %r + +; CHECK-LABEL: testi0 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxsdx 34, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 34, 34, 0 +; CHECK: xxpermdi 34, 0, 1, 1 +} + +define <2 x double> @testi1(<2 x double>* %p1, double* %p2) { + %v = load <2 x double>* %p1 + %s = load double* %p2 + %r = insertelement <2 x double> %v, double %s, i32 1 + ret <2 x double> %r + +; CHECK-LABEL: testi1 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxsdx 34, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 34, 34, 0 +; CHECK: xxpermdi 34, 1, 0, 3 +} + +define double @teste0(<2 x double>* %p1) { + %v = load <2 x double>* %p1 + %r = extractelement <2 x double> %v, i32 0 + ret double %r + +; FIXME: Swap optimization will collapse this into lxvd2x 1, 0, 3. + +; CHECK-LABEL: teste0 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 0, 0, 2 +} + +define double @teste1(<2 x double>* %p1) { + %v = load <2 x double>* %p1 + %r = extractelement <2 x double> %v, i32 1 + ret double %r + +; CHECK-LABEL: teste1 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: xxpermdi 1, 0, 0, 2 +} diff --git a/test/CodeGen/PowerPC/vsx_shuffle_le.ll b/test/CodeGen/PowerPC/vsx_shuffle_le.ll new file mode 100644 index 0000000..588cfda --- /dev/null +++ b/test/CodeGen/PowerPC/vsx_shuffle_le.ll @@ -0,0 +1,207 @@ +; RUN: llc -mcpu=pwr8 -mattr=+vsx -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s + +define <2 x double> @test00(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 0> + ret <2 x double> %v3 + +; CHECK-LABEL: test00 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 34, 0, 0, 3 +} + +define <2 x double> @test01(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 1> + ret <2 x double> %v3 + +; CHECK-LABEL: test01 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: xxpermdi 34, 0, 0, 2 +} + +define <2 x double> @test02(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 2> + ret <2 x double> %v3 + +; CHECK-LABEL: @test02 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxvd2x 1, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxpermdi 34, 1, 0, 3 +} + +define <2 x double> @test03(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 0, i32 3> + ret <2 x double> %v3 + +; CHECK-LABEL: @test03 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxvd2x 1, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxpermdi 34, 1, 0, 1 +} + +define <2 x double> @test10(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 0> + ret <2 x double> %v3 + +; CHECK-LABEL: @test10 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 34, 0, 0, 2 +} + +define <2 x double> @test11(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 1> + ret <2 x double> %v3 + +; CHECK-LABEL: @test11 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 34, 0, 0, 0 +} + +define <2 x double> @test12(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 2> + ret <2 x double> %v3 + +; CHECK-LABEL: @test12 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxvd2x 1, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxpermdi 34, 1, 0, 2 +} + +define <2 x double> @test13(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 1, i32 3> + ret <2 x double> %v3 + +; CHECK-LABEL: @test13 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxvd2x 1, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxpermdi 34, 1, 0, 0 +} + +define <2 x double> @test20(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 0> + ret <2 x double> %v3 + +; CHECK-LABEL: @test20 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxvd2x 1, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxpermdi 34, 0, 1, 3 +} + +define <2 x double> @test21(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 1> + ret <2 x double> %v3 + +; CHECK-LABEL: @test21 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxvd2x 1, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxpermdi 34, 0, 1, 1 +} + +define <2 x double> @test22(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 2> + ret <2 x double> %v3 + +; CHECK-LABEL: @test22 +; CHECK: lxvd2x 0, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 34, 0, 0, 3 +} + +define <2 x double> @test23(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 2, i32 3> + ret <2 x double> %v3 + +; CHECK-LABEL: @test23 +; CHECK: lxvd2x 0, 0, 4 +; CHECK: xxpermdi 34, 0, 0, 2 +} + +define <2 x double> @test30(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 0> + ret <2 x double> %v3 + +; CHECK-LABEL: @test30 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxvd2x 1, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxpermdi 34, 0, 1, 2 +} + +define <2 x double> @test31(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 1> + ret <2 x double> %v3 + +; CHECK-LABEL: @test31 +; CHECK: lxvd2x 0, 0, 3 +; CHECK: lxvd2x 1, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 1, 1, 1, 2 +; CHECK: xxpermdi 34, 0, 1, 0 +} + +define <2 x double> @test32(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 2> + ret <2 x double> %v3 + +; CHECK-LABEL: @test32 +; CHECK: lxvd2x 0, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 34, 0, 0, 2 +} + +define <2 x double> @test33(<2 x double>* %p1, <2 x double>* %p2) { + %v1 = load <2 x double>* %p1 + %v2 = load <2 x double>* %p2 + %v3 = shufflevector <2 x double> %v1, <2 x double> %v2, <2 x i32> < i32 3, i32 3> + ret <2 x double> %v3 + +; CHECK-LABEL: @test33 +; CHECK: lxvd2x 0, 0, 4 +; CHECK: xxpermdi 0, 0, 0, 2 +; CHECK: xxpermdi 34, 0, 0, 0 +} diff --git a/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll b/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll new file mode 100644 index 0000000..4d929c6 --- /dev/null +++ b/test/CodeGen/PowerPC/xxleqv_xxlnand_xxlorc.ll @@ -0,0 +1,52 @@ +; Check the miscellaneous logical vector operations added in P8 +; +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s +; Test x eqv y +define <4 x i32> @test_xxleqv(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp = xor <4 x i32> %x, %y + %ret_val = xor <4 x i32> %tmp, < i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %ret_val +; CHECK: xxleqv 34, 34, 35 +} + +; Test x xxlnand y +define <4 x i32> @test_xxlnand(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp = and <4 x i32> %x, %y + %ret_val = xor <4 x i32> %tmp, <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %ret_val +; CHECK: xxlnand 34, 34, 35 +} + +; Test x xxlorc y +define <4 x i32> @test_xxlorc(<4 x i32> %x, <4 x i32> %y) nounwind { + %tmp = xor <4 x i32> %y, <i32 -1, i32 -1, i32 -1, i32 -1> + %ret_val = or <4 x i32> %x, %tmp + ret <4 x i32> %ret_val +; CHECK: xxlorc 34, 34, 35 +} + +; Test x eqv y +define <8 x i16> @test_xxleqvv8i16(<8 x i16> %x, <8 x i16> %y) nounwind { + %tmp = xor <8 x i16> %x, %y + %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> + ret <8 x i16> %ret_val +; CHECK: xxleqv 34, 34, 35 +} + +; Test x xxlnand y +define <8 x i16> @test_xxlnandv8i16(<8 x i16> %x, <8 x i16> %y) nounwind { + %tmp = and <8 x i16> %x, %y + %ret_val = xor <8 x i16> %tmp, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> + ret <8 x i16> %ret_val +; CHECK: xxlnand 34, 34, 35 +} + +; Test x xxlorc y +define <8 x i16> @test_xxlorcv8i16(<8 x i16> %x, <8 x i16> %y) nounwind { + %tmp = xor <8 x i16> %y, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> + %ret_val = or <8 x i16> %x, %tmp + ret <8 x i16> %ret_val +; CHECK: xxlorc 34, 34, 35 +} + diff --git a/test/CodeGen/PowerPC/zext-free.ll b/test/CodeGen/PowerPC/zext-free.ll new file mode 100644 index 0000000..080dbaa --- /dev/null +++ b/test/CodeGen/PowerPC/zext-free.ll @@ -0,0 +1,37 @@ +; RUN: llc -mcpu=ppc64 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +; Function Attrs: noreturn nounwind +define signext i32 @_Z1fRPc(i8** nocapture dereferenceable(8) %p) #0 { +entry: + %.pre = load i8** %p, align 8 + br label %loop + +loop: ; preds = %loop.backedge, %entry + %0 = phi i8* [ %.pre, %entry ], [ %.be, %loop.backedge ] + %1 = load i8* %0, align 1 + %tobool = icmp eq i8 %1, 0 + %incdec.ptr = getelementptr inbounds i8* %0, i64 1 + store i8* %incdec.ptr, i8** %p, align 8 + %2 = load i8* %incdec.ptr, align 1 + %tobool2 = icmp ne i8 %2, 0 + %or.cond = and i1 %tobool, %tobool2 + br i1 %or.cond, label %if.then3, label %loop.backedge + +if.then3: ; preds = %loop + %incdec.ptr4 = getelementptr inbounds i8* %0, i64 2 + store i8* %incdec.ptr4, i8** %p, align 8 + br label %loop.backedge + +loop.backedge: ; preds = %if.then3, %loop + %.be = phi i8* [ %incdec.ptr4, %if.then3 ], [ %incdec.ptr, %loop ] + br label %loop + +; CHECK-LABEL: @_Z1fRPc +; CHECK-NOT: rlwinm {{[0-9]+}}, {{[0-9]+}}, 0, 24, 31 +; CHECK-NOT: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 +} + +attributes #0 = { noreturn nounwind } + |