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-rw-r--r--test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll33
1 files changed, 33 insertions, 0 deletions
diff --git a/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
new file mode 100644
index 0000000..1acf905
--- /dev/null
+++ b/test/CodeGen/R600/dagcombiner-bug-illegal-vec4-int-to-fp.ll
@@ -0,0 +1,33 @@
+;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
+
+;CHECK: INT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+; This test is for a bug in
+; DAGCombiner::reduceBuildVecConvertToConvertBuildVec() where
+; the wrong type was being passed to
+; TargetLowering::getOperationAction() when checking the legality of
+; ISD::UINT_TO_FP and ISD::SINT_TO_FP opcodes.
+
+define void @sint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
+entry:
+ %ptr = getelementptr i32 addrspace(1)* %in, i32 1
+ %sint = load i32 addrspace(1) * %in
+ %conv = sitofp i32 %sint to float
+ %0 = insertelement <4 x float> undef, float %conv, i32 0
+ %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
+ store <4 x float> %splat, <4 x float> addrspace(1)* %out
+ ret void
+}
+
+;CHECK: UINT_TO_FLT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+
+define void @uint(<4 x float> addrspace(1)* %out, i32 addrspace(1)* %in) {
+entry:
+ %ptr = getelementptr i32 addrspace(1)* %in, i32 1
+ %uint = load i32 addrspace(1) * %in
+ %conv = uitofp i32 %uint to float
+ %0 = insertelement <4 x float> undef, float %conv, i32 0
+ %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
+ store <4 x float> %splat, <4 x float> addrspace(1)* %out
+ ret void
+}