diff options
Diffstat (limited to 'test/CodeGen/R600/sext-in-reg.ll')
| -rw-r--r-- | test/CodeGen/R600/sext-in-reg.ll | 381 |
1 files changed, 235 insertions, 146 deletions
diff --git a/test/CodeGen/R600/sext-in-reg.ll b/test/CodeGen/R600/sext-in-reg.ll index 1b02e4b..d364e6b 100644 --- a/test/CodeGen/R600/sext-in-reg.ll +++ b/test/CodeGen/R600/sext-in-reg.ll @@ -2,13 +2,14 @@ ; RUN: llc -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s declare i32 @llvm.AMDGPU.imax(i32, i32) nounwind readnone +declare i32 @llvm.r600.read.tidig.x() nounwind readnone -; FUNC-LABEL: @sext_in_reg_i1_i32 -; SI: S_LOAD_DWORD [[ARG:s[0-9]+]], -; SI: S_BFE_I32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000 -; SI: V_MOV_B32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]] -; SI: BUFFER_STORE_DWORD [[EXTRACT]], +; FUNC-LABEL: {{^}}sext_in_reg_i1_i32: +; SI: s_load_dword [[ARG:s[0-9]+]], +; SI: s_bfe_i32 [[SEXTRACT:s[0-9]+]], [[ARG]], 0x10000 +; SI: v_mov_b32_e32 [[EXTRACT:v[0-9]+]], [[SEXTRACT]] +; SI: buffer_store_dword [[EXTRACT]], ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]], {{.*}}, 0.0, 1 @@ -20,11 +21,11 @@ define void @sext_in_reg_i1_i32(i32 addrspace(1)* %out, i32 %in) { ret void } -; FUNC-LABEL: @sext_in_reg_i8_to_i32 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] -; SI: BUFFER_STORE_DWORD [[VEXTRACT]], +; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32: +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] +; SI: buffer_store_dword [[VEXTRACT]], ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG: ADD_INT @@ -38,11 +39,11 @@ define void @sext_in_reg_i8_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) nounw ret void } -; FUNC-LABEL: @sext_in_reg_i16_to_i32 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] -; SI: BUFFER_STORE_DWORD [[VEXTRACT]], +; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i32: +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_sext_i32_i16 [[EXTRACT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] +; SI: buffer_store_dword [[VEXTRACT]], ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG: ADD_INT @@ -56,11 +57,11 @@ define void @sext_in_reg_i16_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) noun ret void } -; FUNC-LABEL: @sext_in_reg_i8_to_v1i32 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: V_MOV_B32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] -; SI: BUFFER_STORE_DWORD [[VEXTRACT]], +; FUNC-LABEL: {{^}}sext_in_reg_i8_to_v1i32: +; SI: s_add_i32 [[VAL:s[0-9]+]], +; SI: s_sext_i32_i8 [[EXTRACT:s[0-9]+]], [[VAL]] +; SI: v_mov_b32_e32 [[VEXTRACT:v[0-9]+]], [[EXTRACT]] +; SI: buffer_store_dword [[VEXTRACT]], ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG: ADD_INT @@ -74,29 +75,31 @@ define void @sext_in_reg_i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i32> %a, ret void } -; FUNC-LABEL: @sext_in_reg_i1_to_i64 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_BFE_I32 s{{[0-9]+}}, s{{[0-9]+}}, 0x10000 -; SI: S_MOV_B32 {{s[0-9]+}}, -1 -; SI: BUFFER_STORE_DWORDX2 +; FUNC-LABEL: {{^}}sext_in_reg_i1_to_i64: +; SI: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x10000 +; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] +; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] +; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} define void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { - %c = add i64 %a, %b + %c = shl i64 %a, %b %shl = shl i64 %c, 63 %ashr = ashr i64 %shl, 63 store i64 %ashr, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: @sext_in_reg_i8_to_i64 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I8 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: S_MOV_B32 {{s[0-9]+}}, -1 -; SI: BUFFER_STORE_DWORDX2 +; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i64: +; SI: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x80000 +; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] +; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] +; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] -; EG: ADD_INT -; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal +; EG: LSHL +; EG: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal ; EG: ASHR [[RES_HI]] ; EG-NOT: BFE_INT ; EG: LSHR @@ -104,23 +107,24 @@ define void @sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounw ;; TODO Check address computation, using | with variables in {{}} does not work, ;; also the _LO/_HI order might be different define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { - %c = add i64 %a, %b + %c = shl i64 %a, %b %shl = shl i64 %c, 56 %ashr = ashr i64 %shl, 56 store i64 %ashr, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: @sext_in_reg_i16_to_i64 -; SI: S_ADD_I32 [[VAL:s[0-9]+]], -; SI: S_SEXT_I32_I16 [[EXTRACT:s[0-9]+]], [[VAL]] -; SI: S_MOV_B32 {{s[0-9]+}}, -1 -; SI: BUFFER_STORE_DWORDX2 +; FUNC-LABEL: {{^}}sext_in_reg_i16_to_i64: +; SI: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x100000 +; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] +; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] +; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] -; EG: ADD_INT -; EG-NEXT: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal +; EG: LSHL +; EG: BFE_INT {{\*?}} [[RES_LO]], {{.*}}, 0.0, literal ; EG: ASHR [[RES_HI]] ; EG-NOT: BFE_INT ; EG: LSHR @@ -128,32 +132,32 @@ define void @sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounw ;; TODO Check address computation, using | with variables in {{}} does not work, ;; also the _LO/_HI order might be different define void @sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { - %c = add i64 %a, %b + %c = shl i64 %a, %b %shl = shl i64 %c, 48 %ashr = ashr i64 %shl, 48 store i64 %ashr, i64 addrspace(1)* %out, align 8 ret void } -; FUNC-LABEL: @sext_in_reg_i32_to_i64 -; SI: S_LOAD_DWORD -; SI: S_LOAD_DWORD -; SI: S_ADD_I32 [[ADD:s[0-9]+]], -; SI: S_ASHR_I32 s{{[0-9]+}}, [[ADD]], 31 -; SI: BUFFER_STORE_DWORDX2 +; FUNC-LABEL: {{^}}sext_in_reg_i32_to_i64: +; SI: s_lshl_b64 [[VAL:s\[[0-9]+:[0-9]+\]]] +; SI-DAG: s_bfe_i64 s{{\[}}[[SLO:[0-9]+]]:[[SHI:[0-9]+]]{{\]}}, [[VAL]], 0x200000 +; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SLO]] +; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]] +; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_LO:T[0-9]+\.[XYZW]]], [[ADDR_LO:T[0-9]+.[XYZW]]] ; EG: MEM_{{.*}} STORE_{{.*}} [[RES_HI:T[0-9]+\.[XYZW]]], [[ADDR_HI:T[0-9]+.[XYZW]]] ; EG-NOT: BFE_INT -; EG: ADD_INT {{\*?}} [[RES_LO]] + ; EG: ASHR [[RES_HI]] -; EG: ADD_INT + ; EG: LSHR ; EG: LSHR ;; TODO Check address computation, using | with variables in {{}} does not work, ;; also the _LO/_HI order might be different define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) nounwind { - %c = add i64 %a, %b + %c = shl i64 %a, %b %shl = shl i64 %c, 32 %ashr = ashr i64 %shl, 32 store i64 %ashr, i64 addrspace(1)* %out, align 8 @@ -161,10 +165,10 @@ define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) noun } ; This is broken on Evergreen for some reason related to the <1 x i64> kernel arguments. -; XFUNC-LABEL: @sext_in_reg_i8_to_v1i64 -; XSI: S_BFE_I32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288 -; XSI: S_ASHR_I32 {{v[0-9]+}}, [[EXTRACT]], 31 -; XSI: BUFFER_STORE_DWORD +; XFUNC-LABEL: {{^}}sext_in_reg_i8_to_v1i64: +; XSI: s_bfe_i32 [[EXTRACT:s[0-9]+]], {{s[0-9]+}}, 524288 +; XSI: s_ashr_i32 {{v[0-9]+}}, [[EXTRACT]], 31 +; XSI: buffer_store_dword ; XEG: BFE_INT ; XEG: ASHR ; define void @sext_in_reg_i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i64> %a, <1 x i64> %b) nounwind { @@ -175,10 +179,93 @@ define void @sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) noun ; ret void ; } -; FUNC-LABEL: @sext_in_reg_i1_in_i32_other_amount -; SI-NOT: BFE -; SI: S_LSHL_B32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6 -; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG]], 7 +; FUNC-LABEL: {{^}}v_sext_in_reg_i1_to_i64: +; SI: buffer_load_dwordx2 +; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} +; SI: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 1 +; SI: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] +; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @v_sext_in_reg_i1_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { + %tid = call i32 @llvm.r600.read.tidig.x() + %a.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid + %b.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid + %out.gep = getelementptr i64 addrspace(1)* %out, i32 %tid + %a = load i64 addrspace(1)* %a.gep, align 8 + %b = load i64 addrspace(1)* %b.gep, align 8 + + %c = shl i64 %a, %b + %shl = shl i64 %c, 63 + %ashr = ashr i64 %shl, 63 + store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 + ret void +} + +; FUNC-LABEL: {{^}}v_sext_in_reg_i8_to_i64: +; SI: buffer_load_dwordx2 +; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} +; SI: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 8 +; SI: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] +; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @v_sext_in_reg_i8_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { + %tid = call i32 @llvm.r600.read.tidig.x() + %a.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid + %b.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid + %out.gep = getelementptr i64 addrspace(1)* %out, i32 %tid + %a = load i64 addrspace(1)* %a.gep, align 8 + %b = load i64 addrspace(1)* %b.gep, align 8 + + %c = shl i64 %a, %b + %shl = shl i64 %c, 56 + %ashr = ashr i64 %shl, 56 + store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 + ret void +} + +; FUNC-LABEL: {{^}}v_sext_in_reg_i16_to_i64: +; SI: buffer_load_dwordx2 +; SI: v_lshl_b64 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}} +; SI: v_bfe_i32 v[[LO:[0-9]+]], v[[VAL_LO]], 0, 16 +; SI: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] +; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} +define void @v_sext_in_reg_i16_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { + %tid = call i32 @llvm.r600.read.tidig.x() + %a.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid + %b.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid + %out.gep = getelementptr i64 addrspace(1)* %out, i32 %tid + %a = load i64 addrspace(1)* %a.gep, align 8 + %b = load i64 addrspace(1)* %b.gep, align 8 + + %c = shl i64 %a, %b + %shl = shl i64 %c, 48 + %ashr = ashr i64 %shl, 48 + store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 + ret void +} + +; FUNC-LABEL: {{^}}v_sext_in_reg_i32_to_i64: +; SI: buffer_load_dwordx2 +; SI: v_lshl_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, +; SI: v_ashrrev_i32_e32 v[[SHR:[0-9]+]], 31, v[[LO]] +; SI: buffer_store_dwordx2 v{{\[}}[[LO]]:[[SHR]]{{\]}} +define void @v_sext_in_reg_i32_to_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) nounwind { + %tid = call i32 @llvm.r600.read.tidig.x() + %a.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid + %b.gep = getelementptr i64 addrspace(1)* %aptr, i32 %tid + %out.gep = getelementptr i64 addrspace(1)* %out, i32 %tid + %a = load i64 addrspace(1)* %a.gep, align 8 + %b = load i64 addrspace(1)* %b.gep, align 8 + + %c = shl i64 %a, %b + %shl = shl i64 %c, 32 + %ashr = ashr i64 %shl, 32 + store i64 %ashr, i64 addrspace(1)* %out.gep, align 8 + ret void +} + +; FUNC-LABEL: {{^}}sext_in_reg_i1_in_i32_other_amount: +; SI-NOT: {{[^@]}}bfe +; SI: s_lshl_b32 [[REG:s[0-9]+]], {{s[0-9]+}}, 6 +; SI: s_ashr_i32 {{s[0-9]+}}, [[REG]], 7 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+\.[XYZW]]], [[ADDR:T[0-9]+.[XYZW]]] ; EG-NOT: BFE @@ -194,11 +281,12 @@ define void @sext_in_reg_i1_in_i32_other_amount(i32 addrspace(1)* %out, i32 %a, ret void } -; FUNC-LABEL: @sext_in_reg_v2i1_in_v2i32_other_amount -; SI: S_LSHL_B32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6 -; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG0]], 7 -; SI: S_LSHL_B32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6 -; SI: S_ASHR_I32 {{s[0-9]+}}, [[REG1]], 7 +; FUNC-LABEL: {{^}}sext_in_reg_v2i1_in_v2i32_other_amount: +; SI-DAG: s_lshl_b32 [[REG0:s[0-9]+]], {{s[0-9]}}, 6 +; SI-DAG: s_ashr_i32 {{s[0-9]+}}, [[REG0]], 7 +; SI-DAG: s_lshl_b32 [[REG1:s[0-9]+]], {{s[0-9]}}, 6 +; SI-DAG: s_ashr_i32 {{s[0-9]+}}, [[REG1]], 7 +; SI: s_endpgm ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG-NOT: BFE @@ -217,10 +305,10 @@ define void @sext_in_reg_v2i1_in_v2i32_other_amount(<2 x i32> addrspace(1)* %out } -; FUNC-LABEL: @sext_in_reg_v2i1_to_v2i32 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: BUFFER_STORE_DWORDX2 +; FUNC-LABEL: {{^}}sext_in_reg_v2i1_to_v2i32: +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -234,12 +322,12 @@ define void @sext_in_reg_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> % ret void } -; FUNC-LABEL: @sext_in_reg_v4i1_to_v4i32 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: S_BFE_I32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 -; SI: BUFFER_STORE_DWORDX4 +; FUNC-LABEL: {{^}}sext_in_reg_v4i1_to_v4i32: +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: s_bfe_i32 {{s[0-9]+}}, {{s[0-9]+}}, 0x10000 +; SI: buffer_store_dwordx4 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -255,10 +343,10 @@ define void @sext_in_reg_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> % ret void } -; FUNC-LABEL: @sext_in_reg_v2i8_to_v2i32 -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: BUFFER_STORE_DWORDX2 +; FUNC-LABEL: {{^}}sext_in_reg_v2i8_to_v2i32: +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -272,12 +360,12 @@ define void @sext_in_reg_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> % ret void } -; FUNC-LABEL: @sext_in_reg_v4i8_to_v4i32 -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I8 {{s[0-9]+}}, {{s[0-9]+}} -; SI: BUFFER_STORE_DWORDX4 +; FUNC-LABEL: {{^}}sext_in_reg_v4i8_to_v4i32: +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i8 {{s[0-9]+}}, {{s[0-9]+}} +; SI: buffer_store_dwordx4 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW][XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -293,10 +381,10 @@ define void @sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> % ret void } -; FUNC-LABEL: @sext_in_reg_v2i16_to_v2i32 -; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}} -; SI: S_SEXT_I32_I16 {{s[0-9]+}}, {{s[0-9]+}} -; SI: BUFFER_STORE_DWORDX2 +; FUNC-LABEL: {{^}}sext_in_reg_v2i16_to_v2i32: +; SI: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}} +; SI: s_sext_i32_i16 {{s[0-9]+}}, {{s[0-9]+}} +; SI: buffer_store_dwordx2 ; EG: MEM_{{.*}} STORE_{{.*}} [[RES:T[0-9]+]]{{\.[XYZW][XYZW]}}, [[ADDR:T[0-9]+.[XYZW]]] ; EG: BFE_INT [[RES]] @@ -310,7 +398,7 @@ define void @sext_in_reg_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> ret void } -; FUNC-LABEL: @testcase +; FUNC-LABEL: {{^}}testcase: define void @testcase(i8 addrspace(1)* %out, i8 %a) nounwind { %and_a_1 = and i8 %a, 1 %cmp_eq = icmp eq i8 %and_a_1, 0 @@ -322,7 +410,7 @@ define void @testcase(i8 addrspace(1)* %out, i8 %a) nounwind { ret void } -; FUNC-LABEL: @testcase_3 +; FUNC-LABEL: {{^}}testcase_3: define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind { %and_a_1 = and i8 %a, 1 %cmp_eq = icmp eq i8 %and_a_1, 0 @@ -334,11 +422,11 @@ define void @testcase_3(i8 addrspace(1)* %out, i8 %a) nounwind { ret void } -; FUNC-LABEL: @vgpr_sext_in_reg_v4i8_to_v4i32 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 +; FUNC-LABEL: {{^}}vgpr_sext_in_reg_v4i8_to_v4i32: +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 8 define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind { %loada = load <4 x i32> addrspace(1)* %a, align 16 %loadb = load <4 x i32> addrspace(1)* %b, align 16 @@ -349,9 +437,9 @@ define void @vgpr_sext_in_reg_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i ret void } -; FUNC-LABEL: @vgpr_sext_in_reg_v4i16_to_v4i32 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 -; SI: V_BFE_I32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 +; FUNC-LABEL: {{^}}vgpr_sext_in_reg_v4i16_to_v4i32: +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 +; SI: v_bfe_i32 [[EXTRACT:v[0-9]+]], {{v[0-9]+}}, 0, 16 define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %a, <4 x i32> addrspace(1)* %b) nounwind { %loada = load <4 x i32> addrspace(1)* %a, align 16 %loadb = load <4 x i32> addrspace(1)* %b, align 16 @@ -365,11 +453,11 @@ define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x ; FIXME: The BFE should really be eliminated. I think it should happen ; when computeKnownBitsForTargetNode is implemented for imax. -; FUNC-LABEL: @sext_in_reg_to_illegal_type -; SI: BUFFER_LOAD_SBYTE -; SI: V_MAX_I32 -; SI: V_BFE_I32 -; SI: BUFFER_STORE_SHORT +; FUNC-LABEL: {{^}}sext_in_reg_to_illegal_type: +; SI: buffer_load_sbyte +; SI: v_max_i32 +; SI: v_bfe_i32 +; SI: buffer_store_short define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { %tmp5 = load i8 addrspace(1)* %src, align 1 %tmp2 = sext i8 %tmp5 to i32 @@ -382,9 +470,9 @@ define void @sext_in_reg_to_illegal_type(i16 addrspace(1)* nocapture %out, i8 ad declare i32 @llvm.AMDGPU.bfe.i32(i32, i32, i32) nounwind readnone -; FUNC-LABEL: @bfe_0_width -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_0_width: +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind { %load = load i32 addrspace(1)* %ptr, align 4 %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 8, i32 0) nounwind readnone @@ -392,10 +480,10 @@ define void @bfe_0_width(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwin ret void } -; FUNC-LABEL: @bfe_8_bfe_8 -; SI: V_BFE_I32 -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_8_bfe_8: +; SI: v_bfe_i32 +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind { %load = load i32 addrspace(1)* %ptr, align 4 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone @@ -404,9 +492,9 @@ define void @bfe_8_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwin ret void } -; FUNC-LABEL: @bfe_8_bfe_16 -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_8_bfe_16: +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 +; SI: s_endpgm define void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind { %load = load i32 addrspace(1)* %ptr, align 4 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 8) nounwind readnone @@ -416,10 +504,10 @@ define void @bfe_8_bfe_16(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwi } ; This really should be folded into 1 -; FUNC-LABEL: @bfe_16_bfe_8 -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}bfe_16_bfe_8: +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 8 +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwind { %load = load i32 addrspace(1)* %ptr, align 4 %bfe0 = call i32 @llvm.AMDGPU.bfe.i32(i32 %load, i32 0, i32 16) nounwind readnone @@ -429,10 +517,10 @@ define void @bfe_16_bfe_8(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) nounwi } ; Make sure there isn't a redundant BFE -; FUNC-LABEL: @sext_in_reg_i8_to_i32_bfe -; SI: S_SEXT_I32_I8 s{{[0-9]+}}, s{{[0-9]+}} -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe: +; SI: s_sext_i32_i8 s{{[0-9]+}}, s{{[0-9]+}} +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @sext_in_reg_i8_to_i32_bfe(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %c = add i32 %a, %b ; add to prevent folding into extload %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %c, i32 0, i32 8) nounwind readnone @@ -442,7 +530,7 @@ define void @sext_in_reg_i8_to_i32_bfe(i32 addrspace(1)* %out, i32 %a, i32 %b) n ret void } -; FUNC-LABEL: @sext_in_reg_i8_to_i32_bfe_wrong +; FUNC-LABEL: {{^}}sext_in_reg_i8_to_i32_bfe_wrong: define void @sext_in_reg_i8_to_i32_bfe_wrong(i32 addrspace(1)* %out, i32 %a, i32 %b) nounwind { %c = add i32 %a, %b ; add to prevent folding into extload %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %c, i32 8, i32 0) nounwind readnone @@ -452,10 +540,10 @@ define void @sext_in_reg_i8_to_i32_bfe_wrong(i32 addrspace(1)* %out, i32 %a, i32 ret void } -; FUNC-LABEL: @sextload_i8_to_i32_bfe -; SI: BUFFER_LOAD_SBYTE -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe: +; SI: buffer_load_sbyte +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) nounwind { %load = load i8 addrspace(1)* %ptr, align 1 %sext = sext i8 %load to i32 @@ -466,9 +554,10 @@ define void @sextload_i8_to_i32_bfe(i32 addrspace(1)* %out, i8 addrspace(1)* %pt ret void } -; FUNC-LABEL: @sextload_i8_to_i32_bfe_0: -; SI-NOT: BFE -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}sextload_i8_to_i32_bfe_0: +; SI: .text +; SI-NOT: {{[^@]}}bfe +; SI: s_endpgm define void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* %ptr) nounwind { %load = load i8 addrspace(1)* %ptr, align 1 %sext = sext i8 %load to i32 @@ -479,11 +568,11 @@ define void @sextload_i8_to_i32_bfe_0(i32 addrspace(1)* %out, i8 addrspace(1)* % ret void } -; FUNC-LABEL: @sext_in_reg_i1_bfe_offset_0: -; SI-NOT: SHR -; SI-NOT: SHL -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}sext_in_reg_i1_bfe_offset_0: +; SI-NOT: shr +; SI-NOT: shl +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 0, 1 +; SI: s_endpgm define void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 31 @@ -493,12 +582,12 @@ define void @sext_in_reg_i1_bfe_offset_0(i32 addrspace(1)* %out, i32 addrspace(1 ret void } -; FUNC-LABEL: @sext_in_reg_i1_bfe_offset_1 -; SI: BUFFER_LOAD_DWORD -; SI-NOT: SHL -; SI-NOT: SHR -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 1 -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}sext_in_reg_i1_bfe_offset_1: +; SI: buffer_load_dword +; SI-NOT: shl +; SI-NOT: shr +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 1 +; SI: s_endpgm define void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 30 @@ -508,12 +597,12 @@ define void @sext_in_reg_i1_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1 ret void } -; FUNC-LABEL: @sext_in_reg_i2_bfe_offset_1: -; SI: BUFFER_LOAD_DWORD -; SI: V_LSHLREV_B32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}} -; SI: V_ASHRREV_I32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}} -; SI: V_BFE_I32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2 -; SI: S_ENDPGM +; FUNC-LABEL: {{^}}sext_in_reg_i2_bfe_offset_1: +; SI: buffer_load_dword +; SI: v_lshlrev_b32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}} +; SI: v_ashrrev_i32_e32 v{{[0-9]+}}, 30, v{{[0-9]+}} +; SI: v_bfe_i32 v{{[0-9]+}}, v{{[0-9]+}}, 1, 2 +; SI: s_endpgm define void @sext_in_reg_i2_bfe_offset_1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { %x = load i32 addrspace(1)* %in, align 4 %shl = shl i32 %x, 30 |