diff options
Diffstat (limited to 'test/CodeGen/R600/store.ll')
| -rw-r--r-- | test/CodeGen/R600/store.ll | 328 |
1 files changed, 168 insertions, 160 deletions
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index 713ecd6..e4cb313 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -1,13 +1,14 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s -; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK --check-prefix=FUNC %s -; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s +; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=CM -check-prefix=FUNC %s ;===------------------------------------------------------------------------===; ; Global Address Space ;===------------------------------------------------------------------------===; ; FUNC-LABEL: {{^}}store_i1: -; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: buffer_store_byte +; EG: MEM_RAT MSKOR +; SI: buffer_store_byte define void @store_i1(i1 addrspace(1)* %out) { entry: store i1 true, i1 addrspace(1)* %out @@ -15,27 +16,29 @@ entry: } ; i8 store -; EG-CHECK-LABEL: {{^}}store_i8: -; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X -; EG-CHECK: VTX_READ_8 [[VAL:T[0-9]\.X]], [[VAL]] +; EG-LABEL: {{^}}store_i8: +; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X + ; IG 0: Get the byte index and truncate the value -; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG-CHECK-NEXT: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y -; EG-CHECK-NEXT: 3(4.203895e-45), 255(3.573311e-43) +; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x +; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y +; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43) + + ; IG 1: Truncate the calculated the shift amount for the mask -; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x -; EG-CHECK-NEXT: 3 + ; IG 2: Shift the value and the mask -; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] -; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] -; EG-CHECK-NEXT: 255 +; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] +; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] +; EG-NEXT: 255 ; IG 3: Initialize the Y and Z channels to zero ; XXX: An optimal scheduler should merge this into one of the prevous IGs. -; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0 -; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 +; EG: MOV T[[RW_GPR]].Y, 0.0 +; EG: MOV * T[[RW_GPR]].Z, 0.0 -; SI-CHECK-LABEL: {{^}}store_i8: -; SI-CHECK: buffer_store_byte +; SI-LABEL: {{^}}store_i8: +; SI: buffer_store_byte define void @store_i8(i8 addrspace(1)* %out, i8 %in) { entry: @@ -44,39 +47,44 @@ entry: } ; i16 store -; EG-CHECK-LABEL: {{^}}store_i16: -; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X -; EG-CHECK: VTX_READ_16 [[VAL:T[0-9]\.X]], [[VAL]] +; EG-LABEL: {{^}}store_i16: +; EG: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X + ; IG 0: Get the byte index and truncate the value -; EG-CHECK: AND_INT T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x -; EG-CHECK: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.y -; EG-CHECK-NEXT: 3(4.203895e-45), 65535(9.183409e-41) + + +; EG: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG-NEXT: 3(4.203895e-45), + +; EG: LSHL T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x +; EG: AND_INT * T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], KC0[2].Z, literal.y + +; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41) ; IG 1: Truncate the calculated the shift amount for the mask -; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.x -; EG-CHECK: 3 + ; IG 2: Shift the value and the mask -; EG-CHECK: LSHL T[[RW_GPR]].X, T{{[0-9]}}.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] -; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] -; EG-CHECK-NEXT: 65535 +; EG: LSHL T[[RW_GPR]].X, PS, PV.[[SHIFT_CHAN]] +; EG: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] +; EG-NEXT: 65535 ; IG 3: Initialize the Y and Z channels to zero ; XXX: An optimal scheduler should merge this into one of the prevous IGs. -; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0 -; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 +; EG: MOV T[[RW_GPR]].Y, 0.0 +; EG: MOV * T[[RW_GPR]].Z, 0.0 -; SI-CHECK-LABEL: {{^}}store_i16: -; SI-CHECK: buffer_store_short +; SI-LABEL: {{^}}store_i16: +; SI: buffer_store_short define void @store_i16(i16 addrspace(1)* %out, i16 %in) { entry: store i16 %in, i16 addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_v2i8: -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK-NOT: MEM_RAT MSKOR -; SI-CHECK-LABEL: {{^}}store_v2i8: -; SI-CHECK: buffer_store_byte -; SI-CHECK: buffer_store_byte +; EG-LABEL: {{^}}store_v2i8: +; EG: MEM_RAT MSKOR +; EG-NOT: MEM_RAT MSKOR +; SI-LABEL: {{^}}store_v2i8: +; SI: buffer_store_byte +; SI: buffer_store_byte define void @store_v2i8(<2 x i8> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i8> @@ -85,13 +93,13 @@ entry: } -; EG-CHECK-LABEL: {{^}}store_v2i16: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}store_v2i16: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}store_v2i16: -; SI-CHECK: buffer_store_short -; SI-CHECK: buffer_store_short +; EG-LABEL: {{^}}store_v2i16: +; EG: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}store_v2i16: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}store_v2i16: +; SI: buffer_store_short +; SI: buffer_store_short define void @store_v2i16(<2 x i16> addrspace(1)* %out, <2 x i32> %in) { entry: %0 = trunc <2 x i32> %in to <2 x i16> @@ -99,15 +107,15 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}store_v4i8: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}store_v4i8: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}store_v4i8: -; SI-CHECK: buffer_store_byte -; SI-CHECK: buffer_store_byte -; SI-CHECK: buffer_store_byte -; SI-CHECK: buffer_store_byte +; EG-LABEL: {{^}}store_v4i8: +; EG: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}store_v4i8: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}store_v4i8: +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: buffer_store_byte +; SI: buffer_store_byte define void @store_v4i8(<4 x i8> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i8> @@ -116,30 +124,30 @@ entry: } ; floating-point store -; EG-CHECK-LABEL: {{^}}store_f32: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1 -; CM-CHECK-LABEL: {{^}}store_f32: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} -; SI-CHECK-LABEL: {{^}}store_f32: -; SI-CHECK: buffer_store_dword +; EG-LABEL: {{^}}store_f32: +; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1 +; CM-LABEL: {{^}}store_f32: +; CM: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} +; SI-LABEL: {{^}}store_f32: +; SI: buffer_store_dword define void @store_f32(float addrspace(1)* %out, float %in) { store float %in, float addrspace(1)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_v4i16: -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK: MEM_RAT MSKOR -; EG-CHECK-NOT: MEM_RAT MSKOR -; SI-CHECK-LABEL: {{^}}store_v4i16: -; SI-CHECK: buffer_store_short -; SI-CHECK: buffer_store_short -; SI-CHECK: buffer_store_short -; SI-CHECK: buffer_store_short -; SI-CHECK-NOT: buffer_store_byte +; EG-LABEL: {{^}}store_v4i16: +; EG: MEM_RAT MSKOR +; EG: MEM_RAT MSKOR +; EG: MEM_RAT MSKOR +; EG: MEM_RAT MSKOR +; EG-NOT: MEM_RAT MSKOR +; SI-LABEL: {{^}}store_v4i16: +; SI: buffer_store_short +; SI: buffer_store_short +; SI: buffer_store_short +; SI: buffer_store_short +; SI-NOT: buffer_store_byte define void @store_v4i16(<4 x i16> addrspace(1)* %out, <4 x i32> %in) { entry: %0 = trunc <4 x i32> %in to <4 x i16> @@ -148,12 +156,12 @@ entry: } ; vec2 floating-point stores -; EG-CHECK-LABEL: {{^}}store_v2f32: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}store_v2f32: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}store_v2f32: -; SI-CHECK: buffer_store_dwordx2 +; EG-LABEL: {{^}}store_v2f32: +; EG: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}store_v2f32: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}store_v2f32: +; SI: buffer_store_dwordx2 define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) { entry: @@ -163,14 +171,14 @@ entry: ret void } -; EG-CHECK-LABEL: {{^}}store_v4i32: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; EG-CHECK-NOT: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}store_v4i32: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; CM-CHECK-NOT: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}store_v4i32: -; SI-CHECK: buffer_store_dwordx4 +; EG-LABEL: {{^}}store_v4i32: +; EG: MEM_RAT_CACHELESS STORE_RAW +; EG-NOT: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}store_v4i32: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}store_v4i32: +; SI: buffer_store_dwordx4 define void @store_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(1)* %out @@ -178,8 +186,8 @@ entry: } ; FUNC-LABEL: {{^}}store_i64_i8: -; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: buffer_store_byte +; EG: MEM_RAT MSKOR +; SI: buffer_store_byte define void @store_i64_i8(i8 addrspace(1)* %out, i64 %in) { entry: %0 = trunc i64 %in to i8 @@ -188,8 +196,8 @@ entry: } ; FUNC-LABEL: {{^}}store_i64_i16: -; EG-CHECK: MEM_RAT MSKOR -; SI-CHECK: buffer_store_short +; EG: MEM_RAT MSKOR +; SI: buffer_store_short define void @store_i64_i16(i16 addrspace(1)* %out, i64 %in) { entry: %0 = trunc i64 %in to i16 @@ -202,89 +210,89 @@ entry: ;===------------------------------------------------------------------------===; ; FUNC-LABEL: {{^}}store_local_i1: -; EG-CHECK: LDS_BYTE_WRITE -; SI-CHECK: ds_write_b8 +; EG: LDS_BYTE_WRITE +; SI: ds_write_b8 define void @store_local_i1(i1 addrspace(3)* %out) { entry: store i1 true, i1 addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_i8: -; EG-CHECK: LDS_BYTE_WRITE -; SI-CHECK-LABEL: {{^}}store_local_i8: -; SI-CHECK: ds_write_b8 +; EG-LABEL: {{^}}store_local_i8: +; EG: LDS_BYTE_WRITE +; SI-LABEL: {{^}}store_local_i8: +; SI: ds_write_b8 define void @store_local_i8(i8 addrspace(3)* %out, i8 %in) { store i8 %in, i8 addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_i16: -; EG-CHECK: LDS_SHORT_WRITE -; SI-CHECK-LABEL: {{^}}store_local_i16: -; SI-CHECK: ds_write_b16 +; EG-LABEL: {{^}}store_local_i16: +; EG: LDS_SHORT_WRITE +; SI-LABEL: {{^}}store_local_i16: +; SI: ds_write_b16 define void @store_local_i16(i16 addrspace(3)* %out, i16 %in) { store i16 %in, i16 addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_v2i16: -; EG-CHECK: LDS_WRITE -; CM-CHECK-LABEL: {{^}}store_local_v2i16: -; CM-CHECK: LDS_WRITE -; SI-CHECK-LABEL: {{^}}store_local_v2i16: -; SI-CHECK: ds_write_b16 -; SI-CHECK: ds_write_b16 +; EG-LABEL: {{^}}store_local_v2i16: +; EG: LDS_WRITE +; CM-LABEL: {{^}}store_local_v2i16: +; CM: LDS_WRITE +; SI-LABEL: {{^}}store_local_v2i16: +; SI: ds_write_b16 +; SI: ds_write_b16 define void @store_local_v2i16(<2 x i16> addrspace(3)* %out, <2 x i16> %in) { entry: store <2 x i16> %in, <2 x i16> addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_v4i8: -; EG-CHECK: LDS_WRITE -; CM-CHECK-LABEL: {{^}}store_local_v4i8: -; CM-CHECK: LDS_WRITE -; SI-CHECK-LABEL: {{^}}store_local_v4i8: -; SI-CHECK: ds_write_b8 -; SI-CHECK: ds_write_b8 -; SI-CHECK: ds_write_b8 -; SI-CHECK: ds_write_b8 +; EG-LABEL: {{^}}store_local_v4i8: +; EG: LDS_WRITE +; CM-LABEL: {{^}}store_local_v4i8: +; CM: LDS_WRITE +; SI-LABEL: {{^}}store_local_v4i8: +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 +; SI: ds_write_b8 define void @store_local_v4i8(<4 x i8> addrspace(3)* %out, <4 x i8> %in) { entry: store <4 x i8> %in, <4 x i8> addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_v2i32: -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; CM-CHECK-LABEL: {{^}}store_local_v2i32: -; CM-CHECK: LDS_WRITE -; CM-CHECK: LDS_WRITE -; SI-CHECK-LABEL: {{^}}store_local_v2i32: -; SI-CHECK: ds_write_b64 +; EG-LABEL: {{^}}store_local_v2i32: +; EG: LDS_WRITE +; EG: LDS_WRITE +; CM-LABEL: {{^}}store_local_v2i32: +; CM: LDS_WRITE +; CM: LDS_WRITE +; SI-LABEL: {{^}}store_local_v2i32: +; SI: ds_write_b64 define void @store_local_v2i32(<2 x i32> addrspace(3)* %out, <2 x i32> %in) { entry: store <2 x i32> %in, <2 x i32> addrspace(3)* %out ret void } -; EG-CHECK-LABEL: {{^}}store_local_v4i32: -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; EG-CHECK: LDS_WRITE -; CM-CHECK-LABEL: {{^}}store_local_v4i32: -; CM-CHECK: LDS_WRITE -; CM-CHECK: LDS_WRITE -; CM-CHECK: LDS_WRITE -; CM-CHECK: LDS_WRITE -; SI-CHECK-LABEL: {{^}}store_local_v4i32: -; SI-CHECK: ds_write_b32 -; SI-CHECK: ds_write_b32 -; SI-CHECK: ds_write_b32 -; SI-CHECK: ds_write_b32 +; EG-LABEL: {{^}}store_local_v4i32: +; EG: LDS_WRITE +; EG: LDS_WRITE +; EG: LDS_WRITE +; EG: LDS_WRITE +; CM-LABEL: {{^}}store_local_v4i32: +; CM: LDS_WRITE +; CM: LDS_WRITE +; CM: LDS_WRITE +; CM: LDS_WRITE +; SI-LABEL: {{^}}store_local_v4i32: +; SI: ds_write_b32 +; SI: ds_write_b32 +; SI: ds_write_b32 +; SI: ds_write_b32 define void @store_local_v4i32(<4 x i32> addrspace(3)* %out, <4 x i32> %in) { entry: store <4 x i32> %in, <4 x i32> addrspace(3)* %out @@ -292,8 +300,8 @@ entry: } ; FUNC-LABEL: {{^}}store_local_i64_i8: -; EG-CHECK: LDS_BYTE_WRITE -; SI-CHECK: ds_write_b8 +; EG: LDS_BYTE_WRITE +; SI: ds_write_b8 define void @store_local_i64_i8(i8 addrspace(3)* %out, i64 %in) { entry: %0 = trunc i64 %in to i8 @@ -302,8 +310,8 @@ entry: } ; FUNC-LABEL: {{^}}store_local_i64_i16: -; EG-CHECK: LDS_SHORT_WRITE -; SI-CHECK: ds_write_b16 +; EG: LDS_SHORT_WRITE +; SI: ds_write_b16 define void @store_local_i64_i16(i16 addrspace(3)* %out, i64 %in) { entry: %0 = trunc i64 %in to i16 @@ -318,12 +326,12 @@ entry: ; Evergreen / Northern Islands don't support 64-bit stores yet, so there should ; be two 32-bit stores. -; EG-CHECK-LABEL: {{^}}vecload2: -; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW -; CM-CHECK-LABEL: {{^}}vecload2: -; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD -; SI-CHECK-LABEL: {{^}}vecload2: -; SI-CHECK: buffer_store_dwordx2 +; EG-LABEL: {{^}}vecload2: +; EG: MEM_RAT_CACHELESS STORE_RAW +; CM-LABEL: {{^}}vecload2: +; CM: MEM_RAT_CACHELESS STORE_DWORD +; SI-LABEL: {{^}}vecload2: +; SI: buffer_store_dwordx2 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { entry: %0 = load i32 addrspace(2)* %mem, align 4 @@ -341,14 +349,14 @@ attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"= ; FUNC-LABEL: {{^}}"i128-const-store": ; FIXME: We should be able to to this with one store instruction -; EG-CHECK: STORE_RAW -; EG-CHECK: STORE_RAW -; EG-CHECK: STORE_RAW -; EG-CHECK: STORE_RAW -; CM-CHECK: STORE_DWORD -; CM-CHECK: STORE_DWORD -; CM-CHECK: STORE_DWORD -; CM-CHECK: STORE_DWORD +; EG: STORE_RAW +; EG: STORE_RAW +; EG: STORE_RAW +; EG: STORE_RAW +; CM: STORE_DWORD +; CM: STORE_DWORD +; CM: STORE_DWORD +; CM: STORE_DWORD ; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2 define void @i128-const-store(i32 addrspace(1)* %out) { |