1 files changed, 10 insertions, 10 deletions
diff --git a/test/CodeGen/SystemZ/int-move-09.ll b/test/CodeGen/SystemZ/int-move-09.ll
index b5c9cb1..6476842 100644
--- a/test/CodeGen/SystemZ/int-move-09.ll
+++ b/test/CodeGen/SystemZ/int-move-09.ll
@@ -20,7 +20,7 @@ define i64 @f1() {
 ; CHECK-LABEL: f1:
 ; CHECK: lghrl %r2, gsrc16
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16
+  %val = load i16 , i16 *@gsrc16
   %ext = sext i16 %val to i64
   ret i64 %ext
 }
@@ -30,7 +30,7 @@ define i64 @f2() {
 ; CHECK-LABEL: f2:
 ; CHECK: llghrl %r2, gsrc16
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16
+  %val = load i16 , i16 *@gsrc16
   %ext = zext i16 %val to i64
   ret i64 %ext
 }
@@ -40,7 +40,7 @@ define i64 @f3() {
 ; CHECK-LABEL: f3:
 ; CHECK: lgfrl %r2, gsrc32
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32
+  %val = load i32 , i32 *@gsrc32
   %ext = sext i32 %val to i64
   ret i64 %ext
 }
@@ -50,7 +50,7 @@ define i64 @f4() {
 ; CHECK-LABEL: f4:
 ; CHECK: llgfrl %r2, gsrc32
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32
+  %val = load i32 , i32 *@gsrc32
   %ext = zext i32 %val to i64
   ret i64 %ext
 }
@@ -81,7 +81,7 @@ define void @f7() {
 ; CHECK: lgrl %r0, gsrc64
 ; CHECK: stgrl %r0, gdst64
 ; CHECK: br %r14
-  %val = load i64 *@gsrc64
+  %val = load i64 , i64 *@gsrc64
   store i64 %val, i64 *@gdst64
   ret void
 }
@@ -92,7 +92,7 @@ define i64 @f8() {
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: lgh %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16u, align 1
+  %val = load i16 , i16 *@gsrc16u, align 1
   %ext = sext i16 %val to i64
   ret i64 %ext
 }
@@ -103,7 +103,7 @@ define i64 @f9() {
 ; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
 ; CHECK: llgh %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i16 *@gsrc16u, align 1
+  %val = load i16 , i16 *@gsrc16u, align 1
   %ext = zext i16 %val to i64
   ret i64 %ext
 }
@@ -114,7 +114,7 @@ define i64 @f10() {
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: lgf %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32u, align 2
+  %val = load i32 , i32 *@gsrc32u, align 2
   %ext = sext i32 %val to i64
   ret i64 %ext
 }
@@ -125,7 +125,7 @@ define i64 @f11() {
 ; CHECK: larl [[REG:%r[0-5]]], gsrc32u
 ; CHECK: llgf %r2, 0([[REG]])
 ; CHECK: br %r14
-  %val = load i32 *@gsrc32u, align 2
+  %val = load i32 , i32 *@gsrc32u, align 2
   %ext = zext i32 %val to i64
   ret i64 %ext
 }
@@ -160,7 +160,7 @@ define void @f14() {
 ; CHECK: larl [[REG:%r[0-5]]], gdst64u
 ; CHECK: stg [[VAL]], 0([[REG]])
 ; CHECK: br %r14
-  %val = load i64 *@gsrc64u, align 4
+  %val = load i64 , i64 *@gsrc64u, align 4
   store i64 %val, i64 *@gdst64u, align 4
   ret void
 }