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-rw-r--r--test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll4
-rw-r--r--test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll18
-rw-r--r--test/CodeGen/Thumb2/machine-licm.ll2
-rw-r--r--test/CodeGen/Thumb2/thumb2-barrier.ll31
-rw-r--r--test/CodeGen/Thumb2/thumb2-bcc.ll22
-rw-r--r--test/CodeGen/Thumb2/thumb2-branch.ll18
-rw-r--r--test/CodeGen/Thumb2/thumb2-ifcvt1.ll8
-rw-r--r--test/CodeGen/Thumb2/thumb2-ldm.ll2
-rw-r--r--test/CodeGen/Thumb2/thumb2-mls.ll2
-rw-r--r--test/CodeGen/Thumb2/thumb2-mul.ll2
-rw-r--r--test/CodeGen/Thumb2/thumb2-sxt-uxt.ll29
11 files changed, 66 insertions, 72 deletions
diff --git a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
index 8ca001c..034a28f 100644
--- a/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
+++ b/test/CodeGen/Thumb2/2009-12-01-LoopIVUsers.ll
@@ -6,8 +6,8 @@ entry:
; -- The loop following the load should only use a single add-literation
; instruction.
; CHECK: ldr.64
-; CHECK: adds r{{[0-9]+}}, #1
-; CHECK-NOT: adds r{{[0-9]+}}, #1
+; CHECK: adds r{{[0-9]+.*}}#1
+; CHECK-NOT: adds
; CHECK: subsections_via_symbols
diff --git a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
index f91e1c9..244d0bb 100644
--- a/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
+++ b/test/CodeGen/Thumb2/2010-06-21-TailMergeBug.ll
@@ -32,15 +32,15 @@
define fastcc i32 @parse_percent_token() nounwind {
entry:
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: ittt eq
-; CHECK: moveq r0
-; CHECK-NOT: LBB0_
-; CHECK: ldreq
-; CHECK: popeq
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; CHECK: pop
+; Do not convert into single stream code. BranchProbability Analysis assumes
+; that branches which goes to "ret" intruction have lower probabilities.
switch i32 undef, label %bb7 [
i32 37, label %bb43
i32 48, label %bb5
diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll
index b199d69..46937fc 100644
--- a/test/CodeGen/Thumb2/machine-licm.ll
+++ b/test/CodeGen/Thumb2/machine-licm.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=dynamic-no-pic -disable-fp-elim | FileCheck %s
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
; rdar://7353541
; rdar://7354376
diff --git a/test/CodeGen/Thumb2/thumb2-barrier.ll b/test/CodeGen/Thumb2/thumb2-barrier.ll
deleted file mode 100644
index 93ae7c4..0000000
--- a/test/CodeGen/Thumb2/thumb2-barrier.ll
+++ /dev/null
@@ -1,31 +0,0 @@
-; RUN: llc < %s -march=thumb -mcpu=cortex-a8 | FileCheck %s
-
-declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1)
-
-define void @t_st() {
-; CHECK: t_st:
-; CHECK: dmb st
- call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 true)
- ret void
-}
-
-define void @t_sy() {
-; CHECK: t_sy:
-; CHECK: dmb sy
- call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 true)
- ret void
-}
-
-define void @t_ishst() {
-; CHECK: t_ishst:
-; CHECK: dmb ishst
- call void @llvm.memory.barrier(i1 false, i1 false, i1 false, i1 true, i1 false)
- ret void
-}
-
-define void @t_ish() {
-; CHECK: t_ish:
-; CHECK: dmb ish
- call void @llvm.memory.barrier(i1 true, i1 false, i1 false, i1 true, i1 false)
- ret void
-}
diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll
index 0f76054..4a2d600 100644
--- a/test/CodeGen/Thumb2/thumb2-bcc.ll
+++ b/test/CodeGen/Thumb2/thumb2-bcc.ll
@@ -6,20 +6,18 @@
define i32 @t1(i32 %a, i32 %b, i32 %c) {
; CHECK: t1:
; CHECK: cbz
- %tmp2 = icmp eq i32 %a, 0
- br i1 %tmp2, label %cond_false, label %cond_true
+ %tmp2 = icmp eq i32 %a, 0
+ br i1 %tmp2, label %cond_false, label %cond_true
cond_true:
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
- %tmp5 = add i32 %b, 1
- %tmp6 = and i32 %tmp5, %c
- ret i32 %tmp6
+ fence seq_cst
+ %tmp5 = add i32 %b, 1
+ %tmp6 = and i32 %tmp5, %c
+ ret i32 %tmp6
cond_false:
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
- %tmp7 = add i32 %b, -1
- %tmp8 = xor i32 %tmp7, %c
- ret i32 %tmp8
+ fence seq_cst
+ %tmp7 = add i32 %b, -1
+ %tmp8 = xor i32 %tmp7, %c
+ ret i32 %tmp8
}
-
-declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll
index 4d9eda0..27d8e8f 100644
--- a/test/CodeGen/Thumb2/thumb2-branch.ll
+++ b/test/CodeGen/Thumb2/thumb2-branch.ll
@@ -11,12 +11,12 @@ entry:
br i1 %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ fence seq_cst
store i32 0, i32* %v
ret i32 0
return: ; preds = %entry
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ fence seq_cst
ret i32 1
}
@@ -28,12 +28,12 @@ entry:
br i1 %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ fence seq_cst
store i32 0, i32* %v
ret i32 0
return: ; preds = %entry
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ fence seq_cst
ret i32 1
}
@@ -45,12 +45,12 @@ entry:
br i1 %tmp, label %cond_true, label %return
cond_true: ; preds = %entry
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ fence seq_cst
store i32 0, i32* %v
ret i32 0
return: ; preds = %entry
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ fence seq_cst
ret i32 1
}
@@ -62,13 +62,11 @@ entry:
br i1 %tmp, label %return, label %cond_true
cond_true: ; preds = %entry
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ fence seq_cst
store i32 0, i32* %v
ret i32 0
return: ; preds = %entry
- call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false)
+ fence seq_cst
ret i32 1
}
-
-declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind
diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
index a4035bb..af8fcc6 100644
--- a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
+++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
@@ -21,13 +21,13 @@ cond_next:
ret i32 %tmp15
}
-; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
define i32 @t2(i32 %a, i32 %b) nounwind {
entry:
+; Do not if-convert when branches go to the different loops.
; CHECK: t2:
-; CHECK: ite gt
-; CHECK: subgt
-; CHECK: suble
+; CHECK-NOT: ite gt
+; CHECK-NOT: subgt
+; CHECK-NOT: suble
%tmp1434 = icmp eq i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp1434, label %bb17, label %bb.outer
diff --git a/test/CodeGen/Thumb2/thumb2-ldm.ll b/test/CodeGen/Thumb2/thumb2-ldm.ll
index c5f7e84..4f2b7c1 100644
--- a/test/CodeGen/Thumb2/thumb2-ldm.ll
+++ b/test/CodeGen/Thumb2/thumb2-ldm.ll
@@ -15,7 +15,7 @@ define i32 @t1() {
define i32 @t2() {
; CHECK: t2:
; CHECK: push {r7, lr}
-; CHECK: ldmia
+; CHECK: ldm
; CHECK: pop {r7, pc}
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
diff --git a/test/CodeGen/Thumb2/thumb2-mls.ll b/test/CodeGen/Thumb2/thumb2-mls.ll
index fc9e6ba..24c45c5 100644
--- a/test/CodeGen/Thumb2/thumb2-mls.ll
+++ b/test/CodeGen/Thumb2/thumb2-mls.ll
@@ -15,5 +15,5 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) {
ret i32 %tmp2
}
; CHECK: f2:
-; CHECK: muls r0, r1
+; CHECK: muls r0, r0, r1
diff --git a/test/CodeGen/Thumb2/thumb2-mul.ll b/test/CodeGen/Thumb2/thumb2-mul.ll
index 8d1de55b..bb97d97 100644
--- a/test/CodeGen/Thumb2/thumb2-mul.ll
+++ b/test/CodeGen/Thumb2/thumb2-mul.ll
@@ -2,7 +2,7 @@
define i32 @f1(i32 %a, i32 %b, i32 %c) {
; CHECK: f1:
-; CHECK: muls r0, r1
+; CHECK: muls r0, r0, r1
%tmp = mul i32 %a, %b
ret i32 %tmp
}
diff --git a/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll b/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
new file mode 100644
index 0000000..ab888e6
--- /dev/null
+++ b/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
@@ -0,0 +1,29 @@
+; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s
+
+define i32 @test1(i16 zeroext %z) nounwind {
+; CHECK: test1:
+; CHECK: sxth
+ %r = sext i16 %z to i32
+ ret i32 %r
+}
+
+define i32 @test2(i8 zeroext %z) nounwind {
+; CHECK: test2:
+; CHECK: sxtb
+ %r = sext i8 %z to i32
+ ret i32 %r
+}
+
+define i32 @test3(i16 signext %z) nounwind {
+; CHECK: test3:
+; CHECK: uxth
+ %r = zext i16 %z to i32
+ ret i32 %r
+}
+
+define i32 @test4(i8 signext %z) nounwind {
+; CHECK: test4:
+; CHECK: uxtb
+ %r = zext i8 %z to i32
+ ret i32 %r
+}
generated by cgit v1.1 at 2025-08-15 20:28:07 +0000