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-rw-r--r--test/CodeGen/X86/mmx-fold-load.ll50
1 files changed, 25 insertions, 25 deletions
diff --git a/test/CodeGen/X86/mmx-fold-load.ll b/test/CodeGen/X86/mmx-fold-load.ll
index d49edac..2b9d30f 100644
--- a/test/CodeGen/X86/mmx-fold-load.ll
+++ b/test/CodeGen/X86/mmx-fold-load.ll
@@ -9,8 +9,8 @@ define i64 @t0(<1 x i64>* %a, i32* %b) {
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
- %1 = load x86_mmx* %0, align 8
- %2 = load i32* %b, align 4
+ %1 = load x86_mmx, x86_mmx* %0, align 8
+ %2 = load i32, i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
@@ -26,8 +26,8 @@ define i64 @t1(<1 x i64>* %a, i32* %b) {
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
- %1 = load x86_mmx* %0, align 8
- %2 = load i32* %b, align 4
+ %1 = load x86_mmx, x86_mmx* %0, align 8
+ %2 = load i32, i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrli.q(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
@@ -43,8 +43,8 @@ define i64 @t2(<1 x i64>* %a, i32* %b) {
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
- %1 = load x86_mmx* %0, align 8
- %2 = load i32* %b, align 4
+ %1 = load x86_mmx, x86_mmx* %0, align 8
+ %2 = load i32, i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.pslli.w(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
@@ -60,8 +60,8 @@ define i64 @t3(<1 x i64>* %a, i32* %b) {
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
- %1 = load x86_mmx* %0, align 8
- %2 = load i32* %b, align 4
+ %1 = load x86_mmx, x86_mmx* %0, align 8
+ %2 = load i32, i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
@@ -77,8 +77,8 @@ define i64 @t4(<1 x i64>* %a, i32* %b) {
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
- %1 = load x86_mmx* %0, align 8
- %2 = load i32* %b, align 4
+ %1 = load x86_mmx, x86_mmx* %0, align 8
+ %2 = load i32, i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.pslli.d(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
@@ -94,8 +94,8 @@ define i64 @t5(<1 x i64>* %a, i32* %b) {
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
- %1 = load x86_mmx* %0, align 8
- %2 = load i32* %b, align 4
+ %1 = load x86_mmx, x86_mmx* %0, align 8
+ %2 = load i32, i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrli.d(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
@@ -111,8 +111,8 @@ define i64 @t6(<1 x i64>* %a, i32* %b) {
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
- %1 = load x86_mmx* %0, align 8
- %2 = load i32* %b, align 4
+ %1 = load x86_mmx, x86_mmx* %0, align 8
+ %2 = load i32, i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrai.w(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
@@ -128,8 +128,8 @@ define i64 @t7(<1 x i64>* %a, i32* %b) {
; CHECK-NEXT: retq
entry:
%0 = bitcast <1 x i64>* %a to x86_mmx*
- %1 = load x86_mmx* %0, align 8
- %2 = load i32* %b, align 4
+ %1 = load x86_mmx, x86_mmx* %0, align 8
+ %2 = load i32, i32* %b, align 4
%3 = tail call x86_mmx @llvm.x86.mmx.psrai.d(x86_mmx %1, i32 %2)
%4 = bitcast x86_mmx %3 to i64
ret i64 %4
@@ -144,7 +144,7 @@ define i64 @tt0(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
@@ -161,7 +161,7 @@ define i64 @tt1(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
@@ -177,7 +177,7 @@ define i64 @tt2(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
@@ -193,7 +193,7 @@ define i64 @tt3(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
@@ -209,7 +209,7 @@ define i64 @tt4(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.paddus.b(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
@@ -225,7 +225,7 @@ define i64 @tt5(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.paddus.w(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
@@ -241,7 +241,7 @@ define i64 @tt6(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.psrl.w(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
@@ -257,7 +257,7 @@ define i64 @tt7(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.psrl.d(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
@@ -273,7 +273,7 @@ define i64 @tt8(x86_mmx %t, x86_mmx* %q) {
; CHECK-NEXT: emms
; CHECK-NEXT: retq
entry:
- %v = load x86_mmx* %q
+ %v = load x86_mmx, x86_mmx* %q
%u = tail call x86_mmx @llvm.x86.mmx.psrl.q(x86_mmx %t, x86_mmx %v)
%s = bitcast x86_mmx %u to i64
call void @llvm.x86.mmx.emms()
generated by cgit v1.1 at 2024-05-19 02:41:31 +0000