diff options
Diffstat (limited to 'test/CodeGen/XCore')
30 files changed, 132 insertions, 132 deletions
diff --git a/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll index 84e21e4..2a04963 100644 --- a/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll +++ b/test/CodeGen/XCore/2011-08-01-DynamicAllocBug.ll @@ -13,7 +13,7 @@ allocas: call void @llvm.stackrestore(i8* %0) ret void } -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1] ; CHECK: set sp, [[REGISTER]] ; CHECK: extsp 1 diff --git a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll index 2076057..6445a8f 100644 --- a/test/CodeGen/XCore/2011-08-01-VarargsBug.ll +++ b/test/CodeGen/XCore/2011-08-01-VarargsBug.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=xcore | FileCheck %s define void @_Z1fz(...) { entry: -; CHECK: _Z1fz: +; CHECK-LABEL: _Z1fz: ; CHECK: extsp 3 ; CHECK: stw r[[REG:[0-3]{1,1}]] ; CHECK: , sp{{\[}}[[REG]]{{\]}} diff --git a/test/CodeGen/XCore/addsub64.ll b/test/CodeGen/XCore/addsub64.ll index d062480..89271ce 100644 --- a/test/CodeGen/XCore/addsub64.ll +++ b/test/CodeGen/XCore/addsub64.ll @@ -27,7 +27,7 @@ entry: %3 = add i64 %2, %a ret i64 %3 } -; CHECK: maccu: +; CHECK-LABEL: maccu: ; CHECK: maccu r1, r0, r3, r2 ; CHECK-NEXT: retsp 0 @@ -39,7 +39,7 @@ entry: %3 = add i64 %2, %a ret i64 %3 } -; CHECK: maccs: +; CHECK-LABEL: maccs: ; CHECK: maccs r1, r0, r3, r2 ; CHECK-NEXT: retsp 0 @@ -54,6 +54,6 @@ entry: %6 = add i64 %5, %3 ret i64 %6 } -; CHECK: lmul: +; CHECK-LABEL: lmul: ; CHECK: lmul r1, r0, r1, r0, r2, r3 ; CHECK-NEXT: retsp 0 diff --git a/test/CodeGen/XCore/aliases.ll b/test/CodeGen/XCore/aliases.ll index d83b246..d4da63c 100644 --- a/test/CodeGen/XCore/aliases.ll +++ b/test/CodeGen/XCore/aliases.ll @@ -7,7 +7,7 @@ declare void @a_val() nounwind @b = alias i32* @b_val @c = alias i32* @c_val -; CHECK: a_addr: +; CHECK-LABEL: a_addr: ; CHECK: ldap r11, a ; CHECK: retsp define void ()* @a_addr() nounwind { @@ -15,7 +15,7 @@ entry: ret void ()* @a } -; CHECK: b_addr: +; CHECK-LABEL: b_addr: ; CHECK: ldaw r11, cp[b] ; CHECK: retsp define i32 *@b_addr() nounwind { @@ -23,7 +23,7 @@ entry: ret i32* @b } -; CHECK: c_addr: +; CHECK-LABEL: c_addr: ; CHECK: ldaw r0, dp[c] ; CHECK: retsp define i32 *@c_addr() nounwind { diff --git a/test/CodeGen/XCore/ashr.ll b/test/CodeGen/XCore/ashr.ll index 03b6b1f..2752f52 100644 --- a/test/CodeGen/XCore/ashr.ll +++ b/test/CodeGen/XCore/ashr.ll @@ -3,21 +3,21 @@ define i32 @ashr(i32 %a, i32 %b) { %1 = ashr i32 %a, %b ret i32 %1 } -; CHECK: ashr: +; CHECK-LABEL: ashr: ; CHECK-NEXT: ashr r0, r0, r1 define i32 @ashri1(i32 %a) { %1 = ashr i32 %a, 24 ret i32 %1 } -; CHECK: ashri1: +; CHECK-LABEL: ashri1: ; CHECK-NEXT: ashr r0, r0, 24 define i32 @ashri2(i32 %a) { %1 = ashr i32 %a, 31 ret i32 %1 } -; CHECK: ashri2: +; CHECK-LABEL: ashri2: ; CHECK-NEXT: ashr r0, r0, 32 define i32 @f1(i32 %a) { @@ -28,7 +28,7 @@ less: not_less: ret i32 17 } -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK-NEXT: ashr r0, r0, 32 ; CHECK-NEXT: bt r0 @@ -40,7 +40,7 @@ greater: not_greater: ret i32 17 } -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK-NEXT: ashr r0, r0, 32 ; CHECK-NEXT: bt r0 @@ -49,7 +49,7 @@ define i32 @f3(i32 %a) { %2 = select i1 %1, i32 10, i32 17 ret i32 %2 } -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK-NEXT: ashr r0, r0, 32 ; CHECK-NEXT: bt r0 ; CHECK-NEXT: ldc r0, 17 @@ -60,7 +60,7 @@ define i32 @f4(i32 %a) { %2 = select i1 %1, i32 10, i32 17 ret i32 %2 } -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK-NEXT: ashr r0, r0, 32 ; CHECK-NEXT: bt r0 ; CHECK-NEXT: ldc r0, 10 @@ -71,6 +71,6 @@ define i32 @f5(i32 %a) { %2 = zext i1 %1 to i32 ret i32 %2 } -; CHECK: f5: +; CHECK-LABEL: f5: ; CHECK-NEXT: ashr r0, r0, 32 ; CHECK-NEXT: eq r0, r0, 0 diff --git a/test/CodeGen/XCore/bigstructret.ll b/test/CodeGen/XCore/bigstructret.ll index 56af930..877c571 100644 --- a/test/CodeGen/XCore/bigstructret.ll +++ b/test/CodeGen/XCore/bigstructret.ll @@ -12,7 +12,7 @@ entry: %3 = insertvalue %0 %2, i32 24601, 3 ret %0 %3 } -; CHECK: ReturnBigStruct: +; CHECK-LABEL: ReturnBigStruct: ; CHECK: ldc r0, 12 ; CHECK: ldc r1, 24 ; CHECK: ldc r2, 48 @@ -29,7 +29,7 @@ entry: %4 = insertvalue %1 %3, i32 4321, 4 ret %1 %4 } -; CHECK: ReturnBigStruct2: +; CHECK-LABEL: ReturnBigStruct2: ; CHECK: ldc r1, 4321 ; CHECK: stw r1, r0[4] ; CHECK: ldc r1, 24601 diff --git a/test/CodeGen/XCore/constants.ll b/test/CodeGen/XCore/constants.ll index 1e064f3..c289bf9 100644 --- a/test/CodeGen/XCore/constants.ll +++ b/test/CodeGen/XCore/constants.ll @@ -3,7 +3,7 @@ ; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4 ; CHECK: .LCPI0_0: ; CHECK: .long 12345678 -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: ldw r0, cp[.LCPI0_0] define i32 @f() { entry: @@ -12,7 +12,7 @@ entry: define i32 @g() { entry: -; CHECK: g: +; CHECK-LABEL: g: ; CHECK: mkmsk r0, 1 ; CHECK: retsp 0 ret i32 1; diff --git a/test/CodeGen/XCore/events.ll b/test/CodeGen/XCore/events.ll index 30a6ec3..672669b 100644 --- a/test/CodeGen/XCore/events.ll +++ b/test/CodeGen/XCore/events.ll @@ -6,7 +6,7 @@ declare i8* @llvm.xcore.checkevent(i8*) declare void @llvm.xcore.clre() define i32 @f(i8 addrspace(1)* %r) nounwind { -; CHECK: f: +; CHECK-LABEL: f: entry: ; CHECK: clre call void @llvm.xcore.clre() @@ -25,7 +25,7 @@ ret: } define i32 @g(i8 addrspace(1)* %r) nounwind { -; CHECK: g: +; CHECK-LABEL: g: entry: ; CHECK: clre call void @llvm.xcore.clre() diff --git a/test/CodeGen/XCore/float-intrinsics.ll b/test/CodeGen/XCore/float-intrinsics.ll index 69a40f3..5882036 100644 --- a/test/CodeGen/XCore/float-intrinsics.ll +++ b/test/CodeGen/XCore/float-intrinsics.ll @@ -11,7 +11,7 @@ declare double @llvm.sin.f64(double) declare double @llvm.sqrt.f64(double) define double @cos(double %F) { -; CHECK: cos: +; CHECK-LABEL: cos: ; CHECK: bl cos %result = call double @llvm.cos.f64(double %F) ret double %result @@ -19,7 +19,7 @@ define double @cos(double %F) { declare float @llvm.cos.f32(float) -; CHECK: cosf: +; CHECK-LABEL: cosf: ; CHECK: bl cosf define float @cosf(float %F) { %result = call float @llvm.cos.f32(float %F) @@ -27,7 +27,7 @@ define float @cosf(float %F) { } define double @exp(double %F) { -; CHECK: exp: +; CHECK-LABEL: exp: ; CHECK: bl exp %result = call double @llvm.exp.f64(double %F) ret double %result @@ -36,14 +36,14 @@ define double @exp(double %F) { declare float @llvm.exp.f32(float) define float @expf(float %F) { -; CHECK: expf: +; CHECK-LABEL: expf: ; CHECK: bl expf %result = call float @llvm.exp.f32(float %F) ret float %result } define double @exp2(double %F) { -; CHECK: exp2: +; CHECK-LABEL: exp2: ; CHECK: bl exp2 %result = call double @llvm.exp2.f64(double %F) ret double %result @@ -52,14 +52,14 @@ define double @exp2(double %F) { declare float @llvm.exp2.f32(float) define float @exp2f(float %F) { -; CHECK: exp2f: +; CHECK-LABEL: exp2f: ; CHECK: bl exp2f %result = call float @llvm.exp2.f32(float %F) ret float %result } define double @log(double %F) { -; CHECK: log: +; CHECK-LABEL: log: ; CHECK: bl log %result = call double @llvm.log.f64(double %F) ret double %result @@ -68,14 +68,14 @@ define double @log(double %F) { declare float @llvm.log.f32(float) define float @logf(float %F) { -; CHECK: logf: +; CHECK-LABEL: logf: ; CHECK: bl logf %result = call float @llvm.log.f32(float %F) ret float %result } define double @log10(double %F) { -; CHECK: log10: +; CHECK-LABEL: log10: ; CHECK: bl log10 %result = call double @llvm.log10.f64(double %F) ret double %result @@ -84,14 +84,14 @@ define double @log10(double %F) { declare float @llvm.log10.f32(float) define float @log10f(float %F) { -; CHECK: log10f: +; CHECK-LABEL: log10f: ; CHECK: bl log10f %result = call float @llvm.log10.f32(float %F) ret float %result } define double @log2(double %F) { -; CHECK: log2: +; CHECK-LABEL: log2: ; CHECK: bl log2 %result = call double @llvm.log2.f64(double %F) ret double %result @@ -100,14 +100,14 @@ define double @log2(double %F) { declare float @llvm.log2.f32(float) define float @log2f(float %F) { -; CHECK: log2f: +; CHECK-LABEL: log2f: ; CHECK: bl log2f %result = call float @llvm.log2.f32(float %F) ret float %result } define double @pow(double %F, double %power) { -; CHECK: pow: +; CHECK-LABEL: pow: ; CHECK: bl pow %result = call double @llvm.pow.f64(double %F, double %power) ret double %result @@ -116,14 +116,14 @@ define double @pow(double %F, double %power) { declare float @llvm.pow.f32(float, float) define float @powf(float %F, float %power) { -; CHECK: powf: +; CHECK-LABEL: powf: ; CHECK: bl powf %result = call float @llvm.pow.f32(float %F, float %power) ret float %result } define double @powi(double %F, i32 %power) { -; CHECK: powi: +; CHECK-LABEL: powi: ; CHECK: bl __powidf2 %result = call double @llvm.powi.f64(double %F, i32 %power) ret double %result @@ -132,14 +132,14 @@ define double @powi(double %F, i32 %power) { declare float @llvm.powi.f32(float, i32) define float @powif(float %F, i32 %power) { -; CHECK: powif: +; CHECK-LABEL: powif: ; CHECK: bl __powisf2 %result = call float @llvm.powi.f32(float %F, i32 %power) ret float %result } define double @sin(double %F) { -; CHECK: sin: +; CHECK-LABEL: sin: ; CHECK: bl sin %result = call double @llvm.sin.f64(double %F) ret double %result @@ -148,14 +148,14 @@ define double @sin(double %F) { declare float @llvm.sin.f32(float) define float @sinf(float %F) { -; CHECK: sinf: +; CHECK-LABEL: sinf: ; CHECK: bl sinf %result = call float @llvm.sin.f32(float %F) ret float %result } define double @sqrt(double %F) { -; CHECK: sqrt: +; CHECK-LABEL: sqrt: ; CHECK: bl sqrt %result = call double @llvm.sqrt.f64(double %F) ret double %result @@ -164,7 +164,7 @@ define double @sqrt(double %F) { declare float @llvm.sqrt.f32(float) define float @sqrtf(float %F) { -; CHECK: sqrtf: +; CHECK-LABEL: sqrtf: ; CHECK: bl sqrtf %result = call float @llvm.sqrt.f32(float %F) ret float %result diff --git a/test/CodeGen/XCore/globals.ll b/test/CodeGen/XCore/globals.ll index 7487561..dfa5de6 100644 --- a/test/CodeGen/XCore/globals.ll +++ b/test/CodeGen/XCore/globals.ll @@ -2,21 +2,21 @@ define i32 *@addr_G1() { entry: -; CHECK: addr_G1: +; CHECK-LABEL: addr_G1: ; CHECK: ldaw r0, dp[G1] ret i32* @G1 } define i32 *@addr_G2() { entry: -; CHECK: addr_G2: +; CHECK-LABEL: addr_G2: ; CHECK: ldaw r0, dp[G2] ret i32* @G2 } define i32 *@addr_G3() { entry: -; CHECK: addr_G3: +; CHECK-LABEL: addr_G3: ; CHECK: ldaw r11, cp[G3] ; CHECK: mov r0, r11 ret i32* @G3 @@ -24,14 +24,14 @@ entry: define i32 **@addr_G4() { entry: -; CHECK: addr_G4: +; CHECK-LABEL: addr_G4: ; CHECK: ldaw r0, dp[G4] ret i32** @G4 } define i32 **@addr_G5() { entry: -; CHECK: addr_G5: +; CHECK-LABEL: addr_G5: ; CHECK: ldaw r11, cp[G5] ; CHECK: mov r0, r11 ret i32** @G5 @@ -39,14 +39,14 @@ entry: define i32 **@addr_G6() { entry: -; CHECK: addr_G6: +; CHECK-LABEL: addr_G6: ; CHECK: ldaw r0, dp[G6] ret i32** @G6 } define i32 **@addr_G7() { entry: -; CHECK: addr_G7: +; CHECK-LABEL: addr_G7: ; CHECK: ldaw r11, cp[G7] ; CHECK: mov r0, r11 ret i32** @G7 @@ -54,7 +54,7 @@ entry: define i32 *@addr_G8() { entry: -; CHECK: addr_G8: +; CHECK-LABEL: addr_G8: ; CHECK: ldaw r0, dp[G8] ret i32* @G8 } diff --git a/test/CodeGen/XCore/indirectbr.ll b/test/CodeGen/XCore/indirectbr.ll index 9269002..d7758ea 100644 --- a/test/CodeGen/XCore/indirectbr.ll +++ b/test/CodeGen/XCore/indirectbr.ll @@ -4,7 +4,7 @@ @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] define internal i32 @foo(i32 %i) nounwind { -; CHECK: foo: +; CHECK-LABEL: foo: entry: %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2] %1 = icmp eq i8* %0, null ; <i1> [#uses=1] diff --git a/test/CodeGen/XCore/ladd_lsub_combine.ll b/test/CodeGen/XCore/ladd_lsub_combine.ll index cd89966..b75e30d 100644 --- a/test/CodeGen/XCore/ladd_lsub_combine.ll +++ b/test/CodeGen/XCore/ladd_lsub_combine.ll @@ -8,7 +8,7 @@ entry: %2 = add i64 %1, %0 ; <i64> [#uses=1] ret i64 %2 } -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: ldc r2, 0 ; CHECK-NEXT: ladd r1, r0, r1, r0, r2 ; CHECK-NEXT: retsp 0 @@ -21,7 +21,7 @@ entry: %2 = sub i64 %1, %0 ; <i64> [#uses=1] ret i64 %2 } -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: ldc r2, 0 ; CHECK-NEXT: lsub r1, r0, r1, r0, r2 ; CHECK-NEXT: neg r1, r1 @@ -34,7 +34,7 @@ entry: %1 = add i64 %x, %0 ; <i64> [#uses=1] ret i64 %1 } -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: ldc r3, 0 ; CHECK-NEXT: ladd r2, r0, r0, r2, r3 ; CHECK-NEXT: add r1, r1, r2 @@ -47,7 +47,7 @@ entry: %1 = add i64 %0, %y ; <i64> [#uses=1] ret i64 %1 } -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK: ldc r3, 0 ; CHECK-NEXT: ladd r1, r0, r0, r1, r3 ; CHECK-NEXT: add r1, r2, r1 @@ -60,7 +60,7 @@ entry: %1 = sub i64 %x, %0 ; <i64> [#uses=1] ret i64 %1 } -; CHECK: f5: +; CHECK-LABEL: f5: ; CHECK: ldc r3, 0 ; CHECK-NEXT: lsub r2, r0, r0, r2, r3 ; CHECK-NEXT: sub r1, r1, r2 diff --git a/test/CodeGen/XCore/licm-ldwcp.ll b/test/CodeGen/XCore/licm-ldwcp.ll index 794c6bb..f98c0eb 100644 --- a/test/CodeGen/XCore/licm-ldwcp.ll +++ b/test/CodeGen/XCore/licm-ldwcp.ll @@ -2,7 +2,7 @@ ; MachineLICM should hoist the LDWCP out of the loop. -; CHECK: f: +; CHECK-LABEL: f: ; CHECK-NEXT: ldw [[REG:r[0-9]+]], cp[.LCPI0_0] ; CHECK-NEXT: .LBB0_1: ; CHECK-NEXT: stw [[REG]], r0[0] diff --git a/test/CodeGen/XCore/load.ll b/test/CodeGen/XCore/load.ll index 729fdef..0622f1c 100644 --- a/test/CodeGen/XCore/load.ll +++ b/test/CodeGen/XCore/load.ll @@ -2,7 +2,7 @@ define i32 @load32(i32* %p, i32 %offset) nounwind { entry: -; CHECK: load32: +; CHECK-LABEL: load32: ; CHECK: ldw r0, r0[r1] %0 = getelementptr i32* %p, i32 %offset %1 = load i32* %0, align 4 @@ -11,7 +11,7 @@ entry: define i32 @load32_imm(i32* %p) nounwind { entry: -; CHECK: load32_imm: +; CHECK-LABEL: load32_imm: ; CHECK: ldw r0, r0[11] %0 = getelementptr i32* %p, i32 11 %1 = load i32* %0, align 4 @@ -20,7 +20,7 @@ entry: define i32 @load16(i16* %p, i32 %offset) nounwind { entry: -; CHECK: load16: +; CHECK-LABEL: load16: ; CHECK: ld16s r0, r0[r1] ; CHECK-NOT: sext %0 = getelementptr i16* %p, i32 %offset @@ -31,7 +31,7 @@ entry: define i32 @load8(i8* %p, i32 %offset) nounwind { entry: -; CHECK: load8: +; CHECK-LABEL: load8: ; CHECK: ld8u r0, r0[r1] ; CHECK-NOT: zext %0 = getelementptr i8* %p, i32 %offset @@ -43,7 +43,7 @@ entry: @GConst = external constant i32 define i32 @load_cp() nounwind { entry: -; CHECK: load_cp: +; CHECK-LABEL: load_cp: ; CHECK: ldw r0, cp[GConst] %0 = load i32* @GConst ret i32 %0 diff --git a/test/CodeGen/XCore/misc-intrinsics.ll b/test/CodeGen/XCore/misc-intrinsics.ll index 6d39d77..30d7493 100644 --- a/test/CodeGen/XCore/misc-intrinsics.ll +++ b/test/CodeGen/XCore/misc-intrinsics.ll @@ -10,56 +10,56 @@ declare i32 @llvm.xcore.geted() declare i32 @llvm.xcore.getet() define i32 @bitrev(i32 %val) { -; CHECK: bitrev: +; CHECK-LABEL: bitrev: ; CHECK: bitrev r0, r0 %result = call i32 @llvm.xcore.bitrev(i32 %val) ret i32 %result } define i32 @crc32(i32 %crc, i32 %data, i32 %poly) { -; CHECK: crc32: +; CHECK-LABEL: crc32: ; CHECK: crc32 r0, r1, r2 %result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly) ret i32 %result } define %0 @crc8(i32 %crc, i32 %data, i32 %poly) { -; CHECK: crc8: +; CHECK-LABEL: crc8: ; CHECK: crc8 r0, r1, r1, r2 %result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly) ret %0 %result } define i32 @zext(i32 %a, i32 %b) { -; CHECK: zext: +; CHECK-LABEL: zext: ; CHECK: zext r0, r1 %result = call i32 @llvm.xcore.zext(i32 %a, i32 %b) ret i32 %result } define i32 @zexti(i32 %a) { -; CHECK: zexti: +; CHECK-LABEL: zexti: ; CHECK: zext r0, 4 %result = call i32 @llvm.xcore.zext(i32 %a, i32 4) ret i32 %result } define i32 @sext(i32 %a, i32 %b) { -; CHECK: sext: +; CHECK-LABEL: sext: ; CHECK: sext r0, r1 %result = call i32 @llvm.xcore.sext(i32 %a, i32 %b) ret i32 %result } define i32 @sexti(i32 %a) { -; CHECK: sexti: +; CHECK-LABEL: sexti: ; CHECK: sext r0, 4 %result = call i32 @llvm.xcore.sext(i32 %a, i32 4) ret i32 %result } define i32 @geted() { -; CHECK: geted: +; CHECK-LABEL: geted: ; CHECK: get r11, ed ; CHECK-NEXT: mov r0, r11 %result = call i32 @llvm.xcore.geted() @@ -67,7 +67,7 @@ define i32 @geted() { } define i32 @getet() { -; CHECK: getet: +; CHECK-LABEL: getet: ; CHECK: get r11, et ; CHECK-NEXT: mov r0, r11 %result = call i32 @llvm.xcore.getet() diff --git a/test/CodeGen/XCore/mkmsk.ll b/test/CodeGen/XCore/mkmsk.ll index 377612b..bcec32d 100644 --- a/test/CodeGen/XCore/mkmsk.ll +++ b/test/CodeGen/XCore/mkmsk.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=xcore | FileCheck %s define i32 @f(i32) nounwind { -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: mkmsk r0, r0 ; CHECK-NEXT: retsp 0 entry: diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll index 3d373b1..cfc9855 100644 --- a/test/CodeGen/XCore/mul64.ll +++ b/test/CodeGen/XCore/mul64.ll @@ -7,7 +7,7 @@ entry: %2 = mul i64 %1, %0 ret i64 %2 } -; CHECK: umul_lohi: +; CHECK-LABEL: umul_lohi: ; CHECK: ldc [[REG:r[0-9]+]], 0 ; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]] ; CHECK-NEXT: retsp 0 @@ -19,7 +19,7 @@ entry: %2 = mul i64 %1, %0 ret i64 %2 } -; CHECK: smul_lohi: +; CHECK-LABEL: smul_lohi: ; CHECK: ldc ; CHECK-NEXT: mov ; CHECK-NEXT: maccs @@ -30,7 +30,7 @@ entry: %0 = mul i64 %a, %b ret i64 %0 } -; CHECK: mul64: +; CHECK-LABEL: mul64: ; CHECK: ldc ; CHECK-NEXT: lmul ; CHECK-NEXT: mul @@ -42,7 +42,7 @@ entry: %1 = mul i64 %a, %0 ret i64 %1 } -; CHECK: mul64_2: +; CHECK-LABEL: mul64_2: ; CHECK: ldc ; CHECK-NEXT: lmul ; CHECK-NEXT: mul diff --git a/test/CodeGen/XCore/offset_folding.ll b/test/CodeGen/XCore/offset_folding.ll index 30edfe6..8085a0f 100644 --- a/test/CodeGen/XCore/offset_folding.ll +++ b/test/CodeGen/XCore/offset_folding.ll @@ -5,7 +5,7 @@ define i32 *@f1() nounwind { entry: -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: ldaw r11, cp[a+4] ; CHECK: mov r0, r11 %0 = getelementptr [0 x i32]* @a, i32 0, i32 1 @@ -14,7 +14,7 @@ entry: define i32 *@f2() nounwind { entry: -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: ldaw r0, dp[b+4] %0 = getelementptr [0 x i32]* @b, i32 0, i32 1 ret i32* %0 @@ -25,7 +25,7 @@ entry: define i32 *@f3() nounwind { entry: -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: ldaw r11, cp[a] ; CHECK: sub r0, r11, 4 %0 = getelementptr [0 x i32]* @a, i32 0, i32 -1 @@ -34,7 +34,7 @@ entry: define i32 *@f4() nounwind { entry: -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK: ldaw [[REG:r[0-9]+]], dp[b] ; CHECK: sub r0, [[REG]], 4 %0 = getelementptr [0 x i32]* @b, i32 0, i32 -1 diff --git a/test/CodeGen/XCore/private.ll b/test/CodeGen/XCore/private.ll index 80b7db4..474448a 100644 --- a/test/CodeGen/XCore/private.ll +++ b/test/CodeGen/XCore/private.ll @@ -10,7 +10,7 @@ define private void @foo() { @baz = private global i32 4 define i32 @bar() { -; CHECK: bar: +; CHECK-LABEL: bar: ; CHECK: bl .Lfoo ; CHECK: ldw r0, dp[.Lbaz] call void @foo() diff --git a/test/CodeGen/XCore/ps-intrinsics.ll b/test/CodeGen/XCore/ps-intrinsics.ll index 92b26c7..02609ed 100644 --- a/test/CodeGen/XCore/ps-intrinsics.ll +++ b/test/CodeGen/XCore/ps-intrinsics.ll @@ -3,7 +3,7 @@ declare i32 @llvm.xcore.getps(i32) declare void @llvm.xcore.setps(i32, i32) define i32 @getps(i32 %reg) nounwind { -; CHECK: getps: +; CHECK-LABEL: getps: ; CHECK: get r0, ps[r0] %result = call i32 @llvm.xcore.getps(i32 %reg) ret i32 %result @@ -11,7 +11,7 @@ define i32 @getps(i32 %reg) nounwind { define void @setps(i32 %reg, i32 %value) nounwind { -; CHECK: setps: +; CHECK-LABEL: setps: ; CHECK: set ps[r0], r1 call void @llvm.xcore.setps(i32 %reg, i32 %value) ret void diff --git a/test/CodeGen/XCore/resources.ll b/test/CodeGen/XCore/resources.ll index 74511ad..5385010 100644 --- a/test/CodeGen/XCore/resources.ll +++ b/test/CodeGen/XCore/resources.ll @@ -29,147 +29,147 @@ declare i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r) declare i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r) define i8 addrspace(1)* @getr() { -; CHECK: getr: +; CHECK-LABEL: getr: ; CHECK: getr r0, 5 %result = call i8 addrspace(1)* @llvm.xcore.getr.p1i8(i32 5) ret i8 addrspace(1)* %result } define void @freer(i8 addrspace(1)* %r) { -; CHECK: freer: +; CHECK-LABEL: freer: ; CHECK: freer res[r0] call void @llvm.xcore.freer.p1i8(i8 addrspace(1)* %r) ret void } define i32 @in(i8 addrspace(1)* %r) { -; CHECK: in: +; CHECK-LABEL: in: ; CHECK: in r0, res[r0] %result = call i32 @llvm.xcore.in.p1i8(i8 addrspace(1)* %r) ret i32 %result } define i32 @int(i8 addrspace(1)* %r) { -; CHECK: int: +; CHECK-LABEL: int: ; CHECK: int r0, res[r0] %result = call i32 @llvm.xcore.int.p1i8(i8 addrspace(1)* %r) ret i32 %result } define i32 @inct(i8 addrspace(1)* %r) { -; CHECK: inct: +; CHECK-LABEL: inct: ; CHECK: inct r0, res[r0] %result = call i32 @llvm.xcore.inct.p1i8(i8 addrspace(1)* %r) ret i32 %result } define void @out(i8 addrspace(1)* %r, i32 %value) { -; CHECK: out: +; CHECK-LABEL: out: ; CHECK: out res[r0], r1 call void @llvm.xcore.out.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } define void @outt(i8 addrspace(1)* %r, i32 %value) { -; CHECK: outt: +; CHECK-LABEL: outt: ; CHECK: outt res[r0], r1 call void @llvm.xcore.outt.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } define void @outct(i8 addrspace(1)* %r, i32 %value) { -; CHECK: outct: +; CHECK-LABEL: outct: ; CHECK: outct res[r0], r1 call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } define void @outcti(i8 addrspace(1)* %r) { -; CHECK: outcti: +; CHECK-LABEL: outcti: ; CHECK: outct res[r0], 11 call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 11) ret void } define void @chkct(i8 addrspace(1)* %r, i32 %value) { -; CHECK: chkct: +; CHECK-LABEL: chkct: ; CHECK: chkct res[r0], r1 call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } define void @chkcti(i8 addrspace(1)* %r) { -; CHECK: chkcti: +; CHECK-LABEL: chkcti: ; CHECK: chkct res[r0], 11 call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 11) ret void } define void @setd(i8 addrspace(1)* %r, i32 %value) { -; CHECK: setd: +; CHECK-LABEL: setd: ; CHECK: setd res[r0], r1 call void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } define void @setc(i8 addrspace(1)* %r, i32 %value) { -; CHECK: setc: +; CHECK-LABEL: setc: ; CHECK: setc res[r0], r1 call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } define void @setci(i8 addrspace(1)* %r) { -; CHECK: setci: +; CHECK-LABEL: setci: ; CHECK: setc res[r0], 2 call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 2) ret void } define i32 @inshr(i32 %value, i8 addrspace(1)* %r) { -; CHECK: inshr: +; CHECK-LABEL: inshr: ; CHECK: inshr r0, res[r1] %result = call i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value) ret i32 %result } define i32 @outshr(i32 %value, i8 addrspace(1)* %r) { -; CHECK: outshr: +; CHECK-LABEL: outshr: ; CHECK: outshr res[r1], r0 %result = call i32 @llvm.xcore.outshr.p1i8(i8 addrspace(1)* %r, i32 %value) ret i32 %result } define void @setpt(i8 addrspace(1)* %r, i32 %value) { -; CHECK: setpt: +; CHECK-LABEL: setpt: ; CHECK: setpt res[r0], r1 call void @llvm.xcore.setpt.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } define i32 @getts(i8 addrspace(1)* %r) { -; CHECK: getts: +; CHECK-LABEL: getts: ; CHECK: getts r0, res[r0] %result = call i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r) ret i32 %result } define void @syncr(i8 addrspace(1)* %r) { -; CHECK: syncr: +; CHECK-LABEL: syncr: ; CHECK: syncr res[r0] call void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r) ret void } define void @settw(i8 addrspace(1)* %r, i32 %value) { -; CHECK: settw: +; CHECK-LABEL: settw: ; CHECK: settw res[r0], r1 call void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value) ret void } define void @setv(i8 addrspace(1)* %r, i8* %p) { -; CHECK: setv: +; CHECK-LABEL: setv: ; CHECK: mov r11, r1 ; CHECK-NEXT: setv res[r0], r11 call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p) @@ -177,7 +177,7 @@ define void @setv(i8 addrspace(1)* %r, i8* %p) { } define void @setev(i8 addrspace(1)* %r, i8* %p) { -; CHECK: setev: +; CHECK-LABEL: setev: ; CHECK: mov r11, r1 ; CHECK-NEXT: setev res[r0], r11 call void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p) @@ -185,7 +185,7 @@ define void @setev(i8 addrspace(1)* %r, i8* %p) { } define void @eeu(i8 addrspace(1)* %r) { -; CHECK: eeu: +; CHECK-LABEL: eeu: ; CHECK: eeu res[r0] call void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r) ret void @@ -213,14 +213,14 @@ define void @setpsc(i8 addrspace(1)* %r, i32 %value) { } define i32 @peek(i8 addrspace(1)* %r) { -; CHECK: peek: +; CHECK-LABEL: peek: ; CHECK: peek r0, res[r0] %result = call i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r) ret i32 %result } define i32 @endin(i8 addrspace(1)* %r) { -; CHECK: endin: +; CHECK-LABEL: endin: ; CHECK: endin r0, res[r0] %result = call i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r) ret i32 %result diff --git a/test/CodeGen/XCore/sext.ll b/test/CodeGen/XCore/sext.ll index 9cd4ad6..b3e66ec 100644 --- a/test/CodeGen/XCore/sext.ll +++ b/test/CodeGen/XCore/sext.ll @@ -4,7 +4,7 @@ define i32 @sext1(i32 %a) { %2 = sext i1 %1 to i32 ret i32 %2 } -; CHECK: sext1: +; CHECK-LABEL: sext1: ; CHECK: sext r0, 1 define i32 @sext2(i32 %a) { @@ -12,7 +12,7 @@ define i32 @sext2(i32 %a) { %2 = sext i2 %1 to i32 ret i32 %2 } -; CHECK: sext2: +; CHECK-LABEL: sext2: ; CHECK: sext r0, 2 define i32 @sext8(i32 %a) { @@ -20,7 +20,7 @@ define i32 @sext8(i32 %a) { %2 = sext i8 %1 to i32 ret i32 %2 } -; CHECK: sext8: +; CHECK-LABEL: sext8: ; CHECK: sext r0, 8 define i32 @sext16(i32 %a) { @@ -28,5 +28,5 @@ define i32 @sext16(i32 %a) { %2 = sext i16 %1 to i32 ret i32 %2 } -; CHECK: sext16: +; CHECK-LABEL: sext16: ; CHECK: sext r0, 16 diff --git a/test/CodeGen/XCore/sr-intrinsics.ll b/test/CodeGen/XCore/sr-intrinsics.ll index e12ed03..2c4175d 100644 --- a/test/CodeGen/XCore/sr-intrinsics.ll +++ b/test/CodeGen/XCore/sr-intrinsics.ll @@ -3,7 +3,7 @@ declare void @llvm.xcore.setsr(i32) declare void @llvm.xcore.clrsr(i32) define void @setsr() nounwind { -; CHECK: setsr: +; CHECK-LABEL: setsr: ; CHECK: setsr 128 call void @llvm.xcore.setsr(i32 128) ret void @@ -11,7 +11,7 @@ define void @setsr() nounwind { define void @clrsr() nounwind { -; CHECK: clrsr: +; CHECK-LABEL: clrsr: ; CHECK: clrsr 128 call void @llvm.xcore.clrsr(i32 128) ret void diff --git a/test/CodeGen/XCore/store.ll b/test/CodeGen/XCore/store.ll index 836b125..87553d8 100644 --- a/test/CodeGen/XCore/store.ll +++ b/test/CodeGen/XCore/store.ll @@ -2,7 +2,7 @@ define void @store32(i32* %p, i32 %offset, i32 %val) nounwind { entry: -; CHECK: store32: +; CHECK-LABEL: store32: ; CHECK: stw r2, r0[r1] %0 = getelementptr i32* %p, i32 %offset store i32 %val, i32* %0, align 4 @@ -11,7 +11,7 @@ entry: define void @store32_imm(i32* %p, i32 %val) nounwind { entry: -; CHECK: store32_imm: +; CHECK-LABEL: store32_imm: ; CHECK: stw r1, r0[11] %0 = getelementptr i32* %p, i32 11 store i32 %val, i32* %0, align 4 @@ -20,7 +20,7 @@ entry: define void @store16(i16* %p, i32 %offset, i16 %val) nounwind { entry: -; CHECK: store16: +; CHECK-LABEL: store16: ; CHECK: st16 r2, r0[r1] %0 = getelementptr i16* %p, i32 %offset store i16 %val, i16* %0, align 2 @@ -29,7 +29,7 @@ entry: define void @store8(i8* %p, i32 %offset, i8 %val) nounwind { entry: -; CHECK: store8: +; CHECK-LABEL: store8: ; CHECK: st8 r2, r0[r1] %0 = getelementptr i8* %p, i32 %offset store i8 %val, i8* %0, align 1 diff --git a/test/CodeGen/XCore/threads.ll b/test/CodeGen/XCore/threads.ll index a0558e3..9602623 100644 --- a/test/CodeGen/XCore/threads.ll +++ b/test/CodeGen/XCore/threads.ll @@ -11,56 +11,56 @@ declare void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %r, i8* %value) declare void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %r, i8* %value) define i8 addrspace(1)* @getst(i8 addrspace(1)* %r) { -; CHECK: getst: +; CHECK-LABEL: getst: ; CHECK: getst r0, res[r0] %result = call i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r) ret i8 addrspace(1)* %result } define void @ssync() { -; CHECK: ssync: +; CHECK-LABEL: ssync: ; CHECK: ssync call void @llvm.xcore.ssync() ret void } define void @mjoin(i8 addrspace(1)* %r) { -; CHECK: mjoin: +; CHECK-LABEL: mjoin: ; CHECK: mjoin res[r0] call void @llvm.xcore.mjoin.p1i8(i8 addrspace(1)* %r) ret void } define void @initsp(i8 addrspace(1)* %t, i8* %src) { -; CHECK: initsp: +; CHECK-LABEL: initsp: ; CHECK: init t[r0]:sp, r1 call void @llvm.xcore.initsp.p1i8(i8 addrspace(1)* %t, i8* %src) ret void } define void @initpc(i8 addrspace(1)* %t, i8* %src) { -; CHECK: initpc: +; CHECK-LABEL: initpc: ; CHECK: init t[r0]:pc, r1 call void @llvm.xcore.initpc.p1i8(i8 addrspace(1)* %t, i8* %src) ret void } define void @initlr(i8 addrspace(1)* %t, i8* %src) { -; CHECK: initlr: +; CHECK-LABEL: initlr: ; CHECK: init t[r0]:lr, r1 call void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %t, i8* %src) ret void } define void @initcp(i8 addrspace(1)* %t, i8* %src) { -; CHECK: initcp: +; CHECK-LABEL: initcp: ; CHECK: init t[r0]:cp, r1 call void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %t, i8* %src) ret void } define void @initdp(i8 addrspace(1)* %t, i8* %src) { -; CHECK: initdp: +; CHECK-LABEL: initdp: ; CHECK: init t[r0]:dp, r1 call void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %t, i8* %src) ret void diff --git a/test/CodeGen/XCore/tls.ll b/test/CodeGen/XCore/tls.ll index ed41afa..648d611 100644 --- a/test/CodeGen/XCore/tls.ll +++ b/test/CodeGen/XCore/tls.ll @@ -2,7 +2,7 @@ define i32 *@addr_G() { entry: -; CHECK: addr_G: +; CHECK-LABEL: addr_G: ; CHECK: get r11, id ret i32* @G } diff --git a/test/CodeGen/XCore/trampoline.ll b/test/CodeGen/XCore/trampoline.ll index 6b42134..7ca331a 100644 --- a/test/CodeGen/XCore/trampoline.ll +++ b/test/CodeGen/XCore/trampoline.ll @@ -4,7 +4,7 @@ define void @f() nounwind { entry: -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: ldap r11, g.1101 ; CHECK: stw r11, sp[7] %TRAMP.23 = alloca [20 x i8], align 2 diff --git a/test/CodeGen/XCore/unaligned_load.ll b/test/CodeGen/XCore/unaligned_load.ll index 772a847..b8b8827 100644 --- a/test/CodeGen/XCore/unaligned_load.ll +++ b/test/CodeGen/XCore/unaligned_load.ll @@ -10,7 +10,7 @@ entry: } ; Half word aligned load. -; CHECK: align2: +; CHECK-LABEL: align2: ; CHECK: ld16s ; CHECK: ld16s ; CHECK: or @@ -23,7 +23,7 @@ entry: @a = global [5 x i8] zeroinitializer, align 4 ; Constant offset from word aligned base. -; CHECK: align3: +; CHECK-LABEL: align3: ; CHECK: ldw {{r[0-9]+}}, dp ; CHECK: ldw {{r[0-9]+}}, dp ; CHECK: or diff --git a/test/CodeGen/XCore/unaligned_store.ll b/test/CodeGen/XCore/unaligned_store.ll index 94e1852..27b4280 100644 --- a/test/CodeGen/XCore/unaligned_store.ll +++ b/test/CodeGen/XCore/unaligned_store.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=xcore | FileCheck %s ; Byte aligned store. -; CHECK: align1: +; CHECK-LABEL: align1: ; CHECK: bl __misaligned_store define void @align1(i32* %p, i32 %val) nounwind { entry: diff --git a/test/CodeGen/XCore/unaligned_store_combine.ll b/test/CodeGen/XCore/unaligned_store_combine.ll index c997b78..d1f4e6c 100644 --- a/test/CodeGen/XCore/unaligned_store_combine.ll +++ b/test/CodeGen/XCore/unaligned_store_combine.ll @@ -4,7 +4,7 @@ ; of size 8 define void @f(i64* %dst, i64* %src) nounwind { entry: -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: ldc r2, 8 ; CHECK: bl memmove %0 = load i64* %src, align 1 |