diff options
Diffstat (limited to 'test/CodeGen')
389 files changed, 7274 insertions, 4866 deletions
diff --git a/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll b/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll deleted file mode 100644 index 76fa364..0000000 --- a/test/CodeGen/ARM/2007-03-26-RegScavengerAssert.ll +++ /dev/null @@ -1,947 +0,0 @@ -; RUN: llc < %s -march=arm -; PR1266 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "arm-unknown-linux-gnueabi" - %struct.CUMULATIVE_ARGS = type { i32, i32, i32, i32, i32, i32 } - %struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i32, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i32, [52 x i8] } - %struct.VEC_edge = type { i32, i32, [1 x %struct.edge_def*] } - %struct.VEC_tree = type { i32, i32, [1 x %struct.tree_node*] } - %struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 } - %struct._obstack_chunk = type { i8*, %struct._obstack_chunk*, [4 x i8] } - %struct.addr_diff_vec_flags = type { i8, i8, i8, i8 } - %struct.arm_stack_offsets = type { i32, i32, i32, i32, i32 } - %struct.attribute_spec = type { i8*, i32, i32, i8, i8, i8, %struct.tree_node* (%struct.tree_node**, %struct.tree_node*, %struct.tree_node*, i32, i8*)* } - %struct.basic_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.tree_node*, %struct.VEC_edge*, %struct.VEC_edge*, %struct.bitmap_head_def*, %struct.bitmap_head_def*, i8*, %struct.loop*, [2 x %struct.et_node*], %struct.basic_block_def*, %struct.basic_block_def*, %struct.reorder_block_def*, %struct.bb_ann_d*, i64, i32, i32, i32, i32 } - %struct.bb_ann_d = type { %struct.tree_node*, i8, %struct.edge_prediction* } - %struct.bitmap_element_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, [4 x i32] } - %struct.bitmap_head_def = type { %struct.bitmap_element_def*, %struct.bitmap_element_def*, i32, %struct.bitmap_obstack* } - %struct.bitmap_obstack = type { %struct.bitmap_element_def*, %struct.bitmap_head_def*, %struct.obstack } - %struct.cgraph_edge = type { %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_edge*, %struct.cgraph_edge*, %struct.cgraph_edge*, %struct.cgraph_edge*, %struct.tree_node*, i8*, i8* } - %struct.cgraph_global_info = type { %struct.cgraph_node*, i32, i8 } - %struct.cgraph_local_info = type { i32, i8, i8, i8, i8, i8, i8, i8 } - %struct.cgraph_node = type { %struct.tree_node*, %struct.cgraph_edge*, %struct.cgraph_edge*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, %struct.cgraph_node*, i8*, %struct.cgraph_local_info, %struct.cgraph_global_info, %struct.cgraph_rtl_info, i32, i8, i8, i8, i8, i8 } - %struct.cgraph_rtl_info = type { i32, i8, i8 } - %struct.cl_perfunc_opts = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32 } - %struct.cselib_val_struct = type opaque - %struct.dataflow_d = type { %struct.varray_head_tag*, [2 x %struct.tree_node*] } - %struct.def_operand_ptr = type { %struct.tree_node** } - %struct.def_optype_d = type { i32, [1 x %struct.def_operand_ptr] } - %struct.diagnostic_context = type { %struct.pretty_printer*, [8 x i32], i8, i8, i8, void (%struct.diagnostic_context*, %struct.diagnostic_info*)*, void (%struct.diagnostic_context*, %struct.diagnostic_info*)*, void (i8*, i8**)*, %struct.tree_node*, i32, i32 } - %struct.diagnostic_info = type { %struct.text_info, %struct.location_t, i32 } - %struct.die_struct = type opaque - %struct.edge_def = type { %struct.basic_block_def*, %struct.basic_block_def*, %struct.edge_def_insns, i8*, %struct.location_t*, i32, i32, i64, i32 } - %struct.edge_def_insns = type { %struct.rtx_def* } - %struct.edge_prediction = type { %struct.edge_prediction*, %struct.edge_def*, i32, i32 } - %struct.eh_status = type opaque - %struct.elt_list = type opaque - %struct.elt_t = type { %struct.tree_node*, %struct.tree_node* } - %struct.emit_status = type { i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack*, i32, %struct.location_t, i32, i8*, %struct.rtx_def** } - %struct.et_node = type opaque - %struct.expr_status = type { i32, i32, i32, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def* } - %struct.function = type { %struct.eh_status*, %struct.expr_status*, %struct.emit_status*, %struct.varasm_status*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.function*, i32, i32, i32, i32, %struct.rtx_def*, %struct.CUMULATIVE_ARGS, %struct.rtx_def*, %struct.rtx_def*, %struct.initial_value_struct*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, %struct.rtx_def*, i8, i32, i64, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, %struct.varray_head_tag*, %struct.temp_slot*, i32, %struct.var_refs_queue*, i32, i32, %struct.rtvec_def*, %struct.tree_node*, i32, i32, i32, %struct.machine_function*, i32, i32, i8, i8, %struct.language_function*, %struct.rtx_def*, i32, i32, i32, i32, %struct.location_t, %struct.varray_head_tag*, %struct.tree_node*, i8, i8, i8 } - %struct.ggc_root_tab = type { i8*, i32, i32, void (i8*)*, void (i8*)* } - %struct.gimplify_ctx = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.varray_head_tag*, %struct.htab*, i32, i8, i8 } - %struct.gimplify_init_ctor_preeval_data = type { %struct.tree_node*, i32 } - %struct.ht_identifier = type { i8*, i32, i32 } - %struct.htab = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i32, i32, i32, i32, i32, i8* (i32, i32)*, void (i8*)*, i8*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i32 } - %struct.initial_value_struct = type opaque - %struct.lang_decl = type opaque - %struct.lang_hooks = type { i8*, i32, i32 (i32)*, i32 (i32, i8**)*, void (%struct.diagnostic_context*)*, i32 (i32, i8*, i32)*, i8 (i8*, i32) zeroext *, i8 (i8**) zeroext *, i8 () zeroext *, void ()*, void ()*, void (i32)*, void ()*, i64 (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, %struct.rtx_def* (%struct.tree_node*, %struct.rtx_def*, i32, i32, %struct.rtx_def**)*, i32 (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, i32 (%struct.rtx_def*, %struct.tree_node*)*, void (%struct.tree_node*)*, i8 (%struct.tree_node*) zeroext *, %struct.tree_node* (%struct.tree_node*)*, void (%struct.tree_node*)*, void (%struct.tree_node*)*, i8 () zeroext *, i8, i8, void ()*, void (%struct.FILE*, %struct.tree_node*, i32)*, void (%struct.FILE*, %struct.tree_node*, i32)*, void (%struct.FILE*, %struct.tree_node*, i32)*, void (%struct.FILE*, %struct.tree_node*, i32)*, i8* (%struct.tree_node*, i32)*, i32 (%struct.tree_node*, %struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, void (%struct.diagnostic_context*, i8*)*, %struct.tree_node* (%struct.tree_node*)*, i64 (i64)*, %struct.attribute_spec*, %struct.attribute_spec*, %struct.attribute_spec*, i32 (%struct.tree_node*)*, %struct.lang_hooks_for_functions, %struct.lang_hooks_for_tree_inlining, %struct.lang_hooks_for_callgraph, %struct.lang_hooks_for_tree_dump, %struct.lang_hooks_for_decls, %struct.lang_hooks_for_types, i32 (%struct.tree_node**, %struct.tree_node**, %struct.tree_node**)*, %struct.tree_node* (%struct.tree_node*, %struct.tree_node*)*, %struct.tree_node* (i8*, %struct.tree_node*, i32, i32, i8*, %struct.tree_node*)* } - %struct.lang_hooks_for_callgraph = type { %struct.tree_node* (%struct.tree_node**, i32*, %struct.tree_node*)*, void (%struct.tree_node*)* } - %struct.lang_hooks_for_decls = type { i32 ()*, void (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, %struct.tree_node* ()*, i8 (%struct.tree_node*) zeroext *, void ()*, void (%struct.tree_node*)*, i8 (%struct.tree_node*) zeroext *, i8* (%struct.tree_node*)* } - %struct.lang_hooks_for_functions = type { void (%struct.function*)*, void (%struct.function*)*, void (%struct.function*)*, void (%struct.function*)*, i8 (%struct.tree_node*) zeroext * } - %struct.lang_hooks_for_tree_dump = type { i8 (i8*, %struct.tree_node*) zeroext *, i32 (%struct.tree_node*)* } - %struct.lang_hooks_for_tree_inlining = type { %struct.tree_node* (%struct.tree_node**, i32*, %struct.tree_node* (%struct.tree_node**, i32*, i8*)*, i8*, %struct.pointer_set_t*)*, i32 (%struct.tree_node**)*, i32 (%struct.tree_node*)*, %struct.tree_node* (i8*, %struct.tree_node*)*, i32 (%struct.tree_node*, %struct.tree_node*)*, i32 (%struct.tree_node*)*, i8 (%struct.tree_node*, %struct.tree_node*) zeroext *, i32 (%struct.tree_node*)*, void (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32)* } - %struct.lang_hooks_for_types = type { %struct.tree_node* (i32)*, %struct.tree_node* (i32, i32)*, %struct.tree_node* (i32, i32)*, %struct.tree_node* (%struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, %struct.tree_node* (i32, %struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, void (%struct.tree_node*, i8*)*, void (%struct.tree_node*, %struct.tree_node*)*, %struct.tree_node* (%struct.tree_node*)*, i8 } - %struct.lang_type = type opaque - %struct.language_function = type opaque - %struct.location_t = type { i8*, i32 } - %struct.loop = type opaque - %struct.machine_function = type { %struct.rtx_def*, i32, i32, i32, %struct.arm_stack_offsets, i32, i32, i32, [14 x %struct.rtx_def*] } - %struct.mem_attrs = type { i64, %struct.tree_node*, %struct.rtx_def*, %struct.rtx_def*, i32 } - %struct.obstack = type { i32, %struct._obstack_chunk*, i8*, i8*, i8*, i32, i32, %struct._obstack_chunk* (i8*, i32)*, void (i8*, %struct._obstack_chunk*)*, i8*, i8 } - %struct.output_buffer = type { %struct.obstack, %struct.FILE*, i32, [128 x i8] } - %struct.phi_arg_d = type { %struct.tree_node*, i8 } - %struct.pointer_set_t = type opaque - %struct.pretty_printer = type { %struct.output_buffer*, i8*, i32, i32, i32, i32, i32, i8 (%struct.pretty_printer*, %struct.text_info*) zeroext *, i8, i8 } - %struct.ptr_info_def = type { i8, %struct.bitmap_head_def*, %struct.tree_node* } - %struct.real_value = type { i8, [3 x i8], [5 x i32] } - %struct.reg_attrs = type { %struct.tree_node*, i64 } - %struct.reg_info_def = type opaque - %struct.reorder_block_def = type { %struct.rtx_def*, %struct.rtx_def*, %struct.basic_block_def*, %struct.basic_block_def*, %struct.basic_block_def*, i32, i32, i32 } - %struct.rtunion = type { i32 } - %struct.rtvec_def = type { i32, [1 x %struct.rtx_def*] } - %struct.rtx_def = type { i16, i8, i8, %struct.u } - %struct.sequence_stack = type { %struct.rtx_def*, %struct.rtx_def*, %struct.sequence_stack* } - %struct.stmt_ann_d = type { %struct.tree_ann_common_d, i8, %struct.basic_block_def*, %struct.stmt_operands_d, %struct.dataflow_d*, %struct.bitmap_head_def*, i32 } - %struct.stmt_operands_d = type { %struct.def_optype_d*, %struct.def_optype_d*, %struct.v_may_def_optype_d*, %struct.vuse_optype_d*, %struct.v_may_def_optype_d* } - %struct.temp_slot = type opaque - %struct.text_info = type { i8*, i8**, i32 } - %struct.tree_ann_common_d = type { i32, i8*, %struct.tree_node* } - %struct.tree_ann_d = type { %struct.stmt_ann_d } - %struct.tree_binfo = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.VEC_tree*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.VEC_tree } - %struct.tree_block = type { %struct.tree_common, i8, [3 x i8], %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node* } - %struct.tree_common = type { %struct.tree_node*, %struct.tree_node*, %struct.tree_ann_d*, i8, i8, i8, i8, i8 } - %struct.tree_complex = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* } - %struct.tree_decl = type { %struct.tree_common, %struct.location_t, i32, %struct.tree_node*, i8, i8, i8, i8, i8, i8, i8, i8, i32, %struct.tree_decl_u1, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.rtx_def*, i32, %struct.tree_decl_u2, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_decl* } - %struct.tree_decl_u1 = type { i64 } - %struct.tree_decl_u1_a = type { i32 } - %struct.tree_decl_u2 = type { %struct.function* } - %struct.tree_exp = type { %struct.tree_common, %struct.location_t*, i32, %struct.tree_node*, [1 x %struct.tree_node*] } - %struct.tree_identifier = type { %struct.tree_common, %struct.ht_identifier } - %struct.tree_int_cst = type { %struct.tree_common, %struct.tree_int_cst_lowhi } - %struct.tree_int_cst_lowhi = type { i64, i64 } - %struct.tree_list = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node* } - %struct.tree_node = type { %struct.tree_decl } - %struct.tree_phi_node = type { %struct.tree_common, %struct.tree_node*, i32, i32, i32, %struct.basic_block_def*, %struct.dataflow_d*, [1 x %struct.phi_arg_d] } - %struct.tree_real_cst = type { %struct.tree_common, %struct.real_value* } - %struct.tree_ssa_name = type { %struct.tree_common, %struct.tree_node*, i32, %struct.ptr_info_def*, %struct.tree_node*, i8* } - %struct.tree_statement_list = type { %struct.tree_common, %struct.tree_statement_list_node*, %struct.tree_statement_list_node* } - %struct.tree_statement_list_node = type { %struct.tree_statement_list_node*, %struct.tree_statement_list_node*, %struct.tree_node* } - %struct.tree_stmt_iterator = type { %struct.tree_statement_list_node*, %struct.tree_node* } - %struct.tree_string = type { %struct.tree_common, i32, [1 x i8] } - %struct.tree_type = type { %struct.tree_common, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i32, i16, i8, i8, i32, %struct.tree_node*, %struct.tree_node*, %struct.rtunion, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, i64, %struct.lang_type* } - %struct.tree_type_symtab = type { i32 } - %struct.tree_value_handle = type { %struct.tree_common, %struct.value_set*, i32 } - %struct.tree_vec = type { %struct.tree_common, i32, [1 x %struct.tree_node*] } - %struct.tree_vector = type { %struct.tree_common, %struct.tree_node* } - %struct.u = type { [1 x i64] } - %struct.use_operand_ptr = type { %struct.tree_node** } - %struct.use_optype_d = type { i32, [1 x %struct.def_operand_ptr] } - %struct.v_def_use_operand_type_t = type { %struct.tree_node*, %struct.tree_node* } - %struct.v_may_def_optype_d = type { i32, [1 x %struct.elt_t] } - %struct.v_must_def_optype_d = type { i32, [1 x %struct.elt_t] } - %struct.value_set = type opaque - %struct.var_ann_d = type { %struct.tree_ann_common_d, i8, i8, %struct.tree_node*, %struct.varray_head_tag*, i32, i32, i32, %struct.tree_node*, %struct.tree_node* } - %struct.var_refs_queue = type { %struct.rtx_def*, i32, i32, %struct.var_refs_queue* } - %struct.varasm_status = type opaque - %struct.varray_data = type { [1 x i64] } - %struct.varray_head_tag = type { i32, i32, i32, i8*, %struct.u } - %struct.vuse_optype_d = type { i32, [1 x %struct.tree_node*] } -@gt_pch_rs_gt_gimplify_h = external global [2 x %struct.ggc_root_tab] ; <[2 x %struct.ggc_root_tab]*> [#uses=0] -@tmp_var_id_num = external global i32 ; <i32*> [#uses=0] -@gt_ggc_r_gt_gimplify_h = external global [1 x %struct.ggc_root_tab] ; <[1 x %struct.ggc_root_tab]*> [#uses=0] -@__FUNCTION__.19956 = external global [15 x i8] ; <[15 x i8]*> [#uses=0] -@str = external global [42 x i8] ; <[42 x i8]*> [#uses=1] -@__FUNCTION__.19974 = external global [22 x i8] ; <[22 x i8]*> [#uses=0] -@gimplify_ctxp = external global %struct.gimplify_ctx* ; <%struct.gimplify_ctx**> [#uses=0] -@cl_pf_opts = external global %struct.cl_perfunc_opts ; <%struct.cl_perfunc_opts*> [#uses=0] -@__FUNCTION__.20030 = external global [22 x i8] ; <[22 x i8]*> [#uses=0] -@__FUNCTION__.20099 = external global [24 x i8] ; <[24 x i8]*> [#uses=0] -@global_trees = external global [47 x %struct.tree_node*] ; <[47 x %struct.tree_node*]*> [#uses=0] -@tree_code_type = external global [0 x i32] ; <[0 x i32]*> [#uses=2] -@current_function_decl = external global %struct.tree_node* ; <%struct.tree_node**> [#uses=0] -@str1 = external global [2 x i8] ; <[2 x i8]*> [#uses=0] -@str2 = external global [7 x i8] ; <[7 x i8]*> [#uses=0] -@__FUNCTION__.20151 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@__FUNCTION__.20221 = external global [9 x i8] ; <[9 x i8]*> [#uses=0] -@tree_code_length = external global [0 x i8] ; <[0 x i8]*> [#uses=0] -@__FUNCTION__.20435 = external global [17 x i8] ; <[17 x i8]*> [#uses=0] -@__FUNCTION__.20496 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@cfun = external global %struct.function* ; <%struct.function**> [#uses=0] -@__FUNCTION__.20194 = external global [15 x i8] ; <[15 x i8]*> [#uses=0] -@__FUNCTION__.19987 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.20532 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.20583 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@__FUNCTION__.20606 = external global [22 x i8] ; <[22 x i8]*> [#uses=0] -@__FUNCTION__.20644 = external global [17 x i8] ; <[17 x i8]*> [#uses=0] -@__FUNCTION__.20681 = external global [13 x i8] ; <[13 x i8]*> [#uses=0] -@__FUNCTION__.20700 = external global [13 x i8] ; <[13 x i8]*> [#uses=0] -@__FUNCTION__.21426 = external global [20 x i8] ; <[20 x i8]*> [#uses=0] -@__FUNCTION__.21471 = external global [17 x i8] ; <[17 x i8]*> [#uses=0] -@__FUNCTION__.21962 = external global [27 x i8] ; <[27 x i8]*> [#uses=0] -@__FUNCTION__.22992 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.23735 = external global [15 x i8] ; <[15 x i8]*> [#uses=0] -@lang_hooks = external global %struct.lang_hooks ; <%struct.lang_hooks*> [#uses=0] -@__FUNCTION__.27383 = external global [22 x i8] ; <[22 x i8]*> [#uses=0] -@__FUNCTION__.20776 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.10672 = external global [9 x i8] ; <[9 x i8]*> [#uses=0] -@str3 = external global [47 x i8] ; <[47 x i8]*> [#uses=0] -@str4 = external global [7 x i8] ; <[7 x i8]*> [#uses=0] -@__FUNCTION__.20065 = external global [25 x i8] ; <[25 x i8]*> [#uses=0] -@__FUNCTION__.23256 = external global [16 x i8] ; <[16 x i8]*> [#uses=0] -@__FUNCTION__.23393 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@__FUNCTION__.20043 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.20729 = external global [23 x i8] ; <[23 x i8]*> [#uses=0] -@__FUNCTION__.20563 = external global [24 x i8] ; <[24 x i8]*> [#uses=0] -@__FUNCTION__.10663 = external global [10 x i8] ; <[10 x i8]*> [#uses=0] -@__FUNCTION__.20367 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.20342 = external global [15 x i8] ; <[15 x i8]*> [#uses=0] -@input_location = external global %struct.location_t ; <%struct.location_t*> [#uses=0] -@__FUNCTION__.24510 = external global [27 x i8] ; <[27 x i8]*> [#uses=0] -@__FUNCTION__.25097 = external global [25 x i8] ; <[25 x i8]*> [#uses=0] -@__FUNCTION__.24705 = external global [26 x i8] ; <[26 x i8]*> [#uses=0] -@str5 = external global [2 x i8] ; <[2 x i8]*> [#uses=0] -@__FUNCTION__.25136 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.24450 = external global [31 x i8] ; <[31 x i8]*> [#uses=0] -@implicit_built_in_decls = external global [471 x %struct.tree_node*] ; <[471 x %struct.tree_node*]*> [#uses=0] -@__FUNCTION__.24398 = external global [31 x i8] ; <[31 x i8]*> [#uses=0] -@__FUNCTION__.26156 = external global [14 x i8] ; <[14 x i8]*> [#uses=1] -@unknown_location = external global %struct.location_t ; <%struct.location_t*> [#uses=0] -@__FUNCTION__.23038 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@str6 = external global [43 x i8] ; <[43 x i8]*> [#uses=0] -@__FUNCTION__.25476 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@__FUNCTION__.22136 = external global [20 x i8] ; <[20 x i8]*> [#uses=1] -@__FUNCTION__.21997 = external global [23 x i8] ; <[23 x i8]*> [#uses=0] -@__FUNCTION__.21247 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@built_in_decls = external global [471 x %struct.tree_node*] ; <[471 x %struct.tree_node*]*> [#uses=0] -@__FUNCTION__.21924 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@__FUNCTION__.21861 = external global [25 x i8] ; <[25 x i8]*> [#uses=0] -@global_dc = external global %struct.diagnostic_context* ; <%struct.diagnostic_context**> [#uses=0] -@__FUNCTION__.25246 = external global [32 x i8] ; <[32 x i8]*> [#uses=0] -@str7 = external global [4 x i8] ; <[4 x i8]*> [#uses=0] -@stderr = external global %struct.FILE* ; <%struct.FILE**> [#uses=0] -@str8 = external global [24 x i8] ; <[24 x i8]*> [#uses=0] -@str9 = external global [22 x i8] ; <[22 x i8]*> [#uses=0] -@__FUNCTION__.27653 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.27322 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.27139 = external global [20 x i8] ; <[20 x i8]*> [#uses=0] -@__FUNCTION__.22462 = external global [23 x i8] ; <[23 x i8]*> [#uses=0] -@str10 = external global [6 x i8] ; <[6 x i8]*> [#uses=0] -@__FUNCTION__.25389 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@__FUNCTION__.25650 = external global [18 x i8] ; <[18 x i8]*> [#uses=0] -@str11 = external global [32 x i8] ; <[32 x i8]*> [#uses=0] -@str12 = external global [3 x i8] ; <[3 x i8]*> [#uses=0] -@str13 = external global [44 x i8] ; <[44 x i8]*> [#uses=0] -@__FUNCTION__.27444 = external global [14 x i8] ; <[14 x i8]*> [#uses=0] -@timevar_enable = external global i8 ; <i8*> [#uses=0] -@__FUNCTION__.27533 = external global [23 x i8] ; <[23 x i8]*> [#uses=0] -@flag_instrument_function_entry_exit = external global i32 ; <i32*> [#uses=0] -@__FUNCTION__.25331 = external global [23 x i8] ; <[23 x i8]*> [#uses=0] -@__FUNCTION__.20965 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@str14 = external global [12 x i8] ; <[12 x i8]*> [#uses=0] -@__FUNCTION__.26053 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@__FUNCTION__.26004 = external global [20 x i8] ; <[20 x i8]*> [#uses=0] -@str15 = external global [8 x i8] ; <[8 x i8]*> [#uses=0] -@__FUNCTION__.21584 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] -@str16 = external global [12 x i8] ; <[12 x i8]*> [#uses=0] -@__FUNCTION__.25903 = external global [28 x i8] ; <[28 x i8]*> [#uses=0] -@__FUNCTION__.22930 = external global [23 x i8] ; <[23 x i8]*> [#uses=0] -@__FUNCTION__.23832 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@str17 = external global [6 x i8] ; <[6 x i8]*> [#uses=0] -@__FUNCTION__.24620 = external global [24 x i8] ; <[24 x i8]*> [#uses=0] -@__FUNCTION__.24582 = external global [30 x i8] ; <[30 x i8]*> [#uses=0] -@__FUNCTION__.21382 = external global [19 x i8] ; <[19 x i8]*> [#uses=0] -@__FUNCTION__.21117 = external global [21 x i8] ; <[21 x i8]*> [#uses=0] - - -declare void @push_gimplify_context() - -declare i32 @gimple_tree_hash(i8*) - -declare i32 @iterative_hash_expr(%struct.tree_node*, i32) - -declare i32 @gimple_tree_eq(i8*, i8*) - -declare i32 @operand_equal_p(%struct.tree_node*, %struct.tree_node*, i32) - -declare void @fancy_abort(i8*, i32, i8*) - -declare i8* @xcalloc(i32, i32) - -declare %struct.htab* @htab_create(i32, i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*) - -declare void @free(i8*) - -declare void @gimple_push_bind_expr(%struct.tree_node*) - -declare void @gimple_pop_bind_expr() - -declare %struct.tree_node* @gimple_current_bind_expr() - -declare fastcc void @gimple_push_condition() - -declare %struct.tree_node* @create_artificial_label() - -declare %struct.tree_node* @build_decl_stat(i32, %struct.tree_node*, %struct.tree_node*) - -declare void @tree_class_check_failed(%struct.tree_node*, i32, i8*, i32, i8*) - -declare %struct.tree_node* @create_tmp_var_name(i8*) - -declare i32 @strlen(i8*) - -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) - -declare i32 @sprintf(i8*, i8*, ...) - -declare %struct.tree_node* @get_identifier(i8*) - -declare %struct.tree_node* @create_tmp_var_raw(%struct.tree_node*, i8*) - -declare %struct.tree_node* @build_qualified_type(%struct.tree_node*, i32) - -declare i8* @get_name(%struct.tree_node*) - -declare void @tree_operand_check_failed(i32, i32, i8*, i32, i8*) - -declare void @tree_check_failed(%struct.tree_node*, i8*, i32, i8*, ...) - -declare void @declare_tmp_vars(%struct.tree_node*, %struct.tree_node*) - -declare %struct.tree_node* @nreverse(%struct.tree_node*) - -declare void @gimple_add_tmp_var(%struct.tree_node*) - -declare void @record_vars(%struct.tree_node*) - -declare %struct.tree_node* @create_tmp_var(%struct.tree_node*, i8*) - -declare void @pop_gimplify_context(%struct.tree_node*) - -declare void @htab_delete(%struct.htab*) - -declare fastcc void @annotate_one_with_locus(%struct.tree_node*, i32, i32) - -declare void @annotate_with_locus(%struct.tree_node*, i32, i32) - -declare %struct.tree_node* @mostly_copy_tree_r(%struct.tree_node**, i32*, i8*) - -declare %struct.tree_node* @copy_tree_r(%struct.tree_node**, i32*, i8*) - -declare %struct.tree_node* @mark_decls_volatile_r(%struct.tree_node**, i32*, i8*) - -declare %struct.tree_node* @copy_if_shared_r(%struct.tree_node**, i32*, i8*) - -declare %struct.tree_node* @walk_tree(%struct.tree_node**, %struct.tree_node* (%struct.tree_node**, i32*, i8*)*, i8*, %struct.pointer_set_t*) - -declare %struct.tree_node* @unmark_visited_r(%struct.tree_node**, i32*, i8*) - -declare fastcc void @unshare_body(%struct.tree_node**, %struct.tree_node*) - -declare %struct.cgraph_node* @cgraph_node(%struct.tree_node*) - -declare fastcc void @unvisit_body(%struct.tree_node**, %struct.tree_node*) - -declare void @unshare_all_trees(%struct.tree_node*) - -declare %struct.tree_node* @unshare_expr(%struct.tree_node*) - -declare %struct.tree_node* @build_and_jump(%struct.tree_node**) - -declare %struct.tree_node* @build1_stat(i32, %struct.tree_node*, %struct.tree_node*) - -declare i32 @compare_case_labels(i8*, i8*) - -declare i32 @tree_int_cst_compare(%struct.tree_node*, %struct.tree_node*) - -declare void @sort_case_labels(%struct.tree_node*) - -declare void @tree_vec_elt_check_failed(i32, i32, i8*, i32, i8*) - -declare void @qsort(i8*, i32, i32, i32 (i8*, i8*)*) - -declare %struct.tree_node* @force_labels_r(%struct.tree_node**, i32*, i8*) - -declare fastcc void @canonicalize_component_ref(%struct.tree_node**) - -declare %struct.tree_node* @get_unwidened(%struct.tree_node*, %struct.tree_node*) - -declare fastcc void @maybe_with_size_expr(%struct.tree_node**) - -declare %struct.tree_node* @substitute_placeholder_in_expr(%struct.tree_node*, %struct.tree_node*) - -declare %struct.tree_node* @build2_stat(i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*) - -declare fastcc %struct.tree_node* @gimple_boolify(%struct.tree_node*) - -declare %struct.tree_node* @convert(%struct.tree_node*, %struct.tree_node*) - -declare %struct.tree_node* @gimplify_init_ctor_preeval_1(%struct.tree_node**, i32*, i8*) - -declare i64 @get_alias_set(%struct.tree_node*) - -declare i32 @alias_sets_conflict_p(i64, i64) - -declare fastcc i8 @cpt_same_type(%struct.tree_node*, %struct.tree_node*) zeroext - -declare %struct.tree_node* @check_pointer_types_r(%struct.tree_node**, i32*, i8*) - -declare %struct.tree_node* @voidify_wrapper_expr(%struct.tree_node*, %struct.tree_node*) - -declare i32 @integer_zerop(%struct.tree_node*) - -declare fastcc void @append_to_statement_list_1(%struct.tree_node*, %struct.tree_node**) - -declare %struct.tree_node* @alloc_stmt_list() - -declare void @tsi_link_after(%struct.tree_stmt_iterator*, %struct.tree_node*, i32) - -declare void @append_to_statement_list_force(%struct.tree_node*, %struct.tree_node**) - -declare void @append_to_statement_list(%struct.tree_node*, %struct.tree_node**) - -declare fastcc %struct.tree_node* @shortcut_cond_r(%struct.tree_node*, %struct.tree_node**, %struct.tree_node**) - -declare %struct.tree_node* @build3_stat(i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*) - -declare fastcc %struct.tree_node* @shortcut_cond_expr(%struct.tree_node*) - -declare %struct.tree_node* @expr_last(%struct.tree_node*) - -declare i8 @block_may_fallthru(%struct.tree_node*) zeroext - -declare fastcc void @gimple_pop_condition(%struct.tree_node**) - -declare %struct.tree_node* @gimple_build_eh_filter(%struct.tree_node*, %struct.tree_node*, %struct.tree_node*) - -declare void @annotate_all_with_locus(%struct.tree_node**, i32, i32) - -declare fastcc %struct.tree_node* @internal_get_tmp_var(%struct.tree_node*, %struct.tree_node**, %struct.tree_node**, i8 zeroext ) - -define i32 @gimplify_expr(%struct.tree_node** %expr_p, %struct.tree_node** %pre_p, %struct.tree_node** %post_p, i8 (%struct.tree_node*) zeroext * %gimple_test_f, i32 %fallback) { -entry: - %internal_post = alloca %struct.tree_node*, align 4 ; <%struct.tree_node**> [#uses=2] - %pre_p_addr.0 = select i1 false, %struct.tree_node** null, %struct.tree_node** %pre_p ; <%struct.tree_node**> [#uses=7] - %post_p_addr.0 = select i1 false, %struct.tree_node** %internal_post, %struct.tree_node** %post_p ; <%struct.tree_node**> [#uses=7] - br i1 false, label %bb277, label %bb191 - -bb191: ; preds = %entry - ret i32 0 - -bb277: ; preds = %entry - %tmp283 = call i32 null( %struct.tree_node** %expr_p, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0 ) ; <i32> [#uses=1] - switch i32 %tmp283, label %bb7478 [ - i32 0, label %cond_next289 - i32 -1, label %cond_next298 - ] - -cond_next289: ; preds = %bb277 - ret i32 0 - -cond_next298: ; preds = %bb277 - switch i32 0, label %bb7444 [ - i32 24, label %bb7463 - i32 25, label %bb7463 - i32 26, label %bb7463 - i32 27, label %bb7463 - i32 28, label %bb7463 - i32 33, label %bb4503 - i32 39, label %bb397 - i32 40, label %bb5650 - i32 41, label %bb4339 - i32 42, label %bb4350 - i32 43, label %bb4350 - i32 44, label %bb319 - i32 45, label %bb397 - i32 46, label %bb6124 - i32 47, label %bb7463 - i32 49, label %bb5524 - i32 50, label %bb1283 - i32 51, label %bb1289 - i32 52, label %bb1289 - i32 53, label %bb5969 - i32 54, label %bb408 - i32 56, label %bb5079 - i32 57, label %bb428 - i32 59, label %bb5965 - i32 74, label %bb4275 - i32 75, label %bb4275 - i32 76, label %bb4275 - i32 77, label %bb4275 - i32 91, label %bb1296 - i32 92, label %bb1296 - i32 96, label %bb1322 - i32 112, label %bb2548 - i32 113, label %bb2548 - i32 115, label %bb397 - i32 116, label %bb5645 - i32 117, label %bb1504 - i32 121, label %bb397 - i32 122, label %bb397 - i32 123, label %bb313 - i32 124, label %bb313 - i32 125, label %bb313 - i32 126, label %bb313 - i32 127, label %bb2141 - i32 128, label %cond_next5873 - i32 129, label %cond_next5873 - i32 130, label %bb4536 - i32 131, label %bb5300 - i32 132, label %bb5170 - i32 133, label %bb5519 - i32 134, label %bb5091 - i32 135, label %bb5083 - i32 136, label %bb5087 - i32 137, label %bb5382 - i32 139, label %bb7463 - i32 140, label %bb7463 - i32 142, label %bb5974 - i32 143, label %bb6049 - i32 147, label %bb6296 - i32 151, label %cond_next6474 - ] - -bb313: ; preds = %cond_next298, %cond_next298, %cond_next298, %cond_next298 - ret i32 0 - -bb319: ; preds = %cond_next298 - ret i32 0 - -bb397: ; preds = %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298 - ret i32 0 - -bb408: ; preds = %cond_next298 - %tmp413 = call fastcc i32 @gimplify_cond_expr( %struct.tree_node** %expr_p, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0, %struct.tree_node* null, i32 %fallback ) ; <i32> [#uses=0] - ret i32 0 - -bb428: ; preds = %cond_next298 - ret i32 0 - -bb1283: ; preds = %cond_next298 - ret i32 0 - -bb1289: ; preds = %cond_next298, %cond_next298 - ret i32 0 - -bb1296: ; preds = %cond_next298, %cond_next298 - ret i32 0 - -bb1322: ; preds = %cond_next298 - ret i32 0 - -bb1504: ; preds = %cond_next298 - ret i32 0 - -bb2141: ; preds = %cond_next298 - ret i32 0 - -bb2548: ; preds = %cond_next298, %cond_next298 - %tmp2554 = load %struct.tree_node** %expr_p ; <%struct.tree_node*> [#uses=2] - %tmp2562 = and i32 0, 255 ; <i32> [#uses=1] - %tmp2569 = add i8 0, -4 ; <i8> [#uses=1] - icmp ugt i8 %tmp2569, 5 ; <i1>:0 [#uses=2] - %tmp2587 = load i8* null ; <i8> [#uses=1] - icmp eq i8 %tmp2587, 0 ; <i1>:1 [#uses=2] - %tmp2607 = load %struct.tree_node** null ; <%struct.tree_node*> [#uses=2] - br i1 false, label %bb2754, label %cond_next2617 - -cond_next2617: ; preds = %bb2548 - ret i32 0 - -bb2754: ; preds = %bb2548 - br i1 %0, label %cond_true2780, label %cond_next2783 - -cond_true2780: ; preds = %bb2754 - call void @tree_class_check_failed( %struct.tree_node* %tmp2554, i32 9, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) ) - unreachable - -cond_next2783: ; preds = %bb2754 - %tmp2825 = and i32 0, 255 ; <i32> [#uses=1] - %tmp2829 = load i32* null ; <i32> [#uses=1] - %tmp28292830 = trunc i32 %tmp2829 to i8 ; <i8> [#uses=1] - %tmp2832 = add i8 %tmp28292830, -4 ; <i8> [#uses=1] - icmp ugt i8 %tmp2832, 5 ; <i1>:2 [#uses=1] - icmp eq i8 0, 0 ; <i1>:3 [#uses=1] - %tmp28652866 = bitcast %struct.tree_node* %tmp2607 to %struct.tree_exp* ; <%struct.tree_exp*> [#uses=1] - %tmp2868 = getelementptr %struct.tree_exp* %tmp28652866, i32 0, i32 4, i32 0 ; <%struct.tree_node**> [#uses=1] - %tmp2870 = load %struct.tree_node** %tmp2868 ; <%struct.tree_node*> [#uses=1] - br i1 %1, label %cond_true2915, label %cond_next2927 - -cond_true2915: ; preds = %cond_next2783 - unreachable - -cond_next2927: ; preds = %cond_next2783 - %tmp2938 = load %struct.tree_node** null ; <%struct.tree_node*> [#uses=1] - %tmp2944 = load i32* null ; <i32> [#uses=1] - %tmp2946 = and i32 %tmp2944, 255 ; <i32> [#uses=1] - %tmp2949 = getelementptr [0 x i32]* @tree_code_type, i32 0, i32 %tmp2946 ; <i32*> [#uses=1] - %tmp2950 = load i32* %tmp2949 ; <i32> [#uses=1] - icmp eq i32 %tmp2950, 2 ; <i1>:4 [#uses=1] - br i1 %4, label %cond_next2954, label %cond_true2951 - -cond_true2951: ; preds = %cond_next2927 - call void @tree_class_check_failed( %struct.tree_node* %tmp2938, i32 2, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) ) - unreachable - -cond_next2954: ; preds = %cond_next2927 - br i1 %0, label %cond_true2991, label %cond_next2994 - -cond_true2991: ; preds = %cond_next2954 - unreachable - -cond_next2994: ; preds = %cond_next2954 - br i1 %1, label %cond_true3009, label %cond_next3021 - -cond_true3009: ; preds = %cond_next2994 - call void @tree_operand_check_failed( i32 0, i32 %tmp2562, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) ) - unreachable - -cond_next3021: ; preds = %cond_next2994 - br i1 %2, label %cond_true3044, label %cond_next3047 - -cond_true3044: ; preds = %cond_next3021 - call void @tree_class_check_failed( %struct.tree_node* %tmp2607, i32 9, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) ) - unreachable - -cond_next3047: ; preds = %cond_next3021 - br i1 %3, label %cond_true3062, label %cond_next3074 - -cond_true3062: ; preds = %cond_next3047 - call void @tree_operand_check_failed( i32 0, i32 %tmp2825, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 1415, i8* getelementptr ([20 x i8]* @__FUNCTION__.22136, i32 0, i32 0) ) - unreachable - -cond_next3074: ; preds = %cond_next3047 - %tmp3084 = getelementptr %struct.tree_node* %tmp2870, i32 0, i32 0, i32 0, i32 1 ; <%struct.tree_node**> [#uses=1] - %tmp3085 = load %struct.tree_node** %tmp3084 ; <%struct.tree_node*> [#uses=1] - %tmp31043105 = bitcast %struct.tree_node* %tmp3085 to %struct.tree_type* ; <%struct.tree_type*> [#uses=1] - %tmp3106 = getelementptr %struct.tree_type* %tmp31043105, i32 0, i32 6 ; <i16*> [#uses=1] - %tmp31063107 = bitcast i16* %tmp3106 to i32* ; <i32*> [#uses=1] - %tmp3108 = load i32* %tmp31063107 ; <i32> [#uses=1] - xor i32 %tmp3108, 0 ; <i32>:5 [#uses=1] - %tmp81008368 = and i32 %5, 65024 ; <i32> [#uses=1] - icmp eq i32 %tmp81008368, 0 ; <i1>:6 [#uses=1] - br i1 %6, label %cond_next3113, label %bb3351 - -cond_next3113: ; preds = %cond_next3074 - ret i32 0 - -bb3351: ; preds = %cond_next3074 - %tmp3354 = call i8 @tree_ssa_useless_type_conversion( %struct.tree_node* %tmp2554 ) zeroext ; <i8> [#uses=1] - icmp eq i8 %tmp3354, 0 ; <i1>:7 [#uses=1] - %tmp3424 = load i32* null ; <i32> [#uses=1] - br i1 %7, label %cond_next3417, label %cond_true3356 - -cond_true3356: ; preds = %bb3351 - ret i32 0 - -cond_next3417: ; preds = %bb3351 - br i1 false, label %cond_true3429, label %cond_next4266 - -cond_true3429: ; preds = %cond_next3417 - %tmp3443 = and i32 %tmp3424, 255 ; <i32> [#uses=0] - ret i32 0 - -cond_next4266: ; preds = %cond_next3417 - %tmp4268 = load %struct.tree_node** %expr_p ; <%struct.tree_node*> [#uses=1] - icmp eq %struct.tree_node* %tmp4268, null ; <i1>:8 [#uses=1] - br i1 %8, label %bb4275, label %bb7463 - -bb4275: ; preds = %cond_next4266, %cond_next298, %cond_next298, %cond_next298, %cond_next298 - %tmp4289 = and i32 0, 255 ; <i32> [#uses=2] - %tmp4292 = getelementptr [0 x i32]* @tree_code_type, i32 0, i32 %tmp4289 ; <i32*> [#uses=1] - %tmp4293 = load i32* %tmp4292 ; <i32> [#uses=1] - %tmp42934294 = trunc i32 %tmp4293 to i8 ; <i8> [#uses=1] - %tmp4296 = add i8 %tmp42934294, -4 ; <i8> [#uses=1] - icmp ugt i8 %tmp4296, 5 ; <i1>:9 [#uses=1] - br i1 %9, label %cond_true4297, label %cond_next4300 - -cond_true4297: ; preds = %bb4275 - unreachable - -cond_next4300: ; preds = %bb4275 - %tmp4314 = load i8* null ; <i8> [#uses=1] - icmp eq i8 %tmp4314, 0 ; <i1>:10 [#uses=1] - br i1 %10, label %cond_true4315, label %cond_next4327 - -cond_true4315: ; preds = %cond_next4300 - call void @tree_operand_check_failed( i32 0, i32 %tmp4289, i8* getelementptr ([42 x i8]* @str, i32 0, i32 0), i32 3997, i8* getelementptr ([14 x i8]* @__FUNCTION__.26156, i32 0, i32 0) ) - unreachable - -cond_next4327: ; preds = %cond_next4300 - %tmp4336 = call i32 @gimplify_expr( %struct.tree_node** null, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0, i8 (%struct.tree_node*) zeroext * @is_gimple_val, i32 1 ) ; <i32> [#uses=0] - ret i32 0 - -bb4339: ; preds = %cond_next298 - ret i32 0 - -bb4350: ; preds = %cond_next298, %cond_next298 - ret i32 0 - -bb4503: ; preds = %cond_next298 - ret i32 0 - -bb4536: ; preds = %cond_next298 - ret i32 0 - -bb5079: ; preds = %cond_next298 - ret i32 0 - -bb5083: ; preds = %cond_next298 - ret i32 0 - -bb5087: ; preds = %cond_next298 - ret i32 0 - -bb5091: ; preds = %cond_next298 - ret i32 0 - -bb5170: ; preds = %cond_next298 - ret i32 0 - -bb5300: ; preds = %cond_next298 - ret i32 0 - -bb5382: ; preds = %cond_next298 - ret i32 0 - -bb5519: ; preds = %cond_next298 - ret i32 0 - -bb5524: ; preds = %cond_next298 - ret i32 0 - -bb5645: ; preds = %cond_next298 - ret i32 0 - -bb5650: ; preds = %cond_next298 - ret i32 0 - -cond_next5873: ; preds = %cond_next298, %cond_next298 - ret i32 0 - -bb5965: ; preds = %cond_next298 - %tmp5968 = call fastcc i32 @gimplify_cleanup_point_expr( %struct.tree_node** %expr_p, %struct.tree_node** %pre_p_addr.0 ) ; <i32> [#uses=0] - ret i32 0 - -bb5969: ; preds = %cond_next298 - %tmp5973 = call fastcc i32 @gimplify_target_expr( %struct.tree_node** %expr_p, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0 ) ; <i32> [#uses=0] - ret i32 0 - -bb5974: ; preds = %cond_next298 - ret i32 0 - -bb6049: ; preds = %cond_next298 - ret i32 0 - -bb6124: ; preds = %cond_next298 - ret i32 0 - -bb6296: ; preds = %cond_next298 - ret i32 0 - -cond_next6474: ; preds = %cond_next298 - icmp eq %struct.tree_node** %internal_post, %post_p_addr.0 ; <i1>:11 [#uses=1] - %iftmp.381.0 = select i1 %11, %struct.tree_node** null, %struct.tree_node** %post_p_addr.0 ; <%struct.tree_node**> [#uses=1] - %tmp6490 = call i32 @gimplify_expr( %struct.tree_node** null, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %iftmp.381.0, i8 (%struct.tree_node*) zeroext * %gimple_test_f, i32 %fallback ) ; <i32> [#uses=0] - %tmp6551 = call i32 @gimplify_expr( %struct.tree_node** null, %struct.tree_node** %pre_p_addr.0, %struct.tree_node** %post_p_addr.0, i8 (%struct.tree_node*) zeroext * @is_gimple_val, i32 1 ) ; <i32> [#uses=0] - ret i32 0 - -bb7444: ; preds = %cond_next298 - ret i32 0 - -bb7463: ; preds = %cond_next4266, %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298, %cond_next298 - ret i32 0 - -bb7478: ; preds = %bb277 - ret i32 0 -} - -declare i8 @is_gimple_formal_tmp_rhs(%struct.tree_node*) zeroext - -declare void @gimplify_and_add(%struct.tree_node*, %struct.tree_node**) - -declare %struct.tree_node* @get_initialized_tmp_var(%struct.tree_node*, %struct.tree_node**, %struct.tree_node**) - -declare %struct.tree_node* @get_formal_tmp_var(%struct.tree_node*, %struct.tree_node**) - -declare fastcc void @gimplify_init_ctor_preeval(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, %struct.gimplify_init_ctor_preeval_data*) - -declare i8 @type_contains_placeholder_p(%struct.tree_node*) zeroext - -declare i8 @is_gimple_mem_rhs(%struct.tree_node*) zeroext - -declare fastcc i32 @gimplify_modify_expr_rhs(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, %struct.tree_node**, %struct.tree_node**, i8 zeroext ) - -declare %struct.tree_node* @fold_indirect_ref(%struct.tree_node*) - -declare fastcc i32 @gimplify_compound_expr(%struct.tree_node**, %struct.tree_node**, i8 zeroext ) - -declare i8 @is_gimple_lvalue(%struct.tree_node*) zeroext - -declare void @categorize_ctor_elements(%struct.tree_node*, i64*, i64*, i64*, i8*) - -declare void @lhd_set_decl_assembler_name(%struct.tree_node*) - -declare i64 @int_size_in_bytes(%struct.tree_node*) - -declare i32 @can_move_by_pieces(i64, i32) - -declare i64 @count_type_elements(%struct.tree_node*) - -declare void @gimplify_stmt(%struct.tree_node**) - -declare %struct.tree_node* @get_base_address(%struct.tree_node*) - -declare fastcc void @gimplify_init_ctor_eval(%struct.tree_node*, %struct.tree_node*, %struct.tree_node**, i8 zeroext ) - -declare %struct.tree_node* @build_complex(%struct.tree_node*, %struct.tree_node*, %struct.tree_node*) - -declare i8 (%struct.tree_node*) zeroext * @rhs_predicate_for(%struct.tree_node*) - -declare %struct.tree_node* @build_vector(%struct.tree_node*, %struct.tree_node*) - -declare i8 @is_gimple_val(%struct.tree_node*) zeroext - -declare i8 @is_gimple_reg_type(%struct.tree_node*) zeroext - -declare fastcc i32 @gimplify_cond_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, %struct.tree_node*, i32) - -declare fastcc i32 @gimplify_modify_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, i8 zeroext ) - -declare %struct.tree_node* @tree_cons_stat(%struct.tree_node*, %struct.tree_node*, %struct.tree_node*) - -declare %struct.tree_node* @build_fold_addr_expr(%struct.tree_node*) - -declare %struct.tree_node* @build_function_call_expr(%struct.tree_node*, %struct.tree_node*) - -declare i8 @is_gimple_addressable(%struct.tree_node*) zeroext - -declare i8 @is_gimple_reg(%struct.tree_node*) zeroext - -declare %struct.tree_node* @make_ssa_name(%struct.tree_node*, %struct.tree_node*) - -declare i8 @tree_ssa_useless_type_conversion(%struct.tree_node*) zeroext - -declare fastcc i32 @gimplify_self_mod_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, i8 zeroext ) - -declare fastcc i32 @gimplify_compound_lval(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**, i32) - -declare %struct.tree_node* @get_callee_fndecl(%struct.tree_node*) - -declare %struct.tree_node* @fold_builtin(%struct.tree_node*, i8 zeroext ) - -declare void @error(i8*, ...) - -declare %struct.tree_node* @build_empty_stmt() - -declare i8 @fold_builtin_next_arg(%struct.tree_node*) zeroext - -declare fastcc i32 @gimplify_arg(%struct.tree_node**, %struct.tree_node**) - -declare i8 @is_gimple_call_addr(%struct.tree_node*) zeroext - -declare i32 @call_expr_flags(%struct.tree_node*) - -declare void @recalculate_side_effects(%struct.tree_node*) - -declare %struct.tree_node* @fold_convert(%struct.tree_node*, %struct.tree_node*) - -declare void @recompute_tree_invarant_for_addr_expr(%struct.tree_node*) - -declare i32 @gimplify_va_arg_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**) - -declare %struct.tree_node* @size_int_kind(i64, i32) - -declare %struct.tree_node* @size_binop(i32, %struct.tree_node*, %struct.tree_node*) - -declare %struct.tree_node* @build4_stat(i32, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*, %struct.tree_node*) - -declare void @gimplify_type_sizes(%struct.tree_node*, %struct.tree_node**) - -declare void @gimplify_one_sizepos(%struct.tree_node**, %struct.tree_node**) - -declare %struct.tree_node* @build_pointer_type(%struct.tree_node*) - -declare %struct.tree_node* @build_fold_indirect_ref(%struct.tree_node*) - -declare fastcc i32 @gimplify_bind_expr(%struct.tree_node**, %struct.tree_node*, %struct.tree_node**) - -declare fastcc void @gimplify_loop_expr(%struct.tree_node**, %struct.tree_node**) - -declare fastcc i32 @gimplify_switch_expr(%struct.tree_node**, %struct.tree_node**) - -declare %struct.tree_node* @decl_function_context(%struct.tree_node*) - -declare %struct.varray_head_tag* @varray_grow(%struct.varray_head_tag*, i32) - -declare fastcc void @gimplify_return_expr(%struct.tree_node*, %struct.tree_node**) - -declare fastcc i32 @gimplify_save_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**) - -declare fastcc i32 @gimplify_asm_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**) - -declare void @gimplify_to_stmt_list(%struct.tree_node**) - -declare fastcc i32 @gimplify_cleanup_point_expr(%struct.tree_node**, %struct.tree_node**) - -declare fastcc i32 @gimplify_target_expr(%struct.tree_node**, %struct.tree_node**, %struct.tree_node**) - -declare void @tsi_delink(%struct.tree_stmt_iterator*) - -declare void @tsi_link_before(%struct.tree_stmt_iterator*, %struct.tree_node*, i32) - -declare i8 @is_gimple_stmt(%struct.tree_node*) zeroext - -declare void @print_generic_expr(%struct.FILE*, %struct.tree_node*, i32) - -declare void @debug_tree(%struct.tree_node*) - -declare void @internal_error(i8*, ...) - -declare %struct.tree_node* @force_gimple_operand(%struct.tree_node*, %struct.tree_node**, i8 zeroext , %struct.tree_node*) - -declare i8 @is_gimple_reg_rhs(%struct.tree_node*) zeroext - -declare void @add_referenced_tmp_var(%struct.tree_node*) - -declare i8 @contains_placeholder_p(%struct.tree_node*) zeroext - -declare %struct.varray_head_tag* @varray_init(i32, i32, i8*) - -declare i32 @handled_component_p(%struct.tree_node*) - -declare void @varray_check_failed(%struct.varray_head_tag*, i32, i8*, i32, i8*) - -declare %struct.tree_node* @array_ref_low_bound(%struct.tree_node*) - -declare i8 @is_gimple_min_invariant(%struct.tree_node*) zeroext - -declare i8 @is_gimple_formal_tmp_reg(%struct.tree_node*) zeroext - -declare %struct.tree_node* @array_ref_element_size(%struct.tree_node*) - -declare %struct.tree_node* @component_ref_field_offset(%struct.tree_node*) - -declare i8 @is_gimple_min_lval(%struct.tree_node*) zeroext - -declare void @varray_underflow(%struct.varray_head_tag*, i8*, i32, i8*) - -declare i32 @list_length(%struct.tree_node*) - -declare i8 @parse_output_constraint(i8**, i32, i32, i32, i8*, i8*, i8*) zeroext - -declare i8* @xstrdup(i8*) - -declare %struct.tree_node* @build_string(i32, i8*) - -declare i8* @strchr(i8*, i32) - -declare %struct.tree_node* @build_tree_list_stat(%struct.tree_node*, %struct.tree_node*) - -declare %struct.tree_node* @chainon(%struct.tree_node*, %struct.tree_node*) - -declare i8 @parse_input_constraint(i8**, i32, i32, i32, i32, i8**, i8*, i8*) zeroext - -declare i8 @is_gimple_asm_val(%struct.tree_node*) zeroext - -declare void @gimplify_body(%struct.tree_node**, %struct.tree_node*, i8 zeroext ) - -declare void @timevar_push_1(i32) - -declare %struct.tree_node* @gimplify_parameters() - -declare %struct.tree_node* @expr_only(%struct.tree_node*) - -declare void @timevar_pop_1(i32) - -declare void @gimplify_function_tree(%struct.tree_node*) - -declare void @allocate_struct_function(%struct.tree_node*) - -declare %struct.tree_node* @make_tree_vec_stat(i32) - -declare %struct.tree_node* @tsi_split_statement_list_after(%struct.tree_stmt_iterator*) - -declare i8 @is_gimple_condexpr(%struct.tree_node*) zeroext - -declare %struct.tree_node* @invert_truthvalue(%struct.tree_node*) - -declare i8 @initializer_zerop(%struct.tree_node*) zeroext - -declare i32 @simple_cst_equal(%struct.tree_node*, %struct.tree_node*) - -declare i32 @aggregate_value_p(%struct.tree_node*, %struct.tree_node*) - -declare i32 @fwrite(i8*, i32, i32, %struct.FILE*) diff --git a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll index c73b679..25ac52e 100644 --- a/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll +++ b/test/CodeGen/ARM/2007-05-03-BadPostIndexedLd.ll @@ -2,7 +2,7 @@ %struct.Connection = type { i32, [10 x i8], i32 } %struct.IntChunk = type { %struct.cppobjtype, i32, i32*, i32 } - %struct.Point = type { i8*, %struct.cppobjtype, i16 (%struct.Point*) signext *, i16 (%struct.Point*) signext *, double (%struct.Point*)*, double (%struct.Point*)* } + %struct.Point = type { i8*, %struct.cppobjtype, i16 (%struct.Point*) *, i16 (%struct.Point*) *, double (%struct.Point*)*, double (%struct.Point*)* } %struct.RefPoint = type { %struct.Point*, %struct.cppobjtype } %struct.ShortArray = type { %struct.cppobjtype, i32, i16* } %struct.TestObj = type { i8*, %struct.cppobjtype, i8, [32 x i8], i8*, i8**, i16, i16, i32, i32, i32, i32, float, double, %struct.cppobjtype, i32, i16*, i16**, i8**, i32, %struct.XyPoint, [3 x %struct.Connection], %struct.Point*, %struct.XyPoint*, i32, i8*, i8*, i16*, %struct.ShortArray, %struct.IntChunk, %struct.cppobjtype, %struct.cppobjtype, %struct.RefPoint, i32, %struct.cppobjtype, %struct.cppobjtype } diff --git a/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll b/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll index 234c7b6..6b39a76 100644 --- a/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-04-04-ScavengerAssert.ll @@ -46,7 +46,8 @@ bb17.i: ; preds = %cond_next119.i cond_true53.i: ; preds = %bb17.i ret { i16, %struct.rnode* }* null cond_false99.i: ; preds = %bb17.i - %tmp106.i = malloc %struct.ch_set ; <%struct.ch_set*> [#uses=1] + %malloccall = tail call i8* @malloc(i32 trunc (i64 mul nuw (i64 ptrtoint (i1** getelementptr (i1** null, i32 1) to i64), i64 2) to i32)) + %tmp106.i = bitcast i8* %malloccall to %struct.ch_set* br i1 false, label %bb126.i, label %cond_next119.i cond_next119.i: ; preds = %cond_false99.i, %bb42 %curr_ptr.0.reg2mem.0.i = phi %struct.ch_set* [ %tmp106.i, %cond_false99.i ], [ null, %bb42 ] ; <%struct.ch_set*> [#uses=2] @@ -58,3 +59,5 @@ bb126.i: ; preds = %cond_next119.i, %cond_false99.i bb78: ; preds = %entry ret { i16, %struct.rnode* }* null } + +declare noalias i8* @malloc(i32) diff --git a/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll b/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll deleted file mode 100644 index 5f9d9ae..0000000 --- a/test/CodeGen/ARM/2008-09-14-CoalescerBug.ll +++ /dev/null @@ -1,29 +0,0 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin - -@"\01LC1" = external constant [288 x i8] ; <[288 x i8]*> [#uses=1] - -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) nounwind - -define i32 @main(i32 %argc, i8** %argv) nounwind { -entry: - br label %bb.i - -bb.i: ; preds = %bb.i, %entry - %i.01.i = phi i32 [ 0, %entry ], [ %indvar.next52, %bb.i ] ; <i32> [#uses=1] - %indvar.next52 = add i32 %i.01.i, 1 ; <i32> [#uses=2] - %exitcond53 = icmp eq i32 %indvar.next52, 15 ; <i1> [#uses=1] - br i1 %exitcond53, label %bb.i33.loopexit, label %bb.i - -bb.i33.loopexit: ; preds = %bb.i - %0 = malloc [347 x i8] ; <[347 x i8]*> [#uses=2] - %.sub = getelementptr [347 x i8]* %0, i32 0, i32 0 ; <i8*> [#uses=1] - call void @llvm.memcpy.i32( i8* %.sub, i8* getelementptr ([288 x i8]* @"\01LC1", i32 0, i32 0), i32 287, i32 1 ) nounwind - br label %bb.i28 - -bb.i28: ; preds = %bb.i28, %bb.i33.loopexit - br i1 false, label %repeat_fasta.exit, label %bb.i28 - -repeat_fasta.exit: ; preds = %bb.i28 - free [347 x i8]* %0 - unreachable -} diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll index 90a4a42..382038e 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll @@ -14,7 +14,8 @@ entry: br i1 %p, label %bb8, label %bb1 bb1: ; preds = %entry - %0 = malloc %struct.Village ; <%struct.Village*> [#uses=3] + %malloccall = tail call i8* @malloc(i32 ptrtoint (%struct.Village* getelementptr (%struct.Village* null, i32 1) to i32)) + %0 = bitcast i8* %malloccall to %struct.Village* %exp2 = call double @ldexp(double 1.000000e+00, i32 %level) nounwind ; <double> [#uses=1] %.c = fptosi double %exp2 to i32 ; <i32> [#uses=1] store i32 %.c, i32* null @@ -29,3 +30,4 @@ bb8: ; preds = %entry } declare double @ldexp(double, i32) +declare noalias i8* @malloc(i32) diff --git a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll index 3909c6a..0a157c9 100644 --- a/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll +++ b/test/CodeGen/ARM/2009-09-09-fpcmp-ole.ll @@ -1,16 +1,16 @@ -; RUN: llc -O1 -march=arm -mattr=+vfp2 < %s | FileCheck %s +; RUN: llc -O1 -march=arm -mattr=+vfp2 -mtriple=arm-linux-gnueabi < %s | FileCheck %s ; pr4939 define void @test(double* %x, double* %y) nounwind { - %1 = load double* %x, align 4 - %2 = load double* %y, align 4 + %1 = load double* %x + %2 = load double* %y %3 = fsub double -0.000000e+00, %1 %4 = fcmp ugt double %2, %3 br i1 %4, label %bb1, label %bb2 bb1: ;CHECK: vstrhi.64 - store double %1, double* %y, align 4 + store double %1, double* %y br label %bb2 bb2: diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index 5ad1c09..df9dbca 100644 --- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -7,13 +7,13 @@ define zeroext i8 @t(%struct.foo* %this) noreturn optsize { entry: ; ARM: t: -; ARM: str r0, [r1], r0 +; ARM: str r2, [r1], r0 ; THUMB: t: ; THUMB-NOT: str r0, [r1], r0 -; THUMB: str r0, [r1] +; THUMB: str r2, [r1] %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1] - store i32 undef, i32* inttoptr (i32 8 to i32*), align 8 + store i32 0, i32* inttoptr (i32 8 to i32*), align 8 br i1 undef, label %bb.nph96, label %bb3 bb3: ; preds = %entry diff --git a/test/CodeGen/ARM/2010-08-04-StackVariable.ll b/test/CodeGen/ARM/2010-08-04-StackVariable.ll index f077d04..6aeaa26 100644 --- a/test/CodeGen/ARM/2010-08-04-StackVariable.ll +++ b/test/CodeGen/ARM/2010-08-04-StackVariable.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_fbreg -; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot. +; RUN: llc -O0 -mtriple=arm-apple-darwin < %s | grep DW_OP_breg +; Use DW_OP_breg in variable's location expression if the variable is in a stack slot. %struct.SVal = type { i8*, i32 } @@ -31,7 +31,7 @@ return: ; preds = %bb2 ret i32 %.0, !dbg !29 } -define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { +define linkonce_odr void @_ZN4SValC1Ev(%struct.SVal* %this) nounwind ssp align 2 { entry: %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] call void @llvm.dbg.value(metadata !{%struct.SVal* %this}, i64 0, metadata !31), !dbg !34 diff --git a/test/CodeGen/ARM/2010-12-13-reloc-pic.ll b/test/CodeGen/ARM/2010-12-13-reloc-pic.ll deleted file mode 100644 index d5aefbe..0000000 --- a/test/CodeGen/ARM/2010-12-13-reloc-pic.ll +++ /dev/null @@ -1,100 +0,0 @@ -; RUN: llc %s -mtriple=armv7-linux-gnueabi -relocation-model=pic -filetype=obj -o - | \ -; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=PIC01 %s - -;; FIXME: Reduce this test further, or even better, -;; redo as .s -> .o test once ARM AsmParser is working better - -; ModuleID = 'large2.pnacl.bc' -target triple = "armv7-none-linux-gnueabi" - -%struct._Bigint = type { %struct._Bigint*, i32, i32, i32, i32, [1 x i32] } -%struct.__FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, %struct._reent*, i8*, i32 (%struct._reent*, i8*, i8*, i32)*, i32 (%struct._reent*, i8*, i8*, i32)*, i32 (%struct._reent*, i8*, i32, i32)*, i32 (%struct._reent*, i8*)*, %struct.__sbuf, i8*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i32, %struct._flock_t, %struct._mbstate_t, i32 } -%struct.__sbuf = type { i8*, i32 } -%struct.__tm = type { i32, i32, i32, i32, i32, i32, i32, i32, i32 } -%struct._atexit = type { %struct._atexit*, i32, [32 x void ()*], %struct._on_exit_args* } -%struct._flock_t = type { i32, i32, i32, i32, i32 } -%struct._glue = type { %struct._glue*, i32, %struct.__FILE* } -%struct._mbstate_t = type { i32, %union.anon } -%struct._misc_reent = type { i8*, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, [8 x i8], i32, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t, %struct._mbstate_t } -%struct._mprec = type { %struct._Bigint*, i32, %struct._Bigint*, %struct._Bigint** } -%struct._on_exit_args = type { [32 x i8*], [32 x i8*], i32, i32 } -%struct._rand48 = type { [3 x i16], [3 x i16], i16, i64 } -%struct._reent = type { %struct.__FILE*, %struct.__FILE*, %struct.__FILE*, i32, i32, i8*, i32, i32, i8*, %struct._mprec*, void (%struct._reent*)*, i32, i32, i8*, %struct._rand48*, %struct.__tm*, i8*, void (i32)**, %struct._atexit*, %struct._atexit, %struct._glue, %struct.__FILE*, %struct._misc_reent*, i8* } -%union.anon = type { i32 } - -@buf = constant [2 x i8] c"x\00", align 4 -@_impure_ptr = external thread_local global %struct._reent* -@.str = private constant [22 x i8] c"This should fault...\0A\00", align 4 -@.str1 = private constant [40 x i8] c"We're still running. This is not good.\0A\00", align 4 - -define i32 @main() nounwind { -entry: - %0 = load %struct._reent** @_impure_ptr, align 4 - %1 = getelementptr inbounds %struct._reent* %0, i32 0, i32 1 - %2 = load %struct.__FILE** %1, align 4 - %3 = bitcast %struct.__FILE* %2 to i8* - %4 = tail call i32 @fwrite(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 1, i32 21, i8* %3) nounwind - %5 = load %struct._reent** @_impure_ptr, align 4 - %6 = getelementptr inbounds %struct._reent* %5, i32 0, i32 1 - %7 = load %struct.__FILE** %6, align 4 - %8 = tail call i32 @fflush(%struct.__FILE* %7) nounwind - store i8 121, i8* getelementptr inbounds ([2 x i8]* @buf, i32 0, i32 0), align 4 - %9 = load %struct._reent** @_impure_ptr, align 4 - %10 = getelementptr inbounds %struct._reent* %9, i32 0, i32 1 - %11 = load %struct.__FILE** %10, align 4 - %12 = bitcast %struct.__FILE* %11 to i8* - %13 = tail call i32 @fwrite(i8* getelementptr inbounds ([40 x i8]* @.str1, i32 0, i32 0), i32 1, i32 39, i8* %12) nounwind - ret i32 1 -} - - -; PIC01: Relocation 0x00000000 -; PIC01-NEXT: 'r_offset', 0x0000001c -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001b - - -; PIC01: Relocation 0x00000001 -; PIC01-NEXT: 'r_offset', 0x00000038 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001b - -; PIC01: Relocation 0x00000002 -; PIC01-NEXT: 'r_offset', 0x00000044 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001b - -; PIC01: Relocation 0x00000003 -; PIC01-NEXT: 'r_offset', 0x00000070 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001b - -; PIC01: Relocation 0x00000004 -; PIC01-NEXT: 'r_offset', 0x0000007c -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x00000019 - - -; PIC01: Relocation 0x00000005 -; PIC01-NEXT: 'r_offset', 0x00000080 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x00000018 - -; PIC01: Relocation 0x00000006 -; PIC01-NEXT: 'r_offset', 0x00000084 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x00000068 - -; PIC01: Relocation 0x00000007 -; PIC01-NEXT: 'r_offset', 0x00000088 -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x0000001a - -; PIC01: Relocation 0x00000008 -; PIC01-NEXT: 'r_offset', 0x0000008c -; PIC01-NEXT: 'r_sym' -; PIC01-NEXT: 'r_type', 0x00000018 - -declare i32 @fwrite(i8* nocapture, i32, i32, i8* nocapture) nounwind - -declare i32 @fflush(%struct.__FILE* nocapture) nounwind diff --git a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll index 7642dc4..69d4a14 100644 --- a/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll +++ b/test/CodeGen/ARM/2010-12-15-elf-lcomm.ll @@ -10,7 +10,7 @@ @STRIDE = internal global i32 8 ; ASM: .type array00,%object @ @array00 -; ASM-NEXT: .lcomm array00,80 @ @array00 +; ASM-NEXT: .lcomm array00,80 ; ASM-NEXT: .type _MergedGlobals,%object @ @_MergedGlobals diff --git a/test/CodeGen/ARM/2011-04-07-schediv.ll b/test/CodeGen/ARM/2011-04-07-schediv.ll index a61908f..19f756f 100644 --- a/test/CodeGen/ARM/2011-04-07-schediv.ll +++ b/test/CodeGen/ARM/2011-04-07-schediv.ll @@ -13,6 +13,7 @@ entry: ; Make sure the scheduler schedules all uses of the preincrement ; induction variable before defining the postincrement value. ; CHECK: t: +; CHECK: %bb ; CHECK-NOT: mov bb: ; preds = %entry, %bb %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] diff --git a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll new file mode 100644 index 0000000..568718c --- /dev/null +++ b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s + +; Overly aggressive LICM simply adds copies of constants +; rdar://9266679 + +define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp { +; CHECK: t: +entry: + br label %for.cond + +for.cond: + %0 = phi i32 [ 0, %entry ], [ %inc, %for.inc ] + %cmp = icmp ult i32 %0, %size + br i1 %cmp, label %for.body, label %return + +for.body: +; CHECK: %for. +; CHECK: movs r{{[0-9]+}}, #{{[01]}} + %arrayidx = getelementptr i32* %A, i32 %0 + %tmp4 = load i32* %arrayidx, align 4 + %cmp6 = icmp eq i32 %tmp4, %value + br i1 %cmp6, label %return, label %for.inc + +; CHECK: %for. +; CHECK: movs r{{[0-9]+}}, #{{[01]}} + +for.inc: + %inc = add i32 %0, 1 + br label %for.cond + +return: + %retval.0 = phi i1 [ true, %for.body ], [ false, %for.cond ] + ret i1 %retval.0 +} diff --git a/test/CodeGen/ARM/2011-04-12-AlignBug.ll b/test/CodeGen/ARM/2011-04-12-AlignBug.ll new file mode 100644 index 0000000..317be94 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-12-AlignBug.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10.0.0" + +; CHECK: align 3 +@.v = linker_private unnamed_addr constant <4 x i32> <i32 1, i32 2, i32 3, i32 4>, align 8 +; CHECK: align 2 +@.strA = linker_private unnamed_addr constant [4 x i8] c"bar\00" +; CHECK-NOT: align +@.strB = linker_private unnamed_addr constant [4 x i8] c"foo\00", align 1 +@.strC = linker_private unnamed_addr constant [4 x i8] c"baz\00", section "__TEXT,__cstring,cstring_literals", align 1 diff --git a/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll new file mode 100644 index 0000000..eb23de0 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-12-FastRegAlloc.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -regalloc=fast +; Previously we'd crash as out of registers on this input by clobbering all of +; the aliases. +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10.0.0" + +define void @_Z8TestCasev() nounwind ssp { +entry: + %a = alloca float, align 4 + %tmp = load float* %a, align 4 + call void asm sideeffect "", "w,~{s0},~{s16}"(float %tmp) nounwind, !srcloc !0 + ret void +} + +!0 = metadata !{i32 109} diff --git a/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll new file mode 100644 index 0000000..e712e08 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-15-AndVFlagPeepholeBug.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s + +; CHECK: _f +; CHECK-NOT: ands +; CHECK: cmp +; CHECK: blxle _g + +define i32 @f(i32 %a, i32 %b) nounwind ssp { +entry: + %and = and i32 %b, %a + %cmp = icmp slt i32 %and, 1 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void (...)* @g(i32 %a, i32 %b) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %and +} + +declare void @g(...) diff --git a/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll new file mode 100644 index 0000000..5404cf5 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-15-RegisterCmpPeephole.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s + +; CHECK: _f +; CHECK: adds +; CHECK-NOT: cmp +; CHECK: blxeq _h + +define i32 @f(i32 %a, i32 %b) nounwind ssp { +entry: + %add = add nsw i32 %b, %a + %cmp = icmp eq i32 %add, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void (...)* @h(i32 %a, i32 %b) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %add +} + +; CHECK: _g +; CHECK: orrs +; CHECK-NOT: cmp +; CHECK: blxeq _h + +define i32 @g(i32 %a, i32 %b) nounwind ssp { +entry: + %add = or i32 %b, %a + %cmp = icmp eq i32 %add, 0 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + tail call void (...)* @h(i32 %a, i32 %b) nounwind + br label %if.end + +if.end: ; preds = %if.then, %entry + ret i32 %add +} + +declare void @h(...) diff --git a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll new file mode 100644 index 0000000..ed7dd03 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll @@ -0,0 +1,70 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios -relocation-model=pic -mcpu=cortex-a8 | FileCheck %s + +; Do not move the umull above previous call which would require use of +; more callee-saved registers and introduce copies. +; rdar://9329627 + +%struct.FF = type { i32 (i32*)*, i32 (i32*, i32*, i32, i32, i32, i32)*, i32 (i32, i32, i8*)*, void ()*, i32 (i32, i8*, i32*)*, i32 ()* } +%struct.BD = type { %struct.BD*, i32, i32, i32, i32, i64, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i8*, i64, i32)*, i32 (%struct.BD*, i8*, i32, i32)*, i32 (%struct.BD*, i64, i32)*, [16 x i8], i64, i64 } + +@FuncPtr = external hidden unnamed_addr global %struct.FF* +@.str1 = external hidden unnamed_addr constant [6 x i8], align 4 +@G = external unnamed_addr global i32 +@.str2 = external hidden unnamed_addr constant [58 x i8], align 4 +@.str3 = external hidden unnamed_addr constant [58 x i8], align 4 + +define i32 @test() nounwind optsize ssp { +entry: +; CHECK: test: +; CHECK: push +; CHECK-NOT: push + %block_size = alloca i32, align 4 + %block_count = alloca i32, align 4 + %index_cache = alloca i32, align 4 + store i32 0, i32* %index_cache, align 4 + %tmp = load i32* @G, align 4 + %tmp1 = call i32 @bar(i32 0, i32 0, i32 %tmp) nounwind + switch i32 %tmp1, label %bb8 [ + i32 0, label %bb + i32 536870913, label %bb4 + i32 536870914, label %bb6 + ] + +bb: + %tmp2 = load i32* @G, align 4 + %tmp4 = icmp eq i32 %tmp2, 0 + br i1 %tmp4, label %bb1, label %bb8 + +bb1: +; CHECK: %bb1 +; CHECK-NOT: umull +; CHECK: blx _Get +; CHECK: umull +; CHECK: blx _foo + %tmp5 = load i32* %block_size, align 4 + %tmp6 = load i32* %block_count, align 4 + %tmp7 = call %struct.FF* @Get() nounwind + store %struct.FF* %tmp7, %struct.FF** @FuncPtr, align 4 + %tmp10 = zext i32 %tmp6 to i64 + %tmp11 = zext i32 %tmp5 to i64 + %tmp12 = mul nsw i64 %tmp10, %tmp11 + %tmp13 = call i32 @foo(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0), i64 %tmp12, i32 %tmp5) nounwind + br label %bb8 + +bb4: + ret i32 0 + +bb6: + ret i32 1 + +bb8: + ret i32 -1 +} + +declare i32 @printf(i8*, ...) + +declare %struct.FF* @Get() + +declare i32 @foo(i8*, i64, i32) + +declare i32 @bar(i32, i32, i32) diff --git a/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll b/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll new file mode 100644 index 0000000..0741049 --- /dev/null +++ b/test/CodeGen/ARM/2011-04-27-IfCvtBug.ll @@ -0,0 +1,59 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-ios + +; If converter was being too cute. It look for root BBs (which don't have +; successors) and use inverse depth first search to traverse the BBs. However +; that doesn't work when the CFG has infinite loops. Simply do a linear +; traversal of all BBs work just fine. + +; rdar://9344645 + +%struct.hc = type { i32, i32, i32, i32 } + +define i32 @t(i32 %type) optsize { +entry: + br i1 undef, label %if.then, label %if.else + +if.then: + unreachable + +if.else: + br i1 undef, label %if.then15, label %if.else18 + +if.then15: + unreachable + +if.else18: + switch i32 %type, label %if.else173 [ + i32 3, label %if.then115 + i32 1, label %if.then102 + ] + +if.then102: + br i1 undef, label %cond.true10.i, label %t.exit + +cond.true10.i: + br label %t.exit + +t.exit: + unreachable + +if.then115: + br i1 undef, label %if.else163, label %if.else145 + +if.else145: + %call150 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34865152) optsize + br label %while.body172 + +if.else163: + %call168 = call fastcc %struct.hc* @foo(%struct.hc* undef, i32 34078720) optsize + br label %while.body172 + +while.body172: + br label %while.body172 + +if.else173: + ret i32 -1 +} + +declare hidden fastcc %struct.hc* @foo(%struct.hc* nocapture, i32) nounwind optsize + diff --git a/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll b/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll new file mode 100644 index 0000000..0b5f962 --- /dev/null +++ b/test/CodeGen/ARM/2011-05-04-MultipleLandingPadSuccs.ll @@ -0,0 +1,93 @@ +; RUN: llc < %s -verify-machineinstrs +; <rdar://problem/9187612> +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin" + +define void @func() unnamed_addr align 2 { +entry: + br label %for.cond + +for.cond: + %tmp2 = phi i32 [ 0, %entry ], [ %add, %for.cond.backedge ] + %cmp = icmp ult i32 %tmp2, 14 + br i1 %cmp, label %for.body, label %for.end + +for.body: + %add = add i32 %tmp2, 1 + switch i32 %tmp2, label %sw.default [ + i32 0, label %sw.bb + i32 1, label %sw.bb + i32 2, label %sw.bb + i32 4, label %sw.bb + i32 5, label %sw.bb + i32 10, label %sw.bb + ] + +sw.bb: + invoke void @foo() + to label %invoke.cont17 unwind label %lpad + +invoke.cont17: + invoke void @foo() + to label %for.cond.backedge unwind label %lpad26 + +for.cond.backedge: + br label %for.cond + +lpad: + %exn = tail call i8* @llvm.eh.exception() nounwind + %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + invoke void @foo() + to label %eh.resume unwind label %terminate.lpad + +lpad26: + %exn27 = tail call i8* @llvm.eh.exception() nounwind + %eh.selector28 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn27, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + invoke void @foo() + to label %eh.resume unwind label %terminate.lpad + +sw.default: + br label %for.cond.backedge + +for.end: + invoke void @foo() + to label %call8.i.i.i.noexc unwind label %lpad44 + +call8.i.i.i.noexc: + ret void + +lpad44: + %exn45 = tail call i8* @llvm.eh.exception() nounwind + %eh.selector46 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn45, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + invoke void @foo() + to label %eh.resume unwind label %terminate.lpad + +eh.resume: + %exn.slot.0 = phi i8* [ %exn27, %lpad26 ], [ %exn, %lpad ], [ %exn45, %lpad44 ] + tail call void @_Unwind_SjLj_Resume_or_Rethrow(i8* %exn.slot.0) noreturn + unreachable + +terminate.lpad: + %exn51 = tail call i8* @llvm.eh.exception() nounwind + %eh.selector52 = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn51, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i8* null) nounwind + tail call void @_ZSt9terminatev() noreturn nounwind + unreachable +} + +declare void @foo() + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i32 @__gxx_personality_sj0(...) + +declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind + +declare void @_Unwind_SjLj_Resume_or_Rethrow(i8*) + +declare void @_ZSt9terminatev() + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} +!3 = metadata !{metadata !"bool", metadata !1} +!4 = metadata !{metadata !"int", metadata !1} diff --git a/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll b/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll new file mode 100644 index 0000000..4db3acf --- /dev/null +++ b/test/CodeGen/ARM/2011-06-09-TailCallByVal.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -relocation-model=pic -mcpu=cortex-a8 -arm-tail-calls=1 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +%struct._RuneCharClass = type { [14 x i8], i32 } +%struct._RuneEntry = type { i32, i32, i32, i32* } +%struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i32, i8**)*, i32 (i32, i8*, i32, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* } +%struct._RuneRange = type { i32, %struct._RuneEntry* } +%struct.__collate_st_chain_pri = type { [10 x i32], [2 x i32] } +%struct.__collate_st_char_pri = type { [2 x i32] } +%struct.__collate_st_info = type { [2 x i8], i8, i8, [2 x i32], [2 x i32], i32, i32 } +%struct.__collate_st_large_char_pri = type { i32, %struct.__collate_st_char_pri } +%struct.__collate_st_subst = type { i32, [10 x i32] } +%struct.__xlocale_st_collate = type { i32, void (i8*)*, [32 x i8], %struct.__collate_st_info, [2 x %struct.__collate_st_subst*], %struct.__collate_st_chain_pri*, %struct.__collate_st_large_char_pri*, [256 x %struct.__collate_st_char_pri] } +%struct.__xlocale_st_messages = type { i32, void (i8*)*, i8*, %struct.lc_messages_T } +%struct.__xlocale_st_monetary = type { i32, void (i8*)*, i8*, %struct.lc_monetary_T } +%struct.__xlocale_st_numeric = type { i32, void (i8*)*, i8*, %struct.lc_numeric_T } +%struct.__xlocale_st_runelocale = type { i32, void (i8*)*, [32 x i8], i32, i32, i32 (i32*, i8*, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (%union.__mbstate_t*, %struct._xlocale*)*, i32 (i32*, i8**, i32, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (i8*, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32 (i8*, i32**, i32, i32, %union.__mbstate_t*, %struct._xlocale*)*, i32, %struct._RuneLocale } +%struct.__xlocale_st_time = type { i32, void (i8*)*, i8*, %struct.lc_time_T } +%struct._xlocale = type { i32, void (i8*)*, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, %union.__mbstate_t, i32, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, %struct.__xlocale_st_collate*, %struct.__xlocale_st_runelocale*, %struct.__xlocale_st_messages*, %struct.__xlocale_st_monetary*, %struct.__xlocale_st_numeric*, %struct._xlocale*, %struct.__xlocale_st_time*, %struct.lconv } +%struct.lc_messages_T = type { i8*, i8*, i8*, i8* } +%struct.lc_monetary_T = type { i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8* } +%struct.lc_numeric_T = type { i8*, i8*, i8* } +%struct.lc_time_T = type { [12 x i8*], [12 x i8*], [7 x i8*], [7 x i8*], i8*, i8*, i8*, i8*, i8*, i8*, [12 x i8*], i8*, i8* } +%struct.lconv = type { i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } +%union.__mbstate_t = type { i64, [120 x i8] } + +@"\01_fnmatch.initial" = external constant %union.__mbstate_t, align 4 + +; CHECK: _fnmatch +; CHECK: blx _fnmatch1 + +define i32 @"\01_fnmatch"(i8* %pattern, i8* %string, i32 %flags) nounwind optsize { +entry: + %call4 = tail call i32 @fnmatch1(i8* %pattern, i8* %string, i8* %string, i32 %flags, %union.__mbstate_t* byval @"\01_fnmatch.initial", %union.__mbstate_t* byval @"\01_fnmatch.initial", %struct._xlocale* undef, i32 64) optsize + ret i32 %call4 +} + +declare i32 @fnmatch1(i8*, i8*, i8*, i32, %union.__mbstate_t* byval, %union.__mbstate_t* byval, %struct._xlocale*, i32) nounwind optsize diff --git a/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll b/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll new file mode 100644 index 0000000..7baacfe --- /dev/null +++ b/test/CodeGen/ARM/2011-06-16-TailCallByVal.ll @@ -0,0 +1,20 @@ +; RUN: llc < %s -arm-tail-calls=1 | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +%struct.A = type <{ i16, i16, i32, i16, i16, i32, i16, [8 x %struct.B], [418 x i8], %struct.C }> +%struct.B = type <{ i32, i16, i16 }> +%struct.C = type { i16, i32, i16, i16 } + +; CHECK: f +; CHECK: push {r1, r2, r3} +; CHECK: add sp, #12 +; CHECK: b.w _puts + +define void @f(i8* %s, %struct.A* nocapture byval %a) nounwind optsize { +entry: + %puts = tail call i32 @puts(i8* %s) + ret void +} + +declare i32 @puts(i8* nocapture) nounwind diff --git a/test/CodeGen/ARM/align.ll b/test/CodeGen/ARM/align.ll index d57c159..9589e72 100644 --- a/test/CodeGen/ARM/align.ll +++ b/test/CodeGen/ARM/align.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=ELF -; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=arm-apple-darwin10 | FileCheck %s -check-prefix=DARWIN @a = global i1 true ; no alignment diff --git a/test/CodeGen/ARM/arm-and-tst-peephole.ll b/test/CodeGen/ARM/arm-and-tst-peephole.ll index 444dce7..0762070 100644 --- a/test/CodeGen/ARM/arm-and-tst-peephole.ll +++ b/test/CodeGen/ARM/arm-and-tst-peephole.ll @@ -23,7 +23,7 @@ tailrecurse: ; preds = %sw.bb, %entry %tmp2 = load i8** %scevgep5 %0 = ptrtoint i8* %tmp2 to i32 -; ARM: ands r12, r12, #3 +; ARM: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 ; ARM-NEXT: beq ; THUMB: movs r[[R0:[0-9]+]], #3 @@ -31,7 +31,7 @@ tailrecurse: ; preds = %sw.bb, %entry ; THUMB-NEXT: cmp r[[R0]], #0 ; THUMB-NEXT: beq -; T2: ands r12, r12, #3 +; T2: ands {{r[0-9]+}}, {{r[0-9]+}}, #3 ; T2-NEXT: beq %and = and i32 %0, 3 diff --git a/test/CodeGen/ARM/arm-modifier.ll b/test/CodeGen/ARM/arm-modifier.ll new file mode 100644 index 0000000..0a7bb6c --- /dev/null +++ b/test/CodeGen/ARM/arm-modifier.ll @@ -0,0 +1,59 @@ +; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s + +define i32 @foo(float %scale, float %scale2) nounwind { +entry: + %scale.addr = alloca float, align 4 + %scale2.addr = alloca float, align 4 + store float %scale, float* %scale.addr, align 4 + store float %scale2, float* %scale2.addr, align 4 + %tmp = load float* %scale.addr, align 4 + %tmp1 = load float* %scale2.addr, align 4 + call void asm sideeffect "vmul.f32 q0, q0, ${0:y} \0A\09vmul.f32 q1, q1, ${0:y} \0A\09vmul.f32 q1, q0, ${1:y} \0A\09", "w,w,~{q0},~{q1}"(float %tmp, float %tmp1) nounwind + ret i32 0 +} + +define void @f0() nounwind { +entry: +; CHECK: f0 +; CHECK: .word -1 +call void asm sideeffect ".word ${0:B} \0A\09", "i"(i32 0) nounwind +ret void +} + +define void @f1() nounwind { +entry: +; CHECK: f1 +; CHECK: .word 65535 +call void asm sideeffect ".word ${0:L} \0A\09", "i"(i32 -1) nounwind +ret void +} + +@f2_ptr = internal global i32* @f2_var, align 4 +@f2_var = external global i32 + +define void @f2() nounwind { +entry: +; CHECK: f2 +; CHECK: ldr r0, [r{{[0-9]+}}] +call void asm sideeffect "ldr r0, [${0:m}]\0A\09", "*m,~{r0}"(i32** @f2_ptr) nounwind +ret void +} + +@f3_ptr = internal global i64* @f3_var, align 4 +@f3_var = external global i64 +@f3_var2 = external global i64 + +define void @f3() nounwind { +entry: +; CHECK: f3 +; CHECK: stm r{{[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}} +; CHECK: adds lr, [[REG1]] +; CHECK: ldm r{{[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}} +%tmp = load i64* @f3_var, align 4 +%tmp1 = load i64* @f3_var2, align 4 +%0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind +store i64 %0, i64* @f3_var, align 4 +%1 = call i64 asm sideeffect "ldm ${1:m}, ${0:M}\0A\09", "=r,*m"(i64** @f3_ptr) nounwind +store i64 %1, i64* @f3_var, align 4 +ret void +} diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll new file mode 100644 index 0000000..03940e3 --- /dev/null +++ b/test/CodeGen/ARM/atomic-op.ll @@ -0,0 +1,103 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s + +define void @func(i32 %argc, i8** %argv) nounwind { +entry: + %argc.addr = alloca i32 ; <i32*> [#uses=1] + %argv.addr = alloca i8** ; <i8***> [#uses=1] + %val1 = alloca i32 ; <i32*> [#uses=2] + %val2 = alloca i32 ; <i32*> [#uses=15] + %andt = alloca i32 ; <i32*> [#uses=2] + %ort = alloca i32 ; <i32*> [#uses=2] + %xort = alloca i32 ; <i32*> [#uses=2] + %old = alloca i32 ; <i32*> [#uses=18] + %temp = alloca i32 ; <i32*> [#uses=2] + store i32 %argc, i32* %argc.addr + store i8** %argv, i8*** %argv.addr + store i32 0, i32* %val1 + store i32 31, i32* %val2 + store i32 3855, i32* %andt + store i32 3855, i32* %ort + store i32 3855, i32* %xort + store i32 4, i32* %temp + %tmp = load i32* %temp + ; CHECK: ldrex + ; CHECK: add + ; CHECK: strex + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val1, i32 %tmp ) ; <i32>:0 [#uses=1] + store i32 %0, i32* %old + ; CHECK: ldrex + ; CHECK: sub + ; CHECK: strex + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 30 ) ; <i32>:1 [#uses=1] + store i32 %1, i32* %old + ; CHECK: ldrex + ; CHECK: add + ; CHECK: strex + call i32 @llvm.atomic.load.add.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:2 [#uses=1] + store i32 %2, i32* %old + ; CHECK: ldrex + ; CHECK: sub + ; CHECK: strex + call i32 @llvm.atomic.load.sub.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:3 [#uses=1] + store i32 %3, i32* %old + ; CHECK: ldrex + ; CHECK: and + ; CHECK: strex + call i32 @llvm.atomic.load.and.i32.p0i32( i32* %andt, i32 4080 ) ; <i32>:4 [#uses=1] + store i32 %4, i32* %old + ; CHECK: ldrex + ; CHECK: or + ; CHECK: strex + call i32 @llvm.atomic.load.or.i32.p0i32( i32* %ort, i32 4080 ) ; <i32>:5 [#uses=1] + store i32 %5, i32* %old + ; CHECK: ldrex + ; CHECK: eor + ; CHECK: strex + call i32 @llvm.atomic.load.xor.i32.p0i32( i32* %xort, i32 4080 ) ; <i32>:6 [#uses=1] + store i32 %6, i32* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 16 ) ; <i32>:7 [#uses=1] + store i32 %7, i32* %old + %neg = sub i32 0, 1 ; <i32> [#uses=1] + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + call i32 @llvm.atomic.load.min.i32.p0i32( i32* %val2, i32 %neg ) ; <i32>:8 [#uses=1] + store i32 %8, i32* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 1 ) ; <i32>:9 [#uses=1] + store i32 %9, i32* %old + ; CHECK: ldrex + ; CHECK: cmp + ; CHECK: strex + call i32 @llvm.atomic.load.max.i32.p0i32( i32* %val2, i32 0 ) ; <i32>:10 [#uses=1] + store i32 %10, i32* %old + ret void +} + +declare i32 @llvm.atomic.load.add.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.load.sub.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.load.and.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.load.or.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.load.xor.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.load.min.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.load.max.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.load.umax.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.load.umin.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.swap.i32.p0i32(i32*, i32) nounwind + +declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32*, i32, i32) nounwind diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll new file mode 100644 index 0000000..d0c4f3a --- /dev/null +++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s +; Avoid some 's' 16-bit instruction which partially update CPSR (and add false +; dependency) when it isn't dependent on last CPSR defining instruction. +; rdar://8928208 + +define i32 @t(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { + entry: +; CHECK: t: +; CHECK: muls r2, r3, r2 +; CHECK-NEXT: mul r0, r0, r1 +; CHECK-NEXT: muls r0, r2, r0 + %0 = mul nsw i32 %a, %b + %1 = mul nsw i32 %c, %d + %2 = mul nsw i32 %0, %1 + ret i32 %2 +} diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll index 946db19..84f3813 100644 --- a/test/CodeGen/ARM/bfi.ll +++ b/test/CodeGen/ARM/bfi.ll @@ -31,8 +31,7 @@ define i32 @f3(i32 %A, i32 %B) nounwind { entry: ; CHECK: f3 ; CHECK: lsr{{.*}} #7 -; CHECK: mov r0, r1 -; CHECK: bfi r0, r2, #7, #16 +; CHECK: bfi {{.*}}, #7, #16 %and = and i32 %A, 8388480 ; <i32> [#uses=1] %and2 = and i32 %B, -8388481 ; <i32> [#uses=1] %or = or i32 %and2, %and ; <i32> [#uses=1] @@ -42,8 +41,8 @@ entry: ; rdar://8752056 define i32 @f4(i32 %a) nounwind { ; CHECK: f4 -; CHECK: movw r1, #3137 -; CHECK: bfi r1, r0, #15, #5 +; CHECK: movw [[R1:r[0-9]+]], #3137 +; CHECK: bfi [[R1]], {{r[0-9]+}}, #15, #5 %1 = shl i32 %a, 15 %ins7 = and i32 %1, 1015808 %ins12 = or i32 %ins7, 3137 @@ -62,3 +61,16 @@ entry: %3 = or i32 %2, %0 ret i32 %3 } + +; rdar://9609030 +define i32 @f6(i32 %a, i32 %b) nounwind readnone { +entry: +; CHECK: f6: +; CHECK-NOT: bic +; CHECK: bfi r0, r1, #8, #9 + %and = and i32 %a, -130817 + %and2 = shl i32 %b, 8 + %shl = and i32 %and2, 130816 + %or = or i32 %shl, %and + ret i32 %or +} diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index 4dc37aa..c460f7a 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKV6 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic -mattr=+vfp2 -arm-tail-calls | FileCheck %s -check-prefix=CHECKELF -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2 +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-tail-calls | FileCheck %s -check-prefix=CHECKT2D @t = weak global i32 ()* null ; <i32 ()**> [#uses=1] @@ -16,6 +16,10 @@ define void @t1() { define void @t2() { ; CHECKV6: t2: ; CHECKV6: bx r0 @ TAILCALL +; CHECKT2D: t2: +; CHECKT2D: ldr +; CHECKT2D-NEXT: ldr +; CHECKT2D-NEXT: bx r0 @ TAILCALL %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] ret void @@ -26,6 +30,9 @@ define void @t3() { ; CHECKV6: b _t2 @ TAILCALL ; CHECKELF: t3: ; CHECKELF: b t2(PLT) @ TAILCALL +; CHECKT2D: t3: +; CHECKT2D: b.w _t2 @ TAILCALL + tail call void @t2( ) ; <i32> [#uses=0] ret void } @@ -71,10 +78,10 @@ declare void @foo() nounwind define void @t7() nounwind { entry: -; CHECKT2: t7: -; CHECKT2: blxeq _foo -; CHECKT2-NEXT: pop.w -; CHECKT2-NEXT: b _foo +; CHECKT2D: t7: +; CHECKT2D: blxeq _foo +; CHECKT2D-NEXT: pop.w +; CHECKT2D-NEXT: b.w _foo br i1 undef, label %bb, label %bb1.lr.ph bb1.lr.ph: diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll index a6a7ed6..9b90408 100644 --- a/test/CodeGen/ARM/carry.ll +++ b/test/CodeGen/ARM/carry.ll @@ -19,3 +19,20 @@ entry: %tmp2 = sub i64 %tmp1, %b ret i64 %tmp2 } + +; add with live carry +define i64 @f3(i32 %al, i32 %bl) { +; CHECK: f3: +; CHECK: adds r +; CHECK: adcs r +; CHECK: adc r +entry: + ; unsigned wide add + %aw = zext i32 %al to i64 + %bw = zext i32 %bl to i64 + %cw = add i64 %aw, %bw + ; ch == carry bit + %ch = lshr i64 %cw, 32 + %dw = add i64 %ch, %bw + ret i64 %dw +} diff --git a/test/CodeGen/ARM/crash-greedy.ll b/test/CodeGen/ARM/crash-greedy.ll index 3a94110..8a865e2 100644 --- a/test/CodeGen/ARM/crash-greedy.ll +++ b/test/CodeGen/ARM/crash-greedy.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s +; RUN: llc < %s -regalloc=greedy -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim -verify-machineinstrs | FileCheck %s ; ; ARM tests that crash or fail with the greedy register allocator. @@ -6,7 +6,7 @@ target triple = "thumbv7-apple-darwin" declare double @exp(double) -; CHECK remat_subreg +; CHECK: remat_subreg define void @remat_subreg(float* nocapture %x, i32* %y, i32 %n, i32 %z, float %c, float %lambda, float* nocapture %ret_f, float* nocapture %ret_df) nounwind { entry: %conv16 = fpext float %lambda to double @@ -59,3 +59,26 @@ for.end: ; preds = %cond.end ret void } +; CHECK: insert_elem +; This test has a sub-register copy with a kill flag: +; %vreg6:ssub_3<def> = COPY %vreg6:ssub_2<kill>; QPR_VFP2:%vreg6 +; The rewriter must do something sensible with that, or the scavenger crashes. +define void @insert_elem() nounwind { +entry: + br i1 undef, label %if.end251, label %if.then84 + +if.then84: ; preds = %entry + br i1 undef, label %if.end251, label %if.then195 + +if.then195: ; preds = %if.then84 + %div = fdiv float 1.000000e+00, undef + %vecinit207 = insertelement <4 x float> undef, float %div, i32 1 + %vecinit208 = insertelement <4 x float> %vecinit207, float 1.000000e+00, i32 2 + %vecinit209 = insertelement <4 x float> %vecinit208, float 1.000000e+00, i32 3 + %mul216 = fmul <4 x float> zeroinitializer, %vecinit209 + store <4 x float> %mul216, <4 x float>* undef, align 16 + br label %if.end251 + +if.end251: ; preds = %if.then195, %if.then84, %entry + ret void +} diff --git a/test/CodeGen/ARM/debug-info-branch-folding.ll b/test/CodeGen/ARM/debug-info-branch-folding.ll new file mode 100644 index 0000000..9bdae43 --- /dev/null +++ b/test/CodeGen/ARM/debug-info-branch-folding.ll @@ -0,0 +1,94 @@ +; RUN: llc < %s - | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-macosx10.6.7" + +;CHECK: vadd.f32 q4, q8, q8 +;CHECK-NEXT: Ltmp +;CHECK-NEXT: @DEBUG_VALUE: y <- Q4+0 +;CHECK-NEXT: @DEBUG_VALUE: x <- Q4+0 + + +@.str = external constant [13 x i8] + +declare <4 x float> @test0001(float) nounwind readnone ssp + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { +entry: + br label %for.body9 + +for.body9: ; preds = %for.body9, %entry + %add19 = fadd <4 x float> undef, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, !dbg !39 + tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !27), !dbg !39 + %add20 = fadd <4 x float> undef, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, !dbg !39 + tail call void @llvm.dbg.value(metadata !{<4 x float> %add20}, i64 0, metadata !28), !dbg !39 + br i1 undef, label %for.end54, label %for.body9, !dbg !44 + +for.end54: ; preds = %for.body9 + %tmp115 = extractelement <4 x float> %add19, i32 1 + %conv6.i75 = fpext float %tmp115 to double, !dbg !45 + %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 + %tmp116 = extractelement <4 x float> %add20, i32 1 + %conv6.i76 = fpext float %tmp116 to double, !dbg !45 + %call.i83 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i76, double undef, double undef) nounwind, !dbg !45 + ret i32 0, !dbg !49 +} + +declare i32 @printf(i8* nocapture, ...) nounwind + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0, !10, !14} +!llvm.dbg.lv.test0001 = !{!18} +!llvm.dbg.lv.main = !{!19, !20, !24, !26, !27, !28, !29} +!llvm.dbg.lv.printFV = !{!30} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"build2.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"build2.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129915)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589846, metadata !2, metadata !"v4f32", metadata !1, i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!6 = metadata !{i32 590083, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ] +!7 = metadata !{i32 589860, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!8 = metadata !{metadata !9} +!9 = metadata !{i32 589857, i64 0, i64 3} ; [ DW_TAG_subrange_type ] +!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 589870, i32 0, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", metadata !15, i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 589865, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!16 = metadata !{i32 589845, metadata !15, metadata !"", metadata !15, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!17 = metadata !{null} +!18 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 16777219, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 590081, metadata !10, metadata !"argc", metadata !1, i32 16777275, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 590081, metadata !10, metadata !"argv", metadata !1, i32 33554491, metadata !21, i32 0} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] +!22 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 589860, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!24 = metadata !{i32 590080, metadata !25, metadata !"i", metadata !1, i32 60, metadata !13, i32 0} ; [ DW_TAG_auto_variable ] +!25 = metadata !{i32 589835, metadata !10, i32 59, i32 33, metadata !1, i32 14} ; [ DW_TAG_lexical_block ] +!26 = metadata !{i32 590080, metadata !25, metadata !"j", metadata !1, i32 60, metadata !13, i32 0} ; [ DW_TAG_auto_variable ] +!27 = metadata !{i32 590080, metadata !25, metadata !"x", metadata !1, i32 61, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!28 = metadata !{i32 590080, metadata !25, metadata !"y", metadata !1, i32 62, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 590080, metadata !25, metadata !"z", metadata !1, i32 63, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!30 = metadata !{i32 590081, metadata !14, metadata !"F", metadata !15, i32 16777257, metadata !31, i32 0} ; [ DW_TAG_arg_variable ] +!31 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] +!32 = metadata !{i32 589846, metadata !2, metadata !"FV", metadata !15, i32 25, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ] +!33 = metadata !{i32 589847, metadata !2, metadata !"", metadata !15, i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, i32 0} ; [ DW_TAG_union_type ] +!34 = metadata !{metadata !35, metadata !37} +!35 = metadata !{i32 589837, metadata !15, metadata !"V", metadata !15, i32 23, i64 128, i64 128, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] +!36 = metadata !{i32 589846, metadata !2, metadata !"v4sf", metadata !15, i32 3, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!37 = metadata !{i32 589837, metadata !15, metadata !"A", metadata !15, i32 24, i64 128, i64 32, i64 0, i32 0, metadata !38} ; [ DW_TAG_member ] +!38 = metadata !{i32 589825, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 32, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] +!39 = metadata !{i32 79, i32 7, metadata !40, null} +!40 = metadata !{i32 589835, metadata !41, i32 75, i32 35, metadata !1, i32 18} ; [ DW_TAG_lexical_block ] +!41 = metadata !{i32 589835, metadata !42, i32 75, i32 5, metadata !1, i32 17} ; [ DW_TAG_lexical_block ] +!42 = metadata !{i32 589835, metadata !43, i32 71, i32 32, metadata !1, i32 16} ; [ DW_TAG_lexical_block ] +!43 = metadata !{i32 589835, metadata !25, i32 71, i32 3, metadata !1, i32 15} ; [ DW_TAG_lexical_block ] +!44 = metadata !{i32 75, i32 5, metadata !42, null} +!45 = metadata !{i32 42, i32 2, metadata !46, metadata !48} +!46 = metadata !{i32 589835, metadata !47, i32 42, i32 2, metadata !15, i32 20} ; [ DW_TAG_lexical_block ] +!47 = metadata !{i32 589835, metadata !14, i32 41, i32 28, metadata !15, i32 19} ; [ DW_TAG_lexical_block ] +!48 = metadata !{i32 95, i32 3, metadata !25, null} +!49 = metadata !{i32 99, i32 3, metadata !25, null} diff --git a/test/CodeGen/ARM/debug-info-d16-reg.ll b/test/CodeGen/ARM/debug-info-d16-reg.ll new file mode 100644 index 0000000..8c9095e --- /dev/null +++ b/test/CodeGen/ARM/debug-info-d16-reg.ll @@ -0,0 +1,105 @@ +; RUN: llc < %s - | FileCheck %s +; Radar 9309221 +; Test dwarf reg no for d16 +;CHECK: DW_OP_regx +;CHECK-NEXT: 272 + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +@.str = private unnamed_addr constant [11 x i8] c"%p %lf %c\0A\00", align 4 +@.str1 = private unnamed_addr constant [6 x i8] c"point\00", align 4 + +define i32 @inlineprinter(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !19), !dbg !26 + tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !20), !dbg !26 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !21), !dbg !26 + %0 = zext i8 %c to i32, !dbg !27 + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !27 + ret i32 0, !dbg !29 +} + +define i32 @printer(i8* %ptr, double %val, i8 zeroext %c) nounwind optsize noinline { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !16), !dbg !30 + tail call void @llvm.dbg.value(metadata !{double %val}, i64 0, metadata !17), !dbg !30 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !18), !dbg !30 + %0 = zext i8 %c to i32, !dbg !31 + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %val, i32 %0) nounwind, !dbg !31 + ret i32 0, !dbg !33 +} + +declare i32 @printf(i8* nocapture, ...) nounwind + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !22), !dbg !34 + tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !23), !dbg !34 + %0 = sitofp i32 %argc to double, !dbg !35 + %1 = fadd double %0, 5.555552e+05, !dbg !35 + tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !24), !dbg !35 + %2 = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind, !dbg !36 + %3 = getelementptr inbounds i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !37 + %4 = trunc i32 %argc to i8, !dbg !37 + %5 = add i8 %4, 97, !dbg !37 + tail call void @llvm.dbg.value(metadata !{i8* %3}, i64 0, metadata !19) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata !{double %1}, i64 0, metadata !20) nounwind, !dbg !38 + tail call void @llvm.dbg.value(metadata !{i8 %5}, i64 0, metadata !21) nounwind, !dbg !38 + %6 = zext i8 %5 to i32, !dbg !39 + %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %3, double %1, i32 %6) nounwind, !dbg !39 + %8 = tail call i32 @printer(i8* %3, double %1, i8 zeroext %5) nounwind, !dbg !40 + ret i32 0, !dbg !41 +} + +declare i32 @puts(i8* nocapture) nounwind + +!llvm.dbg.sp = !{!0, !9, !10} +!llvm.dbg.lv.printer = !{!16, !17, !18} +!llvm.dbg.lv.inlineprinter = !{!19, !20, !21} +!llvm.dbg.lv.main = !{!22, !23, !24} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"printer", metadata !"printer", metadata !"printer", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @printer} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"a.c", metadata !"/tmp/", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"/tmp/a.c", metadata !"/tmp", metadata !"(LLVM build 00)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5, metadata !6, metadata !7, metadata !8} +!5 = metadata !{i32 589860, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!7 = metadata !{i32 589860, metadata !1, metadata !"double", metadata !1, i32 0, i64 64, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 589860, metadata !1, metadata !"unsigned char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!9 = metadata !{i32 589870, i32 0, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"inlineprinter", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i8*, double, i8)* @inlineprinter} ; [ DW_TAG_subprogram ] +!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"main", metadata !1, i32 18, metadata !11, i1 false, i1 true, i32 0, i32 0, null, i32 256, i1 true, i32 (i32, i8**)* @main} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !12, i32 0, null} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !5, metadata !5, metadata !13} +!13 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !14} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 589839, metadata !1, metadata !"", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !15} ; [ DW_TAG_pointer_type ] +!15 = metadata !{i32 589860, metadata !1, metadata !"char", metadata !1, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!16 = metadata !{i32 590081, metadata !0, metadata !"ptr", metadata !1, i32 11, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 590081, metadata !0, metadata !"val", metadata !1, i32 11, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 590081, metadata !0, metadata !"c", metadata !1, i32 11, metadata !8, i32 0} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 590081, metadata !9, metadata !"ptr", metadata !1, i32 4, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 590081, metadata !9, metadata !"val", metadata !1, i32 4, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 590081, metadata !9, metadata !"c", metadata !1, i32 4, metadata !8, i32 0} ; [ DW_TAG_arg_variable ] +!22 = metadata !{i32 590081, metadata !10, metadata !"argc", metadata !1, i32 17, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!23 = metadata !{i32 590081, metadata !10, metadata !"argv", metadata !1, i32 17, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!24 = metadata !{i32 590080, metadata !25, metadata !"dval", metadata !1, i32 19, metadata !7, i32 0} ; [ DW_TAG_auto_variable ] +!25 = metadata !{i32 589835, metadata !10, i32 18, i32 0, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!26 = metadata !{i32 4, i32 0, metadata !9, null} +!27 = metadata !{i32 6, i32 0, metadata !28, null} +!28 = metadata !{i32 589835, metadata !9, i32 5, i32 0, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!29 = metadata !{i32 7, i32 0, metadata !28, null} +!30 = metadata !{i32 11, i32 0, metadata !0, null} +!31 = metadata !{i32 13, i32 0, metadata !32, null} +!32 = metadata !{i32 589835, metadata !0, i32 12, i32 0, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!33 = metadata !{i32 14, i32 0, metadata !32, null} +!34 = metadata !{i32 17, i32 0, metadata !10, null} +!35 = metadata !{i32 19, i32 0, metadata !25, null} +!36 = metadata !{i32 20, i32 0, metadata !25, null} +!37 = metadata !{i32 21, i32 0, metadata !25, null} +!38 = metadata !{i32 4, i32 0, metadata !9, metadata !37} +!39 = metadata !{i32 6, i32 0, metadata !28, metadata !37} +!40 = metadata !{i32 22, i32 0, metadata !25, null} +!41 = metadata !{i32 23, i32 0, metadata !25, null} diff --git a/test/CodeGen/ARM/debug-info-qreg.ll b/test/CodeGen/ARM/debug-info-qreg.ll new file mode 100644 index 0000000..e83a83d --- /dev/null +++ b/test/CodeGen/ARM/debug-info-qreg.ll @@ -0,0 +1,94 @@ +; RUN: llc < %s - | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-macosx10.6.7" + +;CHECK: DW_OP_regx for Q register: D1 +;CHECK-NEXT: byte +;CHECK-NEXT: byte +;CHECK-NEXT: DW_OP_piece 8 +;CHECK-NEXT: byte 8 +;CHECK-NEXT: DW_OP_regx for Q register: D2 +;CHECK-NEXT: byte +;CHECK-NEXT: byte +;CHECK-NEXT: DW_OP_piece 8 +;CHECK-NEXT: byte 8 + +@.str = external constant [13 x i8] + +declare <4 x float> @test0001(float) nounwind readnone ssp + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { +entry: + br label %for.body9 + +for.body9: ; preds = %for.body9, %entry + %add19 = fadd <4 x float> undef, <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 1.000000e+00>, !dbg !39 + br i1 undef, label %for.end54, label %for.body9, !dbg !44 + +for.end54: ; preds = %for.body9 + tail call void @llvm.dbg.value(metadata !{<4 x float> %add19}, i64 0, metadata !27), !dbg !39 + %tmp115 = extractelement <4 x float> %add19, i32 1 + %conv6.i75 = fpext float %tmp115 to double, !dbg !45 + %call.i82 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([13 x i8]* @.str, i32 0, i32 0), double undef, double %conv6.i75, double undef, double undef) nounwind, !dbg !45 + ret i32 0, !dbg !49 +} + +declare i32 @printf(i8* nocapture, ...) nounwind + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0, !10, !14} +!llvm.dbg.lv.test0001 = !{!18} +!llvm.dbg.lv.main = !{!19, !20, !24, !26, !27, !28, !29} +!llvm.dbg.lv.printFV = !{!30} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"test0001", metadata !"test0001", metadata !"", metadata !1, i32 3, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, <4 x float> (float)* @test0001, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"build2.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"build2.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129915)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589846, metadata !2, metadata !"v4f32", metadata !1, i32 14, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!6 = metadata !{i32 590083, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 128, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_vector_type ] +!7 = metadata !{i32 589860, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!8 = metadata !{metadata !9} +!9 = metadata !{i32 589857, i64 0, i64 3} ; [ DW_TAG_subrange_type ] +!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 59, metadata !11, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{metadata !13} +!13 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 589870, i32 0, metadata !15, metadata !"printFV", metadata !"printFV", metadata !"", metadata !15, i32 41, metadata !16, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 589865, metadata !"/Volumes/Lalgate/work/llvm/projects/llvm-test/SingleSource/UnitTests/Vector/helpers.h", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!16 = metadata !{i32 589845, metadata !15, metadata !"", metadata !15, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !17, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!17 = metadata !{null} +!18 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 16777219, metadata !7, i32 0} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 590081, metadata !10, metadata !"argc", metadata !1, i32 16777275, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 590081, metadata !10, metadata !"argv", metadata !1, i32 33554491, metadata !21, i32 0} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !22} ; [ DW_TAG_pointer_type ] +!22 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !23} ; [ DW_TAG_pointer_type ] +!23 = metadata !{i32 589860, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!24 = metadata !{i32 590080, metadata !25, metadata !"i", metadata !1, i32 60, metadata !13, i32 0} ; [ DW_TAG_auto_variable ] +!25 = metadata !{i32 589835, metadata !10, i32 59, i32 33, metadata !1, i32 14} ; [ DW_TAG_lexical_block ] +!26 = metadata !{i32 590080, metadata !25, metadata !"j", metadata !1, i32 60, metadata !13, i32 0} ; [ DW_TAG_auto_variable ] +!27 = metadata !{i32 590080, metadata !25, metadata !"x", metadata !1, i32 61, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!28 = metadata !{i32 590080, metadata !25, metadata !"y", metadata !1, i32 62, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 590080, metadata !25, metadata !"z", metadata !1, i32 63, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!30 = metadata !{i32 590081, metadata !14, metadata !"F", metadata !15, i32 16777257, metadata !31, i32 0} ; [ DW_TAG_arg_variable ] +!31 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ] +!32 = metadata !{i32 589846, metadata !2, metadata !"FV", metadata !15, i32 25, i64 0, i64 0, i64 0, i32 0, metadata !33} ; [ DW_TAG_typedef ] +!33 = metadata !{i32 589847, metadata !2, metadata !"", metadata !15, i32 22, i64 128, i64 128, i64 0, i32 0, i32 0, metadata !34, i32 0, i32 0} ; [ DW_TAG_union_type ] +!34 = metadata !{metadata !35, metadata !37} +!35 = metadata !{i32 589837, metadata !15, metadata !"V", metadata !15, i32 23, i64 128, i64 128, i64 0, i32 0, metadata !36} ; [ DW_TAG_member ] +!36 = metadata !{i32 589846, metadata !2, metadata !"v4sf", metadata !15, i32 3, i64 0, i64 0, i64 0, i32 0, metadata !6} ; [ DW_TAG_typedef ] +!37 = metadata !{i32 589837, metadata !15, metadata !"A", metadata !15, i32 24, i64 128, i64 32, i64 0, i32 0, metadata !38} ; [ DW_TAG_member ] +!38 = metadata !{i32 589825, metadata !2, metadata !"", metadata !2, i32 0, i64 128, i64 32, i32 0, i32 0, metadata !7, metadata !8, i32 0, i32 0} ; [ DW_TAG_array_type ] +!39 = metadata !{i32 79, i32 7, metadata !40, null} +!40 = metadata !{i32 589835, metadata !41, i32 75, i32 35, metadata !1, i32 18} ; [ DW_TAG_lexical_block ] +!41 = metadata !{i32 589835, metadata !42, i32 75, i32 5, metadata !1, i32 17} ; [ DW_TAG_lexical_block ] +!42 = metadata !{i32 589835, metadata !43, i32 71, i32 32, metadata !1, i32 16} ; [ DW_TAG_lexical_block ] +!43 = metadata !{i32 589835, metadata !25, i32 71, i32 3, metadata !1, i32 15} ; [ DW_TAG_lexical_block ] +!44 = metadata !{i32 75, i32 5, metadata !42, null} +!45 = metadata !{i32 42, i32 2, metadata !46, metadata !48} +!46 = metadata !{i32 589835, metadata !47, i32 42, i32 2, metadata !15, i32 20} ; [ DW_TAG_lexical_block ] +!47 = metadata !{i32 589835, metadata !14, i32 41, i32 28, metadata !15, i32 19} ; [ DW_TAG_lexical_block ] +!48 = metadata !{i32 95, i32 3, metadata !25, null} +!49 = metadata !{i32 99, i32 3, metadata !25, null} diff --git a/test/CodeGen/ARM/debug-info-s16-reg.ll b/test/CodeGen/ARM/debug-info-s16-reg.ll new file mode 100644 index 0000000..548c9bd --- /dev/null +++ b/test/CodeGen/ARM/debug-info-s16-reg.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s - | FileCheck %s +; Radar 9309221 +; Test dwarf reg no for s16 +;CHECK: DW_OP_regx for S register +;CHECK-NEXT: byte +;CHECK-NEXT: byte +;CHECK-NEXT: DW_OP_bit_piece 32 0 + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-macosx10.6.7" + +@.str = private unnamed_addr constant [11 x i8] c"%p %lf %c\0A\00" +@.str1 = private unnamed_addr constant [6 x i8] c"point\00" + +define i32 @inlineprinter(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !8), !dbg !24 + tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !10), !dbg !25 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !12), !dbg !26 + %conv = fpext float %val to double, !dbg !27 + %conv3 = zext i8 %c to i32, !dbg !27 + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !27 + ret i32 0, !dbg !29 +} + +declare i32 @printf(i8* nocapture, ...) nounwind optsize + +define i32 @printer(i8* %ptr, float %val, i8 zeroext %c) nounwind optsize noinline ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i8* %ptr}, i64 0, metadata !14), !dbg !30 + tail call void @llvm.dbg.value(metadata !{float %val}, i64 0, metadata !15), !dbg !31 + tail call void @llvm.dbg.value(metadata !{i8 %c}, i64 0, metadata !16), !dbg !32 + %conv = fpext float %val to double, !dbg !33 + %conv3 = zext i8 %c to i32, !dbg !33 + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %ptr, double %conv, i32 %conv3) nounwind optsize, !dbg !33 + ret i32 0, !dbg !35 +} + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !17), !dbg !36 + tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !18), !dbg !37 + %conv = sitofp i32 %argc to double, !dbg !38 + %add = fadd double %conv, 5.555552e+05, !dbg !38 + %conv1 = fptrunc double %add to float, !dbg !38 + tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !22), !dbg !38 + %call = tail call i32 @puts(i8* getelementptr inbounds ([6 x i8]* @.str1, i32 0, i32 0)) nounwind optsize, !dbg !39 + %add.ptr = getelementptr i8* bitcast (i32 (i32, i8**)* @main to i8*), i32 %argc, !dbg !40 + %add5 = add nsw i32 %argc, 97, !dbg !40 + %conv6 = trunc i32 %add5 to i8, !dbg !40 + tail call void @llvm.dbg.value(metadata !{i8* %add.ptr}, i64 0, metadata !8) nounwind, !dbg !41 + tail call void @llvm.dbg.value(metadata !{float %conv1}, i64 0, metadata !10) nounwind, !dbg !42 + tail call void @llvm.dbg.value(metadata !{i8 %conv6}, i64 0, metadata !12) nounwind, !dbg !43 + %conv.i = fpext float %conv1 to double, !dbg !44 + %conv3.i = and i32 %add5, 255, !dbg !44 + %call.i = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([11 x i8]* @.str, i32 0, i32 0), i8* %add.ptr, double %conv.i, i32 %conv3.i) nounwind optsize, !dbg !44 + %call14 = tail call i32 @printer(i8* %add.ptr, float %conv1, i8 zeroext %conv6) optsize, !dbg !45 + ret i32 0, !dbg !46 +} + +declare i32 @puts(i8* nocapture) nounwind optsize + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0, !6, !7} +!llvm.dbg.lv.inlineprinter = !{!8, !10, !12} +!llvm.dbg.lv.printer = !{!14, !15, !16} +!llvm.dbg.lv.main = !{!17, !18, !22} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"inlineprinter", metadata !"inlineprinter", metadata !"", metadata !1, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @inlineprinter, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 129915)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589870, i32 0, metadata !1, metadata !"printer", metadata !"printer", metadata !"", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i8*, float, i8)* @printer, null} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 18, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main, null} ; [ DW_TAG_subprogram ] +!8 = metadata !{i32 590081, metadata !0, metadata !"ptr", metadata !1, i32 16777220, metadata !9, i32 0} ; [ DW_TAG_arg_variable ] +!9 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ] +!10 = metadata !{i32 590081, metadata !0, metadata !"val", metadata !1, i32 33554436, metadata !11, i32 0} ; [ DW_TAG_arg_variable ] +!11 = metadata !{i32 589860, metadata !2, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!12 = metadata !{i32 590081, metadata !0, metadata !"c", metadata !1, i32 50331652, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!13 = metadata !{i32 589860, metadata !2, metadata !"unsigned char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 8} ; [ DW_TAG_base_type ] +!14 = metadata !{i32 590081, metadata !6, metadata !"ptr", metadata !1, i32 16777227, metadata !9, i32 0} ; [ DW_TAG_arg_variable ] +!15 = metadata !{i32 590081, metadata !6, metadata !"val", metadata !1, i32 33554443, metadata !11, i32 0} ; [ DW_TAG_arg_variable ] +!16 = metadata !{i32 590081, metadata !6, metadata !"c", metadata !1, i32 50331659, metadata !13, i32 0} ; [ DW_TAG_arg_variable ] +!17 = metadata !{i32 590081, metadata !7, metadata !"argc", metadata !1, i32 16777233, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!18 = metadata !{i32 590081, metadata !7, metadata !"argv", metadata !1, i32 33554449, metadata !19, i32 0} ; [ DW_TAG_arg_variable ] +!19 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !20} ; [ DW_TAG_pointer_type ] +!20 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !21} ; [ DW_TAG_pointer_type ] +!21 = metadata !{i32 589860, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ] +!22 = metadata !{i32 590080, metadata !23, metadata !"dval", metadata !1, i32 19, metadata !11, i32 0} ; [ DW_TAG_auto_variable ] +!23 = metadata !{i32 589835, metadata !7, i32 18, i32 1, metadata !1, i32 2} ; [ DW_TAG_lexical_block ] +!24 = metadata !{i32 4, i32 22, metadata !0, null} +!25 = metadata !{i32 4, i32 33, metadata !0, null} +!26 = metadata !{i32 4, i32 52, metadata !0, null} +!27 = metadata !{i32 6, i32 3, metadata !28, null} +!28 = metadata !{i32 589835, metadata !0, i32 5, i32 1, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!29 = metadata !{i32 7, i32 3, metadata !28, null} +!30 = metadata !{i32 11, i32 42, metadata !6, null} +!31 = metadata !{i32 11, i32 53, metadata !6, null} +!32 = metadata !{i32 11, i32 72, metadata !6, null} +!33 = metadata !{i32 13, i32 3, metadata !34, null} +!34 = metadata !{i32 589835, metadata !6, i32 12, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!35 = metadata !{i32 14, i32 3, metadata !34, null} +!36 = metadata !{i32 17, i32 15, metadata !7, null} +!37 = metadata !{i32 17, i32 28, metadata !7, null} +!38 = metadata !{i32 19, i32 31, metadata !23, null} +!39 = metadata !{i32 20, i32 3, metadata !23, null} +!40 = metadata !{i32 21, i32 3, metadata !23, null} +!41 = metadata !{i32 4, i32 22, metadata !0, metadata !40} +!42 = metadata !{i32 4, i32 33, metadata !0, metadata !40} +!43 = metadata !{i32 4, i32 52, metadata !0, metadata !40} +!44 = metadata !{i32 6, i32 3, metadata !28, metadata !40} +!45 = metadata !{i32 22, i32 3, metadata !23, null} +!46 = metadata !{i32 23, i32 1, metadata !23, null} diff --git a/test/CodeGen/ARM/debug-info-sreg2.ll b/test/CodeGen/ARM/debug-info-sreg2.ll new file mode 100644 index 0000000..16aeab3 --- /dev/null +++ b/test/CodeGen/ARM/debug-info-sreg2.ll @@ -0,0 +1,61 @@ +; RUN: llc < %s - | FileCheck %s +; Radar 9376013 +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-macosx10.6.7" + +;CHECK: Ldebug_loc0: +;CHECK-NEXT: .long Ltmp1 +;CHECK-NEXT: .long Ltmp3 +;CHECK-NEXT: Lset9 = Ltmp10-Ltmp9 @ Loc expr size +;CHECK-NEXT: .short Lset9 +;CHECK-NEXT: Ltmp9: +;CHECK-NEXT: .byte 144 @ DW_OP_regx for S register + +define void @_Z3foov() optsize ssp { +entry: + %call = tail call float @_Z3barv() optsize, !dbg !11 + tail call void @llvm.dbg.value(metadata !{float %call}, i64 0, metadata !5), !dbg !11 + %call16 = tail call float @_Z2f2v() optsize, !dbg !12 + %cmp7 = fcmp olt float %call, %call16, !dbg !12 + br i1 %cmp7, label %for.body, label %for.end, !dbg !12 + +for.body: ; preds = %entry, %for.body + %k.08 = phi float [ %inc, %for.body ], [ %call, %entry ] + %call4 = tail call float @_Z2f3f(float %k.08) optsize, !dbg !13 + %inc = fadd float %k.08, 1.000000e+00, !dbg !14 + %call1 = tail call float @_Z2f2v() optsize, !dbg !12 + %cmp = fcmp olt float %inc, %call1, !dbg !12 + br i1 %cmp, label %for.body, label %for.end, !dbg !12 + +for.end: ; preds = %for.body, %entry + ret void, !dbg !15 +} + +declare float @_Z3barv() optsize + +declare float @_Z2f2v() optsize + +declare float @_Z2f3f(float) optsize + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} +!llvm.dbg.sp = !{!1} +!llvm.dbg.lv._Z3foov = !{!5, !8} + +!0 = metadata !{i32 589841, i32 0, i32 4, metadata !"k.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 130845)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"_Z3foov", metadata !2, i32 5, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void ()* @_Z3foov, null, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 589865, metadata !"k.cc", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null} +!5 = metadata !{i32 590080, metadata !6, metadata !"k", metadata !2, i32 6, metadata !7, i32 0} ; [ DW_TAG_auto_variable ] +!6 = metadata !{i32 589835, metadata !1, i32 5, i32 12, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!7 = metadata !{i32 589860, metadata !0, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 590080, metadata !9, metadata !"y", metadata !2, i32 8, metadata !7, i32 0} ; [ DW_TAG_auto_variable ] +!9 = metadata !{i32 589835, metadata !10, i32 7, i32 25, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!10 = metadata !{i32 589835, metadata !6, i32 7, i32 3, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 6, i32 18, metadata !6, null} +!12 = metadata !{i32 7, i32 3, metadata !6, null} +!13 = metadata !{i32 8, i32 20, metadata !9, null} +!14 = metadata !{i32 7, i32 20, metadata !10, null} +!15 = metadata !{i32 10, i32 1, metadata !6, null} diff --git a/test/CodeGen/ARM/divmod.ll b/test/CodeGen/ARM/divmod.ll deleted file mode 100644 index 04b8fbf..0000000 --- a/test/CodeGen/ARM/divmod.ll +++ /dev/null @@ -1,27 +0,0 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -use-divmod-libcall | FileCheck %s - -define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp { -entry: -; CHECK: foo: -; CHECK: bl ___divmodsi4 -; CHECK-NOT: bl ___divmodsi4 - %div = sdiv i32 %x, %y - store i32 %div, i32* %P, align 4 - %rem = srem i32 %x, %y - %arrayidx6 = getelementptr inbounds i32* %P, i32 1 - store i32 %rem, i32* %arrayidx6, align 4 - ret void -} - -define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp { -entry: -; CHECK: bar: -; CHECK: bl ___udivmodsi4 -; CHECK-NOT: bl ___udivmodsi4 - %div = udiv i32 %x, %y - store i32 %div, i32* %P, align 4 - %rem = urem i32 %x, %y - %arrayidx6 = getelementptr inbounds i32* %P, i32 1 - store i32 %rem, i32* %arrayidx6, align 4 - ret void -} diff --git a/test/CodeGen/ARM/eh-resume-darwin.ll b/test/CodeGen/ARM/eh-resume-darwin.ll new file mode 100644 index 0000000..e475508 --- /dev/null +++ b/test/CodeGen/ARM/eh-resume-darwin.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s -march=arm | FileCheck %s +target triple = "armv6-apple-macosx10.6" + +declare void @func() + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind + +declare void @llvm.eh.resume(i8*, i32) + +declare i32 @__gxx_personality_sj0(...) + +define void @test0() { +entry: + invoke void @func() + to label %cont unwind label %lpad + +cont: + ret void + +lpad: + %exn = call i8* @llvm.eh.exception() + %sel = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_sj0 to i8*), i32 0) + call void @llvm.eh.resume(i8* %exn, i32 %sel) noreturn + unreachable +} + +; CHECK: __Unwind_SjLj_Resume diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll index f03282b..51efe51 100644 --- a/test/CodeGen/ARM/fabss.ll +++ b/test/CodeGen/ARM/fabss.ll @@ -24,4 +24,4 @@ declare float @fabsf(float) ; CORTEXA8: test: ; CORTEXA8: vabs.f32 d1, d1 ; CORTEXA9: test: -; CORTEXA9: vabs.f32 s1, s1 +; CORTEXA9: vabs.f32 s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index 749690e..e35103c 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vadd.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vadd.f32 s0, s1, s0 +; CORTEXA9: vadd.f32 s{{.}}, s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fast-isel-crash2.ll b/test/CodeGen/ARM/fast-isel-crash2.ll new file mode 100644 index 0000000..aa06299 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-crash2.ll @@ -0,0 +1,9 @@ +; RUN: llc < %s -O0 -mtriple=thumbv7-apple-darwin +; rdar://9515076 +; (Make sure this doesn't crash.) + +define i32 @test(i32 %i) { + %t = trunc i32 %i to i4 + %r = sext i4 %t to i32 + ret i32 %r +} diff --git a/test/CodeGen/ARM/fast-isel-redefinition.ll b/test/CodeGen/ARM/fast-isel-redefinition.ll new file mode 100644 index 0000000..08dcc64 --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-redefinition.ll @@ -0,0 +1,11 @@ +; RUN: llc -O0 -regalloc=linearscan < %s +; This isn't exactly a useful set of command-line options, but check that it +; doesn't crash. (It was crashing because a register was getting redefined.) + +target triple = "thumbv7-apple-macosx10.6.7" + +define i32 @f(i32* %x) nounwind ssp { + %y = getelementptr inbounds i32* %x, i32 5000 + %tmp103 = load i32* %y, align 4 + ret i32 %tmp103 +} diff --git a/test/CodeGen/ARM/fast-isel-static.ll b/test/CodeGen/ARM/fast-isel-static.ll index 2d79674..a86e325 100644 --- a/test/CodeGen/ARM/fast-isel-static.ll +++ b/test/CodeGen/ARM/fast-isel-static.ll @@ -23,7 +23,7 @@ entry: %z = alloca float, align 4 store float 0.000000e+00, float* %ztot, align 4 store float 1.000000e+00, float* %z, align 4 -; CHECK-LONG: blx r2 +; CHECK-LONG: blx r ; CHECK-NORM: bl _myadd call void @myadd(float* %ztot, float* %z) ret i32 0 diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index dd806ec..499c97f 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -1,8 +1,7 @@ -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-darwin -; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=armv7-apple-darwin | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=THUMB ; Very basic fast-isel functionality. - define i32 @add(i32 %a, i32 %b) nounwind { entry: %a.addr = alloca i32, align 4 @@ -13,4 +12,149 @@ entry: %tmp1 = load i32* %b.addr %add = add nsw i32 %tmp, %tmp1 ret i32 %add -}
\ No newline at end of file +} + +; Check truncate to bool +define void @test1(i32 %tmp) nounwind { +entry: +%tobool = trunc i32 %tmp to i1 +br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry +call void @test1(i32 0) +br label %if.end + +if.end: ; preds = %if.then, %entry +ret void +; ARM: test1: +; ARM: tst r0, #1 +; THUMB: test1: +; THUMB: tst.w r0, #1 +} + +; Check some simple operations with immediates +define void @test2(i32 %tmp, i32* %ptr) nounwind { +; THUMB: test2: +; ARM: test2: + +b1: + %a = add i32 %tmp, 4096 + store i32 %a, i32* %ptr + br label %b2 + +; THUMB: add.w {{.*}} #4096 +; ARM: add {{.*}} #1, #20 + +b2: + %b = add i32 %tmp, 4095 + store i32 %b, i32* %ptr + br label %b3 +; THUMB: addw {{.*}} #4095 +; ARM: movw {{.*}} #4095 +; ARM: add + +b3: + %c = or i32 %tmp, 4 + store i32 %c, i32* %ptr + ret void + +; THUMB: orr {{.*}} #4 +; ARM: orr {{.*}} #4 +} + +define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind { +; THUMB: test3: +; ARM: test3: + +bb1: + %a1 = trunc i32 %tmp to i16 + %a2 = trunc i16 %a1 to i8 + %a3 = trunc i8 %a2 to i1 + %a4 = zext i1 %a3 to i8 + store i8 %a4, i8* %ptr3 + %a5 = zext i8 %a4 to i16 + store i16 %a5, i16* %ptr2 + %a6 = zext i16 %a5 to i32 + store i32 %a6, i32* %ptr1 + br label %bb2 + +; THUMB: and +; THUMB: strb +; THUMB: uxtb +; THUMB: strh +; THUMB: uxth +; ARM: and +; ARM: strb +; ARM: uxtb +; ARM: strh +; ARM: uxth + +bb2: + %b1 = trunc i32 %tmp to i16 + %b2 = trunc i16 %b1 to i8 + store i8 %b2, i8* %ptr3 + %b3 = sext i8 %b2 to i16 + store i16 %b3, i16* %ptr2 + %b4 = sext i16 %b3 to i32 + store i32 %b4, i32* %ptr1 + br label %bb3 + +; THUMB: strb +; THUMB: sxtb +; THUMB: strh +; THUMB: sxth +; ARM: strb +; ARM: sxtb +; ARM: strh +; ARM: sxth + +bb3: + %c1 = load i8* %ptr3 + %c2 = load i16* %ptr2 + %c3 = load i32* %ptr1 + %c4 = zext i8 %c1 to i32 + %c5 = sext i16 %c2 to i32 + %c6 = add i32 %c4, %c5 + %c7 = sub i32 %c3, %c6 + store i32 %c7, i32* %ptr1 + ret void + +; THUMB: ldrb +; THUMB: ldrh +; THUMB: uxtb +; THUMB: sxth +; THUMB: add +; THUMB: sub +; ARM: ldrb +; ARM: ldrh +; ARM: uxtb +; ARM: sxth +; ARM: add +; ARM: sub +} + +; Check loads/stores with globals +@test4g = external global i32 + +define void @test4() { + %a = load i32* @test4g + %b = add i32 %a, 1 + store i32 %b, i32* @test4g + ret void + +; THUMB: ldr.n r0, LCPI4_1 +; THUMB: ldr r0, [r0] +; THUMB: ldr r0, [r0] +; THUMB: adds r0, #1 +; THUMB: ldr.n r1, LCPI4_0 +; THUMB: ldr r1, [r1] +; THUMB: str r0, [r1] + +; ARM: ldr r0, LCPI4_1 +; ARM: ldr r0, [r0] +; ARM: ldr r0, [r0] +; ARM: add r0, r0, #1 +; ARM: ldr r1, LCPI4_0 +; ARM: ldr r1, [r1] +; ARM: str r0, [r1] +} diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll index 9e94e39..c4dbeb9 100644 --- a/test/CodeGen/ARM/fcopysign.ll +++ b/test/CodeGen/ARM/fcopysign.ll @@ -10,7 +10,7 @@ entry: ; HARD: test1: ; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000 -; HARD: vbsl [[REG1]], d2, d0 +; HARD: vbsl [[REG1]], d %0 = tail call float @copysignf(float %x, float %y) nounwind ret float %0 } @@ -44,15 +44,33 @@ entry: define i32 @test4() ssp { entry: ; SOFT: test4: -; SOFT: vcvt.f32.f64 s0, -; SOFT: vmov.i32 [[REG4:(d[0-9]+)]], #0x80000000 -; SOFT: vbic [[REG5:(d[0-9]+)]], d0, [[REG4]] -; SOFT: vorr d0, [[REG4]], [[REG5]] +; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00 +; This S-reg must be the first sub-reg of the last D-reg on vbsl. +; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]] +; SOFT: vshr.u64 [[REG4]], [[REG4]], #32 +; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000 +; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}} %call80 = tail call double @copysign(double 1.000000e+00, double undef) %conv81 = fptrunc double %call80 to float %tmp88 = bitcast float %conv81 to i32 ret i32 %tmp88 } +; rdar://9287902 +define float @test5() nounwind { +entry: +; SOFT: test5: +; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000 +; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1 +; SOFT: vshr.u64 [[REG7]], [[REG7]], #32 +; SOFT: vbsl [[REG6]], [[REG7]], + %0 = tail call double (...)* @bar() nounwind + %1 = fptrunc double %0 to float + %2 = tail call float @copysignf(float 5.000000e-01, float %1) nounwind readnone + %3 = fadd float %1, %2 + ret float %3 +} + +declare double @bar(...) declare double @copysign(double, double) nounwind declare float @copysignf(float, float) nounwind diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll index 0c31495..31c1ca9 100644 --- a/test/CodeGen/ARM/fdivs.ll +++ b/test/CodeGen/ARM/fdivs.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vdiv.f32 s0, s1, s0 ; CORTEXA9: test: -; CORTEXA9: vdiv.f32 s0, s1, s0 +; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index fb83ef6..b63f609 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -1,6 +1,8 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NEON ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8 +; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9 +; RUN: llc < %s -mtriple=arm-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s -check-prefix=HARD define float @t1(float %acc, float %a, float %b) { entry: @@ -49,3 +51,54 @@ entry: %1 = fadd float %0, %acc ret float %1 } + +; It's possible to make use of fp vmla / vmls on Cortex-A9. +; rdar://8659675 +define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) { +entry: +; A8: t4: +; A8: vmul.f32 +; A8: vmul.f32 +; A8: vadd.f32 +; A8: vadd.f32 + +; Two vmla with now RAW hazard +; A9: t4: +; A9: vmla.f32 +; A9: vmla.f32 + +; HARD: t4: +; HARD: vmla.f32 s0, s1, s2 +; HARD: vmla.f32 s3, s1, s4 + %0 = fmul float %a, %b + %1 = fadd float %acc1, %0 + %2 = fmul float %a, %c + %3 = fadd float %acc2, %2 + store float %1, float* %P1 + store float %3, float* %P2 + ret void +} + +define float @t5(float %a, float %b, float %c, float %d, float %e) { +entry: +; A8: t5: +; A8: vmul.f32 +; A8: vmul.f32 +; A8: vadd.f32 +; A8: vadd.f32 + +; A9: t5: +; A9: vmla.f32 +; A9: vmul.f32 +; A9: vadd.f32 + +; HARD: t5: +; HARD: vmla.f32 s4, s0, s1 +; HARD: vmul.f32 s0, s2, s3 +; HARD: vadd.f32 s0, s4, s0 + %0 = fmul float %a, %b + %1 = fadd float %e, %0 + %2 = fmul float %c, %d + %3 = fadd float %1, %2 + ret float %3 +} diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index ef4e3e5..bc118b8 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -20,4 +20,4 @@ entry: ; CORTEXA8: test: ; CORTEXA8: vmul.f32 d0, d1, d0 ; CORTEXA9: test: -; CORTEXA9: vmul.f32 s0, s1, s0 +; CORTEXA9: vmul.f32 s{{.}}, s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll index 9facf20..6081712 100644 --- a/test/CodeGen/ARM/fnmscs.ll +++ b/test/CodeGen/ARM/fnmscs.ll @@ -29,7 +29,7 @@ entry: ; NEON: vnmla.f32 ; A8: t2: -; A8: vnmul.f32 s{{[0123]}}, s{{[0123]}}, s{{[0123]}} +; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}} ; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} %0 = fmul float %a, %b %1 = fmul float -1.0, %0 diff --git a/test/CodeGen/ARM/fp-arg-shuffle.ll b/test/CodeGen/ARM/fp-arg-shuffle.ll index 59303ac..ae02b79 100644 --- a/test/CodeGen/ARM/fp-arg-shuffle.ll +++ b/test/CodeGen/ARM/fp-arg-shuffle.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon -float-abi=soft | FileCheck %s ; CHECK: function1 -; CHECK-NOT: vmov r +; CHECK-NOT: vmov define double @function1(double %a, double %b, double %c, double %d, double %e, double %f) nounwind noinline ssp { entry: %call = tail call double @function2(double %f, double %e, double %d, double %c, double %b, double %a) nounwind diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll index 1ef9f7f..86c06f1 100644 --- a/test/CodeGen/ARM/fp_convert.ll +++ b/test/CodeGen/ARM/fp_convert.ll @@ -5,7 +5,7 @@ define i32 @test1(float %a, float %b) { ; VFP2: test1: -; VFP2: vcvt.s32.f32 s0, s0 +; VFP2: vcvt.s32.f32 s{{.}}, s{{.}} ; NEON: test1: ; NEON: vcvt.s32.f32 d0, d0 entry: @@ -16,7 +16,7 @@ entry: define i32 @test2(float %a, float %b) { ; VFP2: test2: -; VFP2: vcvt.u32.f32 s0, s0 +; VFP2: vcvt.u32.f32 s{{.}}, s{{.}} ; NEON: test2: ; NEON: vcvt.u32.f32 d0, d0 entry: @@ -27,7 +27,7 @@ entry: define float @test3(i32 %a, i32 %b) { ; VFP2: test3: -; VFP2: vcvt.f32.u32 s0, s0 +; VFP2: vcvt.f32.u32 s{{.}}, s{{.}} ; NEON: test3: ; NEON: vcvt.f32.u32 d0, d0 entry: @@ -38,7 +38,7 @@ entry: define float @test4(i32 %a, i32 %b) { ; VFP2: test4: -; VFP2: vcvt.f32.s32 s0, s0 +; VFP2: vcvt.f32.s32 s{{.}}, s{{.}} ; NEON: test4: ; NEON: vcvt.f32.s32 d0, d0 entry: diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index 19dad3a..f0ab9dd 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -42,20 +42,23 @@ L3: ; preds = %L4, %bb2 br label %L2 L2: ; preds = %L3, %bb2 +; THUMB: muls %res.2 = phi i32 [ %res.1, %L3 ], [ 1, %bb2 ] ; <i32> [#uses=1] %phitmp = mul i32 %res.2, 6 ; <i32> [#uses=1] br label %L1 L1: ; preds = %L2, %bb2 %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ] ; <i32> [#uses=1] -; ARM: ldr r1, LCPI -; ARM: add r1, pc, r1 -; ARM: str r1 -; THUMB: ldr.n r2, LCPI -; THUMB: add r2, pc -; THUMB: str r2 -; THUMB2: ldr.n r2, LCPI -; THUMB2-NEXT: str r2 +; ARM: ldr [[R1:r[0-9]+]], LCPI +; ARM: add [[R1b:r[0-9]+]], pc, [[R1]] +; ARM: str [[R1b]] +; THUMB: ldr.n +; THUMB: add +; THUMB: ldr.n [[R2:r[0-9]+]], LCPI +; THUMB: add [[R2]], pc +; THUMB: str [[R2]] +; THUMB2: ldr.n [[R2:r[0-9]+]], LCPI +; THUMB2-NEXT: str{{(.w)?}} [[R2]] store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4 ret i32 %res.3 } diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index 9f77ad1..58687b9 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -6,7 +6,7 @@ define void @t() nounwind { entry: ; CHECK: vmov.I64 q15, #0 -; CHECK: vmov.32 d30[0], r0 +; CHECK: vmov.32 d30[0], ; CHECK: vmov q8, q15 %tmp = alloca %struct.int32x4_t, align 16 call void asm sideeffect "vmov.I64 q15, #0\0Avmov.32 d30[0], $1\0Avmov ${0:q}, q15\0A", "=*w,r,~{d31},~{d30}"(%struct.int32x4_t* %tmp, i32 8192) nounwind @@ -23,3 +23,38 @@ entry: %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind ret void } + +; Radar 9306086 + +%0 = type { <8 x i8>, <16 x i8>* } + +define hidden void @conv4_8_E() nounwind { +entry: +%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1, :128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind +unreachable +} + +; Radar 9037836 & 9119939 + +define i32 @t3() nounwind { +entry: +tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind +ret i32 0 +} + +; Radar 9037836 & 9119939 + +@k.2126 = internal unnamed_addr global float 1.000000e+00 +define i32 @t4() nounwind { +entry: +call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind +ret i32 0 +} + +; Radar 9037836 & 9119939 + +define i32 @t5() nounwind { +entry: +call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind +ret i32 0 +} diff --git a/test/CodeGen/ARM/intrinsics.ll b/test/CodeGen/ARM/intrinsics.ll new file mode 100644 index 0000000..54cc3e0 --- /dev/null +++ b/test/CodeGen/ARM/intrinsics.ll @@ -0,0 +1,39 @@ +; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s + +define void @coproc() nounwind { +entry: + ; CHECK: mrc + %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcr + tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind + ; CHECK: mrc2 + %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcr2 + tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind + ; CHECK: mcrr + tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind + ; CHECK: mcrr2 + tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind + ; CHECK: cdp + tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind + ; CHECK: cdp2 + tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind + ret void +} + +declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcrr2(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcrr(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcr2(i32, i32, i32, i32, i32, i32) nounwind + +declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind + +declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind + +declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind diff --git a/test/CodeGen/ARM/jumptable-label.ll b/test/CodeGen/ARM/jumptable-label.ll new file mode 100644 index 0000000..49d6986 --- /dev/null +++ b/test/CodeGen/ARM/jumptable-label.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple thumbv6-apple-macosx10.6.0 | FileCheck %s + +; test that we print the label of a bb that is only used in a jump table. + +; CHECK: .long LBB0_2 +; CHECK: LBB0_2: + +define i32 @calculate() { +entry: + switch i32 undef, label %return [ + i32 1, label %sw.bb + i32 2, label %sw.bb6 + i32 3, label %sw.bb13 + i32 4, label %sw.bb20 + ] + +sw.bb: ; preds = %entry + br label %return + +sw.bb6: ; preds = %entry + br label %return + +sw.bb13: ; preds = %entry + br label %return + +sw.bb20: ; preds = %entry + %div = sdiv i32 undef, undef + br label %return + +return: ; preds = %sw.bb20, %sw.bb13, %sw.bb6, %sw.bb, %entry + %retval.0 = phi i32 [ %div, %sw.bb20 ], [ undef, %sw.bb13 ], [ undef, %sw.bb6 ], [ undef, %sw.bb ], [ 0, %entry ] + ret i32 %retval.0 +} diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index 3856944..8010f20 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=armv6-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V6 -; RUN: llc < %s -mtriple=armv5-apple-darwin | FileCheck %s -check-prefix=V5 -; RUN: llc < %s -mtriple=armv6-eabi | FileCheck %s -check-prefix=EABI +; RUN: llc < %s -mtriple=armv5-apple-darwin -regalloc=linearscan | FileCheck %s -check-prefix=V5 +; RUN: llc < %s -mtriple=armv6-eabi -regalloc=linearscan | FileCheck %s -check-prefix=EABI ; rdar://r6949835 ; Magic ARM pair hints works best with linearscan. diff --git a/test/CodeGen/ARM/ldst-f32-2-i32.ll b/test/CodeGen/ARM/ldst-f32-2-i32.ll index 2d016f6..1c69e15 100644 --- a/test/CodeGen/ARM/ldst-f32-2-i32.ll +++ b/test/CodeGen/ARM/ldst-f32-2-i32.ll @@ -10,8 +10,8 @@ entry: br i1 %0, label %return, label %bb bb: -; CHECK: ldr [[REGISTER:(r[0-9]+)]], [r1], r3 -; CHECK: str [[REGISTER]], [r2], #4 +; CHECK: ldr [[REGISTER:(r[0-9]+)]], [{{r[0-9]+}}], {{r[0-9]+}} +; CHECK: str [[REGISTER]], [{{r[0-9]+}}], #4 %j.05 = phi i32 [ %2, %bb ], [ 0, %entry ] %tmp = mul i32 %j.05, %index %uglygep = getelementptr i8* %src6, i32 %tmp diff --git a/test/CodeGen/ARM/ldstrexd.ll b/test/CodeGen/ARM/ldstrexd.ll new file mode 100644 index 0000000..0c0911a --- /dev/null +++ b/test/CodeGen/ARM/ldstrexd.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s + +%0 = type { i32, i32 } + +; CHECK: f0: +; CHECK: ldrexd +define i64 @f0(i8* %p) nounwind readonly { +entry: + %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p) + %0 = extractvalue %0 %ldrexd, 1 + %1 = extractvalue %0 %ldrexd, 0 + %2 = zext i32 %0 to i64 + %3 = zext i32 %1 to i64 + %shl = shl nuw i64 %2, 32 + %4 = or i64 %shl, %3 + ret i64 %4 +} + +; CHECK: f1: +; CHECK: strexd +define i32 @f1(i8* %ptr, i64 %val) nounwind { +entry: + %tmp4 = trunc i64 %val to i32 + %tmp6 = lshr i64 %val, 32 + %tmp7 = trunc i64 %tmp6 to i32 + %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr) + ret i32 %strexd +} + +declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly +declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind + diff --git a/test/CodeGen/ARM/lsr-code-insertion.ll b/test/CodeGen/ARM/lsr-code-insertion.ll index 1bbb96d..153fd8f 100644 --- a/test/CodeGen/ARM/lsr-code-insertion.ll +++ b/test/CodeGen/ARM/lsr-code-insertion.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -stats |& grep {39.*Number of machine instrs printed} -; RUN: llc < %s -stats |& not grep {.*Number of re-materialization} +; RUN: llc < %s | FileCheck %s ; This test really wants to check that the resultant "cond_true" block only ; has a single store in it, and that cond_true55 only has code to materialize ; the constant and do a store. We do *not* want something like this: @@ -8,6 +7,11 @@ ; add r8, r0, r6 ; str r10, [r8, #+4] ; +; CHECK: ldr [[R6:r[0-9*]+]], LCP +; CHECK: cmp {{.*}}, [[R6]] +; CHECK: ldrle +; CHECK-NEXT: strle + target triple = "arm-apple-darwin8" define void @foo(i32* %mc, i32* %mpp, i32* %ip, i32* %dpp, i32* %tpmm, i32 %M, i32* %tpim, i32* %tpdm, i32* %bp, i32* %ms, i32 %xmb) { diff --git a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll index 9882690..c1318ec 100644 --- a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll +++ b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -4,11 +4,6 @@ ; constant offset addressing, so that each of the following stores ; uses the same register. -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-128] -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-96] -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-64] -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #-32] -; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}] ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32] ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64] ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96] diff --git a/test/CodeGen/ARM/lsr-unfolded-offset.ll b/test/CodeGen/ARM/lsr-unfolded-offset.ll new file mode 100644 index 0000000..e3e6eae --- /dev/null +++ b/test/CodeGen/ARM/lsr-unfolded-offset.ll @@ -0,0 +1,80 @@ +; RUN: llc -regalloc=greedy < %s | FileCheck %s + +; LSR shouldn't introduce more induction variables than needed, increasing +; register pressure and therefore spilling. There is more room for improvement +; here. + +; CHECK: sub sp, #{{32|24}} + +; CHECK: ldr r{{.*}}, [sp, #4] +; CHECK-NEXT: ldr r{{.*}}, [sp, #16] +; CHECK-NEXT: ldr r{{.*}}, [sp, #12] +; CHECK-NEXT: adds + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-macosx10.7.0" + +%struct.partition_entry = type { i32, i32, i64, i64 } + +define i32 @partition_overlap_check(%struct.partition_entry* nocapture %part, i32 %num_entries) nounwind readonly optsize ssp { +entry: + %cmp79 = icmp sgt i32 %num_entries, 0 + br i1 %cmp79, label %outer.loop, label %for.end72 + +outer.loop: ; preds = %for.inc69, %entry + %overlap.081 = phi i32 [ %overlap.4, %for.inc69 ], [ 0, %entry ] + %0 = phi i32 [ %inc71, %for.inc69 ], [ 0, %entry ] + %offset = getelementptr %struct.partition_entry* %part, i32 %0, i32 2 + %len = getelementptr %struct.partition_entry* %part, i32 %0, i32 3 + %tmp5 = load i64* %offset, align 4, !tbaa !0 + %tmp15 = load i64* %len, align 4, !tbaa !0 + %add = add nsw i64 %tmp15, %tmp5 + br label %inner.loop + +inner.loop: ; preds = %for.inc, %outer.loop + %overlap.178 = phi i32 [ %overlap.081, %outer.loop ], [ %overlap.4, %for.inc ] + %1 = phi i32 [ 0, %outer.loop ], [ %inc, %for.inc ] + %cmp23 = icmp eq i32 %0, %1 + br i1 %cmp23, label %for.inc, label %if.end + +if.end: ; preds = %inner.loop + %len39 = getelementptr %struct.partition_entry* %part, i32 %1, i32 3 + %offset28 = getelementptr %struct.partition_entry* %part, i32 %1, i32 2 + %tmp29 = load i64* %offset28, align 4, !tbaa !0 + %tmp40 = load i64* %len39, align 4, !tbaa !0 + %add41 = add nsw i64 %tmp40, %tmp29 + %cmp44 = icmp sge i64 %tmp29, %tmp5 + %cmp47 = icmp slt i64 %tmp29, %add + %or.cond = and i1 %cmp44, %cmp47 + %overlap.2 = select i1 %or.cond, i32 1, i32 %overlap.178 + %cmp52 = icmp sle i64 %add41, %add + %cmp56 = icmp sgt i64 %add41, %tmp5 + %or.cond74 = and i1 %cmp52, %cmp56 + %overlap.3 = select i1 %or.cond74, i32 1, i32 %overlap.2 + %cmp61 = icmp sgt i64 %tmp29, %tmp5 + %cmp65 = icmp slt i64 %add41, %add + %or.cond75 = or i1 %cmp61, %cmp65 + br i1 %or.cond75, label %for.inc, label %if.then66 + +if.then66: ; preds = %if.end + br label %for.inc + +for.inc: ; preds = %if.end, %if.then66, %inner.loop + %overlap.4 = phi i32 [ %overlap.178, %inner.loop ], [ 1, %if.then66 ], [ %overlap.3, %if.end ] + %inc = add nsw i32 %1, 1 + %exitcond = icmp eq i32 %inc, %num_entries + br i1 %exitcond, label %for.inc69, label %inner.loop + +for.inc69: ; preds = %for.inc + %inc71 = add nsw i32 %0, 1 + %exitcond83 = icmp eq i32 %inc71, %num_entries + br i1 %exitcond83, label %for.end72, label %outer.loop + +for.end72: ; preds = %for.inc69, %entry + %overlap.0.lcssa = phi i32 [ 0, %entry ], [ %overlap.4, %for.inc69 ] + ret i32 %overlap.0.lcssa +} + +!0 = metadata !{metadata !"long long", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll index e8a2a3b..5bae037 100644 --- a/test/CodeGen/ARM/memcpy-inline.ll +++ b/test/CodeGen/ARM/memcpy-inline.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s -; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic -disable-post-ra | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -regalloc=linearscan -disable-post-ra | FileCheck %s ; The ARM magic hinting works best with linear scan. -; CHECK: ldmia -; CHECK: stmia -; CHECK: ldrh +; CHECK: ldrd +; CHECK: strd ; CHECK: ldrb %struct.x = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } diff --git a/test/CodeGen/ARM/memfunc.ll b/test/CodeGen/ARM/memfunc.ll index 41d5944..757364b 100644 --- a/test/CodeGen/ARM/memfunc.ll +++ b/test/CodeGen/ARM/memfunc.ll @@ -1,10 +1,26 @@ -; RUN: llc < %s -march=arm +; RUN: llc < %s -mtriple=armv7-apple-ios -o - | FileCheck %s +; RUN: llc < %s -mtriple=arm-none-eabi -o - | FileCheck --check-prefix=EABI %s + +@from = common global [500 x i32] zeroinitializer, align 4 +@to = common global [500 x i32] zeroinitializer, align 4 define void @f() { entry: - call void @llvm.memmove.i32( i8* null, i8* null, i32 64, i32 0 ) - call void @llvm.memcpy.i32( i8* null, i8* null, i32 64, i32 0 ) - call void @llvm.memset.i32( i8* null, i8 64, i32 0, i32 0 ) + + ; CHECK: memmove + ; EABI: __aeabi_memmove + call void @llvm.memmove.i32( i8* bitcast ([500 x i32]* @from to i8*), i8* bitcast ([500 x i32]* @to to i8*), i32 500, i32 0 ) + + ; CHECK: memcpy + ; EABI: __aeabi_memcpy + call void @llvm.memcpy.i32( i8* bitcast ([500 x i32]* @from to i8*), i8* bitcast ([500 x i32]* @to to i8*), i32 500, i32 0 ) + + ; EABI memset swaps arguments + ; CHECK: mov r1, #0 + ; CHECK: memset + ; EABI: mov r2, #0 + ; EABI: __aeabi_memset + call void @llvm.memset.i32( i8* bitcast ([500 x i32]* @from to i8*), i8 0, i32 500, i32 0 ) unreachable } diff --git a/test/CodeGen/ARM/movt-movw-global.ll b/test/CodeGen/ARM/movt-movw-global.ll index 886ff3f..991d728 100644 --- a/test/CodeGen/ARM/movt-movw-global.ll +++ b/test/CodeGen/ARM/movt-movw-global.ll @@ -1,20 +1,39 @@ -; RUN: llc < %s | FileCheck %s -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "armv7-eabi" +; RUN: llc < %s -mtriple=armv7-eabi | FileCheck %s -check-prefix=EABI +; RUN: llc < %s -mtriple=armv7-apple-ios -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=IOS +; RUN: llc < %s -mtriple=armv7-apple-ios -relocation-model=pic | FileCheck %s -check-prefix=IOS-PIC +; RUN: llc < %s -mtriple=armv7-apple-ios -relocation-model=static | FileCheck %s -check-prefix=IOS-STATIC -@foo = common global i32 0 ; <i32*> [#uses=1] +@foo = common global i32 0 -define arm_aapcs_vfpcc i32* @bar1() nounwind readnone { +define i32* @bar1() nounwind readnone { entry: -; CHECK: movw r0, :lower16:foo -; CHECK-NEXT: movt r0, :upper16:foo +; EABI: movw r0, :lower16:foo +; EABI-NEXT: movt r0, :upper16:foo + +; IOS: movw r0, :lower16:L_foo$non_lazy_ptr +; IOS-NEXT: movt r0, :upper16:L_foo$non_lazy_ptr + +; IOS-PIC: movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC0_0+8)) +; IOS-PIC-NEXT: movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC0_0+8)) + +; IOS-STATIC-NOT: movw r0, :lower16:_foo +; IOS-STATIC-NOT: movt r0, :upper16:_foo ret i32* @foo } -define arm_aapcs_vfpcc void @bar2(i32 %baz) nounwind { +define void @bar2(i32 %baz) nounwind { entry: -; CHECK: movw r1, :lower16:foo -; CHECK-NEXT: movt r1, :upper16:foo +; EABI: movw r1, :lower16:foo +; EABI-NEXT: movt r1, :upper16:foo + +; IOS: movw r1, :lower16:L_foo$non_lazy_ptr +; IOS-NEXT: movt r1, :upper16:L_foo$non_lazy_ptr + +; IOS-PIC: movw r1, :lower16:(L_foo$non_lazy_ptr-(LPC1_0+8)) +; IOS-PIC-NEXT: movt r1, :upper16:(L_foo$non_lazy_ptr-(LPC1_0+8)) + +; IOS-STATIC-NOT: movw r1, :lower16:_foo +; IOS-STATIC-NOT: movt r1, :upper16:_foo store i32 %baz, i32* @foo, align 4 ret void } diff --git a/test/CodeGen/ARM/neon_div.ll b/test/CodeGen/ARM/neon_div.ll index e337970..de48fee 100644 --- a/test/CodeGen/ARM/neon_div.ll +++ b/test/CodeGen/ARM/neon_div.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -pre-RA-sched=source | FileCheck %s define <8 x i8> @sdivi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: vrecpe.f32 diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll index 895b27b..250a34e 100644 --- a/test/CodeGen/ARM/prefetch.ll +++ b/test/CodeGen/ARM/prefetch.ll @@ -1,10 +1,15 @@ ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v7a,+mp | FileCheck %s -check-prefix=ARM-MP +; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP ; rdar://8601536 define void @t1(i8* %ptr) nounwind { entry: +; ARM: t1: +; ARM-NOT: pldw [r0] +; ARM: pld [r0] + ; ARM-MP: t1: ; ARM-MP: pldw [r0] ; ARM-MP: pld [r0] @@ -12,27 +17,27 @@ entry: ; THUMB2: t1: ; THUMB2-NOT: pldw [r0] ; THUMB2: pld [r0] - tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 ) - tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 ) + tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 ) ret void } define void @t2(i8* %ptr) nounwind { entry: -; ARM-MP: t2: -; ARM-MP: pld [r0, #1023] +; ARM: t2: +; ARM: pld [r0, #1023] ; THUMB2: t2: ; THUMB2: pld [r0, #1023] %tmp = getelementptr i8* %ptr, i32 1023 - tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 ) + tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 ) ret void } define void @t3(i32 %base, i32 %offset) nounwind { entry: -; ARM-MP: t3: -; ARM-MP: pld [r0, r1, lsr #2] +; ARM: t3: +; ARM: pld [r0, r1, lsr #2] ; THUMB2: t3: ; THUMB2: lsrs r1, r1, #2 @@ -40,22 +45,33 @@ entry: %tmp1 = lshr i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 %tmp3 = inttoptr i32 %tmp2 to i8* - tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) + tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 ) ret void } define void @t4(i32 %base, i32 %offset) nounwind { entry: -; ARM-MP: t4: -; ARM-MP: pld [r0, r1, lsl #2] +; ARM: t4: +; ARM: pld [r0, r1, lsl #2] ; THUMB2: t4: ; THUMB2: pld [r0, r1, lsl #2] %tmp1 = shl i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 %tmp3 = inttoptr i32 %tmp2 to i8* - tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 ) + tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 ) ret void } -declare void @llvm.prefetch(i8*, i32, i32) nounwind +declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind + +define void @t5(i8* %ptr) nounwind { +entry: +; ARM: t5: +; ARM: pli [r0] + +; THUMB2: t5: +; THUMB2: pli [r0] + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 ) + ret void +} diff --git a/test/CodeGen/ARM/rev.ll b/test/CodeGen/ARM/rev.ll index 4170ff3..5739086 100644 --- a/test/CodeGen/ARM/rev.ll +++ b/test/CodeGen/ARM/rev.ll @@ -54,3 +54,16 @@ entry: %conv8 = ashr exact i32 %sext, 16 ret i32 %conv8 } + +; rdar://9609059 +define i32 @test5(i32 %i) nounwind readnone { +entry: +; CHECK: test5 +; CHECK: revsh r0, r0 + %shl = shl i32 %i, 24 + %shr = ashr exact i32 %shl, 16 + %shr23 = lshr i32 %i, 8 + %and = and i32 %shr23, 255 + %or = or i32 %shr, %and + ret i32 %or +} diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 82ed018..43f8a66 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -5,8 +5,8 @@ define i32 @t1(i32 %c) nounwind readnone { entry: ; ARM: t1: -; ARM: mov r1, #101 -; ARM: orr r1, r1, #1, #24 +; ARM: mov [[R1:r[0-9]+]], #101 +; ARM: orr [[R1b:r[0-9]+]], [[R1]], #1, #24 ; ARM: movgt r0, #123 ; ARMT2: t1: @@ -34,7 +34,7 @@ entry: ; ARMT2: movwgt r0, #357 ; THUMB2: t2: -; THUMB2: mov.w r0, #123 +; THUMB2: mov{{(s|\.w)}} r0, #123 ; THUMB2: movwgt r0, #357 %0 = icmp sgt i32 %c, 1 @@ -53,7 +53,7 @@ entry: ; ARMT2: moveq r0, #1 ; THUMB2: t3: -; THUMB2: mov.w r0, #0 +; THUMB2: mov{{(s|\.w)}} r0, #0 ; THUMB2: moveq r0, #1 %0 = icmp eq i32 %a, 160 %1 = zext i1 %0 to i32 @@ -67,11 +67,11 @@ entry: ; ARM: movlt ; ARMT2: t4: -; ARMT2: movwlt r0, #65365 -; ARMT2: movtlt r0, #65365 +; ARMT2: movwlt [[R0:r[0-9]+]], #65365 +; ARMT2: movtlt [[R0]], #65365 ; THUMB2: t4: -; THUMB2: mvnlt.w r0, #11141290 +; THUMB2: mvnlt.w [[R0:r[0-9]+]], #11141290 %0 = icmp slt i32 %a, %b %1 = select i1 %0, i32 4283826005, i32 %x ret i32 %1 diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index be891bc..f0e2d10 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -58,7 +58,7 @@ entry: ; A8: str r2, [r0, r1, lsl #2] ; A9: test4: -; A9: add r0, r0, r4, lsl #2 +; A9: add r0, r0, r{{[0-9]+}}, lsl #2 ; A9: ldr r1, [r0] ; A9: str r1, [r0] %0 = tail call i8* (...)* @malloc(i32 undef) nounwind diff --git a/test/CodeGen/ARM/stm.ll b/test/CodeGen/ARM/stm.ll index 2f5fadb..82dc14d 100644 --- a/test/CodeGen/ARM/stm.ll +++ b/test/CodeGen/ARM/stm.ll @@ -9,7 +9,7 @@ define i32 @main() nounwind { entry: ; CHECK: main ; CHECK: push -; CHECK: stmib +; CHECK: stm %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; <i32> [#uses=0] %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; <i32> [#uses=0] ret i32 0 diff --git a/test/CodeGen/ARM/sxt_rot.ll b/test/CodeGen/ARM/sxt_rot.ll index 4752f17..355fee3 100644 --- a/test/CodeGen/ARM/sxt_rot.ll +++ b/test/CodeGen/ARM/sxt_rot.ll @@ -10,7 +10,7 @@ define i32 @test0(i8 %A) { ret i32 %B } -define i8 @test1(i32 %A) signext { +define signext i8 @test1(i32 %A) { %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C @@ -18,7 +18,7 @@ define i8 @test1(i32 %A) signext { ret i8 %E } -define i32 @test2(i32 %A, i32 %X) signext { +define signext i32 @test2(i32 %A, i32 %X) { %B = lshr i32 %A, 8 %C = shl i32 %A, 24 %D = or i32 %B, %C diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll index 189bc8c..38842a9 100644 --- a/test/CodeGen/ARM/trap.ll +++ b/test/CodeGen/ARM/trap.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=INSTR -; RUN: llc < %s -mtriple=arm-apple-darwin -arm-trap-func=_trap | FileCheck %s -check-prefix=FUNC +; RUN: llc < %s -mtriple=arm-apple-darwin -trap-func=_trap | FileCheck %s -check-prefix=FUNC ; rdar://7961298 ; rdar://9249183 diff --git a/test/CodeGen/ARM/umulo-32.ll b/test/CodeGen/ARM/umulo-32.ll index aa7d28a..fa5c016 100644 --- a/test/CodeGen/ARM/umulo-32.ll +++ b/test/CodeGen/ARM/umulo-32.ll @@ -12,3 +12,30 @@ define i32 @func(i32 %a) nounwind { } declare %umul.ty @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone + +define i32 @f(i32 %argc, i8** %argv) ssp { +; CHECK: func +; CHECK: str r0 +; CHECK: movs r2 +; CHECK: mov r1 +; CHECK: mov r3 +; CHECK: muldi3 +%1 = alloca i32, align 4 +%2 = alloca i32, align 4 +%3 = alloca i8**, align 4 +%m_degree = alloca i32, align 4 +store i32 0, i32* %1 +store i32 %argc, i32* %2, align 4 +store i8** %argv, i8*** %3, align 4 +store i32 10, i32* %m_degree, align 4 +%4 = load i32* %m_degree, align 4 +%5 = call %umul.ty @llvm.umul.with.overflow.i32(i32 %4, i32 8) +%6 = extractvalue %umul.ty %5, 1 +%7 = extractvalue %umul.ty %5, 0 +%8 = select i1 %6, i32 -1, i32 %7 +%9 = call noalias i8* @_Znam(i32 %8) +%10 = bitcast i8* %9 to double* +ret i32 0 +} + +declare noalias i8* @_Znam(i32) diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index b42e11f..a8237c6 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -8,14 +8,14 @@ define void @t(i8* nocapture %a, i8* nocapture %b) nounwind { entry: ; GENERIC: t: -; GENERIC: ldrb r2 -; GENERIC: ldrb r3 -; GENERIC: ldrb r12 -; GENERIC: ldrb r1 -; GENERIC: strb r1 -; GENERIC: strb r12 -; GENERIC: strb r3 -; GENERIC: strb r2 +; GENERIC: ldrb [[R2:r[0-9]+]] +; GENERIC: ldrb [[R3:r[0-9]+]] +; GENERIC: ldrb [[R12:r[0-9]+]] +; GENERIC: ldrb [[R1:r[0-9]+]] +; GENERIC: strb [[R1]] +; GENERIC: strb [[R12]] +; GENERIC: strb [[R3]] +; GENERIC: strb [[R2]] ; DARWIN_V6: t: ; DARWIN_V6: ldr r1 diff --git a/test/CodeGen/ARM/uxt_rot.ll b/test/CodeGen/ARM/uxt_rot.ll index 6307795..628c079 100644 --- a/test/CodeGen/ARM/uxt_rot.ll +++ b/test/CodeGen/ARM/uxt_rot.ll @@ -2,19 +2,19 @@ ; RUN: llc < %s -march=arm -mattr=+v6 | grep uxtab | count 1 ; RUN: llc < %s -march=arm -mattr=+v6 | grep uxth | count 1 -define i8 @test1(i32 %A.u) zeroext { +define zeroext i8 @test1(i32 %A.u) { %B.u = trunc i32 %A.u to i8 ret i8 %B.u } -define i32 @test2(i32 %A.u, i32 %B.u) zeroext { +define zeroext i32 @test2(i32 %A.u, i32 %B.u) { %C.u = trunc i32 %B.u to i8 %D.u = zext i8 %C.u to i32 %E.u = add i32 %A.u, %D.u ret i32 %E.u } -define i32 @test3(i32 %A.u) zeroext { +define zeroext i32 @test3(i32 %A.u) { %B.u = lshr i32 %A.u, 8 %C.u = shl i32 %A.u, 24 %D.u = or i32 %B.u, %C.u diff --git a/test/CodeGen/ARM/va_arg.ll b/test/CodeGen/ARM/va_arg.ll index 7cb9762..bb40453 100644 --- a/test/CodeGen/ARM/va_arg.ll +++ b/test/CodeGen/ARM/va_arg.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s ; Test that we correctly align elements when using va_arg ; CHECK: test1: ; CHECK-NOT: bfc -; CHECK: add r0, r0, #7 -; CHECK: bfc r0, #0, #3 +; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 +; CHECK: bfc [[REG]], #0, #3 ; CHECK-NOT: bfc define i64 @test1(i32 %i, ...) nounwind optsize { @@ -19,8 +19,8 @@ entry: ; CHECK: test2: ; CHECK-NOT: bfc -; CHECK: add r0, r0, #7 -; CHECK: bfc r0, #0, #3 +; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 +; CHECK: bfc [[REG]], #0, #3 ; CHECK-NOT: bfc ; CHECK: bx lr diff --git a/test/CodeGen/ARM/vbsl-constant.ll b/test/CodeGen/ARM/vbsl-constant.ll index 9a9cc5b..14e668e 100644 --- a/test/CodeGen/ARM/vbsl-constant.ll +++ b/test/CodeGen/ARM/vbsl-constant.ll @@ -2,6 +2,8 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { ;CHECK: v_bsli8: +;CHECK: vldr.64 +;CHECK: vldr.64 ;CHECK: vbsl %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -14,6 +16,8 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { ;CHECK: v_bsli16: +;CHECK: vldr.64 +;CHECK: vldr.64 ;CHECK: vbsl %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -26,6 +30,8 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { ;CHECK: v_bsli32: +;CHECK: vldr.64 +;CHECK: vldr.64 ;CHECK: vbsl %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -38,6 +44,9 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind { ;CHECK: v_bsli64: +;CHECK: vldr.64 +;CHECK: vldr.64 +;CHECK: vldr.64 ;CHECK: vbsl %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -50,6 +59,8 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { ;CHECK: v_bslQi8: +;CHECK: vldmia +;CHECK: vldmia ;CHECK: vbsl %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -62,6 +73,8 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { ;CHECK: v_bslQi16: +;CHECK: vldmia +;CHECK: vldmia ;CHECK: vbsl %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -74,6 +87,8 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { ;CHECK: v_bslQi32: +;CHECK: vldmia +;CHECK: vldmia ;CHECK: vbsl %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -86,6 +101,9 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind { ;CHECK: v_bslQi64: +;CHECK: vldmia +;CHECK: vldmia +;CHECK: vldmia ;CHECK: vbsl %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll index 390457f..49a6982 100644 --- a/test/CodeGen/ARM/vfp.ll +++ b/test/CodeGen/ARM/vfp.ll @@ -40,8 +40,8 @@ define void @test_add(float* %P, double* %D) { define void @test_ext_round(float* %P, double* %D) { ;CHECK: test_ext_round: %a = load float* %P ; <float> [#uses=1] -;CHECK: vcvt.f32.f64 ;CHECK: vcvt.f64.f32 +;CHECK: vcvt.f32.f64 %b = fpext float %a to double ; <double> [#uses=1] %A = load double* %D ; <double> [#uses=1] %B = fptrunc double %A to float ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index 02e543c..e524395 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -133,8 +133,6 @@ declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly ; Do not crash if the vld1 result is not used. define void @unused_vld1_result() { entry: -;CHECK: unused_vld1_result -;CHECK: vld1.32 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* undef, i32 1) call void @llvm.trap() unreachable diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index 68dd503..0d7d4ec 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -125,7 +125,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;Check for a post-increment updating load. define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind { ;CHECK: vld2lanei32_update: -;CHECK: vld2.32 {d16[1], d17[1]}, [r1]! +;CHECK: vld2.32 {d16[1], d17[1]}, [{{r[0-9]+}}]! %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B @@ -153,7 +153,7 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld2laneQi16: ;Check the (default) alignment. -;CHECK: vld2.16 {d17[1], d19[1]}, [r0] +;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x2_t @llvm.arm.neon.vld2lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 5, i32 1) @@ -166,7 +166,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld2laneQi32: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] +;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}, :64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B %tmp2 = call %struct.__neon_int32x4x2_t @llvm.arm.neon.vld2lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 16) @@ -222,7 +222,7 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind { define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld3lanei16: ;Check the (default) alignment value. VLD3 does not support alignment. -;CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] +;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) @@ -265,7 +265,7 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld3laneQi16: ;Check the (default) alignment value. VLD3 does not support alignment. -;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] +;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) @@ -280,7 +280,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check for a post-increment updating load with register increment. define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { ;CHECK: vld3laneQi16_update: -;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [{{r[0-9]+}}], {{r[0-9]+}} +;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B @@ -344,7 +344,7 @@ declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x flo define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld4lanei8: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}, :32] %tmp1 = load <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 @@ -360,7 +360,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating load. define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { ;CHECK: vld4lanei8_update: -;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1, :32]! +;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}, :32]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) @@ -380,7 +380,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld4lanei16: ;Check that a power-of-two alignment smaller than the total size of the memory ;being loaded is ignored. -;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B %tmp2 = call %struct.__neon_int16x4x4_t @llvm.arm.neon.vld4lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 4) @@ -398,7 +398,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld4lanei32: ;Check the alignment value. An 8-byte alignment is allowed here even though ;it is smaller than the total size of the memory being loaded. -;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :64] +;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}, :64] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B %tmp2 = call %struct.__neon_int32x2x4_t @llvm.arm.neon.vld4lane.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 1, i32 8) @@ -431,7 +431,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld4laneQi16: ;Check the alignment value. Max for this instruction is 64 bits: -;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}, :64] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 16) @@ -448,7 +448,7 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld4laneQi32: ;Check the (default) alignment. -;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] +;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}] %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B %tmp2 = call %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 2, i32 1) @@ -491,7 +491,7 @@ declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x flo ; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because ; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low ; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.) -define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { +define <8 x i16> @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { ;CHECK: test_qqqq_regsequence_subreg ;CHECK: vld3.16 %tmp63 = extractvalue [6 x i64] %b, 5 @@ -500,8 +500,12 @@ define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { %ins67 = or i128 %tmp65, 0 %tmp78 = bitcast i128 %ins67 to <8 x i16> %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2) - call void @llvm.trap() - unreachable + %tmp3 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 0 + %tmp4 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 1 + %tmp5 = extractvalue %struct.__neon_int16x8x3_t %vld3_lane, 2 + %tmp6 = add <8 x i16> %tmp3, %tmp4 + %tmp7 = add <8 x i16> %tmp5, %tmp6 + ret <8 x i16> %tmp7 } declare void @llvm.trap() nounwind diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index 1fd6581..1780d6e 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -439,9 +439,9 @@ define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind { } ; rdar://9197392 -define void @distribue(i16* %dst, i8* %src, i32 %mul) nounwind { +define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind { entry: -; CHECK: distribue: +; CHECK: distribute: ; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]] ; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]] %0 = trunc i32 %mul to i8 @@ -471,9 +471,9 @@ declare void @llvm.arm.neon.vst1.v8i16(i8*, <8 x i16>, i32) nounwind %struct.uint8x8_t = type { <8 x i8> } -define void @distribue2(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind { +define void @distribute2(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind { entry: -; CHECK: distribue2 +; CHECK: distribute2 ; CHECK-NOT: vadd.i8 ; CHECK: vmul.i8 ; CHECK: vmla.i8 @@ -492,3 +492,25 @@ entry: store <8 x i8> %10, <8 x i8>* %11, align 8 ret void } + +define void @distribute2_commutative(%struct.uint8x8_t* nocapture %dst, i8* %src, i32 %mul) nounwind { +entry: +; CHECK: distribute2_commutative +; CHECK-NOT: vadd.i8 +; CHECK: vmul.i8 +; CHECK: vmla.i8 + %0 = trunc i32 %mul to i8 + %1 = insertelement <8 x i8> undef, i8 %0, i32 0 + %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer + %3 = tail call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %src, i32 1) + %4 = bitcast <16 x i8> %3 to <2 x double> + %5 = extractelement <2 x double> %4, i32 1 + %6 = bitcast double %5 to <8 x i8> + %7 = extractelement <2 x double> %4, i32 0 + %8 = bitcast double %7 to <8 x i8> + %9 = add <8 x i8> %6, %8 + %10 = mul <8 x i8> %2, %9 + %11 = getelementptr inbounds %struct.uint8x8_t* %dst, i32 0, i32 0 + store <8 x i8> %10, <8 x i8>* %11, align 8 + ret void +} diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll index 2125573..1ba68f5 100644 --- a/test/CodeGen/ARM/vpadd.ll +++ b/test/CodeGen/ARM/vpadd.ll @@ -138,6 +138,20 @@ define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind { ret <2 x i64> %tmp2 } +; Test AddCombine optimization that generates a vpaddl.s +define void @addCombineToVPADDL() nounwind ssp { +; CHECK: vpaddl.s8 + %cbcr = alloca <16 x i8>, align 16 + %X = alloca <8 x i8>, align 8 + %tmp = load <16 x i8>* %cbcr + %tmp1 = shufflevector <16 x i8> %tmp, <16 x i8> undef, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14> + %tmp2 = load <16 x i8>* %cbcr + %tmp3 = shufflevector <16 x i8> %tmp2, <16 x i8> undef, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15> + %add = add <8 x i8> %tmp3, %tmp1 + store <8 x i8> %add, <8 x i8>* %X, align 8 + ret void +} + declare <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8>) nounwind readnone declare <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16>) nounwind readnone declare <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32>) nounwind readnone diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index f0f9e4e..34acd16 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -147,3 +147,34 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind { store <4 x float> %tmp8, <4 x float>* %v, align 16 ret void } + +; vrev <4 x i16> should use VREV32 and not VREV64 +define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { +; CHECK: test_vrev64: +; CHECK: vext.16 +; CHECK: vrev32.16 +entry: + %0 = bitcast <4 x i16>* %source to <8 x i16>* + %tmp2 = load <8 x i16>* %0, align 4 + %tmp3 = extractelement <8 x i16> %tmp2, i32 6 + %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0 + %tmp9 = extractelement <8 x i16> %tmp2, i32 5 + %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1 + store <2 x i16> %tmp11, <2 x i16>* %dst, align 4 + ret void +} + +; Test vrev of float4 +define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp { +; CHECK: float_vrev64 +; CHECK: vext.32 +; CHECK: vrev64.32 +entry: + %0 = bitcast float* %source to <4 x float>* + %tmp2 = load <4 x float>* %0, align 4 + %tmp5 = shufflevector <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, <4 x float> %tmp2, <4 x i32> <i32 0, i32 7, i32 0, i32 0> + %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11 + store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4 + ret void +} + diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index d262303..e3372a0 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon -O0 | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+neon -disable-arm-fast-isel -O0 | FileCheck %s define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vst3i8: diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index d1bc15a..08b7232 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -54,7 +54,8 @@ define void @vst1lanef(float* %A, <2 x float>* %B) nounwind { define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vst1laneQi8: -;CHECK: vst1.8 {d17[1]}, [r0] +; // Can use scalar load. No need to use vectors. +; // CHE-CK: vst1.8 {d17[1]}, [r0] %tmp1 = load <16 x i8>* %B %tmp2 = extractelement <16 x i8> %tmp1, i32 9 store i8 %tmp2, i8* %A, align 8 @@ -72,7 +73,8 @@ define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vst1laneQi32: -;CHECK: vst1.32 {d17[1]}, [r0, :32] +; // Can use scalar load. No need to use vectors. +; // CHE-CK: vst1.32 {d17[1]}, [r0, :32] %tmp1 = load <4 x i32>* %B %tmp2 = extractelement <4 x i32> %tmp1, i32 3 store i32 %tmp2, i32* %A, align 8 @@ -82,7 +84,8 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;Check for a post-increment updating store. define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { ;CHECK: vst1laneQi32_update: -;CHECK: vst1.32 {d17[1]}, [r1, :32]! +; // Can use scalar load. No need to use vectors. +; // CHE-CK: vst1.32 {d17[1]}, [r1, :32]! %A = load i32** %ptr %tmp1 = load <4 x i32>* %B %tmp2 = extractelement <4 x i32> %tmp1, i32 3 @@ -94,7 +97,8 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind { ;CHECK: vst1laneQf: -;CHECK: vst1.32 {d17[1]}, [r0] +; // Can use scalar load. No need to use vectors. +; // CHE-CK: vst1.32 {d17[1]}, [r0] %tmp1 = load <4 x float>* %B %tmp2 = extractelement <4 x float> %tmp1, i32 3 store float %tmp2, float* %A diff --git a/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll b/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll deleted file mode 100644 index 87d9928..0000000 --- a/test/CodeGen/Alpha/2005-07-12-TwoMallocCalls.ll +++ /dev/null @@ -1,17 +0,0 @@ -; There should be exactly two calls here (memset and malloc), no more. -; RUN: llc < %s -march=alpha | grep jsr | count 2 - -%typedef.bc_struct = type opaque -declare void @llvm.memset.i64(i8*, i8, i64, i32) - -define i1 @l12_l94_bc_divide_endif_2E_3_2E_ce(i32* %tmp.71.reload, i32 %scale2.1.3, i32 %extra.0, %typedef.bc_struct* %n1, %typedef.bc_struct* %n2, i32* %tmp.92.reload, i32 %tmp.94.reload, i32* %tmp.98.reload, i32 %tmp.100.reload, i8** %tmp.112.out, i32* %tmp.157.out, i8** %tmp.158.out) { -newFuncRoot: - %tmp.120 = add i32 %extra.0, 2 ; <i32> [#uses=1] - %tmp.122 = add i32 %tmp.120, %tmp.94.reload ; <i32> [#uses=1] - %tmp.123 = add i32 %tmp.122, %tmp.100.reload ; <i32> [#uses=2] - %tmp.112 = malloc i8, i32 %tmp.123 ; <i8*> [#uses=1] - %tmp.137 = zext i32 %tmp.123 to i64 ; <i64> [#uses=1] - tail call void @llvm.memset.i64( i8* %tmp.112, i8 0, i64 %tmp.137, i32 0 ) - ret i1 true -} - diff --git a/test/CodeGen/Alpha/add.ll b/test/CodeGen/Alpha/add.ll index cd883f6..8a92695 100644 --- a/test/CodeGen/Alpha/add.ll +++ b/test/CodeGen/Alpha/add.ll @@ -17,19 +17,19 @@ ; RUN: grep {s8subq} %t.s | count 2 -define i32 @al(i32 signext %x.s, i32 signext %y.s) signext { +define signext i32 @al(i32 signext %x.s, i32 signext %y.s) { entry: %tmp.3.s = add i32 %y.s, %x.s ; <i32> [#uses=1] ret i32 %tmp.3.s } -define i32 @ali(i32 signext %x.s) signext { +define signext i32 @ali(i32 signext %x.s) { entry: %tmp.3.s = add i32 100, %x.s ; <i32> [#uses=1] ret i32 %tmp.3.s } -define i64 @aq(i64 signext %x.s, i64 signext %y.s) signext { +define signext i64 @aq(i64 signext %x.s, i64 signext %y.s) { entry: %tmp.3.s = add i64 %y.s, %x.s ; <i64> [#uses=1] ret i64 %tmp.3.s @@ -41,13 +41,13 @@ entry: ret i64 %tmp.3.s } -define i32 @sl(i32 signext %x.s, i32 signext %y.s) signext { +define signext i32 @sl(i32 signext %x.s, i32 signext %y.s) { entry: %tmp.3.s = sub i32 %y.s, %x.s ; <i32> [#uses=1] ret i32 %tmp.3.s } -define i32 @sli(i32 signext %x.s) signext { +define signext i32 @sli(i32 signext %x.s) { entry: %tmp.3.s = sub i32 %x.s, 100 ; <i32> [#uses=1] ret i32 %tmp.3.s @@ -65,14 +65,14 @@ entry: ret i64 %tmp.3.s } -define i32 @a4l(i32 signext %x.s, i32 signext %y.s) signext { +define signext i32 @a4l(i32 signext %x.s, i32 signext %y.s) { entry: %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1] %tmp.3.s = add i32 %tmp.1.s, %x.s ; <i32> [#uses=1] ret i32 %tmp.3.s } -define i32 @a8l(i32 signext %x.s, i32 signext %y.s) signext { +define signext i32 @a8l(i32 signext %x.s, i32 signext %y.s) { entry: %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1] %tmp.3.s = add i32 %tmp.1.s, %x.s ; <i32> [#uses=1] @@ -93,14 +93,14 @@ entry: ret i64 %tmp.3.s } -define i32 @a4li(i32 signext %y.s) signext { +define signext i32 @a4li(i32 signext %y.s) { entry: %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1] %tmp.3.s = add i32 100, %tmp.1.s ; <i32> [#uses=1] ret i32 %tmp.3.s } -define i32 @a8li(i32 signext %y.s) signext { +define signext i32 @a8li(i32 signext %y.s) { entry: %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1] %tmp.3.s = add i32 100, %tmp.1.s ; <i32> [#uses=1] @@ -121,14 +121,14 @@ entry: ret i64 %tmp.3.s } -define i32 @s4l(i32 signext %x.s, i32 signext %y.s) signext { +define signext i32 @s4l(i32 signext %x.s, i32 signext %y.s) { entry: %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1] %tmp.3.s = sub i32 %tmp.1.s, %x.s ; <i32> [#uses=1] ret i32 %tmp.3.s } -define i32 @s8l(i32 signext %x.s, i32 signext %y.s) signext { +define signext i32 @s8l(i32 signext %x.s, i32 signext %y.s) { entry: %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1] %tmp.3.s = sub i32 %tmp.1.s, %x.s ; <i32> [#uses=1] @@ -149,14 +149,14 @@ entry: ret i64 %tmp.3.s } -define i32 @s4li(i32 signext %y.s) signext { +define signext i32 @s4li(i32 signext %y.s) { entry: %tmp.1.s = shl i32 %y.s, 2 ; <i32> [#uses=1] %tmp.3.s = sub i32 %tmp.1.s, 100 ; <i32> [#uses=1] ret i32 %tmp.3.s } -define i32 @s8li(i32 signext %y.s) signext { +define signext i32 @s8li(i32 signext %y.s) { entry: %tmp.1.s = shl i32 %y.s, 3 ; <i32> [#uses=1] %tmp.3.s = sub i32 %tmp.1.s, 100 ; <i32> [#uses=1] diff --git a/test/CodeGen/Alpha/i32_sub_1.ll b/test/CodeGen/Alpha/i32_sub_1.ll index ffeafbd..35b1d08 100644 --- a/test/CodeGen/Alpha/i32_sub_1.ll +++ b/test/CodeGen/Alpha/i32_sub_1.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=alpha | grep -i {subl \$16,1,\$0} -define i32 @foo(i32 signext %x) signext { +define signext i32 @foo(i32 signext %x) { entry: %tmp.1 = add i32 %x, -1 ; <int> [#uses=1] ret i32 %tmp.1 diff --git a/test/CodeGen/Alpha/zapnot.ll b/test/CodeGen/Alpha/zapnot.ll index d00984a..a47035e 100644 --- a/test/CodeGen/Alpha/zapnot.ll +++ b/test/CodeGen/Alpha/zapnot.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=alpha | grep zapnot -define i16 @foo(i64 %y) zeroext { +define zeroext i16 @foo(i64 %y) { entry: %tmp.1 = trunc i64 %y to i16 ; <ushort> [#uses=1] ret i16 %tmp.1 diff --git a/test/CodeGen/CPP/llvm2cpp.ll b/test/CodeGen/CPP/llvm2cpp.ll deleted file mode 100644 index d0ba0cf..0000000 --- a/test/CodeGen/CPP/llvm2cpp.ll +++ /dev/null @@ -1,756 +0,0 @@ -; RUN: llvm-as < %s | llvm-dis > /dev/null -; RUN: llc < %s -march=cpp -cppgen=program -o - - -@X = global i32 4, align 16 ; <i32*> [#uses=0] - -define i32* @test1012() align 32 { - %X = alloca i32, align 4 ; <i32*> [#uses=1] - %Y = alloca i32, i32 42, align 16 ; <i32*> [#uses=0] - %Z = alloca i32 ; <i32*> [#uses=0] - ret i32* %X -} - -define i32* @test1013() { - %X = malloc i32, align 4 ; <i32*> [#uses=1] - %Y = malloc i32, i32 42, align 16 ; <i32*> [#uses=0] - %Z = malloc i32 ; <i32*> [#uses=0] - ret i32* %X -} - -define void @void(i32, i32) { - add i32 0, 0 ; <i32>:3 [#uses=2] - sub i32 0, 4 ; <i32>:4 [#uses=2] - br label %5 - -; <label>:5 ; preds = %5, %2 - add i32 %0, %1 ; <i32>:6 [#uses=2] - sub i32 %6, %4 ; <i32>:7 [#uses=1] - icmp sle i32 %7, %3 ; <i1>:8 [#uses=1] - br i1 %8, label %9, label %5 - -; <label>:9 ; preds = %5 - add i32 %0, %1 ; <i32>:10 [#uses=0] - sub i32 %6, %4 ; <i32>:11 [#uses=1] - icmp sle i32 %11, %3 ; <i1>:12 [#uses=0] - ret void -} - -define i32 @zarro() { -Startup: - ret i32 0 -} - -define fastcc void @foo() { - ret void -} - -define coldcc void @bar() { - call fastcc void @foo( ) - ret void -} - -define void @structret({ i8 }* sret %P) { - call void @structret( { i8 }* %P sret ) - ret void -} - -define void @foo4() { - ret void -} - -define coldcc void @bar2() { - call fastcc void @foo( ) - ret void -} - -define cc42 void @bar3() { - invoke fastcc void @foo( ) - to label %Ok unwind label %U - -Ok: ; preds = %0 - ret void - -U: ; preds = %0 - unwind -} - -define void @bar4() { - call cc42 void @bar( ) - invoke cc42 void @bar3( ) - to label %Ok unwind label %U - -Ok: ; preds = %0 - ret void - -U: ; preds = %0 - unwind -} -; ModuleID = 'calltest.ll' - %FunTy = type i32 (i32) - -define i32 @test1000(i32 %i0) { - ret i32 %i0 -} - -define void @invoke(%FunTy* %x) { - %foo = call i32 %x( i32 123 ) ; <i32> [#uses=0] - %foo2 = tail call i32 %x( i32 123 ) ; <i32> [#uses=0] - ret void -} - -define i32 @main(i32 %argc) { - %retval = call i32 @test1000( i32 %argc ) ; <i32> [#uses=2] - %two = add i32 %retval, %retval ; <i32> [#uses=1] - %retval2 = invoke i32 @test1000( i32 %argc ) - to label %Next unwind label %Error ; <i32> [#uses=1] - -Next: ; preds = %0 - %two2 = add i32 %two, %retval2 ; <i32> [#uses=1] - call void @invoke( %FunTy* @test1000 ) - ret i32 %two2 - -Error: ; preds = %0 - ret i32 -1 -} -; ModuleID = 'casttest.ll' - -define i16 @FunFunc(i64 %x, i8 %z) { -bb0: - %cast110 = sext i8 %z to i16 ; <i16> [#uses=1] - %cast10 = trunc i64 %x to i16 ; <i16> [#uses=1] - %reg109 = add i16 %cast110, %cast10 ; <i16> [#uses=1] - ret i16 %reg109 -} -; ModuleID = 'cfgstructures.ll' - -define void @irreducible(i1 %cond) { - br i1 %cond, label %X, label %Y - -X: ; preds = %Y, %0 - br label %Y - -Y: ; preds = %X, %0 - br label %X -} - -define void @sharedheader(i1 %cond) { - br label %A - -A: ; preds = %Y, %X, %0 - br i1 %cond, label %X, label %Y - -X: ; preds = %A - br label %A - -Y: ; preds = %A - br label %A -} - -define void @nested(i1 %cond1, i1 %cond2, i1 %cond3) { - br label %Loop1 - -Loop1: ; preds = %L2Exit, %0 - br label %Loop2 - -Loop2: ; preds = %L3Exit, %Loop1 - br label %Loop3 - -Loop3: ; preds = %Loop3, %Loop2 - br i1 %cond3, label %Loop3, label %L3Exit - -L3Exit: ; preds = %Loop3 - br i1 %cond2, label %Loop2, label %L2Exit - -L2Exit: ; preds = %L3Exit - br i1 %cond1, label %Loop1, label %L1Exit - -L1Exit: ; preds = %L2Exit - ret void -} -; ModuleID = 'constexpr.ll' - %SAType = type { i32, { [2 x float], i64 } } - %SType = type { i32, { float, { i8 } }, i64 } -global i64 1 ; <i64*>:0 [#uses=0] -global i64 74514 ; <i64*>:1 [#uses=0] -@t2 = global i32* @t1 ; <i32**> [#uses=0] -@t3 = global i32* @t1 ; <i32**> [#uses=2] -@t1 = global i32 4 ; <i32*> [#uses=2] -@t4 = global i32** @t3 ; <i32***> [#uses=1] -@t5 = global i32** @t3 ; <i32***> [#uses=0] -@t6 = global i32*** @t4 ; <i32****> [#uses=0] -@t7 = global float* inttoptr (i32 12345678 to float*) ; <float**> [#uses=0] -@t9 = global i32 8 ; <i32*> [#uses=0] -global i32* bitcast (float* @4 to i32*) ; <i32**>:2 [#uses=0] -global float* @4 ; <float**>:3 [#uses=0] -global float 0.000000e+00 ; <float*>:4 [#uses=2] -@array = constant [2 x i32] [ i32 12, i32 52 ] ; <[2 x i32]*> [#uses=1] -@arrayPtr = global i32* getelementptr ([2 x i32]* @array, i64 0, i64 0) ; <i32**> [#uses=1] -@arrayPtr5 = global i32** getelementptr (i32** @arrayPtr, i64 5) ; <i32***> [#uses=0] -@somestr = constant [11 x i8] c"hello world" ; <[11 x i8]*> [#uses=2] -@char5 = global i8* getelementptr ([11 x i8]* @somestr, i64 0, i64 5) ; <i8**> [#uses=0] -@char8a = global i32* bitcast (i8* getelementptr ([11 x i8]* @somestr, i64 0, i64 8) to i32*) ; <i32**> [#uses=0] -@char8b = global i8* getelementptr ([11 x i8]* @somestr, i64 0, i64 8) ; <i8**> [#uses=0] -@S1 = global %SType* null ; <%SType**> [#uses=1] -@S2c = constant %SType { - i32 1, - { float, { i8 } } { float 2.000000e+00, { i8 } { i8 3 } }, - i64 4 } ; <%SType*> [#uses=3] -@S3c = constant %SAType { i32 1, { [2 x float], i64 } { [2 x float] [ float 2.000000e+00, float 3.000000e+00 ], i64 4 } } ; <%SAType*> [#uses=1] -@S1ptr = global %SType** @S1 ; <%SType***> [#uses=0] -@S2 = global %SType* @S2c ; <%SType**> [#uses=0] -@S3 = global %SAType* @S3c ; <%SAType**> [#uses=0] -@S1fld1a = global float* getelementptr (%SType* @S2c, i64 0, i32 1, i32 0) ; <float**> [#uses=0] -@S1fld1b = global float* getelementptr (%SType* @S2c, i64 0, i32 1, i32 0) ; <float**> [#uses=1] -@S1fld1bptr = global float** @S1fld1b ; <float***> [#uses=0] -@S2fld3 = global i8* getelementptr (%SType* @S2c, i64 0, i32 1, i32 1, i32 0) ; <i8**> [#uses=0] - -; ModuleID = 'constpointer.ll' -@cpt3 = global i32* @cpt1 ; <i32**> [#uses=1] -@cpt1 = global i32 4 ; <i32*> [#uses=2] -@cpt4 = global i32** @cpt3 ; <i32***> [#uses=0] -@cpt2 = global i32* @cpt1 ; <i32**> [#uses=0] -global float* @7 ; <float**>:0 [#uses=0] -global float* @7 ; <float**>:1 [#uses=0] -global float 0.000000e+00 ; <float*>:2 [#uses=3] -global float* @7 ; <float**>:3 [#uses=0] -@fptr = global void ()* @f ; <void ()**> [#uses=0] -@sptr1 = global [11 x i8]* @somestr ; <[11 x i8]**> [#uses=0] -@somestr2 = constant [11 x i8] c"hello world" ; <[11 x i8]*> [#uses=2] -@sptr2 = global [11 x i8]* @somestr2 ; <[11 x i8]**> [#uses=0] - -declare void @f() -; ModuleID = 'escaped_label.ll' - -define i32 @foo3() { - br label "foo`~!@#$%^&*()-_=+{}[]\\|;:',<.>/?" - -"foo`~!@#$%^&*()-_=+{}[]\\|;:',<.>/?": ; preds = %0 - ret i32 17 -} -; ModuleID = 'float.ll' -@F1 = global float 4.000000e+00 ; <float*> [#uses=0] -@D1 = global double 4.000000e+00 ; <double*> [#uses=0] -; ModuleID = 'fold-fpcast.ll' - -define i32 @test1() { - ret i32 1080872141 -} - -define float @test1002() { - ret float 0x36E1000000000000 -} - -define i64 @test3() { - ret i64 4614256656431372362 -} - -define double @test4() { - ret double 2.075076e-322 -} -; ModuleID = 'forwardreftest.ll' - %myfn = type float (i32, double, i32, i16) - %myty = type i32 - %thisfuncty = type i32 (i32)* - -declare void @F(%thisfuncty, %thisfuncty, %thisfuncty) - -define i32 @zarro2(i32 %Func) { -Startup: - add i32 0, 10 ; <i32>:0 [#uses=0] - ret i32 0 -} - -define i32 @test1004(i32) { - call void @F( %thisfuncty @zarro2, %thisfuncty @test1004, %thisfuncty @foozball ) - ret i32 0 -} - -define i32 @foozball(i32) { - ret i32 0 -} - -; ModuleID = 'globalredefinition.ll' -@A = global i32* @B ; <i32**> [#uses=0] -@B = global i32 7 ; <i32*> [#uses=1] - -define void @test12312() { - ret void -} -; ModuleID = 'global_section.ll' -@GlobSec = global i32 4, section "foo", align 16 - -define void @test1005() section "bar" { - ret void -} - -; ModuleID = 'globalvars.ll' -@MyVar = external global i32 ; <i32*> [#uses=1] -@MyIntList = external global { \2*, i32 } ; <{ \2*, i32 }*> [#uses=1] -external global i32 ; <i32*>:0 [#uses=0] -@AConst = constant i32 123 ; <i32*> [#uses=0] -@AString = constant [4 x i8] c"test" ; <[4 x i8]*> [#uses=0] -@ZeroInit = global { [100 x i32], [40 x float] } zeroinitializer ; <{ [100 x i32], [40 x float] }*> [#uses=0] - -define i32 @foo10015(i32 %blah) { - store i32 5, i32* @MyVar - %idx = getelementptr { \2*, i32 }* @MyIntList, i64 0, i32 1 ; <i32*> [#uses=1] - store i32 12, i32* %idx - ret i32 %blah -} -; ModuleID = 'indirectcall2.ll' - -define i64 @test1006(i64 %X) { - ret i64 %X -} - -define i64 @fib(i64 %n) { -; <label>:0 - %T = icmp ult i64 %n, 2 ; <i1> [#uses=1] - br i1 %T, label %BaseCase, label %RecurseCase - -RecurseCase: ; preds = %0 - %result = call i64 @test1006( i64 %n ) ; <i64> [#uses=0] - br label %BaseCase - -BaseCase: ; preds = %RecurseCase, %0 - %X = phi i64 [ 1, %0 ], [ 2, %RecurseCase ] ; <i64> [#uses=1] - ret i64 %X -} -; ModuleID = 'indirectcall.ll' - -declare i32 @atoi(i8*) - -define i64 @fibonacc(i64 %n) { - icmp ult i64 %n, 2 ; <i1>:1 [#uses=1] - br i1 %1, label %BaseCase, label %RecurseCase - -BaseCase: ; preds = %0 - ret i64 1 - -RecurseCase: ; preds = %0 - %n2 = sub i64 %n, 2 ; <i64> [#uses=1] - %n1 = sub i64 %n, 1 ; <i64> [#uses=1] - %f2 = call i64 @fibonacc( i64 %n2 ) ; <i64> [#uses=1] - %f1 = call i64 @fibonacc( i64 %n1 ) ; <i64> [#uses=1] - %result = add i64 %f2, %f1 ; <i64> [#uses=1] - ret i64 %result -} - -define i64 @realmain(i32 %argc, i8** %argv) { -; <label>:0 - icmp eq i32 %argc, 2 ; <i1>:1 [#uses=1] - br i1 %1, label %HasArg, label %Continue - -HasArg: ; preds = %0 - %n1 = add i32 1, 1 ; <i32> [#uses=1] - br label %Continue - -Continue: ; preds = %HasArg, %0 - %n = phi i32 [ %n1, %HasArg ], [ 1, %0 ] ; <i32> [#uses=1] - %N = sext i32 %n to i64 ; <i64> [#uses=1] - %F = call i64 @fib( i64 %N ) ; <i64> [#uses=1] - ret i64 %F -} - -define i64 @trampoline(i64 %n, i64 (i64)* %fibfunc) { - %F = call i64 %fibfunc( i64 %n ) ; <i64> [#uses=1] - ret i64 %F -} - -define i32 @main2() { - %Result = call i64 @trampoline( i64 10, i64 (i64)* @fib ) ; <i64> [#uses=1] - %Result.upgrd.1 = trunc i64 %Result to i32 ; <i32> [#uses=1] - ret i32 %Result.upgrd.1 -} -; ModuleID = 'inlineasm.ll' -module asm "this is an inline asm block" -module asm "this is another inline asm block" - -define i32 @test1007() { - %X = call i32 asm "tricky here $0, $1", "=r,r"( i32 4 ) ; <i32> [#uses=1] - call void asm sideeffect "eieio", ""( ) - ret i32 %X -} -; ModuleID = 'instructions.ll' - -define i32 @test_extractelement(<4 x i32> %V) { - %R = extractelement <4 x i32> %V, i32 1 ; <i32> [#uses=1] - ret i32 %R -} - -define <4 x i32> @test_insertelement(<4 x i32> %V) { - %R = insertelement <4 x i32> %V, i32 0, i32 0 ; <<4 x i32>> [#uses=1] - ret <4 x i32> %R -} - -define <4 x i32> @test_shufflevector_u(<4 x i32> %V) { - %R = shufflevector <4 x i32> %V, <4 x i32> %V, <4 x i32> < i32 1, i32 undef, i32 7, i32 2 > ; <<4 x i32>> [#uses=1] - ret <4 x i32> %R -} - -define <4 x float> @test_shufflevector_f(<4 x float> %V) { - %R = shufflevector <4 x float> %V, <4 x float> undef, <4 x i32> < i32 1, i32 undef, i32 7, i32 2 > ; <<4 x float>> [#uses=1] - ret <4 x float> %R -} -; ModuleID = 'intrinsics.ll' - -declare i1 @llvm.isunordered.f32(float, float) - -declare i1 @llvm.isunordered.f64(double, double) - -declare void @llvm.prefetch(i8*, i32, i32) - -declare float @llvm.sqrt.f32(float) - -declare double @llvm.sqrt.f64(double) - -define void @libm() { - fcmp uno float 1.000000e+00, 2.000000e+00 ; <i1>:1 [#uses=0] - fcmp uno double 3.000000e+00, 4.000000e+00 ; <i1>:2 [#uses=0] - call void @llvm.prefetch( i8* null, i32 1, i32 3 ) - call float @llvm.sqrt.f32( float 5.000000e+00 ) ; <float>:3 [#uses=0] - call double @llvm.sqrt.f64( double 6.000000e+00 ) ; <double>:4 [#uses=0] - call i8 @llvm.ctpop.i8( i8 10 ) ; <i32>:5 [#uses=1] - call i16 @llvm.ctpop.i16( i16 11 ) ; <i32>:7 [#uses=1] - call i32 @llvm.ctpop.i32( i32 12 ) ; <i32>:9 [#uses=1] - call i64 @llvm.ctpop.i64( i64 13 ) ; <i32>:11 [#uses=1] - call i8 @llvm.ctlz.i8( i8 14 ) ; <i32>:13 [#uses=1] - call i16 @llvm.ctlz.i16( i16 15 ) ; <i32>:15 [#uses=1] - call i32 @llvm.ctlz.i32( i32 16 ) ; <i32>:17 [#uses=1] - call i64 @llvm.ctlz.i64( i64 17 ) ; <i32>:19 [#uses=1] - call i8 @llvm.cttz.i8( i8 18 ) ; <i32>:21 [#uses=1] - call i16 @llvm.cttz.i16( i16 19 ) ; <i32>:23 [#uses=1] - call i32 @llvm.cttz.i32( i32 20 ) ; <i32>:25 [#uses=1] - call i64 @llvm.cttz.i64( i64 21 ) ; <i32>:27 [#uses=1] - ret void -} - -declare i8 @llvm.ctpop.i8(i8) - -declare i16 @llvm.ctpop.i16(i16) - -declare i32 @llvm.ctpop.i32(i32) - -declare i64 @llvm.ctpop.i64(i64) - -declare i8 @llvm.ctlz.i8(i8) - -declare i16 @llvm.ctlz.i16(i16) - -declare i32 @llvm.ctlz.i32(i32) - -declare i64 @llvm.ctlz.i64(i64) - -declare i8 @llvm.cttz.i8(i8) - -declare i16 @llvm.cttz.i16(i16) - -declare i32 @llvm.cttz.i32(i32) - -declare i64 @llvm.cttz.i64(i64) - -; ModuleID = 'packed.ll' -@foo1 = external global <4 x float> ; <<4 x float>*> [#uses=2] -@foo102 = external global <2 x i32> ; <<2 x i32>*> [#uses=2] - -define void @main3() { - store <4 x float> < float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00 >, <4 x float>* @foo1 - store <2 x i32> < i32 4, i32 4 >, <2 x i32>* @foo102 - %l1 = load <4 x float>* @foo1 ; <<4 x float>> [#uses=0] - %l2 = load <2 x i32>* @foo102 ; <<2 x i32>> [#uses=0] - ret void -} - -; ModuleID = 'properties.ll' -target datalayout = "e-p:32:32" -target triple = "proc-vend-sys" -deplibs = [ "m", "c" ] -; ModuleID = 'prototype.ll' - -declare i32 @bar1017(i32 %in) - -define i32 @foo1016(i32 %blah) { - %xx = call i32 @bar1017( i32 %blah ) ; <i32> [#uses=1] - ret i32 %xx -} - -; ModuleID = 'recursivetype.ll' - %list = type { %list*, i32 } - -declare i8* @malloc(i32) - -define void @InsertIntoListTail(%list** %L, i32 %Data) { -bb1: - %reg116 = load %list** %L ; <%list*> [#uses=1] - %cast1004 = inttoptr i64 0 to %list* ; <%list*> [#uses=1] - %cond1000 = icmp eq %list* %reg116, %cast1004 ; <i1> [#uses=1] - br i1 %cond1000, label %bb3, label %bb2 - -bb2: ; preds = %bb2, %bb1 - %reg117 = phi %list** [ %reg118, %bb2 ], [ %L, %bb1 ] ; <%list**> [#uses=1] - %cast1010 = bitcast %list** %reg117 to %list*** ; <%list***> [#uses=1] - %reg118 = load %list*** %cast1010 ; <%list**> [#uses=3] - %reg109 = load %list** %reg118 ; <%list*> [#uses=1] - %cast1005 = inttoptr i64 0 to %list* ; <%list*> [#uses=1] - %cond1001 = icmp ne %list* %reg109, %cast1005 ; <i1> [#uses=1] - br i1 %cond1001, label %bb2, label %bb3 - -bb3: ; preds = %bb2, %bb1 - %reg119 = phi %list** [ %reg118, %bb2 ], [ %L, %bb1 ] ; <%list**> [#uses=1] - %cast1006 = bitcast %list** %reg119 to i8** ; <i8**> [#uses=1] - %reg111 = call i8* @malloc( i32 16 ) ; <i8*> [#uses=3] - store i8* %reg111, i8** %cast1006 - %reg111.upgrd.1 = ptrtoint i8* %reg111 to i64 ; <i64> [#uses=1] - %reg1002 = add i64 %reg111.upgrd.1, 8 ; <i64> [#uses=1] - %reg1002.upgrd.2 = inttoptr i64 %reg1002 to i8* ; <i8*> [#uses=1] - %cast1008 = bitcast i8* %reg1002.upgrd.2 to i32* ; <i32*> [#uses=1] - store i32 %Data, i32* %cast1008 - %cast1003 = inttoptr i64 0 to i64* ; <i64*> [#uses=1] - %cast1009 = bitcast i8* %reg111 to i64** ; <i64**> [#uses=1] - store i64* %cast1003, i64** %cast1009 - ret void -} - -define %list* @FindData(%list* %L, i32 %Data) { -bb1: - br label %bb2 - -bb2: ; preds = %bb6, %bb1 - %reg115 = phi %list* [ %reg116, %bb6 ], [ %L, %bb1 ] ; <%list*> [#uses=4] - %cast1014 = inttoptr i64 0 to %list* ; <%list*> [#uses=1] - %cond1011 = icmp ne %list* %reg115, %cast1014 ; <i1> [#uses=1] - br i1 %cond1011, label %bb4, label %bb3 - -bb3: ; preds = %bb2 - ret %list* null - -bb4: ; preds = %bb2 - %idx = getelementptr %list* %reg115, i64 0, i32 1 ; <i32*> [#uses=1] - %reg111 = load i32* %idx ; <i32> [#uses=1] - %cond1013 = icmp ne i32 %reg111, %Data ; <i1> [#uses=1] - br i1 %cond1013, label %bb6, label %bb5 - -bb5: ; preds = %bb4 - ret %list* %reg115 - -bb6: ; preds = %bb4 - %idx2 = getelementptr %list* %reg115, i64 0, i32 0 ; <%list**> [#uses=1] - %reg116 = load %list** %idx2 ; <%list*> [#uses=1] - br label %bb2 -} -; ModuleID = 'simplecalltest.ll' - %FunTy = type i32 (i32) - -define void @invoke1019(%FunTy* %x) { - %foo = call i32 %x( i32 123 ) ; <i32> [#uses=0] - ret void -} - -define i32 @main4(i32 %argc, i8** %argv, i8** %envp) { - %retval = call i32 @test1008( i32 %argc ) ; <i32> [#uses=2] - %two = add i32 %retval, %retval ; <i32> [#uses=1] - %retval2 = call i32 @test1008( i32 %argc ) ; <i32> [#uses=1] - %two2 = add i32 %two, %retval2 ; <i32> [#uses=1] - call void @invoke1019( %FunTy* @test1008 ) - ret i32 %two2 -} - -define i32 @test1008(i32 %i0) { - ret i32 %i0 -} -; ModuleID = 'smallest.ll' -; ModuleID = 'small.ll' - %x = type i32 - -define i32 @foo1020(i32 %in) { -label: - ret i32 2 -} -; ModuleID = 'testalloca.ll' - %inners = type { float, { i8 } } - %struct = type { i32, %inners, i64 } - -define i32 @testfunction(i32 %i0, i32 %j0) { - alloca i8, i32 5 ; <i8*>:1 [#uses=0] - %ptr = alloca i32 ; <i32*> [#uses=2] - store i32 3, i32* %ptr - %val = load i32* %ptr ; <i32> [#uses=0] - %sptr = alloca %struct ; <%struct*> [#uses=2] - %nsptr = getelementptr %struct* %sptr, i64 0, i32 1 ; <%inners*> [#uses=1] - %ubsptr = getelementptr %inners* %nsptr, i64 0, i32 1 ; <{ i8 }*> [#uses=1] - %idx = getelementptr { i8 }* %ubsptr, i64 0, i32 0 ; <i8*> [#uses=1] - store i8 4, i8* %idx - %fptr = getelementptr %struct* %sptr, i64 0, i32 1, i32 0 ; <float*> [#uses=1] - store float 4.000000e+00, float* %fptr - ret i32 3 -} -; ModuleID = 'testconstants.ll' -@somestr3 = constant [11 x i8] c"hello world" -@array99 = constant [2 x i32] [ i32 12, i32 52 ] -constant { i32, i32 } { i32 4, i32 3 } ; <{ i32, i32 }*>:0 [#uses=0] - -define [2 x i32]* @testfunction99(i32 %i0, i32 %j0) { - ret [2 x i32]* @array -} - -define i8* @otherfunc(i32, double) { - %somestr = getelementptr [11 x i8]* @somestr3, i64 0, i64 0 ; <i8*> [#uses=1] - ret i8* %somestr -} - -define i8* @yetanotherfunc(i32, double) { - ret i8* null -} - -define i32 @negativeUnsigned() { - ret i32 -1 -} - -define i32 @largeSigned() { - ret i32 -394967296 -} -; ModuleID = 'testlogical.ll' - -define i32 @simpleAdd(i32 %i0, i32 %j0) { - %t1 = xor i32 %i0, %j0 ; <i32> [#uses=1] - %t2 = or i32 %i0, %j0 ; <i32> [#uses=1] - %t3 = and i32 %t1, %t2 ; <i32> [#uses=1] - ret i32 %t3 -} -; ModuleID = 'testmemory.ll' - %complexty = type { i32, { [4 x i8*], float }, double } - %struct = type { i32, { float, { i8 } }, i64 } - -define i32 @main6() { - call i32 @testfunction98( i64 0, i64 1 ) - ret i32 0 -} - -define i32 @testfunction98(i64 %i0, i64 %j0) { - %array0 = malloc [4 x i8] ; <[4 x i8]*> [#uses=2] - %size = add i32 2, 2 ; <i32> [#uses=1] - %array1 = malloc i8, i32 4 ; <i8*> [#uses=1] - %array2 = malloc i8, i32 %size ; <i8*> [#uses=1] - %idx = getelementptr [4 x i8]* %array0, i64 0, i64 2 ; <i8*> [#uses=1] - store i8 123, i8* %idx - free [4 x i8]* %array0 - free i8* %array1 - free i8* %array2 - %aa = alloca %complexty, i32 5 ; <%complexty*> [#uses=1] - %idx2 = getelementptr %complexty* %aa, i64 %i0, i32 1, i32 0, i64 %j0 ; <i8**> [#uses=1] - store i8* null, i8** %idx2 - %ptr = alloca i32 ; <i32*> [#uses=2] - store i32 3, i32* %ptr - %val = load i32* %ptr ; <i32> [#uses=0] - %sptr = alloca %struct ; <%struct*> [#uses=1] - %ubsptr = getelementptr %struct* %sptr, i64 0, i32 1, i32 1 ; <{ i8 }*> [#uses=1] - %idx3 = getelementptr { i8 }* %ubsptr, i64 0, i32 0 ; <i8*> [#uses=1] - store i8 4, i8* %idx3 - ret i32 3 -} -; ModuleID = 'testswitch.ll' - %int = type i32 - -define i32 @squared(i32 %i0) { - switch i32 %i0, label %Default [ - i32 1, label %Case1 - i32 2, label %Case2 - i32 4, label %Case4 - ] - -Default: ; preds = %0 - ret i32 -1 - -Case1: ; preds = %0 - ret i32 1 - -Case2: ; preds = %0 - ret i32 4 - -Case4: ; preds = %0 - ret i32 16 -} -; ModuleID = 'testvarargs.ll' - -declare i32 @printf(i8*, ...) - -define i32 @testvarar() { - call i32 (i8*, ...)* @printf( i8* null, i32 12, i8 42 ) ; <i32>:1 [#uses=1] - ret i32 %1 -} -; ModuleID = 'undefined.ll' -@X2 = global i32 undef ; <i32*> [#uses=0] - -declare i32 @atoi(i8*) - -define i32 @test1009() { - ret i32 undef -} - -define i32 @test1003() { - %X = add i32 undef, 1 ; <i32> [#uses=1] - ret i32 %X -} -; ModuleID = 'unreachable.ll' - -declare void @bar() - -define i32 @foo1021() { - unreachable -} - -define double @xyz() { - call void @bar( ) - unreachable -} -; ModuleID = 'varargs.ll' - -declare void @llvm.va_start(i8* %ap) - -declare void @llvm.va_copy(i8* %aq, i8* %ap) - -declare void @llvm.va_end(i8* %ap) - -define i32 @test1010(i32 %X, ...) { - %ap = alloca i8* ; <i8**> [#uses=4] - %va.upgrd.1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1] - call void @llvm.va_start( i8* %va.upgrd.1 ) - %tmp = va_arg i8** %ap, i32 ; <i32> [#uses=1] - %aq = alloca i8* ; <i8**> [#uses=2] - %va0.upgrd.2 = bitcast i8** %aq to i8* ; <i8*> [#uses=1] - %va1.upgrd.3 = bitcast i8** %ap to i8* ; <i8*> [#uses=1] - call void @llvm.va_copy( i8* %va0.upgrd.2, i8* %va1.upgrd.3 ) - %va.upgrd.4 = bitcast i8** %aq to i8* ; <i8*> [#uses=1] - call void @llvm.va_end( i8* %va.upgrd.4 ) - %va.upgrd.5 = bitcast i8** %ap to i8* ; <i8*> [#uses=1] - call void @llvm.va_end( i8* %va.upgrd.5 ) - ret i32 %tmp -} -; ModuleID = 'varargs_new.ll' - -declare void @llvm.va_start(i8*) - -declare void @llvm.va_copy(i8*, i8*) - -declare void @llvm.va_end(i8*) - -define i32 @test1011(i32 %X, ...) { - %ap = alloca i8* ; <i8**> [#uses=4] - %aq = alloca i8* ; <i8**> [#uses=2] - %va.upgrd.1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1] - call void @llvm.va_start( i8* %va.upgrd.1 ) - %tmp = va_arg i8** %ap, i32 ; <i32> [#uses=1] - %apv = load i8** %ap ; <i8*> [#uses=1] - %va0.upgrd.2 = bitcast i8** %aq to i8* ; <i8*> [#uses=1] - %va1.upgrd.3 = bitcast i8* %apv to i8* ; <i8*> [#uses=1] - call void @llvm.va_copy( i8* %va0.upgrd.2, i8* %va1.upgrd.3 ) - %va.upgrd.4 = bitcast i8** %aq to i8* ; <i8*> [#uses=1] - call void @llvm.va_end( i8* %va.upgrd.4 ) - %va.upgrd.5 = bitcast i8** %ap to i8* ; <i8*> [#uses=1] - call void @llvm.va_end( i8* %va.upgrd.5 ) - ret i32 %tmp -} -; ModuleID = 'weirdnames.ll' - "&^ " = type { i32 } -@"%.*+ foo" = global "&^ " { i32 5 } ; <"&^ "*> [#uses=0] -@"0" = global float 0.000000e+00 ; <float*> [#uses=0] diff --git a/test/CodeGen/CellSPU/and_ops.ll b/test/CodeGen/CellSPU/and_ops.ll index 139e97b..72478a1 100644 --- a/test/CodeGen/CellSPU/and_ops.ll +++ b/test/CodeGen/CellSPU/and_ops.ll @@ -201,12 +201,12 @@ define <4 x i32> @andi_v4i32_4(<4 x i32> %in) { ret <4 x i32> %tmp2 } -define i32 @andi_u32(i32 zeroext %in) zeroext { +define zeroext i32 @andi_u32(i32 zeroext %in) { %tmp37 = and i32 %in, 37 ret i32 %tmp37 } -define i32 @andi_i32(i32 signext %in) signext { +define signext i32 @andi_i32(i32 signext %in) { %tmp38 = and i32 %in, 37 ret i32 %tmp38 } @@ -241,12 +241,12 @@ define <8 x i16> @andhi_v8i16_4(<8 x i16> %in) { ret <8 x i16> %tmp2 } -define i16 @andhi_u16(i16 zeroext %in) zeroext { +define zeroext i16 @andhi_u16(i16 zeroext %in) { %tmp37 = and i16 %in, 37 ; <i16> [#uses=1] ret i16 %tmp37 } -define i16 @andhi_i16(i16 signext %in) signext { +define signext i16 @andhi_i16(i16 signext %in) { %tmp38 = and i16 %in, 37 ; <i16> [#uses=1] ret i16 %tmp38 } @@ -260,13 +260,13 @@ define <16 x i8> @and_v16i8(<16 x i8> %in) { ret <16 x i8> %tmp2 } -define i8 @and_u8(i8 zeroext %in) zeroext { +define zeroext i8 @and_u8(i8 zeroext %in) { ; ANDBI generated: %tmp37 = and i8 %in, 37 ret i8 %tmp37 } -define i8 @and_sext8(i8 signext %in) signext { +define signext i8 @and_sext8(i8 signext %in) { ; ANDBI generated %tmp38 = and i8 %in, 37 ret i8 %tmp38 diff --git a/test/CodeGen/CellSPU/eqv.ll b/test/CodeGen/CellSPU/eqv.ll index 22c8c3b..7967681 100644 --- a/test/CodeGen/CellSPU/eqv.ll +++ b/test/CodeGen/CellSPU/eqv.ll @@ -79,7 +79,7 @@ define i32 @equiv_i32_5(i32 %arg1, i32 %arg2) { ret i32 %C } -define i16 @equiv_i16_1(i16 signext %arg1, i16 signext %arg2) signext { +define signext i16 @equiv_i16_1(i16 signext %arg1, i16 signext %arg2) { %A = and i16 %arg1, %arg2 ; <i16> [#uses=1] %B = or i16 %arg1, %arg2 ; <i16> [#uses=1] %Bnot = xor i16 %B, -1 ; <i16> [#uses=1] @@ -87,7 +87,7 @@ define i16 @equiv_i16_1(i16 signext %arg1, i16 signext %arg2) signext { ret i16 %C } -define i16 @equiv_i16_2(i16 signext %arg1, i16 signext %arg2) signext { +define signext i16 @equiv_i16_2(i16 signext %arg1, i16 signext %arg2) { %B = or i16 %arg1, %arg2 ; <i16> [#uses=1] %Bnot = xor i16 %B, -1 ; <i16> [#uses=1] %A = and i16 %arg1, %arg2 ; <i16> [#uses=1] @@ -95,7 +95,7 @@ define i16 @equiv_i16_2(i16 signext %arg1, i16 signext %arg2) signext { ret i16 %C } -define i16 @equiv_i16_3(i16 signext %arg1, i16 signext %arg2) signext { +define signext i16 @equiv_i16_3(i16 signext %arg1, i16 signext %arg2) { %B = or i16 %arg1, %arg2 ; <i16> [#uses=1] %A = and i16 %arg1, %arg2 ; <i16> [#uses=1] %Bnot = xor i16 %B, -1 ; <i16> [#uses=1] @@ -103,7 +103,7 @@ define i16 @equiv_i16_3(i16 signext %arg1, i16 signext %arg2) signext { ret i16 %C } -define i8 @equiv_i8_1(i8 signext %arg1, i8 signext %arg2) signext { +define signext i8 @equiv_i8_1(i8 signext %arg1, i8 signext %arg2) { %A = and i8 %arg1, %arg2 ; <i8> [#uses=1] %B = or i8 %arg1, %arg2 ; <i8> [#uses=1] %Bnot = xor i8 %B, -1 ; <i8> [#uses=1] @@ -111,7 +111,7 @@ define i8 @equiv_i8_1(i8 signext %arg1, i8 signext %arg2) signext { ret i8 %C } -define i8 @equiv_i8_2(i8 signext %arg1, i8 signext %arg2) signext { +define signext i8 @equiv_i8_2(i8 signext %arg1, i8 signext %arg2) { %B = or i8 %arg1, %arg2 ; <i8> [#uses=1] %Bnot = xor i8 %B, -1 ; <i8> [#uses=1] %A = and i8 %arg1, %arg2 ; <i8> [#uses=1] @@ -119,7 +119,7 @@ define i8 @equiv_i8_2(i8 signext %arg1, i8 signext %arg2) signext { ret i8 %C } -define i8 @equiv_i8_3(i8 signext %arg1, i8 signext %arg2) signext { +define signext i8 @equiv_i8_3(i8 signext %arg1, i8 signext %arg2) { %B = or i8 %arg1, %arg2 ; <i8> [#uses=1] %A = and i8 %arg1, %arg2 ; <i8> [#uses=1] %Bnot = xor i8 %B, -1 ; <i8> [#uses=1] @@ -127,7 +127,7 @@ define i8 @equiv_i8_3(i8 signext %arg1, i8 signext %arg2) signext { ret i8 %C } -define i8 @equiv_u8_1(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { +define zeroext i8 @equiv_u8_1(i8 zeroext %arg1, i8 zeroext %arg2) { %A = and i8 %arg1, %arg2 ; <i8> [#uses=1] %B = or i8 %arg1, %arg2 ; <i8> [#uses=1] %Bnot = xor i8 %B, -1 ; <i8> [#uses=1] @@ -135,7 +135,7 @@ define i8 @equiv_u8_1(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { ret i8 %C } -define i8 @equiv_u8_2(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { +define zeroext i8 @equiv_u8_2(i8 zeroext %arg1, i8 zeroext %arg2) { %B = or i8 %arg1, %arg2 ; <i8> [#uses=1] %Bnot = xor i8 %B, -1 ; <i8> [#uses=1] %A = and i8 %arg1, %arg2 ; <i8> [#uses=1] @@ -143,7 +143,7 @@ define i8 @equiv_u8_2(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { ret i8 %C } -define i8 @equiv_u8_3(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { +define zeroext i8 @equiv_u8_3(i8 zeroext %arg1, i8 zeroext %arg2) { %B = or i8 %arg1, %arg2 ; <i8> [#uses=1] %A = and i8 %arg1, %arg2 ; <i8> [#uses=1] %Bnot = xor i8 %B, -1 ; <i8> [#uses=1] diff --git a/test/CodeGen/CellSPU/mul-with-overflow.ll b/test/CodeGen/CellSPU/mul-with-overflow.ll index d15da12..c04e69e 100644 --- a/test/CodeGen/CellSPU/mul-with-overflow.ll +++ b/test/CodeGen/CellSPU/mul-with-overflow.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -march=cellspu declare {i16, i1} @llvm.smul.with.overflow.i16(i16 %a, i16 %b) -define i1 @a(i16 %x) zeroext nounwind { +define zeroext i1 @a(i16 %x) nounwind { %res = call {i16, i1} @llvm.smul.with.overflow.i16(i16 %x, i16 3) %obil = extractvalue {i16, i1} %res, 1 ret i1 %obil } declare {i16, i1} @llvm.umul.with.overflow.i16(i16 %a, i16 %b) -define i1 @b(i16 %x) zeroext nounwind { +define zeroext i1 @b(i16 %x) nounwind { %res = call {i16, i1} @llvm.umul.with.overflow.i16(i16 %x, i16 3) %obil = extractvalue {i16, i1} %res, 1 ret i1 %obil diff --git a/test/CodeGen/CellSPU/nand.ll b/test/CodeGen/CellSPU/nand.ll index e141923..b770cad 100644 --- a/test/CodeGen/CellSPU/nand.ll +++ b/test/CodeGen/CellSPU/nand.ll @@ -60,49 +60,49 @@ define i32 @nand_i32_2(i32 %arg1, i32 %arg2) { ret i32 %B } -define i16 @nand_i16_1(i16 signext %arg1, i16 signext %arg2) signext { +define signext i16 @nand_i16_1(i16 signext %arg1, i16 signext %arg2) { %A = and i16 %arg2, %arg1 ; <i16> [#uses=1] %B = xor i16 %A, -1 ; <i16> [#uses=1] ret i16 %B } -define i16 @nand_i16_2(i16 signext %arg1, i16 signext %arg2) signext { +define signext i16 @nand_i16_2(i16 signext %arg1, i16 signext %arg2) { %A = and i16 %arg1, %arg2 ; <i16> [#uses=1] %B = xor i16 %A, -1 ; <i16> [#uses=1] ret i16 %B } -define i16 @nand_i16u_1(i16 zeroext %arg1, i16 zeroext %arg2) zeroext { +define zeroext i16 @nand_i16u_1(i16 zeroext %arg1, i16 zeroext %arg2) { %A = and i16 %arg2, %arg1 ; <i16> [#uses=1] %B = xor i16 %A, -1 ; <i16> [#uses=1] ret i16 %B } -define i16 @nand_i16u_2(i16 zeroext %arg1, i16 zeroext %arg2) zeroext { +define zeroext i16 @nand_i16u_2(i16 zeroext %arg1, i16 zeroext %arg2) { %A = and i16 %arg1, %arg2 ; <i16> [#uses=1] %B = xor i16 %A, -1 ; <i16> [#uses=1] ret i16 %B } -define i8 @nand_i8u_1(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { +define zeroext i8 @nand_i8u_1(i8 zeroext %arg1, i8 zeroext %arg2) { %A = and i8 %arg2, %arg1 ; <i8> [#uses=1] %B = xor i8 %A, -1 ; <i8> [#uses=1] ret i8 %B } -define i8 @nand_i8u_2(i8 zeroext %arg1, i8 zeroext %arg2) zeroext { +define zeroext i8 @nand_i8u_2(i8 zeroext %arg1, i8 zeroext %arg2) { %A = and i8 %arg1, %arg2 ; <i8> [#uses=1] %B = xor i8 %A, -1 ; <i8> [#uses=1] ret i8 %B } -define i8 @nand_i8_1(i8 signext %arg1, i8 signext %arg2) signext { +define signext i8 @nand_i8_1(i8 signext %arg1, i8 signext %arg2) { %A = and i8 %arg2, %arg1 ; <i8> [#uses=1] %B = xor i8 %A, -1 ; <i8> [#uses=1] ret i8 %B } -define i8 @nand_i8_2(i8 signext %arg1, i8 signext %arg2) signext { +define signext i8 @nand_i8_2(i8 signext %arg1, i8 signext %arg2) { %A = and i8 %arg1, %arg2 ; <i8> [#uses=1] %B = xor i8 %A, -1 ; <i8> [#uses=1] ret i8 %B diff --git a/test/CodeGen/CellSPU/or_ops.ll b/test/CodeGen/CellSPU/or_ops.ll index 8aa1e99..46349b9 100644 --- a/test/CodeGen/CellSPU/or_ops.ll +++ b/test/CodeGen/CellSPU/or_ops.ll @@ -200,12 +200,12 @@ define <4 x i32> @ori_v4i32_4(<4 x i32> %in) { ret <4 x i32> %tmp2 } -define i32 @ori_u32(i32 zeroext %in) zeroext { +define zeroext i32 @ori_u32(i32 zeroext %in) { %tmp37 = or i32 %in, 37 ; <i32> [#uses=1] ret i32 %tmp37 } -define i32 @ori_i32(i32 signext %in) signext { +define signext i32 @ori_i32(i32 signext %in) { %tmp38 = or i32 %in, 37 ; <i32> [#uses=1] ret i32 %tmp38 } @@ -235,12 +235,12 @@ define <8 x i16> @orhi_v8i16_4(<8 x i16> %in) { ret <8 x i16> %tmp2 } -define i16 @orhi_u16(i16 zeroext %in) zeroext { +define zeroext i16 @orhi_u16(i16 zeroext %in) { %tmp37 = or i16 %in, 37 ; <i16> [#uses=1] ret i16 %tmp37 } -define i16 @orhi_i16(i16 signext %in) signext { +define signext i16 @orhi_i16(i16 signext %in) { %tmp38 = or i16 %in, 37 ; <i16> [#uses=1] ret i16 %tmp38 } @@ -253,12 +253,12 @@ define <16 x i8> @orbi_v16i8(<16 x i8> %in) { ret <16 x i8> %tmp2 } -define i8 @orbi_u8(i8 zeroext %in) zeroext { +define zeroext i8 @orbi_u8(i8 zeroext %in) { %tmp37 = or i8 %in, 37 ; <i8> [#uses=1] ret i8 %tmp37 } -define i8 @orbi_i8(i8 signext %in) signext { +define signext i8 @orbi_i8(i8 signext %in) { %tmp38 = or i8 %in, 37 ; <i8> [#uses=1] ret i8 %tmp38 } diff --git a/test/CodeGen/CellSPU/shift_ops.ll b/test/CodeGen/CellSPU/shift_ops.ll index c4a5abd..3252c77 100644 --- a/test/CodeGen/CellSPU/shift_ops.ll +++ b/test/CodeGen/CellSPU/shift_ops.ll @@ -33,22 +33,22 @@ define i16 @shlh_i16_2(i16 %arg1, i16 %arg2) { ret i16 %A } -define i16 @shlh_i16_3(i16 signext %arg1, i16 signext %arg2) signext { +define signext i16 @shlh_i16_3(i16 signext %arg1, i16 signext %arg2) { %A = shl i16 %arg1, %arg2 ret i16 %A } -define i16 @shlh_i16_4(i16 signext %arg1, i16 signext %arg2) signext { +define signext i16 @shlh_i16_4(i16 signext %arg1, i16 signext %arg2) { %A = shl i16 %arg2, %arg1 ret i16 %A } -define i16 @shlh_i16_5(i16 zeroext %arg1, i16 zeroext %arg2) zeroext { +define zeroext i16 @shlh_i16_5(i16 zeroext %arg1, i16 zeroext %arg2) { %A = shl i16 %arg1, %arg2 ret i16 %A } -define i16 @shlh_i16_6(i16 zeroext %arg1, i16 zeroext %arg2) zeroext { +define zeroext i16 @shlh_i16_6(i16 zeroext %arg1, i16 zeroext %arg2) { %A = shl i16 %arg2, %arg1 ret i16 %A } @@ -76,46 +76,46 @@ define i16 @shlhi_i16_4(i16 %arg1) { ret i16 %A } -define i16 @shlhi_i16_5(i16 signext %arg1) signext { +define signext i16 @shlhi_i16_5(i16 signext %arg1) { %A = shl i16 %arg1, 12 ret i16 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 -define i16 @shlhi_i16_6(i16 signext %arg1) signext { +define signext i16 @shlhi_i16_6(i16 signext %arg1) { %A = shl i16 %arg1, 0 ret i16 %A } -define i16 @shlhi_i16_7(i16 signext %arg1) signext { +define signext i16 @shlhi_i16_7(i16 signext %arg1) { %A = shl i16 16383, %arg1 ret i16 %A } ; Should generate 0, 0 << arg1 = 0 -define i16 @shlhi_i16_8(i16 signext %arg1) signext { +define signext i16 @shlhi_i16_8(i16 signext %arg1) { %A = shl i16 0, %arg1 ret i16 %A } -define i16 @shlhi_i16_9(i16 zeroext %arg1) zeroext { +define zeroext i16 @shlhi_i16_9(i16 zeroext %arg1) { %A = shl i16 %arg1, 12 ret i16 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 -define i16 @shlhi_i16_10(i16 zeroext %arg1) zeroext { +define zeroext i16 @shlhi_i16_10(i16 zeroext %arg1) { %A = shl i16 %arg1, 0 ret i16 %A } -define i16 @shlhi_i16_11(i16 zeroext %arg1) zeroext { +define zeroext i16 @shlhi_i16_11(i16 zeroext %arg1) { %A = shl i16 16383, %arg1 ret i16 %A } ; Should generate 0, 0 << arg1 = 0 -define i16 @shlhi_i16_12(i16 zeroext %arg1) zeroext { +define zeroext i16 @shlhi_i16_12(i16 zeroext %arg1) { %A = shl i16 0, %arg1 ret i16 %A } @@ -133,22 +133,22 @@ define i32 @shl_i32_2(i32 %arg1, i32 %arg2) { ret i32 %A } -define i32 @shl_i32_3(i32 signext %arg1, i32 signext %arg2) signext { +define signext i32 @shl_i32_3(i32 signext %arg1, i32 signext %arg2) { %A = shl i32 %arg1, %arg2 ret i32 %A } -define i32 @shl_i32_4(i32 signext %arg1, i32 signext %arg2) signext { +define signext i32 @shl_i32_4(i32 signext %arg1, i32 signext %arg2) { %A = shl i32 %arg2, %arg1 ret i32 %A } -define i32 @shl_i32_5(i32 zeroext %arg1, i32 zeroext %arg2) zeroext { +define zeroext i32 @shl_i32_5(i32 zeroext %arg1, i32 zeroext %arg2) { %A = shl i32 %arg1, %arg2 ret i32 %A } -define i32 @shl_i32_6(i32 zeroext %arg1, i32 zeroext %arg2) zeroext { +define zeroext i32 @shl_i32_6(i32 zeroext %arg1, i32 zeroext %arg2) { %A = shl i32 %arg2, %arg1 ret i32 %A } @@ -176,46 +176,46 @@ define i32 @shli_i32_4(i32 %arg1) { ret i32 %A } -define i32 @shli_i32_5(i32 signext %arg1) signext { +define signext i32 @shli_i32_5(i32 signext %arg1) { %A = shl i32 %arg1, 12 ret i32 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 -define i32 @shli_i32_6(i32 signext %arg1) signext { +define signext i32 @shli_i32_6(i32 signext %arg1) { %A = shl i32 %arg1, 0 ret i32 %A } -define i32 @shli_i32_7(i32 signext %arg1) signext { +define signext i32 @shli_i32_7(i32 signext %arg1) { %A = shl i32 16383, %arg1 ret i32 %A } ; Should generate 0, 0 << arg1 = 0 -define i32 @shli_i32_8(i32 signext %arg1) signext { +define signext i32 @shli_i32_8(i32 signext %arg1) { %A = shl i32 0, %arg1 ret i32 %A } -define i32 @shli_i32_9(i32 zeroext %arg1) zeroext { +define zeroext i32 @shli_i32_9(i32 zeroext %arg1) { %A = shl i32 %arg1, 12 ret i32 %A } ; Should not generate anything other than the return, arg1 << 0 = arg1 -define i32 @shli_i32_10(i32 zeroext %arg1) zeroext { +define zeroext i32 @shli_i32_10(i32 zeroext %arg1) { %A = shl i32 %arg1, 0 ret i32 %A } -define i32 @shli_i32_11(i32 zeroext %arg1) zeroext { +define zeroext i32 @shli_i32_11(i32 zeroext %arg1) { %A = shl i32 16383, %arg1 ret i32 %A } ; Should generate 0, 0 << arg1 = 0 -define i32 @shli_i32_12(i32 zeroext %arg1) zeroext { +define zeroext i32 @shli_i32_12(i32 zeroext %arg1) { %A = shl i32 0, %arg1 ret i32 %A } diff --git a/test/CodeGen/CellSPU/struct_1.ll b/test/CodeGen/CellSPU/struct_1.ll index 8ee7d93..adbb5ef 100644 --- a/test/CodeGen/CellSPU/struct_1.ll +++ b/test/CodeGen/CellSPU/struct_1.ll @@ -47,19 +47,19 @@ target triple = "spu" ; struct hackstate state = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } @state = global %struct.hackstate zeroinitializer, align 16 -define i8 @get_hackstate_c1() zeroext nounwind { +define zeroext i8 @get_hackstate_c1() nounwind { entry: %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 0), align 16 ret i8 %tmp2 } -define i8 @get_hackstate_c2() zeroext nounwind { +define zeroext i8 @get_hackstate_c2() nounwind { entry: %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 1), align 16 ret i8 %tmp2 } -define i8 @get_hackstate_c3() zeroext nounwind { +define zeroext i8 @get_hackstate_c3() nounwind { entry: %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 2), align 16 ret i8 %tmp2 @@ -71,19 +71,19 @@ entry: ret i32 %tmp2 } -define i16 @get_hackstate_s1() signext nounwind { +define signext i16 @get_hackstate_s1() nounwind { entry: %tmp2 = load i16* getelementptr (%struct.hackstate* @state, i32 0, i32 4), align 16 ret i16 %tmp2 } -define i8 @get_hackstate_c6() zeroext nounwind { +define zeroext i8 @get_hackstate_c6() nounwind { entry: %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 8), align 16 ret i8 %tmp2 } -define i8 @get_hackstate_c7() zeroext nounwind { +define zeroext i8 @get_hackstate_c7() nounwind { entry: %tmp2 = load i8* getelementptr (%struct.hackstate* @state, i32 0, i32 9), align 16 ret i8 %tmp2 diff --git a/test/CodeGen/CellSPU/v2f32.ll b/test/CodeGen/CellSPU/v2f32.ll index efd0320..09e15ff 100644 --- a/test/CodeGen/CellSPU/v2f32.ll +++ b/test/CodeGen/CellSPU/v2f32.ll @@ -33,6 +33,7 @@ define %vec @test_mul(%vec %param) ret %vec %1 } +; CHECK: test_splat: define %vec @test_splat(float %param ) { ;CHECK: lqa ;CHECK: shufb @@ -43,16 +44,17 @@ define %vec @test_splat(float %param ) { } define void @test_store(%vec %val, %vec* %ptr){ - +; CHECK: test_store: ;CHECK: stqd - store %vec undef, %vec* null + store %vec zeroinitializer, %vec* null -;CHECK: stqd $3, 0(${{.}}) +;CHECK: stqd $3, 0(${{.*}}) ;CHECK: bi $lr store %vec %val, %vec* %ptr ret void } +; CHECK: test_insert: define %vec @test_insert(){ ;CHECK: cwd ;CHECK: shufb $3 @@ -61,6 +63,8 @@ define %vec @test_insert(){ ret %vec %rv } +; CHECK: test_unaligned_store: + define void @test_unaligned_store() { ;CHECK: cdd ;CHECK: shufb @@ -68,7 +72,7 @@ define void @test_unaligned_store() { %data = alloca [4 x float], align 16 ; <[4 x float]*> [#uses=1] %ptr = getelementptr [4 x float]* %data, i32 0, i32 2 ; <float*> [#uses=1] %vptr = bitcast float* %ptr to <2 x float>* ; <[1 x <2 x float>]*> [#uses=1] - store <2 x float> undef, <2 x float>* %vptr + store <2 x float> zeroinitializer, <2 x float>* %vptr ret void } diff --git a/test/CodeGen/Generic/2010-11-04-BigByval.ll b/test/CodeGen/Generic/2010-11-04-BigByval.ll index ecb354e..df2ca4c 100644 --- a/test/CodeGen/Generic/2010-11-04-BigByval.ll +++ b/test/CodeGen/Generic/2010-11-04-BigByval.ll @@ -1,6 +1,5 @@ ; RUN: llc < %s ; PR7170 -; XFAIL: arm %big = type [131072 x i8] diff --git a/test/CodeGen/Generic/badlive.ll b/test/CodeGen/Generic/badlive.ll deleted file mode 100644 index 43b03e3..0000000 --- a/test/CodeGen/Generic/badlive.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc < %s - -define i32 @main() { -bb0: - %reg109 = malloc i32, i32 100 ; <i32*> [#uses=2] - br label %bb2 - -bb2: ; preds = %bb2, %bb0 - %cann-indvar1 = phi i32 [ 0, %bb0 ], [ %add1-indvar1, %bb2 ] ; <i32> [#uses=2] - %reg127 = mul i32 %cann-indvar1, 2 ; <i32> [#uses=1] - %add1-indvar1 = add i32 %cann-indvar1, 1 ; <i32> [#uses=1] - store i32 999, i32* %reg109 - %cond1015 = icmp sle i32 1, 99 ; <i1> [#uses=1] - %reg128 = add i32 %reg127, 2 ; <i32> [#uses=0] - br i1 %cond1015, label %bb2, label %bb4 - -bb4: ; preds = %bb4, %bb2 - %cann-indvar = phi i32 [ %add1-indvar, %bb4 ], [ 0, %bb2 ] ; <i32> [#uses=1] - %add1-indvar = add i32 %cann-indvar, 1 ; <i32> [#uses=2] - store i32 333, i32* %reg109 - %reg131 = add i32 %add1-indvar, 3 ; <i32> [#uses=1] - %cond1017 = icmp ule i32 %reg131, 99 ; <i1> [#uses=1] - br i1 %cond1017, label %bb4, label %bb5 - -bb5: ; preds = %bb4 - ret i32 0 -} - diff --git a/test/CodeGen/Generic/crash.ll b/test/CodeGen/Generic/crash.ll index 0427398..e7cc7e3 100644 --- a/test/CodeGen/Generic/crash.ll +++ b/test/CodeGen/Generic/crash.ll @@ -38,3 +38,31 @@ unreachable declare void @Parse_Vector(double*) declare i32 @llvm.objectsize.i32(i8*, i1) + +; PR9578 +%struct.S0 = type { i32, i8, i32 } + +define void @func_82() nounwind optsize { +entry: + br label %for.body.i + +for.body.i: ; preds = %for.body.i, %entry + br i1 undef, label %func_74.exit.for.cond29.thread_crit_edge, label %for.body.i + +func_74.exit.for.cond29.thread_crit_edge: ; preds = %for.body.i + %f13576.pre = getelementptr inbounds %struct.S0* undef, i64 0, i32 1 + store i8 0, i8* %f13576.pre, align 4, !tbaa !0 + br label %lbl_468 + +lbl_468: ; preds = %lbl_468, %func_74.exit.for.cond29.thread_crit_edge + %f13577.ph = phi i8* [ %f13576.pre, %func_74.exit.for.cond29.thread_crit_edge ], [ %f135.pre, %lbl_468 ] + store i8 1, i8* %f13577.ph, align 1 + %f135.pre = getelementptr inbounds %struct.S0* undef, i64 0, i32 1 + br i1 undef, label %lbl_468, label %for.end74 + +for.end74: ; preds = %lbl_468 + ret void +} + +!0 = metadata !{metadata !"omnipotent char", metadata !1} +!1 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Generic/edge-bundles-blockIDs.ll b/test/CodeGen/Generic/edge-bundles-blockIDs.ll new file mode 100644 index 0000000..b4ae415 --- /dev/null +++ b/test/CodeGen/Generic/edge-bundles-blockIDs.ll @@ -0,0 +1,81 @@ +; Make sure EdgeBoundles handles the case when the function size is less then +; the number of block IDs. +; RUN: llc -regalloc=fast < %s + +define void @foo() nounwind { +entry: + br i1 undef, label %bb5.i1632, label %bb1.i1605 + +bb1.i1605: ; preds = %entry + br i1 undef, label %bb5.i73.i, label %bb3.i68.i + +bb3.i68.i: ; preds = %bb1.i1605 + unreachable + +bb5.i73.i: ; preds = %bb1.i1605 + br i1 undef, label %bb7.i79.i, label %bb6.i76.i + +bb6.i76.i: ; preds = %bb5.i73.i + unreachable + +bb7.i79.i: ; preds = %bb5.i73.i + br i1 undef, label %bb.i.i1608, label %bb8.i82.i + +bb8.i82.i: ; preds = %bb7.i79.i + unreachable + +bb.i.i1608: ; preds = %bb.i.i1608, %bb7.i79.i + br i1 undef, label %bb1.i.dis.preheader_crit_edge.i, label %bb.i.i1608 + +bb1.i.dis.preheader_crit_edge.i: ; preds = %bb.i.i1608 + br label %dis.i + +bb3.i.i1610: ; preds = %bb8.i.i, %bb7.i.i1615 + br i1 undef, label %bb5.i.i1613, label %bb4.i.i1611 + +bb4.i.i1611: ; preds = %bb3.i.i1610 + br label %bb5.i.i1613 + +bb5.i.i1613: ; preds = %bb4.i.i1611, %bb3.i.i1610 + unreachable + +bb7.i.i1615: ; preds = %getfloder.exit.i + br i1 undef, label %bb3.i.i1610, label %bb8.i.i + +bb8.i.i: ; preds = %bb7.i.i1615 + br i1 undef, label %bb3.i.i1610, label %bb9.i.i + +bb9.i.i: ; preds = %bb8.i.i + br label %bb12.i.i + +bb12.i.i: ; preds = %bb12.i.i, %bb9.i.i + br i1 undef, label %bb13.i.bb14.i_crit_edge.i, label %bb12.i.i + +bb13.i.bb14.i_crit_edge.i: ; preds = %bb12.i.i + br i1 undef, label %bb25.i.i, label %bb20.i.i + +bb19.i.i: ; preds = %bb20.i.i + br label %bb20.i.i + +bb20.i.i: ; preds = %bb19.i.i, %bb13.i.bb14.i_crit_edge.i + %or.cond.i = or i1 undef, undef + br i1 %or.cond.i, label %bb25.i.i, label %bb19.i.i + +bb25.i.i: ; preds = %bb20.i.i, %bb13.i.bb14.i_crit_edge.i + unreachable + +bb5.i1632: ; preds = %entry + unreachable + +dis.i: ; preds = %getfloder.exit.i, %bb1.i.dis.preheader_crit_edge.i + br i1 undef, label %bb.i96.i, label %bb1.i102.i + +bb.i96.i: ; preds = %dis.i + br label %getfloder.exit.i + +bb1.i102.i: ; preds = %dis.i + br label %getfloder.exit.i + +getfloder.exit.i: ; preds = %bb1.i102.i, %bb.i96.i + br i1 undef, label %bb7.i.i1615, label %dis.i +} diff --git a/test/CodeGen/Generic/promote-integers.ll b/test/CodeGen/Generic/promote-integers.ll new file mode 100644 index 0000000..5812592 --- /dev/null +++ b/test/CodeGen/Generic/promote-integers.ll @@ -0,0 +1,15 @@ +; Test that vectors are scalarized/lowered correctly. +; RUN: llc -march=x86 -promote-elements < %s | FileCheck %s + +; This test is the poster-child for integer-element-promotion. +; Until this feature is complete, we mark this test as expected to fail. +; XFAIL: * +; CHECK: vector_code +; CHECK: ret +define <4 x float> @vector_code(<4 x i64> %A, <4 x i64> %B, <4 x float> %R0, <4 x float> %R1 ) { + %C = icmp eq <4 x i64> %A, %B + %K = xor <4 x i1> <i1 1, i1 1, i1 1, i1 1>, %C + %D = select <4 x i1> %K, <4 x float> %R1, <4 x float> %R0 + ret <4 x float> %D +} + diff --git a/test/CodeGen/Generic/zero-sized-array.ll b/test/CodeGen/Generic/zero-sized-array.ll new file mode 100644 index 0000000..280ba00 --- /dev/null +++ b/test/CodeGen/Generic/zero-sized-array.ll @@ -0,0 +1,81 @@ +; RUN: llc < %s +; PR9900 + +%zero = type [0 x i8] +%foobar = type { i32, %zero } + +define void @f(%foobar %arg) { + %arg1 = extractvalue %foobar %arg, 0 + %arg2 = extractvalue %foobar %arg, 1 + call i32 @f2(%zero %arg2, i32 5, i32 42) + ret void +} + +define i32 @f2(%zero %x, i32 %y, i32 %z) { + ret i32 %y +} + +define void @f3(%zero %x, i32 %y) { + call i32 @f2(%zero %x, i32 5, i32 %y) + ret void +} + +define void @f4(%zero %z) { + insertvalue %foobar undef, %zero %z, 1 + ret void +} + +define void @f5(%foobar %x) { +allocas: + %y = extractvalue %foobar %x, 1 + br label %b1 + +b1: + %insert120 = insertvalue %foobar undef, %zero %y, 1 + ret void +} + +define void @f6(%zero %x, %zero %y) { +b1: + br i1 undef, label %end, label %b2 + +b2: + br label %end + +end: + %z = phi %zero [ %y, %b1 ], [ %x, %b2 ] + call void @f4(%zero %z) + ret void +} + +%zero2 = type {} + +define i32 @g1(%zero2 %x, i32 %y, i32 %z) { + ret i32 %y +} + +define void @g2(%zero2 %x, i32 %y) { + call i32 @g1(%zero2 %x, i32 5, i32 %y) + ret void +} + +%zero2r = type {%zero2} + +define i32 @h1(%zero2r %x, i32 %y, i32 %z) { + ret i32 %y +} + +define void @h2(%zero2r %x, i32 %y) { + call i32 @h1(%zero2r %x, i32 5, i32 %y) + ret void +} + +%foobar2 = type { i32, %zero2r } + +define void @h3(%foobar2 %arg) { + %arg1 = extractvalue %foobar2 %arg, 0 + %arg2 = extractvalue %foobar2 %arg, 1 + %arg21 = extractvalue %zero2r %arg2, 0 + call void @g2(%zero2 %arg21, i32 5) + ret void +} diff --git a/test/CodeGen/MBlaze/fsl.ll b/test/CodeGen/MBlaze/fsl.ll index f9c6205..5444f82 100644 --- a/test/CodeGen/MBlaze/fsl.ll +++ b/test/CodeGen/MBlaze/fsl.ll @@ -3,7 +3,7 @@ ; dynamic version of the instructions and that constant values use the ; constant version of the instructions. ; -; RUN: llc < %s -march=mblaze | FileCheck %s +; RUN: llc -O3 < %s -march=mblaze | FileCheck %s declare i32 @llvm.mblaze.fsl.get(i32 %port) declare i32 @llvm.mblaze.fsl.aget(i32 %port) @@ -55,8 +55,7 @@ declare void @llvm.mblaze.fsl.tnaput(i32 %port) declare void @llvm.mblaze.fsl.tncput(i32 %port) declare void @llvm.mblaze.fsl.tncaput(i32 %port) -define i32 @fsl_get(i32 %port) -{ +define void @fsl_get(i32 %port) { ; CHECK: fsl_get: %v0 = call i32 @llvm.mblaze.fsl.get(i32 %port) ; CHECK: getd @@ -122,12 +121,11 @@ define i32 @fsl_get(i32 %port) ; CHECK-NEXT: tnecgetd %v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 %port) ; CHECK-NEXT: tnecagetd - ret i32 1 + ret void ; CHECK: rtsd } -define i32 @fslc_get() -{ +define void @fslc_get() { ; CHECK: fslc_get: %v0 = call i32 @llvm.mblaze.fsl.get(i32 1) ; CHECK: get @@ -224,12 +222,11 @@ define i32 @fslc_get() %v31 = call i32 @llvm.mblaze.fsl.tnecaget(i32 1) ; CHECK-NOT: tnecagetd ; CHECK: tnecaget - ret i32 1 + ret void ; CHECK: rtsd } -define void @putfsl(i32 %value, i32 %port) -{ +define void @putfsl(i32 %value, i32 %port) { ; CHECK: putfsl: call void @llvm.mblaze.fsl.put(i32 %value, i32 %port) ; CHECK: putd @@ -267,8 +264,7 @@ define void @putfsl(i32 %value, i32 %port) ; CHECK: rtsd } -define void @putfsl_const(i32 %value) -{ +define void @putfsl_const(i32 %value) { ; CHECK: putfsl_const: call void @llvm.mblaze.fsl.put(i32 %value, i32 1) ; CHECK-NOT: putd diff --git a/test/CodeGen/MBlaze/loop.ll b/test/CodeGen/MBlaze/loop.ll index 8973f75..7439d0b 100644 --- a/test/CodeGen/MBlaze/loop.ll +++ b/test/CodeGen/MBlaze/loop.ll @@ -29,14 +29,12 @@ loop_inner_finish: %inner.5 = add i32 %inner.2, 1 call i32 (i8*,...)* @printf( i8* getelementptr([19 x i8]* @MSG,i32 0,i32 0), i32 %inner.0, i32 %inner.1, i32 %inner.2 ) - ; CHECK: brlid - ; CHECK: addik {{.*, 1}} %inner.6 = icmp eq i32 %inner.5, 100 - ; CHECK: cmp + ; CHECK: cmp [[REG:r[0-9]*]] br i1 %inner.6, label %loop_inner, label %loop_outer_finish - ; CHECK: {{beq|bne}} + ; CHECK: {{beqid|bneid}} [[REG]] loop_outer_finish: %outer.1 = add i32 %outer.0, 1 diff --git a/test/CodeGen/MSP430/Inst8rr.ll b/test/CodeGen/MSP430/Inst8rr.ll index 0f5fc12..45342e2 100644 --- a/test/CodeGen/MSP430/Inst8rr.ll +++ b/test/CodeGen/MSP430/Inst8rr.ll @@ -10,7 +10,7 @@ define i8 @mov(i8 %a, i8 %b) nounwind { define i8 @add(i8 %a, i8 %b) nounwind { ; CHECK: add: -; CHECK: add.b r12, r15 +; CHECK: add.b %1 = add i8 %a, %b ret i8 %1 } diff --git a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll index 41ae5dd..855194a 100644 --- a/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll +++ b/test/CodeGen/Mips/2008-07-16-SignExtInReg.ll @@ -5,13 +5,13 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" -define i8 @A(i8 %e.0, i8 signext %sum) signext nounwind { +define signext i8 @A(i8 %e.0, i8 signext %sum) nounwind { entry: add i8 %sum, %e.0 ; <i8>:0 [#uses=1] ret i8 %0 } -define i16 @B(i16 %e.0, i16 signext %sum) signext nounwind { +define signext i16 @B(i16 %e.0, i16 signext %sum) nounwind { entry: add i16 %sum, %e.0 ; <i16>:0 [#uses=1] ret i16 %0 diff --git a/test/CodeGen/Mips/2008-07-31-fcopysign.ll b/test/CodeGen/Mips/2008-07-31-fcopysign.ll index 47382f9..f152acc 100644 --- a/test/CodeGen/Mips/2008-07-31-fcopysign.ll +++ b/test/CodeGen/Mips/2008-07-31-fcopysign.ll @@ -2,6 +2,10 @@ ; RUN: grep abs.s %t | count 1 ; RUN: grep neg.s %t | count 1 +; FIXME: Should not emit abs.s or neg.s since these instructions produce +; incorrect results if the operand is NaN. +; REQUIRES: disabled + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" target triple = "mipsallegrexel-unknown-psp-elf" diff --git a/test/CodeGen/Mips/2011-05-26-BranchKillsVreg.ll b/test/CodeGen/Mips/2011-05-26-BranchKillsVreg.ll new file mode 100644 index 0000000..1255949 --- /dev/null +++ b/test/CodeGen/Mips/2011-05-26-BranchKillsVreg.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -verify-coalescing +; PR10046 +; +; PHI elimination splits the critical edge from %while.end415 to %if.end427. +; This requires updating the BNE-J terminators to a BEQ. The BNE instruction +; kills a virtual register, and LiveVariables must be updated with the new kill +; instruction. + +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-n32" +target triple = "mips-ellcc-linux" + +define i32 @mergesort(i8* %base, i32 %nmemb, i32 %size, i32 (i8*, i8*)* nocapture %cmp) nounwind { +entry: + br i1 undef, label %return, label %if.end13 + +if.end13: ; preds = %entry + br label %while.body + +while.body: ; preds = %while.body, %if.end13 + %list1.0482 = phi i8* [ %base, %if.end13 ], [ null, %while.body ] + br i1 undef, label %while.end415, label %while.body + +while.end415: ; preds = %while.body + br i1 undef, label %if.then419, label %if.end427 + +if.then419: ; preds = %while.end415 + %call425 = tail call i8* @memmove(i8* %list1.0482, i8* undef, i32 undef) nounwind + br label %if.end427 + +if.end427: ; preds = %if.then419, %while.end415 + %list2.1 = phi i8* [ undef, %if.then419 ], [ %list1.0482, %while.end415 ] + tail call void @free(i8* %list2.1) + unreachable + +return: ; preds = %entry + ret i32 -1 +} + + +declare i8* @memmove(i8*, i8*, i32) + +declare void @free(i8*) + diff --git a/test/CodeGen/Mips/alloca.ll b/test/CodeGen/Mips/alloca.ll new file mode 100644 index 0000000..50eeecf --- /dev/null +++ b/test/CodeGen/Mips/alloca.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s + +define i32 @twoalloca(i32 %size) nounwind { +entry: +; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]] +; CHECK: addu $sp, $zero, $[[T0]] +; CHECK: addu $[[SP1:[0-9]+]], $zero, $sp +; CHECK: subu $[[T1:[0-9]+]], $sp, $[[SZ]] +; CHECK: addu $sp, $zero, $[[T1]] +; CHECK: addu $[[SP2:[0-9]+]], $zero, $sp +; CHECK: lw $25, %call16(foo)($gp) +; CHECK: addiu $4, $[[SP1]], 24 +; CHECK: jalr $25 +; CHECK: lw $25, %call16(foo)($gp) +; CHECK: addiu $4, $[[SP2]], 24 +; CHECK: jalr $25 + %tmp1 = alloca i8, i32 %size, align 4 + %add.ptr = getelementptr inbounds i8* %tmp1, i32 5 + store i8 97, i8* %add.ptr, align 1 + %tmp4 = alloca i8, i32 %size, align 4 + call void @foo2(double 1.000000e+00, double 2.000000e+00, i32 3) nounwind + %call = call i32 @foo(i8* %tmp1) nounwind + %call7 = call i32 @foo(i8* %tmp4) nounwind + %add = add nsw i32 %call7, %call + ret i32 %add +} + +declare void @foo2(double, double, i32) + +declare i32 @foo(i8*) + diff --git a/test/CodeGen/Mips/atomic.ll b/test/CodeGen/Mips/atomic.ll new file mode 100644 index 0000000..2d5555b --- /dev/null +++ b/test/CodeGen/Mips/atomic.ll @@ -0,0 +1,253 @@ +; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s + + +declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind +declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* nocapture, i32) nounwind +declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind +declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind + +declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind +declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind +declare i8 @llvm.atomic.load.nand.i8.p0i8(i8* nocapture, i8) nounwind +declare i8 @llvm.atomic.swap.i8.p0i8(i8* nocapture, i8) nounwind +declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind + + +@x = common global i32 0, align 4 + +define i32 @AtomicLoadAdd32(i32 %incr) nounwind { +entry: + %0 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* @x, i32 %incr) + ret i32 %0 + +; CHECK: AtomicLoadAdd32: +; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: or $2, $zero, $[[R1]] +; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 +; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: beq $[[R2]], $zero, $[[BB0]] +} + +define i32 @AtomicLoadNand32(i32 %incr) nounwind { +entry: + %0 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* @x, i32 %incr) + ret i32 %0 + +; CHECK: AtomicLoadNand32: +; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: or $2, $zero, $[[R1]] +; CHECK: and $[[R1]], $[[R1]], $4 +; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R1]] +; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: beq $[[R2]], $zero, $[[BB0]] +} + +define i32 @AtomicSwap32(i32 %oldval) nounwind { +entry: + %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %oldval) + ret i32 %0 + +; CHECK: AtomicSwap32: +; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: or $2, $zero, $[[R1]] +; CHECK: lw $[[R2:[0-9]+]], [[OFFSET]]($sp) +; CHECK: or $[[R3:[0-9]+]], $zero, $[[R2]] +; CHECK: sc $[[R3]], 0($[[R0]]) +; CHECK: beq $[[R3]], $zero, $[[BB0]] +} + +define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind { +entry: + %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %newval) + ret i32 %0 + +; CHECK: AtomicCmpSwap32: +; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: sw $5, [[OFFSET:[0-9]+]]($sp) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $2, 0($[[R0]]) +; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]] +; CHECK: lw $[[R1:[0-9]+]], [[OFFSET]]($sp) +; CHECK: or $[[R2:[0-9]+]], $zero, $[[R1]] +; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: beq $[[R2]], $zero, $[[BB0]] +; CHECK: $[[BB1]]: +} + + + +@y = common global i8 0, align 1 + +define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { +entry: + %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @y, i8 %incr) + ret i8 %0 + +; CHECK: AtomicLoadAdd8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: andi $[[R8:[0-9]+]], $4, 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) +; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] +; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] +; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: sc $[[R14]], 0($[[R2]]) +; CHECK: beq $[[R14]], $zero, $[[BB0]] + +; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] +; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} + +define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { +entry: + %0 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @y, i8 %incr) + ret i8 %0 + +; CHECK: AtomicLoadSub8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: subu $[[R18:[0-9]+]], $zero, $4 +; CHECK: andi $[[R8:[0-9]+]], $[[R18]], 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) +; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] +; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] +; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: sc $[[R14]], 0($[[R2]]) +; CHECK: beq $[[R14]], $zero, $[[BB0]] + +; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] +; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} + +define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { +entry: + %0 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @y, i8 %incr) + ret i8 %0 + +; CHECK: AtomicLoadNand8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: andi $[[R8:[0-9]+]], $4, 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) +; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]] +; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]] +; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] +; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: sc $[[R14]], 0($[[R2]]) +; CHECK: beq $[[R14]], $zero, $[[BB0]] + +; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] +; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} + +define signext i8 @AtomicSwap8(i8 signext %oldval) nounwind { +entry: + %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %oldval) + ret i8 %0 + +; CHECK: AtomicSwap8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: andi $[[R8:[0-9]+]], $4, 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sw $[[R9]], [[OFFSET:[0-9]+]]($sp) + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) +; CHECK: lw $[[R18:[0-9]+]], [[OFFSET]]($sp) +; CHECK: or $[[R11:[0-9]+]], $zero, $[[R18]] +; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] +; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: sc $[[R14]], 0($[[R2]]) +; CHECK: beq $[[R14]], $zero, $[[BB0]] + +; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] +; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} + +define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind { +entry: + %0 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @y, i8 %oldval, i8 %newval) + ret i8 %0 + +; CHECK: AtomicCmpSwap8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: andi $[[R8:[0-9]+]], $4, 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: andi $[[R10:[0-9]+]], $5, 255 +; CHECK: sll $[[R11:[0-9]+]], $[[R10]], $[[R4]] + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]]) +; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]] +; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]] + +; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]] +; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]] +; CHECK: sc $[[R15]], 0($[[R2]]) +; CHECK: beq $[[R15]], $zero, $[[BB0]] + +; CHECK: $[[BB1]]: +; CHECK: srl $[[R16:[0-9]+]], $[[R13]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} diff --git a/test/CodeGen/Mips/blockaddr.ll b/test/CodeGen/Mips/blockaddr.ll index 2b06314..6de6b77 100644 --- a/test/CodeGen/Mips/blockaddr.ll +++ b/test/CodeGen/Mips/blockaddr.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=mipsel < %s | FileCheck %s +; RUN: llc -march=mipsel -relocation-model=pic < %s | FileCheck %s -check-prefix=CHECK-PIC +; RUN: llc -march=mipsel -relocation-model=static < %s | FileCheck %s -check-prefix=CHECK-STATIC @reg = common global i8* null, align 4 @@ -7,10 +8,14 @@ entry: ret i8* %x } -; CHECK: lw $2, %got($tmp1)($gp) -; CHECK: addiu $4, $2, %lo($tmp1) -; CHECK: lw $2, %got($tmp2)($gp) -; CHECK: addiu $2, $2, %lo($tmp2) +; CHECK-PIC: lw $[[R0:[0-9]+]], %got($tmp[[T0:[0-9]+]])($gp) +; CHECK-PIC: addiu ${{[0-9]+}}, $[[R0]], %lo($tmp[[T0]]) +; CHECK-PIC: lw $[[R1:[0-9]+]], %got($tmp[[T1:[0-9]+]])($gp) +; CHECK-PIC: addiu ${{[0-9]+}}, $[[R1]], %lo($tmp[[T1]]) +; CHECK-STATIC: lui $[[R2:[0-9]+]], %hi($tmp[[T0:[0-9]+]]) +; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R2]], %lo($tmp[[T0]]) +; CHECK-STATIC: lui $[[R3:[0-9]+]], %hi($tmp[[T1:[0-9]+]]) +; CHECK-STATIC: addiu ${{[0-9]+}}, $[[R3]], %lo($tmp[[T1]]) define void @f() nounwind { entry: %call = tail call i8* @dummy(i8* blockaddress(@f, %baz)) diff --git a/test/CodeGen/Mips/buildpairextractelementf64.ll b/test/CodeGen/Mips/buildpairextractelementf64.ll new file mode 100644 index 0000000..585bc25 --- /dev/null +++ b/test/CodeGen/Mips/buildpairextractelementf64.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -march=mipsel | FileCheck %s +; RUN: llc < %s -march=mips | FileCheck %s +@a = external global i32 + +define double @f(i32 %a1, double %d) nounwind { +entry: +; CHECK: mtc1 +; CHECK: mtc1 + store i32 %a1, i32* @a, align 4 + %add = fadd double %d, 2.000000e+00 + ret double %add +} + +define void @f3(double %d, i32 %a1) nounwind { +entry: +; CHECK: mfc1 +; CHECK: mfc1 + tail call void @f2(i32 %a1, double %d) nounwind + ret void +} + +declare void @f2(i32, double) + diff --git a/test/CodeGen/Mips/cmov.ll b/test/CodeGen/Mips/cmov.ll index 8329c89..ec37961 100755 --- a/test/CodeGen/Mips/cmov.ll +++ b/test/CodeGen/Mips/cmov.ll @@ -4,8 +4,8 @@ @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4 @i3 = common global i32* null, align 4 -; CHECK: lw ${{[0-9]+}}, %got(i3)($gp) ; CHECK: addiu ${{[0-9]+}}, $gp, %got(i1) +; CHECK: lw ${{[0-9]+}}, %got(i3)($gp) define i32* @cmov1(i32 %s) nounwind readonly { entry: %tobool = icmp ne i32 %s, 0 @@ -14,3 +14,19 @@ entry: ret i32* %cond } +@c = global i32 1, align 4 +@d = global i32 0, align 4 + +; CHECK: cmov2: +; CHECK: addiu $[[R0:[0-9]+]], $gp, %got(c) +; CHECK: addiu $[[R1:[0-9]+]], $gp, %got(d) +; CHECK: movn $[[R1]], $[[R0]], ${{[0-9]+}} +define i32 @cmov2(i32 %s) nounwind readonly { +entry: + %tobool = icmp ne i32 %s, 0 + %tmp1 = load i32* @c, align 4 + %tmp2 = load i32* @d, align 4 + %cond = select i1 %tobool, i32 %tmp1, i32 %tmp2 + ret i32 %cond +} + diff --git a/test/CodeGen/Mips/double2int.ll b/test/CodeGen/Mips/double2int.ll new file mode 100644 index 0000000..3d033e1 --- /dev/null +++ b/test/CodeGen/Mips/double2int.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +define i32 @f1(double %d) nounwind readnone { +entry: +; CHECK: trunc.w.d $f{{[0-9]+}}, $f12 + %conv = fptosi double %d to i32 + ret i32 %conv +} diff --git a/test/CodeGen/Mips/eh.ll b/test/CodeGen/Mips/eh.ll new file mode 100644 index 0000000..765b778 --- /dev/null +++ b/test/CodeGen/Mips/eh.ll @@ -0,0 +1,78 @@ +; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL +; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB + +@g1 = global double 0.000000e+00, align 8 +@_ZTId = external constant i8* + +define void @_Z1fd(double %i2) { +entry: +; CHECK-EL: addiu $sp, $sp +; CHECK-EL: .cfi_def_cfa_offset +; CHECK-EL: sdc1 $f20 +; CHECK-EL: sw $ra +; CHECK-EL: sw $17 +; CHECK-EL: sw $16 +; CHECK-EL: .cfi_offset 52, -8 +; CHECK-EL: .cfi_offset 53, -4 +; CHECK-EB: .cfi_offset 53, -8 +; CHECK-EB: .cfi_offset 52, -4 +; CHECK-EL: .cfi_offset 31, -12 +; CHECK-EL: .cfi_offset 17, -16 +; CHECK-EL: .cfi_offset 16, -20 +; CHECK-EL: .cprestore + + %exception = tail call i8* @__cxa_allocate_exception(i32 8) nounwind + %0 = bitcast i8* %exception to double* + store double 3.200000e+00, double* %0, align 8, !tbaa !0 + invoke void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTId to i8*), i8* null) noreturn + to label %unreachable unwind label %lpad + +lpad: ; preds = %entry +; CHECK-EL: # %lpad +; CHECK-EL: lw $gp +; CHECK-EL: beq $5 + + %exn = tail call i8* @llvm.eh.exception() nounwind + %eh.selector = tail call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* bitcast (i8** @_ZTId to i8*)) nounwind + %1 = tail call i32 @llvm.eh.typeid.for(i8* bitcast (i8** @_ZTId to i8*)) nounwind + %2 = icmp eq i32 %eh.selector, %1 + br i1 %2, label %catch, label %eh.resume + +catch: ; preds = %lpad + %3 = tail call i8* @__cxa_begin_catch(i8* %exn) nounwind + %4 = bitcast i8* %3 to double* + %exn.scalar = load double* %4, align 8 + %add = fadd double %exn.scalar, %i2 + store double %add, double* @g1, align 8, !tbaa !0 + tail call void @__cxa_end_catch() nounwind + ret void + +eh.resume: ; preds = %lpad + tail call void @llvm.eh.resume(i8* %exn, i32 %eh.selector) noreturn + unreachable + +unreachable: ; preds = %entry + unreachable +} + +declare i8* @__cxa_allocate_exception(i32) + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i32 @__gxx_personality_v0(...) + +declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind + +declare i32 @llvm.eh.typeid.for(i8*) nounwind + +declare void @llvm.eh.resume(i8*, i32) + +declare void @__cxa_throw(i8*, i8*, i8*) + +declare i8* @__cxa_begin_catch(i8*) + +declare void @__cxa_end_catch() + +!0 = metadata !{metadata !"double", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/Mips/fcopysign.ll b/test/CodeGen/Mips/fcopysign.ll new file mode 100644 index 0000000..14c6507 --- /dev/null +++ b/test/CodeGen/Mips/fcopysign.ll @@ -0,0 +1,55 @@ +; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EL +; RUN: llc < %s -march=mips -mcpu=4ke | FileCheck %s -check-prefix=CHECK-EB + +define double @func0(double %d0, double %d1) nounwind readnone { +entry: +; CHECK-EL: func0: +; CHECK-EL: lui $[[T0:[0-9]+]], 32767 +; CHECK-EL: lui $[[T1:[0-9]+]], 32768 +; CHECK-EL: mfc1 $[[HI0:[0-9]+]], $f13 +; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; CHECK-EL: mfc1 $[[HI1:[0-9]+]], $f15 +; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0 +; CHECK-EL: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]] +; CHECK-EL: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]] +; CHECK-EL: mfc1 $[[LO0:[0-9]+]], $f12 +; CHECK-EL: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] +; CHECK-EL: mtc1 $[[LO0]], $f0 +; CHECK-EL: mtc1 $[[OR]], $f1 +; +; CHECK-EB: lui $[[T0:[0-9]+]], 32767 +; CHECK-EB: lui $[[T1:[0-9]+]], 32768 +; CHECK-EB: mfc1 $[[HI0:[0-9]+]], $f12 +; CHECK-EB: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; CHECK-EB: mfc1 $[[HI1:[0-9]+]], $f14 +; CHECK-EB: ori $[[MSK1:[0-9]+]], $[[T1]], 0 +; CHECK-EB: and $[[AND0:[0-9]+]], $[[HI0]], $[[MSK0]] +; CHECK-EB: and $[[AND1:[0-9]+]], $[[HI1]], $[[MSK1]] +; CHECK-EB: or $[[OR:[0-9]+]], $[[AND0]], $[[AND1]] +; CHECK-EB: mfc1 $[[LO0:[0-9]+]], $f13 +; CHECK-EB: mtc1 $[[OR]], $f0 +; CHECK-EB: mtc1 $[[LO0]], $f1 + %call = tail call double @copysign(double %d0, double %d1) nounwind readnone + ret double %call +} + +declare double @copysign(double, double) nounwind readnone + +define float @func1(float %f0, float %f1) nounwind readnone { +entry: +; CHECK-EL: func1: +; CHECK-EL: lui $[[T0:[0-9]+]], 32767 +; CHECK-EL: lui $[[T1:[0-9]+]], 32768 +; CHECK-EL: mfc1 $[[ARG0:[0-9]+]], $f12 +; CHECK-EL: ori $[[MSK0:[0-9]+]], $[[T0]], 65535 +; CHECK-EL: mfc1 $[[ARG1:[0-9]+]], $f14 +; CHECK-EL: ori $[[MSK1:[0-9]+]], $[[T1]], 0 +; CHECK-EL: and $[[T2:[0-9]+]], $[[ARG0]], $[[MSK0]] +; CHECK-EL: and $[[T3:[0-9]+]], $[[ARG1]], $[[MSK1]] +; CHECK-EL: or $[[T4:[0-9]+]], $[[T2]], $[[T3]] +; CHECK-EL: mtc1 $[[T4]], $f0 + %call = tail call float @copysignf(float %f0, float %f1) nounwind readnone + ret float %call +} + +declare float @copysignf(float, float) nounwind readnone diff --git a/test/CodeGen/Mips/frame-address.ll b/test/CodeGen/Mips/frame-address.ll new file mode 100644 index 0000000..c48ce7e --- /dev/null +++ b/test/CodeGen/Mips/frame-address.ll @@ -0,0 +1,12 @@ +; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s + +declare i8* @llvm.frameaddress(i32) nounwind readnone + +define i8* @f() nounwind { +entry: + %0 = call i8* @llvm.frameaddress(i32 0) + ret i8* %0 + +; CHECK: addu $fp, $sp, $zero +; CHECK: addu $2, $zero, $fp +} diff --git a/test/CodeGen/Mips/gprestore.ll b/test/CodeGen/Mips/gprestore.ll new file mode 100644 index 0000000..ee7e131 --- /dev/null +++ b/test/CodeGen/Mips/gprestore.ll @@ -0,0 +1,32 @@ +; RUN: llc -march=mips < %s | FileCheck %s + +@p = external global i32 +@q = external global i32 +@r = external global i32 + +define void @f0() nounwind { +entry: +; CHECK: jalr +; CHECK-NOT: got({{.*}})($gp) +; CHECK: lw $gp +; CHECK: jalr +; CHECK-NOT: got({{.*}})($gp) +; CHECK: lw $gp +; CHECK: jalr +; CHECK-NOT: got({{.*}})($gp) +; CHECK: lw $gp + tail call void (...)* @f1() nounwind + %tmp = load i32* @p, align 4 + tail call void @f2(i32 %tmp) nounwind + %tmp1 = load i32* @q, align 4 + %tmp2 = load i32* @r, align 4 + tail call void @f3(i32 %tmp1, i32 %tmp2) nounwind + ret void +} + +declare void @f1(...) + +declare void @f2(i32) + +declare void @f3(i32, i32) + diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll new file mode 100644 index 0000000..9a30453 --- /dev/null +++ b/test/CodeGen/Mips/i64arg.ll @@ -0,0 +1,34 @@ +; RUN: llc -march=mips -mcpu=4ke < %s | FileCheck %s + +define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { +entry: +; CHECK: addu $[[R1:[0-9]+]], $zero, $5 +; CHECK: addu $[[R0:[0-9]+]], $zero, $4 +; CHECK: lw $25, %call16(ff1) +; CHECK: ori $6, ${{[0-9]+}}, 3855 +; CHECK: ori $7, ${{[0-9]+}}, 22136 +; CHECK: jalr + tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind +; CHECK: lw $25, %call16(ff2) +; CHECK: lw $[[R2:[0-9]+]], 80($sp) +; CHECK: lw $[[R3:[0-9]+]], 84($sp) +; CHECK: addu $4, $zero, $[[R2]] +; CHECK: addu $5, $zero, $[[R3]] +; CHECK: jalr $25 + tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind + %sub = add nsw i32 %i, -1 +; CHECK: sw $[[R0]], 24($sp) +; CHECK: sw $[[R1]], 28($sp) +; CHECK: lw $25, %call16(ff3) +; CHECK: addu $6, $zero, $[[R2]] +; CHECK: addu $7, $zero, $[[R3]] +; CHECK: jalr $25 + tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind + ret void +} + +declare void @ff1(i32, i64) + +declare void @ff2(i64, double) + +declare void @ff3(i32, i64, i32, i64) diff --git a/test/CodeGen/Mips/internalfunc.ll b/test/CodeGen/Mips/internalfunc.ll index fdfa01a..50d0993 100644 --- a/test/CodeGen/Mips/internalfunc.ll +++ b/test/CodeGen/Mips/internalfunc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=mips | FileCheck %s +; RUN: llc < %s -march=mipsel -mcpu=4ke | FileCheck %s @caller.sf1 = internal unnamed_addr global void (...)* null, align 4 @gf1 = external global void (...)* diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll new file mode 100644 index 0000000..fd7ae9e --- /dev/null +++ b/test/CodeGen/Mips/largeimmprinting.ll @@ -0,0 +1,23 @@ +; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s + +%struct.S1 = type { [65536 x i8] } + +@s1 = external global %struct.S1 + +define void @f() nounwind { +entry: +; CHECK: lui $at, 65534 +; CHECK: addu $at, $sp, $at +; CHECK: addiu $sp, $at, -16 +; CHECK: .cprestore 65536 + + %agg.tmp = alloca %struct.S1, align 1 + %tmp = getelementptr inbounds %struct.S1* %agg.tmp, i32 0, i32 0, i32 0 + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp, i8* getelementptr inbounds (%struct.S1* @s1, i32 0, i32 0, i32 0), i32 65536, i32 1, i1 false) + call void @f2(%struct.S1* byval %agg.tmp) nounwind + ret void +} + +declare void @f2(%struct.S1* byval) + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll new file mode 100644 index 0000000..b78c393 --- /dev/null +++ b/test/CodeGen/Mips/o32_cc_byval.ll @@ -0,0 +1,127 @@ +; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s + +%0 = type { i8, i16, i32, i64, double, i32, [4 x i8] } +%struct.S1 = type { i8, i16, i32, i64, double, i32 } +%struct.S2 = type { [4 x i32] } +%struct.S3 = type { i8 } + +@f1.s1 = internal unnamed_addr constant %0 { i8 1, i16 2, i32 3, i64 4, double 5.000000e+00, i32 6, [4 x i8] undef }, align 8 +@f1.s2 = internal unnamed_addr constant %struct.S2 { [4 x i32] [i32 7, i32 8, i32 9, i32 10] }, align 4 + +define void @f1() nounwind { +entry: +; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp) +; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) +; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) +; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) +; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) +; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) +; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) +; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) +; CHECK: sw $[[R2]], 16($sp) +; CHECK: sw $[[R7]], 20($sp) +; CHECK: sw $[[R3]], 24($sp) +; CHECK: sw $[[R4]], 28($sp) +; CHECK: sw $[[R5]], 32($sp) +; CHECK: sw $[[R6]], 36($sp) +; CHECK: lw $6, 0($[[R0]]) +; CHECK: lw $7, 4($[[R0]]) + %agg.tmp10 = alloca %struct.S3, align 4 + call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind + call void @callee2(%struct.S2* byval @f1.s2) nounwind + %tmp11 = getelementptr inbounds %struct.S3* %agg.tmp10, i32 0, i32 0 + store i8 11, i8* %tmp11, align 4 + call void @callee3(float 2.100000e+01, %struct.S3* byval %agg.tmp10, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind + ret void +} + +declare void @callee1(float, %struct.S1* byval) + +declare void @callee2(%struct.S2* byval) + +declare void @callee3(float, %struct.S3* byval, %struct.S1* byval) + +define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { +entry: +; CHECK: addiu $sp, $sp, -56 +; CHECK: sw $6, 64($sp) +; CHECK: sw $7, 68($sp) +; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp) +; CHECK: lw $[[R2:[0-9]+]], 68($sp) +; CHECK: lh $[[R1:[0-9]+]], 66($sp) +; CHECK: lb $[[R0:[0-9]+]], 64($sp) +; CHECK: lw $[[R3:[0-9]+]], 72($sp) +; CHECK: lw $[[R4:[0-9]+]], 76($sp) +; CHECK: lw $4, 88($sp) +; CHECK: sw $[[R3]], 16($sp) +; CHECK: sw $[[R4]], 20($sp) +; CHECK: sw $[[R2]], 24($sp) +; CHECK: sw $[[R1]], 28($sp) +; CHECK: sw $[[R0]], 32($sp) +; CHECK: mfc1 $6, $f[[F0]] + + %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5 + %tmp = load i32* %i2, align 4, !tbaa !0 + %d = getelementptr inbounds %struct.S1* %s1, i32 0, i32 4 + %tmp1 = load double* %d, align 8, !tbaa !3 + %ll = getelementptr inbounds %struct.S1* %s1, i32 0, i32 3 + %tmp2 = load i64* %ll, align 8, !tbaa !4 + %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2 + %tmp3 = load i32* %i, align 4, !tbaa !0 + %s = getelementptr inbounds %struct.S1* %s1, i32 0, i32 1 + %tmp4 = load i16* %s, align 2, !tbaa !5 + %c = getelementptr inbounds %struct.S1* %s1, i32 0, i32 0 + %tmp5 = load i8* %c, align 1, !tbaa !1 + tail call void @callee4(i32 %tmp, double %tmp1, i64 %tmp2, i32 %tmp3, i16 signext %tmp4, i8 signext %tmp5, float %f) nounwind + ret void +} + +declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float) + +define void @f3(%struct.S2* nocapture byval %s2) nounwind { +entry: +; CHECK: addiu $sp, $sp, -56 +; CHECK: sw $4, 56($sp) +; CHECK: sw $5, 60($sp) +; CHECK: sw $6, 64($sp) +; CHECK: sw $7, 68($sp) +; CHECK: lw $[[R0:[0-9]+]], 68($sp) +; CHECK: lw $4, 56($sp) +; CHECK: sw $[[R0]], 24($sp) + + %arrayidx = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 0 + %tmp = load i32* %arrayidx, align 4, !tbaa !0 + %arrayidx2 = getelementptr inbounds %struct.S2* %s2, i32 0, i32 0, i32 3 + %tmp3 = load i32* %arrayidx2, align 4, !tbaa !0 + tail call void @callee4(i32 %tmp, double 2.000000e+00, i64 3, i32 %tmp3, i16 signext 4, i8 signext 5, float 6.000000e+00) nounwind + ret void +} + +define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { +entry: +; CHECK: addiu $sp, $sp, -56 +; CHECK: sw $5, 60($sp) +; CHECK: sw $6, 64($sp) +; CHECK: sw $7, 68($sp) +; CHECK: lw $[[R1:[0-9]+]], 88($sp) +; CHECK: lb $[[R0:[0-9]+]], 60($sp) +; CHECK: lw $4, 68($sp) +; CHECK: sw $[[R1]], 24($sp) +; CHECK: sw $[[R0]], 32($sp) + + %i = getelementptr inbounds %struct.S1* %s1, i32 0, i32 2 + %tmp = load i32* %i, align 4, !tbaa !0 + %i2 = getelementptr inbounds %struct.S1* %s1, i32 0, i32 5 + %tmp1 = load i32* %i2, align 4, !tbaa !0 + %c = getelementptr inbounds %struct.S3* %s3, i32 0, i32 0 + %tmp2 = load i8* %c, align 1, !tbaa !1 + tail call void @callee4(i32 %tmp, double 2.000000e+00, i64 3, i32 %tmp1, i16 signext 4, i8 signext %tmp2, float 6.000000e+00) nounwind + ret void +} + +!0 = metadata !{metadata !"int", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} +!3 = metadata !{metadata !"double", metadata !1} +!4 = metadata !{metadata !"long long", metadata !1} +!5 = metadata !{metadata !"short", metadata !1} diff --git a/test/CodeGen/Mips/o32_cc_vararg.ll b/test/CodeGen/Mips/o32_cc_vararg.ll index 6601d25..14ce04b 100644 --- a/test/CodeGen/Mips/o32_cc_vararg.ll +++ b/test/CodeGen/Mips/o32_cc_vararg.ll @@ -1,12 +1,11 @@ -; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -; RUN: llc -march=mipsel -mcpu=mips2 < %s -regalloc=basic | FileCheck %s +; RUN: llc -march=mipsel -mcpu=mips2 -pre-RA-sched=source < %s | FileCheck %s ; All test functions do the same thing - they return the first variable ; argument. -; All CHECK's do the same thing - they check whether variable arguments from -; registers are placed on correct stack locations, and whether the first +; All CHECK's do the same thing - they check whether variable arguments from +; registers are placed on correct stack locations, and whether the first ; variable argument is returned from the correct stack location. @@ -30,15 +29,15 @@ entry: ret i32 %tmp ; CHECK: va1: -; CHECK: addiu $sp, $sp, -32 -; CHECK: sw $5, 36($sp) -; CHECK: sw $6, 40($sp) -; CHECK: sw $7, 44($sp) -; CHECK: lw $2, 36($sp) +; CHECK: addiu $sp, $sp, -16 +; CHECK: sw $7, 28($sp) +; CHECK: sw $6, 24($sp) +; CHECK: sw $5, 20($sp) +; CHECK: lw $2, 20($sp) } -; check whether the variable double argument will be accessed from the 8-byte -; aligned location (i.e. whether the address is computed by adding 7 and +; check whether the variable double argument will be accessed from the 8-byte +; aligned location (i.e. whether the address is computed by adding 7 and ; clearing lower 3 bits) define double @va2(i32 %a, ...) nounwind { entry: @@ -56,11 +55,11 @@ entry: ret double %tmp ; CHECK: va2: -; CHECK: addiu $sp, $sp, -40 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 44 -; CHECK: sw $5, 44($sp) -; CHECK: sw $6, 48($sp) -; CHECK: sw $7, 52($sp) +; CHECK: addiu $sp, $sp, -16 +; CHECK: sw $7, 28($sp) +; CHECK: sw $6, 24($sp) +; CHECK: sw $5, 20($sp) +; CHECK: addiu $[[R0:[0-9]+]], $sp, 20 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] @@ -84,10 +83,10 @@ entry: ret i32 %tmp ; CHECK: va3: -; CHECK: addiu $sp, $sp, -40 -; CHECK: sw $6, 48($sp) -; CHECK: sw $7, 52($sp) -; CHECK: lw $2, 48($sp) +; CHECK: addiu $sp, $sp, -16 +; CHECK: sw $7, 28($sp) +; CHECK: sw $6, 24($sp) +; CHECK: lw $2, 24($sp) } ; double @@ -107,14 +106,11 @@ entry: ret double %tmp ; CHECK: va4: -; CHECK: addiu $sp, $sp, -48 -; CHECK: sw $6, 56($sp) -; CHECK: sw $7, 60($sp) -; CHECK: addiu $[[R0:[0-9]+]], $sp, 56 -; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 -; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 -; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] -; CHECK: ldc1 $f0, 0($[[R3]]) +; CHECK: addiu $sp, $sp, -24 +; CHECK: sw $7, 36($sp) +; CHECK: sw $6, 32($sp) +; CHECK: addiu ${{[0-9]+}}, $sp, 32 +; CHECK: ldc1 $f0, 32($sp) } ; int @@ -138,9 +134,9 @@ entry: ret i32 %tmp ; CHECK: va5: -; CHECK: addiu $sp, $sp, -40 -; CHECK: sw $7, 52($sp) -; CHECK: lw $2, 52($sp) +; CHECK: addiu $sp, $sp, -24 +; CHECK: sw $7, 36($sp) +; CHECK: lw $2, 36($sp) } ; double @@ -164,9 +160,9 @@ entry: ret double %tmp ; CHECK: va6: -; CHECK: addiu $sp, $sp, -48 -; CHECK: sw $7, 60($sp) -; CHECK: addiu $[[R0:[0-9]+]], $sp, 60 +; CHECK: addiu $sp, $sp, -24 +; CHECK: sw $7, 36($sp) +; CHECK: addiu $[[R0:[0-9]+]], $sp, 36 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] @@ -192,8 +188,8 @@ entry: ret i32 %tmp ; CHECK: va7: -; CHECK: addiu $sp, $sp, -40 -; CHECK: lw $2, 56($sp) +; CHECK: addiu $sp, $sp, -24 +; CHECK: lw $2, 40($sp) } ; double @@ -215,12 +211,9 @@ entry: ret double %tmp ; CHECK: va8: -; CHECK: addiu $sp, $sp, -48 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 64 -; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 -; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 -; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] -; CHECK: ldc1 $f0, 0($[[R3]]) +; CHECK: addiu $sp, $sp, -32 +; CHECK: addiu ${{[0-9]+}}, $sp, 48 +; CHECK: ldc1 $f0, 48($sp) } ; int @@ -244,8 +237,8 @@ entry: ret i32 %tmp ; CHECK: va9: -; CHECK: addiu $sp, $sp, -56 -; CHECK: lw $2, 76($sp) +; CHECK: addiu $sp, $sp, -32 +; CHECK: lw $2, 52($sp) } ; double @@ -269,8 +262,8 @@ entry: ret double %tmp ; CHECK: va10: -; CHECK: addiu $sp, $sp, -56 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 76 +; CHECK: addiu $sp, $sp, -32 +; CHECK: addiu $[[R0:[0-9]+]], $sp, 52 ; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7 ; CHECK: addiu $[[R2:[0-9]+]], $zero, -8 ; CHECK: and $[[R3:[0-9]+]], $[[R1]], $[[R2]] diff --git a/test/CodeGen/Mips/tls.ll b/test/CodeGen/Mips/tls.ll new file mode 100644 index 0000000..034738b --- /dev/null +++ b/test/CodeGen/Mips/tls.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \ +; RUN: | FileCheck %s -check-prefix=STATIC + + +@t1 = thread_local global i32 0, align 4 + +define i32 @f1() nounwind { +entry: + %tmp = load i32* @t1, align 4 + ret i32 %tmp + +; CHECK: f1: + +; PIC: lw $25, %call16(__tls_get_addr)($gp) +; PIC: addiu $4, $gp, %tlsgd(t1) +; PIC: jalr $25 +; PIC: lw $2, 0($2) + +; STATIC: rdhwr $3, $29 +; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1) +; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1) +; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]] +; STATIC: lw $2, 0($[[R2]]) +} + + +@t2 = external thread_local global i32 + +define i32 @f2() nounwind { +entry: + %tmp = load i32* @t2, align 4 + ret i32 %tmp + +; CHECK: f2: + +; PIC: lw $25, %call16(__tls_get_addr)($gp) +; PIC: addiu $4, $gp, %tlsgd(t2) +; PIC: jalr $25 +; PIC: lw $2, 0($2) + +; STATIC: rdhwr $3, $29 +; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp) +; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]] +; STATIC: lw $2, 0($[[R1]]) +} diff --git a/test/CodeGen/Mips/weak.ll b/test/CodeGen/Mips/weak.ll new file mode 100644 index 0000000..09dd2a4 --- /dev/null +++ b/test/CodeGen/Mips/weak.ll @@ -0,0 +1,12 @@ +; RUN: llc -march=mips < %s | FileCheck %s + +@t = common global i32 (...)* null, align 4 + +define void @f() nounwind { +entry: + store i32 (...)* @test_weak, i32 (...)** @t, align 4 + ret void +} + +; CHECK: .weak test_weak +declare extern_weak i32 @test_weak(...) diff --git a/test/CodeGen/PTX/add.ll b/test/CodeGen/PTX/add.ll index 598591c..b89a2f6 100644 --- a/test/CodeGen/PTX/add.ll +++ b/test/CodeGen/PTX/add.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device i16 @t1_u16(i16 %x, i16 %y) { ; CHECK: add.u16 rh0, rh1, rh2; @@ -22,14 +22,14 @@ define ptx_device i64 @t1_u64(i64 %x, i64 %y) { } define ptx_device float @t1_f32(float %x, float %y) { -; CHECK: add.f32 f0, f1, f2 +; CHECK: add.f32 r0, r1, r2 ; CHECK-NEXT: ret; %z = fadd float %x, %y ret float %z } define ptx_device double @t1_f64(double %x, double %y) { -; CHECK: add.f64 fd0, fd1, fd2 +; CHECK: add.f64 rd0, rd1, rd2 ; CHECK-NEXT: ret; %z = fadd double %x, %y ret double %z @@ -57,14 +57,14 @@ define ptx_device i64 @t2_u64(i64 %x) { } define ptx_device float @t2_f32(float %x) { -; CHECK: add.f32 f0, f1, 0F3F800000; +; CHECK: add.f32 r0, r1, 0F3F800000; ; CHECK-NEXT: ret; %z = fadd float %x, 1.0 ret float %z } define ptx_device double @t2_f64(double %x) { -; CHECK: add.f64 fd0, fd1, 0D3FF0000000000000; +; CHECK: add.f64 rd0, rd1, 0D3FF0000000000000; ; CHECK-NEXT: ret; %z = fadd double %x, 1.0 ret double %z diff --git a/test/CodeGen/PTX/bitwise.ll b/test/CodeGen/PTX/bitwise.ll new file mode 100644 index 0000000..dbc77e5 --- /dev/null +++ b/test/CodeGen/PTX/bitwise.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +; preds + +define ptx_device i32 @t1_and_preds(i1 %x, i1 %y) { +; CHECK: and.pred p0, p1, p2 + %c = and i1 %x, %y + %d = zext i1 %c to i32 + ret i32 %d +} + +define ptx_device i32 @t1_or_preds(i1 %x, i1 %y) { +; CHECK: or.pred p0, p1, p2 + %a = or i1 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} + +define ptx_device i32 @t1_xor_preds(i1 %x, i1 %y) { +; CHECK: xor.pred p0, p1, p2 + %a = xor i1 %x, %y + %b = zext i1 %a to i32 + ret i32 %b +} diff --git a/test/CodeGen/PTX/bra.ll b/test/CodeGen/PTX/bra.ll index 0506a99..49383eb 100644 --- a/test/CodeGen/PTX/bra.ll +++ b/test/CodeGen/PTX/bra.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device void @test_bra_direct() { ; CHECK: bra $L__BB0_1; diff --git a/test/CodeGen/PTX/cvt.ll b/test/CodeGen/PTX/cvt.ll new file mode 100644 index 0000000..984cb4d --- /dev/null +++ b/test/CodeGen/PTX/cvt.ll @@ -0,0 +1,234 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +; preds +; (note: we convert back to i32 to return) + +define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) { +; CHECK: cvt.pred.u16 p0, rh1; +; CHECK: ret; + %a = trunc i16 %x to i1 + %b = and i1 %a, %y + %c = zext i1 %b to i32 + ret i32 %c +} + +define ptx_device i32 @cvt_pred_i32(i32 %x, i1 %y) { +; CHECK: cvt.pred.u32 p0, r1; +; CHECK: ret; + %a = trunc i32 %x to i1 + %b = and i1 %a, %y + %c = zext i1 %b to i32 + ret i32 %c +} + +define ptx_device i32 @cvt_pred_i64(i64 %x, i1 %y) { +; CHECK: cvt.pred.u64 p0, rd1; +; CHECK: ret; + %a = trunc i64 %x to i1 + %b = and i1 %a, %y + %c = zext i1 %b to i32 + ret i32 %c +} + +define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) { +; CHECK: cvt.rni.pred.f32 p0, r1; +; CHECK: ret; + %a = fptoui float %x to i1 + %b = and i1 %a, %y + %c = zext i1 %b to i32 + ret i32 %c +} + +define ptx_device i32 @cvt_pred_f64(double %x, i1 %y) { +; CHECK: cvt.rni.pred.f64 p0, rd1; +; CHECK: ret; + %a = fptoui double %x to i1 + %b = and i1 %a, %y + %c = zext i1 %b to i32 + ret i32 %c +} + +; i16 + +define ptx_device i16 @cvt_i16_preds(i1 %x) { +; CHECK: cvt.u16.pred rh0, p1; +; CHECK: ret; + %a = zext i1 %x to i16 + ret i16 %a +} + +define ptx_device i16 @cvt_i16_i32(i32 %x) { +; CHECK: cvt.u16.u32 rh0, r1; +; CHECK: ret; + %a = trunc i32 %x to i16 + ret i16 %a +} + +define ptx_device i16 @cvt_i16_i64(i64 %x) { +; CHECK: cvt.u16.u64 rh0, rd1; +; CHECK: ret; + %a = trunc i64 %x to i16 + ret i16 %a +} + +define ptx_device i16 @cvt_i16_f32(float %x) { +; CHECK: cvt.rni.u16.f32 rh0, r1; +; CHECK: ret; + %a = fptoui float %x to i16 + ret i16 %a +} + +define ptx_device i16 @cvt_i16_f64(double %x) { +; CHECK: cvt.rni.u16.f64 rh0, rd1; +; CHECK: ret; + %a = fptoui double %x to i16 + ret i16 %a +} + +; i32 + +define ptx_device i32 @cvt_i32_preds(i1 %x) { +; CHECK: cvt.u32.pred r0, p1; +; CHECK: ret; + %a = zext i1 %x to i32 + ret i32 %a +} + +define ptx_device i32 @cvt_i32_i16(i16 %x) { +; CHECK: cvt.u32.u16 r0, rh1; +; CHECK: ret; + %a = zext i16 %x to i32 + ret i32 %a +} + +define ptx_device i32 @cvt_i32_i64(i64 %x) { +; CHECK: cvt.u32.u64 r0, rd1; +; CHECK: ret; + %a = trunc i64 %x to i32 + ret i32 %a +} + +define ptx_device i32 @cvt_i32_f32(float %x) { +; CHECK: cvt.rni.u32.f32 r0, r1; +; CHECK: ret; + %a = fptoui float %x to i32 + ret i32 %a +} + +define ptx_device i32 @cvt_i32_f64(double %x) { +; CHECK: cvt.rni.u32.f64 r0, rd1; +; CHECK: ret; + %a = fptoui double %x to i32 + ret i32 %a +} + +; i64 + +define ptx_device i64 @cvt_i64_preds(i1 %x) { +; CHECK: cvt.u64.pred rd0, p1; +; CHECK: ret; + %a = zext i1 %x to i64 + ret i64 %a +} + +define ptx_device i64 @cvt_i64_i16(i16 %x) { +; CHECK: cvt.u64.u16 rd0, rh1; +; CHECK: ret; + %a = zext i16 %x to i64 + ret i64 %a +} + +define ptx_device i64 @cvt_i64_i32(i32 %x) { +; CHECK: cvt.u64.u32 rd0, r1; +; CHECK: ret; + %a = zext i32 %x to i64 + ret i64 %a +} + +define ptx_device i64 @cvt_i64_f32(float %x) { +; CHECK: cvt.rni.u64.f32 rd0, r1; +; CHECK: ret; + %a = fptoui float %x to i64 + ret i64 %a +} + +define ptx_device i64 @cvt_i64_f64(double %x) { +; CHECK: cvt.rni.u64.f64 rd0, rd1; +; CHECK: ret; + %a = fptoui double %x to i64 + ret i64 %a +} + +; f32 + +define ptx_device float @cvt_f32_preds(i1 %x) { +; CHECK: cvt.rn.f32.pred r0, p1; +; CHECK: ret; + %a = uitofp i1 %x to float + ret float %a +} + +define ptx_device float @cvt_f32_i16(i16 %x) { +; CHECK: cvt.rn.f32.u16 r0, rh1; +; CHECK: ret; + %a = uitofp i16 %x to float + ret float %a +} + +define ptx_device float @cvt_f32_i32(i32 %x) { +; CHECK: cvt.rn.f32.u32 r0, r1; +; CHECK: ret; + %a = uitofp i32 %x to float + ret float %a +} + +define ptx_device float @cvt_f32_i64(i64 %x) { +; CHECK: cvt.rn.f32.u64 r0, rd1; +; CHECK: ret; + %a = uitofp i64 %x to float + ret float %a +} + +define ptx_device float @cvt_f32_f64(double %x) { +; CHECK: cvt.rn.f32.f64 r0, rd1; +; CHECK: ret; + %a = fptrunc double %x to float + ret float %a +} + +; f64 + +define ptx_device double @cvt_f64_preds(i1 %x) { +; CHECK: cvt.rn.f64.pred rd0, p1; +; CHECK: ret; + %a = uitofp i1 %x to double + ret double %a +} + +define ptx_device double @cvt_f64_i16(i16 %x) { +; CHECK: cvt.rn.f64.u16 rd0, rh1; +; CHECK: ret; + %a = uitofp i16 %x to double + ret double %a +} + +define ptx_device double @cvt_f64_i32(i32 %x) { +; CHECK: cvt.rn.f64.u32 rd0, r1; +; CHECK: ret; + %a = uitofp i32 %x to double + ret double %a +} + +define ptx_device double @cvt_f64_i64(i64 %x) { +; CHECK: cvt.rn.f64.u64 rd0, rd1; +; CHECK: ret; + %a = uitofp i64 %x to double + ret double %a +} + +define ptx_device double @cvt_f64_f32(float %x) { +; CHECK: cvt.f64.f32 rd0, r1; +; CHECK: ret; + %a = fpext float %x to double + ret double %a +} diff --git a/test/CodeGen/PTX/exit.ll b/test/CodeGen/PTX/exit.ll index 4071bab..7816c80 100644 --- a/test/CodeGen/PTX/exit.ll +++ b/test/CodeGen/PTX/exit.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_kernel void @t1() { ; CHECK: exit; diff --git a/test/CodeGen/PTX/fdiv-sm10.ll b/test/CodeGen/PTX/fdiv-sm10.ll index 42f615d..9aff251 100644 --- a/test/CodeGen/PTX/fdiv-sm10.ll +++ b/test/CodeGen/PTX/fdiv-sm10.ll @@ -1,14 +1,14 @@ -; RUN: llc < %s -march=ptx -mattr=+sm10 | FileCheck %s +; RUN: llc < %s -march=ptx32 -mattr=+sm10 | FileCheck %s define ptx_device float @t1_f32(float %x, float %y) { -; CHECK: div.approx.f32 f0, f1, f2; +; CHECK: div.approx.f32 r0, r1, r2; ; CHECK-NEXT: ret; %a = fdiv float %x, %y ret float %a } define ptx_device double @t1_f64(double %x, double %y) { -; CHECK: div.f64 fd0, fd1, fd2; +; CHECK: div.f64 rd0, rd1, rd2; ; CHECK-NEXT: ret; %a = fdiv double %x, %y ret double %a diff --git a/test/CodeGen/PTX/fdiv-sm13.ll b/test/CodeGen/PTX/fdiv-sm13.ll index eb20f78..84e0ada 100644 --- a/test/CodeGen/PTX/fdiv-sm13.ll +++ b/test/CodeGen/PTX/fdiv-sm13.ll @@ -1,14 +1,14 @@ -; RUN: llc < %s -march=ptx -mattr=+sm13 | FileCheck %s +; RUN: llc < %s -march=ptx32 -mattr=+sm13 | FileCheck %s define ptx_device float @t1_f32(float %x, float %y) { -; CHECK: div.approx.f32 f0, f1, f2; +; CHECK: div.approx.f32 r0, r1, r2; ; CHECK-NEXT: ret; %a = fdiv float %x, %y ret float %a } define ptx_device double @t1_f64(double %x, double %y) { -; CHECK: div.rn.f64 fd0, fd1, fd2; +; CHECK: div.rn.f64 rd0, rd1, rd2; ; CHECK-NEXT: ret; %a = fdiv double %x, %y ret double %a diff --git a/test/CodeGen/PTX/fneg.ll b/test/CodeGen/PTX/fneg.ll new file mode 100644 index 0000000..185c37c --- /dev/null +++ b/test/CodeGen/PTX/fneg.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +define ptx_device float @t1_f32(float %x) { +; CHECK: neg.f32 r0, r1; +; CHECK-NEXT: ret; + %y = fsub float -0.000000e+00, %x + ret float %y +} + +define ptx_device double @t1_f64(double %x) { +; CHECK: neg.f64 rd0, rd1; +; CHECK-NEXT: ret; + %y = fsub double -0.000000e+00, %x + ret double %y +} diff --git a/test/CodeGen/PTX/intrinsic.ll b/test/CodeGen/PTX/intrinsic.ll index 7405dd6..cea4182 100644 --- a/test/CodeGen/PTX/intrinsic.ll +++ b/test/CodeGen/PTX/intrinsic.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx -mattr=+ptx20,+sm20 | FileCheck %s +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | FileCheck %s define ptx_device i32 @test_tid_x() { ; CHECK: mov.u32 r0, %tid.x; diff --git a/test/CodeGen/PTX/ld.ll b/test/CodeGen/PTX/ld.ll index 1119aa4..9b75998 100644 --- a/test/CodeGen/PTX/ld.ll +++ b/test/CodeGen/PTX/ld.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s ;CHECK: .extern .global .b8 array_i16[20]; @array_i16 = external global [10 x i16] @@ -64,7 +64,7 @@ define ptx_device i16 @t1_u16(i16* %p) { entry: ;CHECK: ld.global.u16 rh0, [r1]; -;CHECK-NEXT; ret; +;CHECK-NEXT: ret; %x = load i16* %p ret i16 %x } @@ -87,7 +87,7 @@ entry: define ptx_device float @t1_f32(float* %p) { entry: -;CHECK: ld.global.f32 f0, [r1]; +;CHECK: ld.global.f32 r0, [r1]; ;CHECK-NEXT: ret; %x = load float* %p ret float %x @@ -95,7 +95,7 @@ entry: define ptx_device double @t1_f64(double* %p) { entry: -;CHECK: ld.global.f64 fd0, [r1]; +;CHECK: ld.global.f64 rd0, [r1]; ;CHECK-NEXT: ret; %x = load double* %p ret double %x @@ -130,7 +130,7 @@ entry: define ptx_device float @t2_f32(float* %p) { entry: -;CHECK: ld.global.f32 f0, [r1+4]; +;CHECK: ld.global.f32 r0, [r1+4]; ;CHECK-NEXT: ret; %i = getelementptr float* %p, i32 1 %x = load float* %i @@ -139,7 +139,7 @@ entry: define ptx_device double @t2_f64(double* %p) { entry: -;CHECK: ld.global.f64 fd0, [r1+8]; +;CHECK: ld.global.f64 rd0, [r1+8]; ;CHECK-NEXT: ret; %i = getelementptr double* %p, i32 1 %x = load double* %i @@ -180,7 +180,7 @@ define ptx_device float @t3_f32(float* %p, i32 %q) { entry: ;CHECK: shl.b32 r0, r2, 2; ;CHECK-NEXT: add.u32 r0, r1, r0; -;CHECK-NEXT: ld.global.f32 f0, [r0]; +;CHECK-NEXT: ld.global.f32 r0, [r0]; %i = getelementptr float* %p, i32 %q %x = load float* %i ret float %x @@ -190,7 +190,7 @@ define ptx_device double @t3_f64(double* %p, i32 %q) { entry: ;CHECK: shl.b32 r0, r2, 3; ;CHECK-NEXT: add.u32 r0, r1, r0; -;CHECK-NEXT: ld.global.f64 fd0, [r0]; +;CHECK-NEXT: ld.global.f64 rd0, [r0]; %i = getelementptr double* %p, i32 %q %x = load double* %i ret double %x @@ -229,7 +229,7 @@ entry: define ptx_device float @t4_global_f32() { entry: ;CHECK: mov.u32 r0, array_float; -;CHECK-NEXT: ld.global.f32 f0, [r0]; +;CHECK-NEXT: ld.global.f32 r0, [r0]; ;CHECK-NEXT: ret; %i = getelementptr [10 x float]* @array_float, i32 0, i32 0 %x = load float* %i @@ -239,7 +239,7 @@ entry: define ptx_device double @t4_global_f64() { entry: ;CHECK: mov.u32 r0, array_double; -;CHECK-NEXT: ld.global.f64 fd0, [r0]; +;CHECK-NEXT: ld.global.f64 rd0, [r0]; ;CHECK-NEXT: ret; %i = getelementptr [10 x double]* @array_double, i32 0, i32 0 %x = load double* %i @@ -279,7 +279,7 @@ entry: define ptx_device float @t4_const_f32() { entry: ;CHECK: mov.u32 r0, array_constant_float; -;CHECK-NEXT: ld.const.f32 f0, [r0]; +;CHECK-NEXT: ld.const.f32 r0, [r0]; ;CHECK-NEXT: ret; %i = getelementptr [10 x float] addrspace(1)* @array_constant_float, i32 0, i32 0 %x = load float addrspace(1)* %i @@ -289,7 +289,7 @@ entry: define ptx_device double @t4_const_f64() { entry: ;CHECK: mov.u32 r0, array_constant_double; -;CHECK-NEXT: ld.const.f64 fd0, [r0]; +;CHECK-NEXT: ld.const.f64 rd0, [r0]; ;CHECK-NEXT: ret; %i = getelementptr [10 x double] addrspace(1)* @array_constant_double, i32 0, i32 0 %x = load double addrspace(1)* %i @@ -329,7 +329,7 @@ entry: define ptx_device float @t4_local_f32() { entry: ;CHECK: mov.u32 r0, array_local_float; -;CHECK-NEXT: ld.local.f32 f0, [r0]; +;CHECK-NEXT: ld.local.f32 r0, [r0]; ;CHECK-NEXT: ret; %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0 %x = load float addrspace(2)* %i @@ -339,7 +339,7 @@ entry: define ptx_device double @t4_local_f64() { entry: ;CHECK: mov.u32 r0, array_local_double; -;CHECK-NEXT: ld.local.f64 fd0, [r0]; +;CHECK-NEXT: ld.local.f64 rd0, [r0]; ;CHECK-NEXT: ret; %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0 %x = load double addrspace(2)* %i @@ -379,7 +379,7 @@ entry: define ptx_device float @t4_shared_f32() { entry: ;CHECK: mov.u32 r0, array_shared_float; -;CHECK-NEXT: ld.shared.f32 f0, [r0]; +;CHECK-NEXT: ld.shared.f32 r0, [r0]; ;CHECK-NEXT: ret; %i = getelementptr [10 x float] addrspace(4)* @array_shared_float, i32 0, i32 0 %x = load float addrspace(4)* %i @@ -389,7 +389,7 @@ entry: define ptx_device double @t4_shared_f64() { entry: ;CHECK: mov.u32 r0, array_shared_double; -;CHECK-NEXT: ld.shared.f64 fd0, [r0]; +;CHECK-NEXT: ld.shared.f64 rd0, [r0]; ;CHECK-NEXT: ret; %i = getelementptr [10 x double] addrspace(4)* @array_shared_double, i32 0, i32 0 %x = load double addrspace(4)* %i @@ -429,7 +429,7 @@ entry: define ptx_device float @t5_f32() { entry: ;CHECK: mov.u32 r0, array_float; -;CHECK-NEXT: ld.global.f32 f0, [r0+4]; +;CHECK-NEXT: ld.global.f32 r0, [r0+4]; ;CHECK-NEXT: ret; %i = getelementptr [10 x float]* @array_float, i32 0, i32 1 %x = load float* %i @@ -439,7 +439,7 @@ entry: define ptx_device double @t5_f64() { entry: ;CHECK: mov.u32 r0, array_double; -;CHECK-NEXT: ld.global.f64 fd0, [r0+8]; +;CHECK-NEXT: ld.global.f64 rd0, [r0+8]; ;CHECK-NEXT: ret; %i = getelementptr [10 x double]* @array_double, i32 0, i32 1 %x = load double* %i diff --git a/test/CodeGen/PTX/llvm-intrinsic.ll b/test/CodeGen/PTX/llvm-intrinsic.ll index 3ce4c29..a317645 100644 --- a/test/CodeGen/PTX/llvm-intrinsic.ll +++ b/test/CodeGen/PTX/llvm-intrinsic.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=ptx -mattr=+ptx20,+sm20 | FileCheck %s +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | FileCheck %s define ptx_device float @test_sqrt_f32(float %x) { entry: -; CHECK: sqrt.rn.f32 f0, f1; +; CHECK: sqrt.rn.f32 r0, r1; ; CHECK-NEXT: ret; %y = call float @llvm.sqrt.f32(float %x) ret float %y @@ -10,7 +10,7 @@ entry: define ptx_device double @test_sqrt_f64(double %x) { entry: -; CHECK: sqrt.rn.f64 fd0, fd1; +; CHECK: sqrt.rn.f64 rd0, rd1; ; CHECK-NEXT: ret; %y = call double @llvm.sqrt.f64(double %x) ret double %y @@ -18,7 +18,7 @@ entry: define ptx_device float @test_sin_f32(float %x) { entry: -; CHECK: sin.approx.f32 f0, f1; +; CHECK: sin.approx.f32 r0, r1; ; CHECK-NEXT: ret; %y = call float @llvm.sin.f32(float %x) ret float %y @@ -26,7 +26,7 @@ entry: define ptx_device double @test_sin_f64(double %x) { entry: -; CHECK: sin.approx.f64 fd0, fd1; +; CHECK: sin.approx.f64 rd0, rd1; ; CHECK-NEXT: ret; %y = call double @llvm.sin.f64(double %x) ret double %y @@ -34,7 +34,7 @@ entry: define ptx_device float @test_cos_f32(float %x) { entry: -; CHECK: cos.approx.f32 f0, f1; +; CHECK: cos.approx.f32 r0, r1; ; CHECK-NEXT: ret; %y = call float @llvm.cos.f32(float %x) ret float %y @@ -42,7 +42,7 @@ entry: define ptx_device double @test_cos_f64(double %x) { entry: -; CHECK: cos.approx.f64 fd0, fd1; +; CHECK: cos.approx.f64 rd0, rd1; ; CHECK-NEXT: ret; %y = call double @llvm.cos.f64(double %x) ret double %y diff --git a/test/CodeGen/PTX/mad-disabling.ll b/test/CodeGen/PTX/mad-disabling.ll new file mode 100644 index 0000000..ad7b341 --- /dev/null +++ b/test/CodeGen/PTX/mad-disabling.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | grep "mad" +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20,+no-fma | grep -v "mad" + +define ptx_device float @test_mul_add_f(float %x, float %y, float %z) { +entry: + %a = fmul float %x, %y + %b = fadd float %a, %z + ret float %b +} + +define ptx_device double @test_mul_add_d(double %x, double %y, double %z) { +entry: + %a = fmul double %x, %y + %b = fadd double %a, %z + ret double %b +} diff --git a/test/CodeGen/PTX/mad.ll b/test/CodeGen/PTX/mad.ll index 786345b..56d3811 100644 --- a/test/CodeGen/PTX/mad.ll +++ b/test/CodeGen/PTX/mad.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=ptx -mattr=+sm13 | FileCheck %s +; RUN: llc < %s -march=ptx32 -mattr=+sm13 | FileCheck %s define ptx_device float @t1_f32(float %x, float %y, float %z) { -; CHECK: mad.rn.f32 f0, f1, f2, f3; +; CHECK: mad.rn.f32 r0, r1, r2, r3; ; CHECK-NEXT: ret; %a = fmul float %x, %y %b = fadd float %a, %z @@ -9,7 +9,7 @@ define ptx_device float @t1_f32(float %x, float %y, float %z) { } define ptx_device double @t1_f64(double %x, double %y, double %z) { -; CHECK: mad.rn.f64 fd0, fd1, fd2, fd3; +; CHECK: mad.rn.f64 rd0, rd1, rd2, rd3; ; CHECK-NEXT: ret; %a = fmul double %x, %y %b = fadd double %a, %z diff --git a/test/CodeGen/PTX/mov.ll b/test/CodeGen/PTX/mov.ll index 00dcf19..05ce4c0 100644 --- a/test/CodeGen/PTX/mov.ll +++ b/test/CodeGen/PTX/mov.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device i16 @t1_u16() { ; CHECK: mov.u16 rh0, 0; @@ -19,13 +19,13 @@ define ptx_device i64 @t1_u64() { } define ptx_device float @t1_f32() { -; CHECK: mov.f32 f0, 0F00000000; +; CHECK: mov.f32 r0, 0F00000000; ; CHECK: ret; ret float 0.0 } define ptx_device double @t1_f64() { -; CHECK: mov.f64 fd0, 0D0000000000000000; +; CHECK: mov.f64 rd0, 0D0000000000000000; ; CHECK: ret; ret double 0.0 } @@ -49,13 +49,13 @@ define ptx_device i64 @t2_u64(i64 %x) { } define ptx_device float @t3_f32(float %x) { -; CHECK: mov.f32 f0, f1; +; CHECK: mov.u32 r0, r1; ; CHECK-NEXT: ret; ret float %x } define ptx_device double @t3_f64(double %x) { -; CHECK: mov.f64 fd0, fd1; +; CHECK: mov.u64 rd0, rd1; ; CHECK-NEXT: ret; ret double %x } diff --git a/test/CodeGen/PTX/mul.ll b/test/CodeGen/PTX/mul.ll index fd0788f..93f94e3 100644 --- a/test/CodeGen/PTX/mul.ll +++ b/test/CodeGen/PTX/mul.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s ;define ptx_device i32 @t1(i32 %x, i32 %y) { ; %z = mul i32 %x, %y @@ -11,28 +11,28 @@ ;} define ptx_device float @t1_f32(float %x, float %y) { -; CHECK: mul.f32 f0, f1, f2 +; CHECK: mul.f32 r0, r1, r2 ; CHECK-NEXT: ret; %z = fmul float %x, %y ret float %z } define ptx_device double @t1_f64(double %x, double %y) { -; CHECK: mul.f64 fd0, fd1, fd2 +; CHECK: mul.f64 rd0, rd1, rd2 ; CHECK-NEXT: ret; %z = fmul double %x, %y ret double %z } define ptx_device float @t2_f32(float %x) { -; CHECK: mul.f32 f0, f1, 0F40A00000; +; CHECK: mul.f32 r0, r1, 0F40A00000; ; CHECK-NEXT: ret; %z = fmul float %x, 5.0 ret float %z } define ptx_device double @t2_f64(double %x) { -; CHECK: mul.f64 fd0, fd1, 0D4014000000000000; +; CHECK: mul.f64 rd0, rd1, 0D4014000000000000; ; CHECK-NEXT: ret; %z = fmul double %x, 5.0 ret double %z diff --git a/test/CodeGen/PTX/options.ll b/test/CodeGen/PTX/options.ll index 6576a6d..92effa6 100644 --- a/test/CodeGen/PTX/options.ll +++ b/test/CodeGen/PTX/options.ll @@ -1,9 +1,10 @@ -; RUN: llc < %s -march=ptx -mattr=ptx20 | grep ".version 2.0" -; RUN: llc < %s -march=ptx -mattr=ptx21 | grep ".version 2.1" -; RUN: llc < %s -march=ptx -mattr=ptx22 | grep ".version 2.2" -; RUN: llc < %s -march=ptx -mattr=sm10 | grep ".target sm_10" -; RUN: llc < %s -march=ptx -mattr=sm13 | grep ".target sm_13" -; RUN: llc < %s -march=ptx -mattr=sm20 | grep ".target sm_20" +; RUN: llc < %s -march=ptx32 -mattr=ptx20 | grep ".version 2.0" +; RUN: llc < %s -march=ptx32 -mattr=ptx21 | grep ".version 2.1" +; RUN: llc < %s -march=ptx32 -mattr=ptx22 | grep ".version 2.2" +; RUN: llc < %s -march=ptx32 -mattr=ptx23 | grep ".version 2.3" +; RUN: llc < %s -march=ptx32 -mattr=sm10 | grep ".target sm_10" +; RUN: llc < %s -march=ptx32 -mattr=sm13 | grep ".target sm_13" +; RUN: llc < %s -march=ptx32 -mattr=sm20 | grep ".target sm_20" define ptx_device void @t1() { ret void diff --git a/test/CodeGen/PTX/parameter-order.ll b/test/CodeGen/PTX/parameter-order.ll index dbbbb67..5486472 100644 --- a/test/CodeGen/PTX/parameter-order.ll +++ b/test/CodeGen/PTX/parameter-order.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s -; CHECK: .func (.reg .u32 r0) test_parameter_order (.reg .u32 r1, .reg .u32 r2) -define ptx_device i32 @test_parameter_order(i32 %x, i32 %y) { -; CHECK: sub.u32 r0, r1, r2 - %z = sub i32 %x, %y - ret i32 %z +; CHECK: .func (.reg .b32 r0) test_parameter_order (.reg .b32 r1, .reg .b32 r2, .reg .b32 r3, .reg .b32 r4) +define ptx_device i32 @test_parameter_order(float %a, i32 %b, i32 %c, float %d) { +; CHECK: sub.u32 r0, r2, r3 + %result = sub i32 %b, %c + ret i32 %result } diff --git a/test/CodeGen/PTX/ret.ll b/test/CodeGen/PTX/ret.ll index d5037f2..ba0523f 100644 --- a/test/CodeGen/PTX/ret.ll +++ b/test/CodeGen/PTX/ret.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device void @t1() { ; CHECK: ret; diff --git a/test/CodeGen/PTX/selp.ll b/test/CodeGen/PTX/selp.ll new file mode 100644 index 0000000..19cfa53 --- /dev/null +++ b/test/CodeGen/PTX/selp.ll @@ -0,0 +1,25 @@ +; RUN: llc < %s -march=ptx32 | FileCheck %s + +define ptx_device i32 @test_selp_i32(i1 %x, i32 %y, i32 %z) { +; CHECK: selp.u32 r0, r1, r2, p1; + %a = select i1 %x, i32 %y, i32 %z + ret i32 %a +} + +define ptx_device i64 @test_selp_i64(i1 %x, i64 %y, i64 %z) { +; CHECK: selp.u64 rd0, rd1, rd2, p1; + %a = select i1 %x, i64 %y, i64 %z + ret i64 %a +} + +define ptx_device float @test_selp_f32(i1 %x, float %y, float %z) { +; CHECK: selp.f32 r0, r1, r2, p1; + %a = select i1 %x, float %y, float %z + ret float %a +} + +define ptx_device double @test_selp_f64(i1 %x, double %y, double %z) { +; CHECK: selp.f64 rd0, rd1, rd2, p1; + %a = select i1 %x, double %y, double %z + ret double %a +} diff --git a/test/CodeGen/PTX/setp.ll b/test/CodeGen/PTX/setp.ll index 5348482..5836122 100644 --- a/test/CodeGen/PTX/setp.ll +++ b/test/CodeGen/PTX/setp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device i32 @test_setp_eq_u32_rr(i32 %x, i32 %y) { ; CHECK: setp.eq.u32 p0, r1, r2; diff --git a/test/CodeGen/PTX/shl.ll b/test/CodeGen/PTX/shl.ll index b564b43..6e72c92 100644 --- a/test/CodeGen/PTX/shl.ll +++ b/test/CodeGen/PTX/shl.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device i32 @t1(i32 %x, i32 %y) { ; CHECK: shl.b32 r0, r1, r2 diff --git a/test/CodeGen/PTX/shr.ll b/test/CodeGen/PTX/shr.ll index 3f8ade8..8693e0e 100644 --- a/test/CodeGen/PTX/shr.ll +++ b/test/CodeGen/PTX/shr.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device i32 @t1(i32 %x, i32 %y) { ; CHECK: shr.u32 r0, r1, r2 diff --git a/test/CodeGen/PTX/st.ll b/test/CodeGen/PTX/st.ll index 4e9b08a..612967a 100644 --- a/test/CodeGen/PTX/st.ll +++ b/test/CodeGen/PTX/st.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s ;CHECK: .extern .global .b8 array_i16[20]; @array_i16 = external global [10 x i16] @@ -87,7 +87,7 @@ entry: define ptx_device void @t1_f32(float* %p, float %x) { entry: -;CHECK: st.global.f32 [r1], f1; +;CHECK: st.global.f32 [r1], r2; ;CHECK-NEXT: ret; store float %x, float* %p ret void @@ -95,7 +95,7 @@ entry: define ptx_device void @t1_f64(double* %p, double %x) { entry: -;CHECK: st.global.f64 [r1], fd1; +;CHECK: st.global.f64 [r1], rd1; ;CHECK-NEXT: ret; store double %x, double* %p ret void @@ -130,7 +130,7 @@ entry: define ptx_device void @t2_f32(float* %p, float %x) { entry: -;CHECK: st.global.f32 [r1+4], f1; +;CHECK: st.global.f32 [r1+4], r2; ;CHECK-NEXT: ret; %i = getelementptr float* %p, i32 1 store float %x, float* %i @@ -139,7 +139,7 @@ entry: define ptx_device void @t2_f64(double* %p, double %x) { entry: -;CHECK: st.global.f64 [r1+8], fd1; +;CHECK: st.global.f64 [r1+8], rd1; ;CHECK-NEXT: ret; %i = getelementptr double* %p, i32 1 store double %x, double* %i @@ -183,7 +183,7 @@ define ptx_device void @t3_f32(float* %p, i32 %q, float %x) { entry: ;CHECK: shl.b32 r0, r2, 2; ;CHECK-NEXT: add.u32 r0, r1, r0; -;CHECK-NEXT: st.global.f32 [r0], f1; +;CHECK-NEXT: st.global.f32 [r0], r3; ;CHECK-NEXT: ret; %i = getelementptr float* %p, i32 %q store float %x, float* %i @@ -194,7 +194,7 @@ define ptx_device void @t3_f64(double* %p, i32 %q, double %x) { entry: ;CHECK: shl.b32 r0, r2, 3; ;CHECK-NEXT: add.u32 r0, r1, r0; -;CHECK-NEXT: st.global.f64 [r0], fd1; +;CHECK-NEXT: st.global.f64 [r0], rd1; ;CHECK-NEXT: ret; %i = getelementptr double* %p, i32 %q store double %x, double* %i @@ -234,7 +234,7 @@ entry: define ptx_device void @t4_global_f32(float %x) { entry: ;CHECK: mov.u32 r0, array_float; -;CHECK-NEXT: st.global.f32 [r0], f1; +;CHECK-NEXT: st.global.f32 [r0], r1; ;CHECK-NEXT: ret; %i = getelementptr [10 x float]* @array_float, i32 0, i32 0 store float %x, float* %i @@ -244,7 +244,7 @@ entry: define ptx_device void @t4_global_f64(double %x) { entry: ;CHECK: mov.u32 r0, array_double; -;CHECK-NEXT: st.global.f64 [r0], fd1; +;CHECK-NEXT: st.global.f64 [r0], rd1; ;CHECK-NEXT: ret; %i = getelementptr [10 x double]* @array_double, i32 0, i32 0 store double %x, double* %i @@ -284,7 +284,7 @@ entry: define ptx_device void @t4_local_f32(float %x) { entry: ;CHECK: mov.u32 r0, array_local_float; -;CHECK-NEXT: st.local.f32 [r0], f1; +;CHECK-NEXT: st.local.f32 [r0], r1; ;CHECK-NEXT: ret; %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0 store float %x, float addrspace(2)* %i @@ -294,7 +294,7 @@ entry: define ptx_device void @t4_local_f64(double %x) { entry: ;CHECK: mov.u32 r0, array_local_double; -;CHECK-NEXT: st.local.f64 [r0], fd1; +;CHECK-NEXT: st.local.f64 [r0], rd1; ;CHECK-NEXT: ret; %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0 store double %x, double addrspace(2)* %i @@ -334,7 +334,7 @@ entry: define ptx_device void @t4_shared_f32(float %x) { entry: ;CHECK: mov.u32 r0, array_shared_float; -;CHECK-NEXT: st.shared.f32 [r0], f1; +;CHECK-NEXT: st.shared.f32 [r0], r1; ;CHECK-NEXT: ret; %i = getelementptr [10 x float] addrspace(4)* @array_shared_float, i32 0, i32 0 store float %x, float addrspace(4)* %i @@ -344,7 +344,7 @@ entry: define ptx_device void @t4_shared_f64(double %x) { entry: ;CHECK: mov.u32 r0, array_shared_double; -;CHECK-NEXT: st.shared.f64 [r0], fd1; +;CHECK-NEXT: st.shared.f64 [r0], rd1; ;CHECK-NEXT: ret; %i = getelementptr [10 x double] addrspace(4)* @array_shared_double, i32 0, i32 0 store double %x, double addrspace(4)* %i @@ -384,7 +384,7 @@ entry: define ptx_device void @t5_f32(float %x) { entry: ;CHECK: mov.u32 r0, array_float; -;CHECK-NEXT: st.global.f32 [r0+4], f1; +;CHECK-NEXT: st.global.f32 [r0+4], r1; ;CHECK-NEXT: ret; %i = getelementptr [10 x float]* @array_float, i32 0, i32 1 store float %x, float* %i @@ -394,7 +394,7 @@ entry: define ptx_device void @t5_f64(double %x) { entry: ;CHECK: mov.u32 r0, array_double; -;CHECK-NEXT: st.global.f64 [r0+8], fd1; +;CHECK-NEXT: st.global.f64 [r0+8], rd1; ;CHECK-NEXT: ret; %i = getelementptr [10 x double]* @array_double, i32 0, i32 1 store double %x, double* %i diff --git a/test/CodeGen/PTX/sub.ll b/test/CodeGen/PTX/sub.ll index 4810e4f..9efeaac 100644 --- a/test/CodeGen/PTX/sub.ll +++ b/test/CodeGen/PTX/sub.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ptx | FileCheck %s +; RUN: llc < %s -march=ptx32 | FileCheck %s define ptx_device i16 @t1_u16(i16 %x, i16 %y) { ; CHECK: sub.u16 rh0, rh1, rh2; @@ -22,14 +22,14 @@ define ptx_device i64 @t1_u64(i64 %x, i64 %y) { } define ptx_device float @t1_f32(float %x, float %y) { -; CHECK: sub.f32 f0, f1, f2 +; CHECK: sub.f32 r0, r1, r2 ; CHECK-NEXT: ret; %z = fsub float %x, %y ret float %z } define ptx_device double @t1_f64(double %x, double %y) { -; CHECK: sub.f64 fd0, fd1, fd2 +; CHECK: sub.f64 rd0, rd1, rd2 ; CHECK-NEXT: ret; %z = fsub double %x, %y ret double %z @@ -57,14 +57,14 @@ define ptx_device i64 @t2_u64(i64 %x) { } define ptx_device float @t2_f32(float %x) { -; CHECK: add.f32 f0, f1, 0FBF800000; +; CHECK: add.f32 r0, r1, 0FBF800000; ; CHECK-NEXT: ret; %z = fsub float %x, 1.0 ret float %z } define ptx_device double @t2_f64(double %x) { -; CHECK: add.f64 fd0, fd1, 0DBFF0000000000000; +; CHECK: add.f64 rd0, rd1, 0DBFF0000000000000; ; CHECK-NEXT: ret; %z = fsub double %x, 1.0 ret double %z diff --git a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll index 2938c70..72e93a9 100644 --- a/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll +++ b/test/CodeGen/PowerPC/2007-05-30-dagcombine-miscomp.ll @@ -4,7 +4,7 @@ target triple = "powerpc-apple-darwin8.8.0" ; RUN: llc < %s -march=ppc32 | grep {rlwinm r3, r3, 23, 30, 30} ; PR1473 -define i8 @foo(i16 zeroext %a) zeroext { +define zeroext i8 @foo(i16 zeroext %a) { %tmp2 = lshr i16 %a, 10 ; <i16> [#uses=1] %tmp23 = trunc i16 %tmp2 to i8 ; <i8> [#uses=1] %tmp4 = shl i8 %tmp23, 1 ; <i8> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll index 8776d9a..01c83cb 100644 --- a/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll +++ b/test/CodeGen/PowerPC/2008-03-24-CoalescerBug.ll @@ -18,7 +18,7 @@ define void @"-[PFTPersistentSymbols saveSymbolWithName:address:path:lineNumber: entry: br i1 false, label %bb12, label %bb21 bb12: ; preds = %entry - %tmp17 = tail call i8 inttoptr (i64 4294901504 to i8 (%struct..0objc_object*, %struct.objc_selector*, %struct.NSArray*)*)( %struct..0objc_object* null, %struct.objc_selector* null, %struct.NSArray* bitcast (%struct.__builtin_CFString* @0 to %struct.NSArray*) ) signext nounwind ; <i8> [#uses=0] + %tmp17 = tail call signext i8 inttoptr (i64 4294901504 to i8 (%struct..0objc_object*, %struct.objc_selector*, %struct.NSArray*)*)( %struct..0objc_object* null, %struct.objc_selector* null, %struct.NSArray* bitcast (%struct.__builtin_CFString* @0 to %struct.NSArray*) ) nounwind ; <i8> [#uses=0] br i1 false, label %bb25, label %bb21 bb21: ; preds = %bb12, %entry %tmp24 = or i64 %flags, 4 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll index 5cd8c34..21b0c61 100644 --- a/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll +++ b/test/CodeGen/PowerPC/2008-07-15-SignExtendInreg.ll @@ -2,7 +2,7 @@ target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin9" -define i16 @t(i16* %dct) signext nounwind { +define signext i16 @t(i16* %dct) nounwind { entry: load i16* null, align 2 ; <i16>:0 [#uses=2] lshr i16 %0, 11 ; <i16>:1 [#uses=0] diff --git a/test/CodeGen/PowerPC/2008-12-12-EH.ll b/test/CodeGen/PowerPC/2008-12-12-EH.ll index 2315e36..a2a5e9e 100644 --- a/test/CodeGen/PowerPC/2008-12-12-EH.ll +++ b/test/CodeGen/PowerPC/2008-12-12-EH.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh +; RUN: llc < %s -disable-cfi -march=ppc32 -mtriple=powerpc-apple-darwin9 | grep ^__Z1fv.eh define void @_Z1fv() { entry: diff --git a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll index d094509..6b31397 100644 --- a/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll +++ b/test/CodeGen/PowerPC/2010-03-09-indirect-call.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=ppc32 -mcpu=g5 -mtriple=powerpc-apple-darwin10.0 | FileCheck %s +; RUN: llc < %s -march=ppc32 -mcpu=g5 -mtriple=powerpc-apple-darwin10.0 -join-physregs | FileCheck %s ; ModuleID = 'nn.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128" target triple = "powerpc-apple-darwin11.0" diff --git a/test/CodeGen/PowerPC/and-elim.ll b/test/CodeGen/PowerPC/and-elim.ll index 3685361..a1ec29b 100644 --- a/test/CodeGen/PowerPC/and-elim.ll +++ b/test/CodeGen/PowerPC/and-elim.ll @@ -9,7 +9,7 @@ define void @test(i8* %P) { ret void } -define i16 @test2(i16 zeroext %crc) zeroext { +define zeroext i16 @test2(i16 zeroext %crc) { ; No and's should be needed for the i16s here. %tmp.1 = lshr i16 %crc, 1 %tmp.7 = xor i16 %tmp.1, 40961 diff --git a/test/CodeGen/PowerPC/and_sext.ll b/test/CodeGen/PowerPC/and_sext.ll index c6d234e..df48ccf 100644 --- a/test/CodeGen/PowerPC/and_sext.ll +++ b/test/CodeGen/PowerPC/and_sext.ll @@ -9,7 +9,7 @@ define i32 @test1(i32 %mode.0.i.0) { ret i32 %tmp.81 } -define i16 @test2(i16 signext %X, i16 signext %x) signext { +define signext i16 @test2(i16 signext %X, i16 signext %x) { %tmp = sext i16 %X to i32 %tmp1 = sext i16 %x to i32 %tmp2 = add i32 %tmp, %tmp1 @@ -20,7 +20,7 @@ define i16 @test2(i16 signext %X, i16 signext %x) signext { ret i16 %retval } -define i16 @test3(i32 zeroext %X) signext { +define signext i16 @test3(i32 zeroext %X) { %tmp1 = lshr i32 %X, 16 %tmp2 = trunc i32 %tmp1 to i16 ret i16 %tmp2 diff --git a/test/CodeGen/PowerPC/big-endian-formal-args.ll b/test/CodeGen/PowerPC/big-endian-formal-args.ll index e46e1ec..318ccb0 100644 --- a/test/CodeGen/PowerPC/big-endian-formal-args.ll +++ b/test/CodeGen/PowerPC/big-endian-formal-args.ll @@ -1,14 +1,12 @@ -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ -; RUN: grep {li 6, 3} -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ -; RUN: grep {li 4, 2} -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ -; RUN: grep {li 3, 0} -; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | \ -; RUN: grep {mr 5, 3} +; RUN: llc < %s -march=ppc32 -mtriple=powerpc-unknown-linux-gnu | FileCheck %s declare void @bar(i64 %x, i64 %y) +; CHECK: li 4, 2 +; CHECK: li {{[53]}}, 0 +; CHECK: li 6, 3 +; CHECK: mr {{[53]}}, {{[53]}} + define void @foo() { call void @bar(i64 2, i64 3) ret void diff --git a/test/CodeGen/PowerPC/calls.ll b/test/CodeGen/PowerPC/calls.ll index 0db184f..29bcb20 100644 --- a/test/CodeGen/PowerPC/calls.ll +++ b/test/CodeGen/PowerPC/calls.ll @@ -1,7 +1,7 @@ ; Test various forms of calls. ; RUN: llc < %s -march=ppc32 | \ -; RUN: grep {bl } | count 2 +; RUN: grep {bl } | count 1 ; RUN: llc < %s -march=ppc32 | \ ; RUN: grep {bctrl} | count 1 ; RUN: llc < %s -march=ppc32 | \ @@ -14,11 +14,6 @@ define void @test_direct() { ret void } -define void @test_extsym(i8* %P) { - free i8* %P - ret void -} - define void @test_indirect(void ()* %fp) { call void %fp( ) ret void diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll index ac56625..29c620e 100644 --- a/test/CodeGen/PowerPC/indirectbr.ll +++ b/test/CodeGen/PowerPC/indirectbr.ll @@ -1,5 +1,6 @@ ; RUN: llc < %s -relocation-model=pic -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=PIC ; RUN: llc < %s -relocation-model=static -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=STATIC +; RUN: llc < %s -relocation-model=pic -march=ppc64 -mtriple=powerpc64-apple-darwin | FileCheck %s -check-prefix=PPC64 @nextaddr = global i8* null ; <i8**> [#uses=2] @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] @@ -7,6 +8,7 @@ define internal i32 @foo(i32 %i) nounwind { ; PIC: foo: ; STATIC: foo: +; PPC64: foo: entry: %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2] %1 = icmp eq i8* %0, null ; <i1> [#uses=1] @@ -18,6 +20,8 @@ bb2: ; preds = %entry, %bb3 ; PIC-NEXT: bctr ; STATIC: mtctr ; STATIC-NEXT: bctr +; PPC64: mtctr +; PPC64-NEXT: bctr indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] bb3: ; preds = %entry diff --git a/test/CodeGen/PowerPC/mul-with-overflow.ll b/test/CodeGen/PowerPC/mul-with-overflow.ll index f03e3cb..76d06df 100644 --- a/test/CodeGen/PowerPC/mul-with-overflow.ll +++ b/test/CodeGen/PowerPC/mul-with-overflow.ll @@ -1,14 +1,14 @@ ; RUN: llc < %s -march=ppc32 declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) -define i1 @a(i32 %x) zeroext nounwind { +define zeroext i1 @a(i32 %x) nounwind { %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3) %obil = extractvalue {i32, i1} %res, 1 ret i1 %obil } declare {i32, i1} @llvm.smul.with.overflow.i32(i32 %a, i32 %b) -define i1 @b(i32 %x) zeroext nounwind { +define zeroext i1 @b(i32 %x) nounwind { %res = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %x, i32 3) %obil = extractvalue {i32, i1} %res, 1 ret i1 %obil diff --git a/test/CodeGen/PowerPC/mulhs.ll b/test/CodeGen/PowerPC/mulhs.ll index 9ab8d99..5b02e18 100644 --- a/test/CodeGen/PowerPC/mulhs.ll +++ b/test/CodeGen/PowerPC/mulhs.ll @@ -5,7 +5,7 @@ ; RUN: not grep add %t ; RUN: grep mulhw %t | count 1 -define i32 @mulhs(i32 %a, i32 %b) { +define i32 @mulhs(i32 %a, i32 %b) nounwind { entry: %tmp.1 = sext i32 %a to i64 ; <i64> [#uses=1] %tmp.3 = sext i32 %b to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/PowerPC/ppc-prologue.ll b/test/CodeGen/PowerPC/ppc-prologue.ll index 2ebfd3c..5538371 100644 --- a/test/CodeGen/PowerPC/ppc-prologue.ll +++ b/test/CodeGen/PowerPC/ppc-prologue.ll @@ -5,9 +5,7 @@ define i32 @_Z4funci(i32 %a) ssp { ; CHECK-NEXT: stw r31, -4(r1) ; CHECK-NEXT: stw r0, 8(r1) ; CHECK-NEXT: stwu r1, -80(r1) -; CHECK-NEXT: Ltmp0: -; CHECK-NEXT: mr r31, r1 -; CHECK-NEXT: Ltmp1: +; CHECK: mr r31, r1 entry: %a_addr = alloca i32 ; <i32*> [#uses=2] %retval = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/PowerPC/small-arguments.ll b/test/CodeGen/PowerPC/small-arguments.ll index 31bcee6..b4767b0 100644 --- a/test/CodeGen/PowerPC/small-arguments.ll +++ b/test/CodeGen/PowerPC/small-arguments.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=ppc32 | not grep {extsh\\|rlwinm} -declare i16 @foo() signext +declare signext i16 @foo() define i32 @test1(i16 signext %X) { %Y = sext i16 %X to i32 ;; dead @@ -14,12 +14,12 @@ define i32 @test2(i16 zeroext %X) { } define void @test3() { - %tmp.0 = call i16 @foo() signext ;; no extsh! + %tmp.0 = call signext i16 @foo() ;; no extsh! %tmp.1 = icmp slt i16 %tmp.0, 1234 br i1 %tmp.1, label %then, label %UnifiedReturnBlock then: - call i32 @test1(i16 0 signext) + call i32 @test1(i16 signext 0) ret void UnifiedReturnBlock: ret void @@ -46,7 +46,7 @@ define i32 @test6(i32* %P) { ret i32 %tmp.2 } -define i16 @test7(float %a) zeroext { +define zeroext i16 @test7(float %a) { %tmp.1 = fptoui float %a to i16 ret i16 %tmp.1 } diff --git a/test/CodeGen/SPARC/2011-01-22-SRet.ll b/test/CodeGen/SPARC/2011-01-22-SRet.ll index 506d3a8..5393392 100644 --- a/test/CodeGen/SPARC/2011-01-22-SRet.ll +++ b/test/CodeGen/SPARC/2011-01-22-SRet.ll @@ -6,7 +6,6 @@ define weak void @make_foo(%struct.foo_t* noalias sret %agg.result, i32 %a, i32 entry: ;CHECK: make_foo ;CHECK: ld [%fp+64], {{.+}} -;CHECK: or {{.+}}, {{.+}}, %i0 ;CHECK: jmp %i7+12 %0 = getelementptr inbounds %struct.foo_t* %agg.result, i32 0, i32 0 store i32 %a, i32* %0, align 4 diff --git a/test/CodeGen/SystemZ/02-MemArith.ll b/test/CodeGen/SystemZ/02-MemArith.ll index 04022a0..ee9e5e9 100644 --- a/test/CodeGen/SystemZ/02-MemArith.ll +++ b/test/CodeGen/SystemZ/02-MemArith.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=systemz | FileCheck %s -define i32 @foo1(i32 %a, i32 *%b, i64 %idx) signext { +define signext i32 @foo1(i32 %a, i32 *%b, i64 %idx) { ; CHECK: foo1: ; CHECK: a %r2, 4(%r1,%r3) entry: @@ -11,7 +11,7 @@ entry: ret i32 %d } -define i32 @foo2(i32 %a, i32 *%b, i64 %idx) signext { +define signext i32 @foo2(i32 %a, i32 *%b, i64 %idx) { ; CHECK: foo2: ; CHECK: ay %r2, -4(%r1,%r3) entry: @@ -22,7 +22,7 @@ entry: ret i32 %d } -define i64 @foo3(i64 %a, i64 *%b, i64 %idx) signext { +define signext i64 @foo3(i64 %a, i64 *%b, i64 %idx) { ; CHECK: foo3: ; CHECK: ag %r2, 8(%r1,%r3) entry: @@ -33,7 +33,7 @@ entry: ret i64 %d } -define i32 @foo4(i32 %a, i32 *%b, i64 %idx) signext { +define signext i32 @foo4(i32 %a, i32 *%b, i64 %idx) { ; CHECK: foo4: ; CHECK: n %r2, 4(%r1,%r3) entry: @@ -44,7 +44,7 @@ entry: ret i32 %d } -define i32 @foo5(i32 %a, i32 *%b, i64 %idx) signext { +define signext i32 @foo5(i32 %a, i32 *%b, i64 %idx) { ; CHECK: foo5: ; CHECK: ny %r2, -4(%r1,%r3) entry: @@ -55,7 +55,7 @@ entry: ret i32 %d } -define i64 @foo6(i64 %a, i64 *%b, i64 %idx) signext { +define signext i64 @foo6(i64 %a, i64 *%b, i64 %idx) { ; CHECK: foo6: ; CHECK: ng %r2, 8(%r1,%r3) entry: @@ -66,7 +66,7 @@ entry: ret i64 %d } -define i32 @foo7(i32 %a, i32 *%b, i64 %idx) signext { +define signext i32 @foo7(i32 %a, i32 *%b, i64 %idx) { ; CHECK: foo7: ; CHECK: o %r2, 4(%r1,%r3) entry: @@ -77,7 +77,7 @@ entry: ret i32 %d } -define i32 @foo8(i32 %a, i32 *%b, i64 %idx) signext { +define signext i32 @foo8(i32 %a, i32 *%b, i64 %idx) { ; CHECK: foo8: ; CHECK: oy %r2, -4(%r1,%r3) entry: @@ -88,7 +88,7 @@ entry: ret i32 %d } -define i64 @foo9(i64 %a, i64 *%b, i64 %idx) signext { +define signext i64 @foo9(i64 %a, i64 *%b, i64 %idx) { ; CHECK: foo9: ; CHECK: og %r2, 8(%r1,%r3) entry: @@ -99,7 +99,7 @@ entry: ret i64 %d } -define i32 @foo10(i32 %a, i32 *%b, i64 %idx) signext { +define signext i32 @foo10(i32 %a, i32 *%b, i64 %idx) { ; CHECK: foo10: ; CHECK: x %r2, 4(%r1,%r3) entry: @@ -110,7 +110,7 @@ entry: ret i32 %d } -define i32 @foo11(i32 %a, i32 *%b, i64 %idx) signext { +define signext i32 @foo11(i32 %a, i32 *%b, i64 %idx) { ; CHECK: foo11: ; CHECK: xy %r2, -4(%r1,%r3) entry: @@ -121,7 +121,7 @@ entry: ret i32 %d } -define i64 @foo12(i64 %a, i64 *%b, i64 %idx) signext { +define signext i64 @foo12(i64 %a, i64 *%b, i64 %idx) { ; CHECK: foo12: ; CHECK: xg %r2, 8(%r1,%r3) entry: diff --git a/test/CodeGen/SystemZ/03-RetAddImmSubreg.ll b/test/CodeGen/SystemZ/03-RetAddImmSubreg.ll index 0a81271..0a7f5ee 100644 --- a/test/CodeGen/SystemZ/03-RetAddImmSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetAddImmSubreg.ll @@ -16,25 +16,25 @@ entry: ret i32 %c } -define i32 @foo3(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo3(i32 %a, i32 %b) { entry: %c = add i32 %a, 1 ret i32 %c } -define i32 @foo4(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo4(i32 %a, i32 %b) { entry: %c = add i32 %a, 131072 ret i32 %c } -define i32 @foo5(i32 %a, i32 %b) signext { +define signext i32 @foo5(i32 %a, i32 %b) { entry: %c = add i32 %a, 1 ret i32 %c } -define i32 @foo6(i32 %a, i32 %b) signext { +define signext i32 @foo6(i32 %a, i32 %b) { entry: %c = add i32 %a, 131072 ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetAddSubreg.ll b/test/CodeGen/SystemZ/03-RetAddSubreg.ll index 2787083..337bb3f 100644 --- a/test/CodeGen/SystemZ/03-RetAddSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetAddSubreg.ll @@ -8,13 +8,13 @@ entry: ret i32 %c } -define i32 @foo1(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo1(i32 %a, i32 %b) { entry: %c = add i32 %a, %b ret i32 %c } -define i32 @foo2(i32 %a, i32 %b) signext { +define signext i32 @foo2(i32 %a, i32 %b) { entry: %c = add i32 %a, %b ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll b/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll index 32673dd..c5326ab 100644 --- a/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetAndImmSubreg.ll @@ -12,25 +12,25 @@ entry: ret i32 %c } -define i32 @foo3(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo3(i32 %a, i32 %b) { entry: %c = and i32 %a, 1 ret i32 %c } -define i32 @foo4(i32 %a, i32 %b) signext { +define signext i32 @foo4(i32 %a, i32 %b) { entry: %c = and i32 %a, 131072 ret i32 %c } -define i32 @foo5(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo5(i32 %a, i32 %b) { entry: %c = and i32 %a, 1 ret i32 %c } -define i32 @foo6(i32 %a, i32 %b) signext { +define signext i32 @foo6(i32 %a, i32 %b) { entry: %c = and i32 %a, 131072 ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetAndSubreg.ll b/test/CodeGen/SystemZ/03-RetAndSubreg.ll index ed5e526..75dc90a 100644 --- a/test/CodeGen/SystemZ/03-RetAndSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetAndSubreg.ll @@ -7,13 +7,13 @@ entry: ret i32 %c } -define i32 @foo1(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo1(i32 %a, i32 %b) { entry: %c = and i32 %a, %b ret i32 %c } -define i32 @foo2(i32 %a, i32 %b) signext { +define signext i32 @foo2(i32 %a, i32 %b) { entry: %c = and i32 %a, %b ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetArgSubreg.ll b/test/CodeGen/SystemZ/03-RetArgSubreg.ll index 0c9bb14..476821a 100644 --- a/test/CodeGen/SystemZ/03-RetArgSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetArgSubreg.ll @@ -8,12 +8,12 @@ entry: ret i32 %b } -define i32 @foo1(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo1(i32 %a, i32 %b) { entry: ret i32 %b } -define i32 @foo2(i32 %a, i32 %b) signext { +define signext i32 @foo2(i32 %a, i32 %b) { entry: ret i32 %b } diff --git a/test/CodeGen/SystemZ/03-RetImmSubreg.ll b/test/CodeGen/SystemZ/03-RetImmSubreg.ll index 343e30b..70da913 100644 --- a/test/CodeGen/SystemZ/03-RetImmSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetImmSubreg.ll @@ -30,12 +30,12 @@ entry: ret i32 4294967295 } -define i32 @foo6() zeroext { +define zeroext i32 @foo6() { entry: ret i32 4294967295 } -define i32 @foo7() signext { +define signext i32 @foo7() { entry: ret i32 4294967295 } diff --git a/test/CodeGen/SystemZ/03-RetOrImmSubreg.ll b/test/CodeGen/SystemZ/03-RetOrImmSubreg.ll index 6d118b5..99adea8 100644 --- a/test/CodeGen/SystemZ/03-RetOrImmSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetOrImmSubreg.ll @@ -22,37 +22,37 @@ entry: ret i32 %c } -define i32 @foo3(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo3(i32 %a, i32 %b) { entry: %c = or i32 %a, 1 ret i32 %c } -define i32 @foo8(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo8(i32 %a, i32 %b) { entry: %c = or i32 %a, 123456 ret i32 %c } -define i32 @foo4(i32 %a, i32 %b) signext { +define signext i32 @foo4(i32 %a, i32 %b) { entry: %c = or i32 %a, 131072 ret i32 %c } -define i32 @foo5(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo5(i32 %a, i32 %b) { entry: %c = or i32 %a, 1 ret i32 %c } -define i32 @foo6(i32 %a, i32 %b) signext { +define signext i32 @foo6(i32 %a, i32 %b) { entry: %c = or i32 %a, 131072 ret i32 %c } -define i32 @foo9(i32 %a, i32 %b) signext { +define signext i32 @foo9(i32 %a, i32 %b) { entry: %c = or i32 %a, 123456 ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetOrSubreg.ll b/test/CodeGen/SystemZ/03-RetOrSubreg.ll index 4d7661a..7dab5ca 100644 --- a/test/CodeGen/SystemZ/03-RetOrSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetOrSubreg.ll @@ -9,13 +9,13 @@ entry: ret i32 %c } -define i32 @foo1(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo1(i32 %a, i32 %b) { entry: %c = or i32 %a, %b ret i32 %c } -define i32 @foo2(i32 %a, i32 %b) signext { +define signext i32 @foo2(i32 %a, i32 %b) { entry: %c = or i32 %a, %b ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetSubImmSubreg.ll b/test/CodeGen/SystemZ/03-RetSubImmSubreg.ll index 11ca796..21ea9b5 100644 --- a/test/CodeGen/SystemZ/03-RetSubImmSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetSubImmSubreg.ll @@ -16,25 +16,25 @@ entry: ret i32 %c } -define i32 @foo3(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo3(i32 %a, i32 %b) { entry: %c = sub i32 %a, 1 ret i32 %c } -define i32 @foo4(i32 %a, i32 %b) signext { +define signext i32 @foo4(i32 %a, i32 %b) { entry: %c = sub i32 %a, 131072 ret i32 %c } -define i32 @foo5(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo5(i32 %a, i32 %b) { entry: %c = sub i32 %a, 1 ret i32 %c } -define i32 @foo6(i32 %a, i32 %b) signext { +define signext i32 @foo6(i32 %a, i32 %b) { entry: %c = sub i32 %a, 131072 ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetSubSubreg.ll b/test/CodeGen/SystemZ/03-RetSubSubreg.ll index b3e1ac2..24b7631 100644 --- a/test/CodeGen/SystemZ/03-RetSubSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetSubSubreg.ll @@ -8,13 +8,13 @@ entry: ret i32 %c } -define i32 @foo1(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo1(i32 %a, i32 %b) { entry: %c = sub i32 %a, %b ret i32 %c } -define i32 @foo2(i32 %a, i32 %b) signext { +define signext i32 @foo2(i32 %a, i32 %b) { entry: %c = sub i32 %a, %b ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetXorImmSubreg.ll b/test/CodeGen/SystemZ/03-RetXorImmSubreg.ll index 0033126..70ee454 100644 --- a/test/CodeGen/SystemZ/03-RetXorImmSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetXorImmSubreg.ll @@ -20,37 +20,37 @@ entry: ret i32 %c } -define i32 @foo3(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo3(i32 %a, i32 %b) { entry: %c = xor i32 %a, 1 ret i32 %c } -define i32 @foo8(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo8(i32 %a, i32 %b) { entry: %c = xor i32 %a, 123456 ret i32 %c } -define i32 @foo4(i32 %a, i32 %b) signext { +define signext i32 @foo4(i32 %a, i32 %b) { entry: %c = xor i32 %a, 131072 ret i32 %c } -define i32 @foo5(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo5(i32 %a, i32 %b) { entry: %c = xor i32 %a, 1 ret i32 %c } -define i32 @foo6(i32 %a, i32 %b) signext { +define signext i32 @foo6(i32 %a, i32 %b) { entry: %c = xor i32 %a, 131072 ret i32 %c } -define i32 @foo9(i32 %a, i32 %b) signext { +define signext i32 @foo9(i32 %a, i32 %b) { entry: %c = xor i32 %a, 123456 ret i32 %c diff --git a/test/CodeGen/SystemZ/03-RetXorSubreg.ll b/test/CodeGen/SystemZ/03-RetXorSubreg.ll index a9af231..02c4a2a 100644 --- a/test/CodeGen/SystemZ/03-RetXorSubreg.ll +++ b/test/CodeGen/SystemZ/03-RetXorSubreg.ll @@ -9,13 +9,13 @@ entry: ret i32 %c } -define i32 @foo1(i32 %a, i32 %b) zeroext { +define zeroext i32 @foo1(i32 %a, i32 %b) { entry: %c = xor i32 %a, %b ret i32 %c } -define i32 @foo2(i32 %a, i32 %b) signext { +define signext i32 @foo2(i32 %a, i32 %b) { entry: %c = xor i32 %a, %b ret i32 %c diff --git a/test/CodeGen/SystemZ/11-BSwap.ll b/test/CodeGen/SystemZ/11-BSwap.ll index b170a80..1aa9c67 100644 --- a/test/CodeGen/SystemZ/11-BSwap.ll +++ b/test/CodeGen/SystemZ/11-BSwap.ll @@ -5,34 +5,34 @@ target datalayout = "E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:3 target triple = "s390x-ibm-linux" -define i16 @foo(i16 zeroext %a) zeroext { +define zeroext i16 @foo(i16 zeroext %a) { %res = tail call i16 @llvm.bswap.i16(i16 %a) ret i16 %res } -define i32 @foo2(i32 zeroext %a) zeroext { +define zeroext i32 @foo2(i32 zeroext %a) { ; CHECK: foo2: -; CHECK: lrvr %r1, %r2 +; CHECK: lrvr [[R1:%r.]], %r2 %res = tail call i32 @llvm.bswap.i32(i32 %a) ret i32 %res } -define i64 @foo3(i64 %a) zeroext { +define zeroext i64 @foo3(i64 %a) { ; CHECK: foo3: ; CHECK: lrvgr %r2, %r2 %res = tail call i64 @llvm.bswap.i64(i64 %a) ret i64 %res } -define i16 @foo4(i16* %b) zeroext { +define zeroext i16 @foo4(i16* %b) { %a = load i16* %b %res = tail call i16 @llvm.bswap.i16(i16 %a) ret i16 %res } -define i32 @foo5(i32* %b) zeroext { +define zeroext i32 @foo5(i32* %b) { ; CHECK: foo5: -; CHECK: lrv %r1, 0(%r2) +; CHECK: lrv [[R1:%r.]], 0(%r2) %a = load i32* %b %res = tail call i32 @llvm.bswap.i32(i32 %a) ret i32 %res diff --git a/test/CodeGen/Thumb/2007-03-06-AddR7.ll b/test/CodeGen/Thumb/2007-03-06-AddR7.ll deleted file mode 100644 index 8d139e9..0000000 --- a/test/CodeGen/Thumb/2007-03-06-AddR7.ll +++ /dev/null @@ -1,117 +0,0 @@ -; RUN: llc < %s -march=thumb -; RUN: llc < %s -mtriple=thumb-apple-darwin -relocation-model=pic \ -; RUN: -mattr=+v6,+vfp2 | not grep {add r., r7, #2 \\* 4} - - %struct.__fooAllocator = type opaque - %struct.__fooY = type { %struct.fooXBase, %struct.__fooString*, %struct.__fooU*, %struct.__fooV*, i8** } - %struct.__fooZ = type opaque - %struct.__fooU = type opaque - %struct.__fooString = type opaque - %struct.__fooV = type opaque - %struct.fooXBase = type { i32, [4 x i8] } - %struct.fooXClass = type { i32, i8*, void (i8*)*, i8* (%struct.__fooAllocator*, i8*)*, void (i8*)*, i8 (i8*, i8*) zeroext *, i32 (i8*)*, %struct.__fooString* (i8*, %struct.__fooZ*)*, %struct.__fooString* (i8*)* } - %struct.aa_cache = type { i32, i32, [1 x %struct.aa_method*] } - %struct.aa_class = type { %struct.aa_class*, %struct.aa_class*, i8*, i32, i32, i32, %struct.aa_ivar_list*, %struct.aa_method_list**, %struct.aa_cache*, %struct.aa_protocol_list* } - %struct.aa_ivar = type { i8*, i8*, i32 } - %struct.aa_ivar_list = type { i32, [1 x %struct.aa_ivar] } - %struct.aa_method = type { %struct.aa_ss*, i8*, %struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* } - %struct.aa_method_list = type { %struct.aa_method_list*, i32, [1 x %struct.aa_method] } - %struct.aa_object = type { %struct.aa_class* } - %struct.aa_protocol_list = type { %struct.aa_protocol_list*, i32, [1 x %struct.aa_object*] } - %struct.aa_ss = type opaque -@__kfooYTypeID = external global i32 ; <i32*> [#uses=3] -@__fooYClass = external constant %struct.fooXClass ; <%struct.fooXClass*> [#uses=1] -@__fooXClassTableSize = external global i32 ; <i32*> [#uses=1] -@__fooXAaClassTable = external global i32* ; <i32**> [#uses=1] -@s.10319 = external global %struct.aa_ss* ; <%struct.aa_ss**> [#uses=2] -@str15 = external constant [24 x i8] ; <[24 x i8]*> [#uses=1] - - -define i8 @test(%struct.__fooY* %calendar, double* %atp, i8* %componentDesc, ...) zeroext { -entry: - %args = alloca i8*, align 4 ; <i8**> [#uses=5] - %args4 = bitcast i8** %args to i8* ; <i8*> [#uses=2] - call void @llvm.va_start( i8* %args4 ) - %tmp6 = load i32* @__kfooYTypeID ; <i32> [#uses=1] - icmp eq i32 %tmp6, 0 ; <i1>:0 [#uses=1] - br i1 %0, label %cond_true, label %cond_next - -cond_true: ; preds = %entry - %tmp7 = call i32 @_fooXRegisterClass( %struct.fooXClass* @__fooYClass ) ; <i32> [#uses=1] - store i32 %tmp7, i32* @__kfooYTypeID - br label %cond_next - -cond_next: ; preds = %cond_true, %entry - %tmp8 = load i32* @__kfooYTypeID ; <i32> [#uses=2] - %tmp15 = load i32* @__fooXClassTableSize ; <i32> [#uses=1] - icmp ugt i32 %tmp15, %tmp8 ; <i1>:1 [#uses=1] - br i1 %1, label %cond_next18, label %cond_true58 - -cond_next18: ; preds = %cond_next - %tmp21 = getelementptr %struct.__fooY* %calendar, i32 0, i32 0, i32 0 ; <i32*> [#uses=1] - %tmp22 = load i32* %tmp21 ; <i32> [#uses=2] - %tmp29 = load i32** @__fooXAaClassTable ; <i32*> [#uses=1] - %tmp31 = getelementptr i32* %tmp29, i32 %tmp8 ; <i32*> [#uses=1] - %tmp32 = load i32* %tmp31 ; <i32> [#uses=1] - icmp eq i32 %tmp22, %tmp32 ; <i1>:2 [#uses=1] - %.not = xor i1 %2, true ; <i1> [#uses=1] - icmp ugt i32 %tmp22, 4095 ; <i1>:3 [#uses=1] - %bothcond = and i1 %.not, %3 ; <i1> [#uses=1] - br i1 %bothcond, label %cond_true58, label %bb48 - -bb48: ; preds = %cond_next18 - %tmp78 = call i32 @strlen( i8* %componentDesc ) ; <i32> [#uses=4] - %tmp92 = alloca i32, i32 %tmp78 ; <i32*> [#uses=2] - icmp sgt i32 %tmp78, 0 ; <i1>:4 [#uses=1] - br i1 %4, label %cond_true111, label %bb114 - -cond_true58: ; preds = %cond_next18, %cond_next - %tmp59 = load %struct.aa_ss** @s.10319 ; <%struct.aa_ss*> [#uses=2] - icmp eq %struct.aa_ss* %tmp59, null ; <i1>:5 [#uses=1] - %tmp6869 = bitcast %struct.__fooY* %calendar to i8* ; <i8*> [#uses=2] - br i1 %5, label %cond_true60, label %cond_next64 - -cond_true60: ; preds = %cond_true58 - %tmp63 = call %struct.aa_ss* @sel_registerName( i8* getelementptr ([24 x i8]* @str15, i32 0, i32 0) ) ; <%struct.aa_ss*> [#uses=2] - store %struct.aa_ss* %tmp63, %struct.aa_ss** @s.10319 - %tmp66137 = volatile load i8** %args ; <i8*> [#uses=1] - %tmp73138 = call i8 (i8*, %struct.aa_ss*, ...) zeroext * bitcast (%struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* @aa_mm to i8 (i8*, %struct.aa_ss*, ...) zeroext *)( i8* %tmp6869, %struct.aa_ss* %tmp63, double* %atp, i8* %componentDesc, i8* %tmp66137) zeroext ; <i8> [#uses=1] - ret i8 %tmp73138 - -cond_next64: ; preds = %cond_true58 - %tmp66 = volatile load i8** %args ; <i8*> [#uses=1] - %tmp73 = call i8 (i8*, %struct.aa_ss*, ...) zeroext * bitcast (%struct.aa_object* (%struct.aa_object*, %struct.aa_ss*, ...)* @aa_mm to i8 (i8*, %struct.aa_ss*, ...) zeroext *)( i8* %tmp6869, %struct.aa_ss* %tmp59, double* %atp, i8* %componentDesc, i8* %tmp66 ) zeroext ; <i8> [#uses=1] - ret i8 %tmp73 - -cond_true111: ; preds = %cond_true111, %bb48 - %idx.2132.0 = phi i32 [ 0, %bb48 ], [ %indvar.next, %cond_true111 ] ; <i32> [#uses=2] - %tmp95 = volatile load i8** %args ; <i8*> [#uses=2] - %tmp97 = getelementptr i8* %tmp95, i32 4 ; <i8*> [#uses=1] - volatile store i8* %tmp97, i8** %args - %tmp9899 = bitcast i8* %tmp95 to i32* ; <i32*> [#uses=1] - %tmp100 = load i32* %tmp9899 ; <i32> [#uses=1] - %tmp104 = getelementptr i32* %tmp92, i32 %idx.2132.0 ; <i32*> [#uses=1] - store i32 %tmp100, i32* %tmp104 - %indvar.next = add i32 %idx.2132.0, 1 ; <i32> [#uses=2] - icmp eq i32 %indvar.next, %tmp78 ; <i1>:6 [#uses=1] - br i1 %6, label %bb114, label %cond_true111 - -bb114: ; preds = %cond_true111, %bb48 - call void @llvm.va_end( i8* %args4 ) - %tmp122 = call i8 @_fooYCCV( %struct.__fooY* %calendar, double* %atp, i8* %componentDesc, i32* %tmp92, i32 %tmp78 ) zeroext ; <i8> [#uses=1] - ret i8 %tmp122 -} - -declare i32 @_fooXRegisterClass(%struct.fooXClass*) - -declare i8 @_fooYCCV(%struct.__fooY*, double*, i8*, i32*, i32) zeroext - -declare %struct.aa_object* @aa_mm(%struct.aa_object*, %struct.aa_ss*, ...) - -declare %struct.aa_ss* @sel_registerName(i8*) - -declare void @llvm.va_start(i8*) - -declare i32 @strlen(i8*) - -declare void @llvm.va_end(i8*) diff --git a/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll b/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll deleted file mode 100644 index 9cdcd31..0000000 --- a/test/CodeGen/Thumb/2009-07-19-SPDecBug.ll +++ /dev/null @@ -1,33 +0,0 @@ -; RUN: llc < %s -mtriple=thumbv6-elf | not grep "subs sp" -; PR4567 - -define i8* @__gets_chk(i8* %s, i32 %slen) nounwind { -entry: - br i1 undef, label %bb, label %bb1 - -bb: ; preds = %entry - ret i8* undef - -bb1: ; preds = %entry - br i1 undef, label %bb3, label %bb2 - -bb2: ; preds = %bb1 - %0 = alloca i8, i32 undef, align 4 ; <i8*> [#uses=0] - br label %bb4 - -bb3: ; preds = %bb1 - %1 = malloc i8, i32 undef ; <i8*> [#uses=0] - br label %bb4 - -bb4: ; preds = %bb3, %bb2 - br i1 undef, label %bb5, label %bb6 - -bb5: ; preds = %bb4 - %2 = call i8* @gets(i8* %s) nounwind ; <i8*> [#uses=1] - ret i8* %2 - -bb6: ; preds = %bb4 - unreachable -} - -declare i8* @gets(i8*) nounwind diff --git a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll index d6ca0d7..7876557 100644 --- a/test/CodeGen/Thumb/2009-08-20-ISelBug.ll +++ b/test/CodeGen/Thumb/2009-08-20-ISelBug.ll @@ -11,7 +11,7 @@ define i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize { ; CHECK: t: -; CHECK: adds r0, #8 +; CHECK: adds {{r[0-7]}}, #8 entry: %val = alloca i64, align 4 ; <i64*> [#uses=3] %0 = icmp eq %struct.asl_file_t* %s, null ; <i1> [#uses=1] diff --git a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll b/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll deleted file mode 100644 index fad2669..0000000 --- a/test/CodeGen/Thumb/2010-01-15-local-alloc-spill-physical.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: llc < %s -regalloc=fast -relocation-model=pic | FileCheck %s - -target triple = "thumbv6-apple-darwin10" - -@fred = internal global i32 0 ; <i32*> [#uses=1] - -define void @foo() nounwind { -entry: -; CHECK: str r0, [sp - %0 = call i32 (...)* @bar() nounwind ; <i32> [#uses=1] -; CHECK: blx _bar -; CHECK: ldr r1, [sp - store i32 %0, i32* @fred, align 4 - br label %return - -return: ; preds = %entry - ret void -} - -declare i32 @bar(...) diff --git a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll index 06c0dfe..9f5a677 100644 --- a/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll +++ b/test/CodeGen/Thumb/2010-07-15-debugOrdering.ll @@ -10,7 +10,7 @@ define void @_Z19getClosestDiagonal3ii(%0* noalias sret, i32, i32) nounwind { ; CHECK: blx ___muldf3 ; CHECK: blx ___muldf3 -; CHECK: beq LBB0_7 +; CHECK: beq LBB0 ; CHECK: blx ___muldf3 ; <label>:3 switch i32 %1, label %4 [ diff --git a/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll b/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll new file mode 100644 index 0000000..ed55bb5 --- /dev/null +++ b/test/CodeGen/Thumb/2011-05-11-DAGLegalizer.ll @@ -0,0 +1,60 @@ +; RUN: llc -mtriple=thumbv6-apple-darwin < %s +; rdar://problem/9416774 +; ModuleID = 'reduced.ll' + +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-ios" + +%struct.MMMMMMMMMMMM = type { [4 x %struct.RRRRRRRR] } +%struct.RRRRRRRR = type { [78 x i32] } + +@kkkkkk = external constant i8* +@__PRETTY_FUNCTION__._ZN12CLGll = private unnamed_addr constant [62 x i8] c"static void tttttttttttt::lllllllllllll(const MMMMMMMMMMMM &)\00" +@.str = private unnamed_addr constant [75 x i8] c"\09GGGGGGGGGGGGGGGGGGGGGGG:,BE:0x%08lx,ALM:0x%08lx,LTO:0x%08lx,CBEE:0x%08lx\0A\00" + +define void @_ZN12CLGll(%struct.MMMMMMMMMMMM* %aidData) ssp align 2 { +entry: + %aidData.addr = alloca %struct.MMMMMMMMMMMM*, align 4 + %agg.tmp = alloca %struct.RRRRRRRR, align 4 + %agg.tmp4 = alloca %struct.RRRRRRRR, align 4 + %agg.tmp10 = alloca %struct.RRRRRRRR, align 4 + %agg.tmp16 = alloca %struct.RRRRRRRR, align 4 + store %struct.MMMMMMMMMMMM* %aidData, %struct.MMMMMMMMMMMM** %aidData.addr, align 4 + br label %do.body + +do.body: ; preds = %entry + %tmp = load i8** @kkkkkk, align 4 + %tmp1 = load %struct.MMMMMMMMMMMM** %aidData.addr + %eph = getelementptr inbounds %struct.MMMMMMMMMMMM* %tmp1, i32 0, i32 0 + %arrayidx = getelementptr inbounds [4 x %struct.RRRRRRRR]* %eph, i32 0, i32 0 + %tmp2 = bitcast %struct.RRRRRRRR* %agg.tmp to i8* + %tmp3 = bitcast %struct.RRRRRRRR* %arrayidx to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* %tmp3, i32 312, i32 4, i1 false) + %tmp5 = load %struct.MMMMMMMMMMMM** %aidData.addr + %eph6 = getelementptr inbounds %struct.MMMMMMMMMMMM* %tmp5, i32 0, i32 0 + %arrayidx7 = getelementptr inbounds [4 x %struct.RRRRRRRR]* %eph6, i32 0, i32 1 + %tmp8 = bitcast %struct.RRRRRRRR* %agg.tmp4 to i8* + %tmp9 = bitcast %struct.RRRRRRRR* %arrayidx7 to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp8, i8* %tmp9, i32 312, i32 4, i1 false) + %tmp11 = load %struct.MMMMMMMMMMMM** %aidData.addr + %eph12 = getelementptr inbounds %struct.MMMMMMMMMMMM* %tmp11, i32 0, i32 0 + %arrayidx13 = getelementptr inbounds [4 x %struct.RRRRRRRR]* %eph12, i32 0, i32 2 + %tmp14 = bitcast %struct.RRRRRRRR* %agg.tmp10 to i8* + %tmp15 = bitcast %struct.RRRRRRRR* %arrayidx13 to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp14, i8* %tmp15, i32 312, i32 4, i1 false) + %tmp17 = load %struct.MMMMMMMMMMMM** %aidData.addr + %eph18 = getelementptr inbounds %struct.MMMMMMMMMMMM* %tmp17, i32 0, i32 0 + %arrayidx19 = getelementptr inbounds [4 x %struct.RRRRRRRR]* %eph18, i32 0, i32 3 + %tmp20 = bitcast %struct.RRRRRRRR* %agg.tmp16 to i8* + %tmp21 = bitcast %struct.RRRRRRRR* %arrayidx19 to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp20, i8* %tmp21, i32 312, i32 4, i1 false) + call void (i8*, i32, i8*, i8*, ...)* @CLLoggingLog(i8* %tmp, i32 2, i8* getelementptr inbounds ([62 x i8]* @__PRETTY_FUNCTION__._ZN12CLGll, i32 0, i32 0), i8* getelementptr inbounds ([75 x i8]* @.str, i32 0, i32 0), %struct.RRRRRRRR* byval %agg.tmp, %struct.RRRRRRRR* byval %agg.tmp4, %struct.RRRRRRRR* byval %agg.tmp10, %struct.RRRRRRRR* byval %agg.tmp16) + br label %do.end + +do.end: ; preds = %do.body + ret void +} + +declare void @CLLoggingLog(i8*, i32, i8*, i8*, ...) + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind diff --git a/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll b/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll new file mode 100644 index 0000000..d39a760 --- /dev/null +++ b/test/CodeGen/Thumb/2011-06-16-NoGPRs.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s +; +; This test would crash because isel creates a GPR register for the return +; value from f1. The register is only used by tBLXr_r9 which accepts a full GPR +; register, but we cannot have live GPRs in thumb mode because we don't know how +; to spill them. +; +; <rdar://problem/9624323> +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv6-apple-darwin10" + +%0 = type opaque + +declare i8* (i8*, i8*, ...)* @f1(i8*, i8*) optsize +declare i8* @f2(i8*, i8*, ...) + +define internal void @f(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize ssp { +entry: + %call14 = tail call i8* (i8*, i8*, ...)* (i8*, i8*)* @f1(i8* undef, i8* %_cmd) optsize + %0 = bitcast i8* (i8*, i8*, ...)* %call14 to void (i8*, i8*, %0*, %0*)* + tail call void %0(i8* %self, i8* %_cmd, %0* %inObjects, %0* %inIndexes) optsize + tail call void bitcast (i8* (i8*, i8*, ...)* @f2 to void (i8*, i8*, i32, %0*, %0*)*)(i8* %self, i8* undef, i32 2, %0* %inIndexes, %0* undef) optsize + ret void +} diff --git a/test/CodeGen/Thumb/rev.ll b/test/CodeGen/Thumb/rev.ll new file mode 100644 index 0000000..5e163f8 --- /dev/null +++ b/test/CodeGen/Thumb/rev.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -march=thumb -mattr=+v6 | FileCheck %s + +define i32 @test1(i32 %X) nounwind { +; CHECK: test1 +; CHECK: rev16 r0, r0 + %tmp1 = lshr i32 %X, 8 + %X15 = bitcast i32 %X to i32 + %tmp4 = shl i32 %X15, 8 + %tmp2 = and i32 %tmp1, 16711680 + %tmp5 = and i32 %tmp4, -16777216 + %tmp9 = and i32 %tmp1, 255 + %tmp13 = and i32 %tmp4, 65280 + %tmp6 = or i32 %tmp5, %tmp2 + %tmp10 = or i32 %tmp6, %tmp13 + %tmp14 = or i32 %tmp10, %tmp9 + ret i32 %tmp14 +} + +define i32 @test2(i32 %X) nounwind { +; CHECK: test2 +; CHECK: revsh r0, r0 + %tmp1 = lshr i32 %X, 8 + %tmp1.upgrd.1 = trunc i32 %tmp1 to i16 + %tmp3 = trunc i32 %X to i16 + %tmp2 = and i16 %tmp1.upgrd.1, 255 + %tmp4 = shl i16 %tmp3, 8 + %tmp5 = or i16 %tmp2, %tmp4 + %tmp5.upgrd.2 = sext i16 %tmp5 to i32 + ret i32 %tmp5.upgrd.2 +} + +; rdar://9147637 +define i32 @test3(i16 zeroext %a) nounwind { +entry: +; CHECK: test3: +; CHECK: revsh r0, r0 + %0 = tail call i16 @llvm.bswap.i16(i16 %a) + %1 = sext i16 %0 to i32 + ret i32 %1 +} + +declare i16 @llvm.bswap.i16(i16) nounwind readnone + +define i32 @test4(i16 zeroext %a) nounwind { +entry: +; CHECK: test4: +; CHECK: revsh r0, r0 + %conv = zext i16 %a to i32 + %shr9 = lshr i16 %a, 8 + %conv2 = zext i16 %shr9 to i32 + %shl = shl nuw nsw i32 %conv, 8 + %or = or i32 %conv2, %shl + %sext = shl i32 %or, 16 + %conv8 = ashr exact i32 %sext, 16 + ret i32 %conv8 +} diff --git a/test/CodeGen/Thumb/select.ll b/test/CodeGen/Thumb/select.ll index 780e5fa..3f10b05 100644 --- a/test/CodeGen/Thumb/select.ll +++ b/test/CodeGen/Thumb/select.ll @@ -1,10 +1,5 @@ -; RUN: llc < %s -march=thumb | grep beq | count 1 -; RUN: llc < %s -march=thumb | grep bgt | count 1 -; RUN: llc < %s -march=thumb | grep blt | count 3 -; RUN: llc < %s -march=thumb | grep ble | count 1 -; RUN: llc < %s -march=thumb | grep bls | count 1 -; RUN: llc < %s -march=thumb | grep bhi | count 1 -; RUN: llc < %s -mtriple=thumb-apple-darwin | grep __ltdf2 +; RUN: llc < %s -mtriple=thumb-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=thumb-pc-linux-gnueabi | FileCheck -check-prefix=CHECK-EABI %s define i32 @f1(i32 %a.s) { entry: @@ -12,6 +7,10 @@ entry: %tmp1.s = select i1 %tmp, i32 2, i32 3 ret i32 %tmp1.s } +; CHECK: f1: +; CHECK: beq +; CHECK-EABI: f1: +; CHECK-EABI: beq define i32 @f2(i32 %a.s) { entry: @@ -19,6 +18,10 @@ entry: %tmp1.s = select i1 %tmp, i32 2, i32 3 ret i32 %tmp1.s } +; CHECK: f2: +; CHECK: bgt +; CHECK-EABI: f2: +; CHECK-EABI: bgt define i32 @f3(i32 %a.s, i32 %b.s) { entry: @@ -26,6 +29,10 @@ entry: %tmp1.s = select i1 %tmp, i32 2, i32 3 ret i32 %tmp1.s } +; CHECK: f3: +; CHECK: blt +; CHECK-EABI: f3: +; CHECK-EABI: blt define i32 @f4(i32 %a.s, i32 %b.s) { entry: @@ -33,6 +40,10 @@ entry: %tmp1.s = select i1 %tmp, i32 2, i32 3 ret i32 %tmp1.s } +; CHECK: f4: +; CHECK: ble +; CHECK-EABI: f4: +; CHECK-EABI: ble define i32 @f5(i32 %a.u, i32 %b.u) { entry: @@ -40,6 +51,10 @@ entry: %tmp1.s = select i1 %tmp, i32 2, i32 3 ret i32 %tmp1.s } +; CHECK: f5: +; CHECK: bls +; CHECK-EABI: f5: +; CHECK-EABI: bls define i32 @f6(i32 %a.u, i32 %b.u) { entry: @@ -47,9 +62,21 @@ entry: %tmp1.s = select i1 %tmp, i32 2, i32 3 ret i32 %tmp1.s } +; CHECK: f6: +; CHECK: bhi +; CHECK-EABI: f6: +; CHECK-EABI: bhi define double @f7(double %a, double %b) { %tmp = fcmp olt double %a, 1.234e+00 %tmp1 = select i1 %tmp, double -1.000e+00, double %b ret double %tmp1 } +; CHECK: f7: +; CHECK: blt +; CHECK: blt +; CHECK: __ltdf2 +; CHECK-EABI: f7: +; CHECK-EABI: __aeabi_dcmplt +; CHECK-EABI: bne +; CHECK-EABI: bne diff --git a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll index 789a891..9aee910 100644 --- a/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll +++ b/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll @@ -12,8 +12,8 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) { ; CHECK: _ZNKSs7compareERKSs: ; CHECK: it eq -; CHECK-NEXT: subeq r0, r{{[0-9]+}}, r{{[0-9]+}} -; CHECK-NEXT: ldmia.w sp!, {r4, r5, r6, r7, r8, pc} +; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-NEXT: ldmia.w sp!, entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this) ; <i32> [#uses=3] %1 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) ; <i32> [#uses=3] diff --git a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll index 41f7f29..47d7a9c 100644 --- a/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll +++ b/test/CodeGen/Thumb2/2010-08-10-VarSizedAllocaBug.ll @@ -7,8 +7,8 @@ entry: ; CHECK: Callee: ; CHECK: push ; CHECK: mov r4, sp -; CHECK: sub.w r12, r4, #1000 -; CHECK: mov sp, r12 +; CHECK: sub.w [[R12:r[0-9]+]], r4, #1000 +; CHECK: mov sp, [[R12]] %0 = icmp eq i32 %i, 0 ; <i1> [#uses=1] br i1 %0, label %bb2, label %bb diff --git a/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll b/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll new file mode 100644 index 0000000..604a352 --- /dev/null +++ b/test/CodeGen/Thumb2/2011-04-21-FILoweringBug.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s + +; Use sp, #imm to lower frame indices when the offset is multiple of 4 +; and in the range of 0-1020. This saves code size by utilizing +; 16-bit instructions. +; rdar://9321541 + +define i32 @t() nounwind { +entry: +; CHECK: t: +; CHECK: sub sp, #12 +; CHECK-NOT: sub +; CHECK: add r0, sp, #4 +; CHECK: add r1, sp, #8 +; CHECK: mov r2, sp + %size = alloca i32, align 4 + %count = alloca i32, align 4 + %index = alloca i32, align 4 + %0 = call i32 @foo(i32* %count, i32* %size, i32* %index) nounwind + ret i32 %0 +} + +declare i32 @foo(i32*, i32*, i32*) diff --git a/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll b/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll new file mode 100644 index 0000000..9e6d78e --- /dev/null +++ b/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll @@ -0,0 +1,36 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +%struct.op = type { %struct.op*, %struct.op*, %struct.op* ()*, i32, i16, i16, i8, i8 } + +; CHECK: Perl_ck_sort +; CHECK: ldr +; CHECK: mov [[REGISTER:(r[0-9]+)|(lr)]] +; CHECK: str {{(r[0-9])|(lr)}}, {{\[}}[[REGISTER]]{{\]}}, #24 + +define void @Perl_ck_sort() nounwind optsize { +entry: + %tmp27 = load %struct.op** undef, align 4 + switch i16 undef, label %if.end151 [ + i16 178, label %if.then60 + i16 177, label %if.then60 + ] + +if.then60: ; preds = %if.then40 + br i1 undef, label %if.then67, label %if.end95 + +if.then67: ; preds = %if.then60 + %op_next71 = getelementptr inbounds %struct.op* %tmp27, i32 0, i32 0 + store %struct.op* %tmp27, %struct.op** %op_next71, align 4 + %0 = getelementptr inbounds %struct.op* %tmp27, i32 1, i32 0 + br label %if.end95 + +if.end95: ; preds = %if.else92, %if.then67 + %.pre-phi = phi %struct.op** [ undef, %if.then60 ], [ %0, %if.then67 ] + %tmp98 = load %struct.op** %.pre-phi, align 4 + br label %if.end151 + +if.end151: ; preds = %if.end100, %if.end, %entry + ret void +} diff --git a/test/CodeGen/Thumb2/bfi.ll b/test/CodeGen/Thumb2/bfi.ll index 0405d98..3612e27 100644 --- a/test/CodeGen/Thumb2/bfi.ll +++ b/test/CodeGen/Thumb2/bfi.ll @@ -30,9 +30,8 @@ entry: define i32 @f3(i32 %A, i32 %B) nounwind readnone optsize { entry: ; CHECK: f3 -; CHECK: lsrs r2, r0, #7 -; CHECK: mov r0, r1 -; CHECK: bfi r0, r2, #7, #16 +; CHECK: lsrs {{.*}}, #7 +; CHECK: bfi {{.*}}, #7, #16 %and = and i32 %A, 8388480 ; <i32> [#uses=1] %and2 = and i32 %B, -8388481 ; <i32> [#uses=1] %or = or i32 %and2, %and ; <i32> [#uses=1] @@ -42,8 +41,8 @@ entry: ; rdar://8752056 define i32 @f4(i32 %a) nounwind { ; CHECK: f4 -; CHECK: movw r1, #3137 -; CHECK: bfi r1, r0, #15, #5 +; CHECK: movw [[R1:r[0-9]+]], #3137 +; CHECK: bfi [[R1]], {{.*}}, #15, #5 %1 = shl i32 %a, 15 %ins7 = and i32 %1, 1015808 %ins12 = or i32 %ins7, 3137 @@ -53,7 +52,7 @@ define i32 @f4(i32 %a) nounwind { ; rdar://9177502 define i32 @f5(i32 %a, i32 %b) nounwind readnone { entry: -; CHECK f5 +; CHECK: f5 ; CHECK-NOT: bfi r0, r2, #0, #1 %and = and i32 %a, 2 %b.masked = and i32 %b, -2 diff --git a/test/CodeGen/Thumb2/ldr-str-imm12.ll b/test/CodeGen/Thumb2/ldr-str-imm12.ll index 08265b8..e1932bd 100644 --- a/test/CodeGen/Thumb2/ldr-str-imm12.ll +++ b/test/CodeGen/Thumb2/ldr-str-imm12.ll @@ -22,7 +22,7 @@ define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind { entry: -; CHECK: ldr.w {{(r[0-9])|(lr)}}, [r7, #28] +; CHECK: ldr.w {{(r[0-9]+)|(lr)}}, [r7, #28] %xgaps.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] %ycomp.i = alloca [32 x %union.rec*], align 4 ; <[32 x %union.rec*]*> [#uses=0] br label %bb20 diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 5e776dd..ee054a1 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -14,19 +14,19 @@ entry: bb.nph: ; preds = %entry ; CHECK: BB#1 -; CHECK: movw r2, :lower16:L_GV$non_lazy_ptr -; CHECK: movt r2, :upper16:L_GV$non_lazy_ptr -; CHECK: ldr r2, [r2] -; CHECK: ldr r3, [r2] +; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr +; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr +; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] +; CHECK: ldr{{.*}}, [r[[R2b]] ; CHECK: LBB0_2 ; CHECK-NOT: LCPI0_0: ; PIC: BB#1 -; PIC: movw r2, :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) -; PIC: movt r2, :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) -; PIC: add r2, pc -; PIC: ldr r2, [r2] -; PIC: ldr r3, [r2] +; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) +; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) +; PIC: add r[[R2]], pc +; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] +; PIC: ldr{{.*}}, [r[[R2b]] ; PIC: LBB0_2 ; PIC-NOT: LCPI0_0: ; PIC: .section @@ -88,10 +88,10 @@ define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone { bb.nph: ; CHECK: bb.nph ; CHECK: movw {{(r[0-9])|(lr)}}, #32768 -; CHECK: movs {{(r[0-9])|(lr)}}, #8 -; CHECK: movw [[REGISTER:(r[0-9])|(lr)]], #16386 -; CHECK: movw {{(r[0-9])|(lr)}}, #65534 -; CHECK: movt {{(r[0-9])|(lr)}}, #65535 +; CHECK: movs {{(r[0-9]+)|(lr)}}, #0 +; CHECK: movw [[REGISTER:(r[0-9]+)|(lr)]], #16386 +; CHECK: movw {{(r[0-9]+)|(lr)}}, #65534 +; CHECK: movt {{(r[0-9]+)|(lr)}}, #65535 br label %bb bb: ; preds = %bb, %bb.nph diff --git a/test/CodeGen/Thumb2/thumb2-cbnz.ll b/test/CodeGen/Thumb2/thumb2-cbnz.ll index 10a4985..0992fa8 100644 --- a/test/CodeGen/Thumb2/thumb2-cbnz.ll +++ b/test/CodeGen/Thumb2/thumb2-cbnz.ll @@ -3,26 +3,29 @@ declare double @floor(double) nounwind readnone -define void @t(i1 %a, double %b) { +define void @t(i32 %c, double %b) { entry: - br i1 %a, label %bb3, label %bb1 + %cmp1 = icmp ne i32 %c, 0 + br i1 %cmp1, label %bb3, label %bb1 bb1: ; preds = %entry unreachable bb3: ; preds = %entry - br i1 %a, label %bb7, label %bb5 + %cmp2 = icmp ne i32 %c, 0 + br i1 %cmp2, label %bb7, label %bb5 bb5: ; preds = %bb3 unreachable bb7: ; preds = %bb3 - br i1 %a, label %bb11, label %bb9 + %cmp3 = icmp ne i32 %c, 0 + br i1 %cmp3, label %bb11, label %bb9 bb9: ; preds = %bb7 -; CHECK: cmp r0, #0 -; CHECK: cmp r0, #0 -; CHECK-NEXT: cbnz +; CHECK: cmp r0, #0 +; CHECK: cmp r0, #0 +; CHECK-NEXT: cbnz %0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0] br label %bb11 diff --git a/test/CodeGen/Thumb2/thumb2-cmn.ll b/test/CodeGen/Thumb2/thumb2-cmn.ll index eeaaa7f..df221b9 100644 --- a/test/CodeGen/Thumb2/thumb2-cmn.ll +++ b/test/CodeGen/Thumb2/thumb2-cmn.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -join-physregs | FileCheck %s + +; These tests implicitly depend on 'movs r0, #0' being rematerialized below the +; test as 'mov.w r0, #0'. So far, that requires physreg joining. define i1 @f1(i32 %a, i32 %b) { %nb = sub i32 0, %b diff --git a/test/CodeGen/Thumb2/thumb2-cmp.ll b/test/CodeGen/Thumb2/thumb2-cmp.ll index 63249f4..da12114 100644 --- a/test/CodeGen/Thumb2/thumb2-cmp.ll +++ b/test/CodeGen/Thumb2/thumb2-cmp.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -join-physregs | FileCheck %s + +; These tests implicitly depend on 'movs r0, #0' being rematerialized below the +; test as 'mov.w r0, #0'. So far, that requires physreg joining. ; 0x000000bb = 187 define i1 @f1(i32 %a) { diff --git a/test/CodeGen/Thumb2/thumb2-cmp2.ll b/test/CodeGen/Thumb2/thumb2-cmp2.ll index 55c321d..15052e0 100644 --- a/test/CodeGen/Thumb2/thumb2-cmp2.ll +++ b/test/CodeGen/Thumb2/thumb2-cmp2.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -join-physregs | FileCheck %s + +; These tests implicitly depend on 'movs r0, #0' being rematerialized below the +; test as 'mov.w r0, #0'. So far, that requires physreg joining. define i1 @f1(i32 %a, i32 %b) { ; CHECK: f1: diff --git a/test/CodeGen/Thumb2/thumb2-lsr3.ll b/test/CodeGen/Thumb2/thumb2-lsr3.ll index 5cfd3f5..e7ba782 100644 --- a/test/CodeGen/Thumb2/thumb2-lsr3.ll +++ b/test/CodeGen/Thumb2/thumb2-lsr3.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i1 @test1(i64 %poscnt, i32 %work) { entry: -; CHECK: rrx r0, r0 ; CHECK: lsrs.w r1, r1, #1 +; CHECK: rrx r0, r0 %0 = lshr i64 %poscnt, 1 %1 = icmp eq i64 %0, 0 ret i1 %1 @@ -11,8 +11,8 @@ entry: define i1 @test2(i64 %poscnt, i32 %work) { entry: -; CHECK: rrx r0, r0 ; CHECK: asrs.w r1, r1, #1 +; CHECK: rrx r0, r0 %0 = ashr i64 %poscnt, 1 %1 = icmp eq i64 %0, 0 ret i1 %1 diff --git a/test/CodeGen/Thumb2/thumb2-ror.ll b/test/CodeGen/Thumb2/thumb2-ror.ll index 0200116..590c333 100644 --- a/test/CodeGen/Thumb2/thumb2-ror.ll +++ b/test/CodeGen/Thumb2/thumb2-ror.ll @@ -1,11 +1,24 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; CHECK: f1: +; CHECK: ror.w r0, r0, #22 define i32 @f1(i32 %a) { %l8 = shl i32 %a, 10 %r8 = lshr i32 %a, 22 %tmp = or i32 %l8, %r8 ret i32 %tmp } -; CHECK: f1: -; CHECK: ror.w r0, r0, #22 + +; CHECK: f2: +; CHECK-NOT: and +; CHECK: ror +define i32 @f2(i32 %v, i32 %nbits) { +entry: + %and = and i32 %nbits, 31 + %shr = lshr i32 %v, %and + %sub = sub i32 32, %and + %shl = shl i32 %v, %sub + %or = or i32 %shl, %shr + ret i32 %or +}
\ No newline at end of file diff --git a/test/CodeGen/Thumb2/thumb2-ror2.ll b/test/CodeGen/Thumb2/thumb2-ror2.ll deleted file mode 100644 index ffd1dd7..0000000 --- a/test/CodeGen/Thumb2/thumb2-ror2.ll +++ /dev/null @@ -1,11 +0,0 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s - -define i32 @f1(i32 %a, i32 %b) { -; CHECK: f1: -; CHECK: rors r0, r1 - %db = sub i32 32, %b - %l8 = shl i32 %a, %b - %r8 = lshr i32 %a, %db - %tmp = or i32 %l8, %r8 - ret i32 %tmp -} diff --git a/test/CodeGen/Thumb2/thumb2-sbc.ll b/test/CodeGen/Thumb2/thumb2-sbc.ll index de6502d..53f45ea 100644 --- a/test/CodeGen/Thumb2/thumb2-sbc.ll +++ b/test/CodeGen/Thumb2/thumb2-sbc.ll @@ -39,7 +39,7 @@ define i64 @f5(i64 %a) { ; CHECK: f5 ; CHECK: subs r0, #2 ; CHECK: adc r1, r1, #-1448498775 - %tmp = sub i64 %a, 6221254862626095106 + %tmp = sub i64 %a, 6221254862626095106 ret i64 %tmp } @@ -48,7 +48,22 @@ define i64 @f6(i64 %a) { ; CHECK: f6 ; CHECK: subs r0, #2 ; CHECK: sbc r1, r1, #66846720 - %tmp = sub i64 %a, 287104476244869122 + %tmp = sub i64 %a, 287104476244869122 ret i64 %tmp } +; Example from numerics code that manually computes wider-than-64 values. +; +; CHECK: livecarry: +; CHECK: adds +; CHECK: adcs +; CHECK: adc +define i64 @livecarry(i64 %carry, i32 %digit) nounwind { + %ch = lshr i64 %carry, 32 + %cl = and i64 %carry, 4294967295 + %truncdigit = zext i32 %digit to i64 + %prod = add i64 %cl, %truncdigit + %ph = lshr i64 %prod, 32 + %carryresult = add i64 %ch, %ph + ret i64 %carryresult +} diff --git a/test/CodeGen/Thumb2/thumb2-sub3.ll b/test/CodeGen/Thumb2/thumb2-sub3.ll index 855ad06..1dbda57 100644 --- a/test/CodeGen/Thumb2/thumb2-sub3.ll +++ b/test/CodeGen/Thumb2/thumb2-sub3.ll @@ -4,7 +4,7 @@ define i64 @f1(i64 %a) { ; CHECK: f1 ; CHECK: subs r0, #171 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 171 ret i64 %tmp } @@ -13,7 +13,7 @@ define i64 @f1(i64 %a) { define i64 @f2(i64 %a) { ; CHECK: f2 ; CHECK: subs.w r0, r0, #1179666 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 1179666 ret i64 %tmp } @@ -22,7 +22,7 @@ define i64 @f2(i64 %a) { define i64 @f3(i64 %a) { ; CHECK: f3 ; CHECK: subs.w r0, r0, #872428544 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 872428544 ret i64 %tmp } @@ -31,7 +31,7 @@ define i64 @f3(i64 %a) { define i64 @f4(i64 %a) { ; CHECK: f4 ; CHECK: subs.w r0, r0, #1448498774 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 1448498774 ret i64 %tmp } @@ -40,7 +40,7 @@ define i64 @f4(i64 %a) { define i64 @f5(i64 %a) { ; CHECK: f5 ; CHECK: subs.w r0, r0, #66846720 -; CHECK: adc r1, r1, #-1 +; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 66846720 ret i64 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-sub5.ll b/test/CodeGen/Thumb2/thumb2-sub5.ll index c3b56bc..6edd789 100644 --- a/test/CodeGen/Thumb2/thumb2-sub5.ll +++ b/test/CodeGen/Thumb2/thumb2-sub5.ll @@ -1,9 +1,10 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -mattr=+32bit | FileCheck %s define i64 @f1(i64 %a, i64 %b) { ; CHECK: f1: -; CHECK: subs r0, r0, r2 -; CHECK: sbcs r1, r3 +; CHECK: subs.w r0, r0, r2 +; To test dead_carry, +32bit prevents sbc conveting to 16-bit sbcs +; CHECK: sbc.w r1, r1, r3 %tmp = sub i64 %a, %b ret i64 %tmp } diff --git a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll index 4b685a8..f3d0edf 100644 --- a/test/CodeGen/Thumb2/thumb2-sxt_rot.ll +++ b/test/CodeGen/Thumb2/thumb2-sxt_rot.ll @@ -7,7 +7,7 @@ define i32 @test0(i8 %A) { ret i32 %B } -define i8 @test1(i32 %A) signext { +define signext i8 @test1(i32 %A) { ; CHECK: test1 ; CHECK: sxtb.w r0, r0, ror #8 %B = lshr i32 %A, 8 @@ -17,7 +17,7 @@ define i8 @test1(i32 %A) signext { ret i8 %E } -define i32 @test2(i32 %A, i32 %X) signext { +define signext i32 @test2(i32 %A, i32 %X) { ; CHECK: test2 ; CHECK: lsrs r0, r0, #8 ; CHECK: sxtab r0, r1, r0 diff --git a/test/CodeGen/Thumb2/thumb2-teq.ll b/test/CodeGen/Thumb2/thumb2-teq.ll index 69f0383..566408a 100644 --- a/test/CodeGen/Thumb2/thumb2-teq.ll +++ b/test/CodeGen/Thumb2/thumb2-teq.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -join-physregs | FileCheck %s +; These tests implicitly depend on 'movs r0, #0' being rematerialized below the +; test as 'mov.w r0, #0'. So far, that requires physreg joining. ; 0x000000bb = 187 define i1 @f1(i32 %a) { diff --git a/test/CodeGen/Thumb2/thumb2-teq2.ll b/test/CodeGen/Thumb2/thumb2-teq2.ll index 0f122f2..cdd3489 100644 --- a/test/CodeGen/Thumb2/thumb2-teq2.ll +++ b/test/CodeGen/Thumb2/thumb2-teq2.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -join-physregs | FileCheck %s + +; These tests implicitly depend on 'movs r0, #0' being rematerialized below the +; tst as 'mov.w r0, #0'. So far, that requires physreg joining. define i1 @f1(i32 %a, i32 %b) { ; CHECK: f1 diff --git a/test/CodeGen/Thumb2/thumb2-tst.ll b/test/CodeGen/Thumb2/thumb2-tst.ll index d905217..47f553f 100644 --- a/test/CodeGen/Thumb2/thumb2-tst.ll +++ b/test/CodeGen/Thumb2/thumb2-tst.ll @@ -1,5 +1,7 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -join-physregs | FileCheck %s +; These tests implicitly depend on 'movs r0, #0' being rematerialized below the +; tst as 'mov.w r0, #0'. So far, that requires physreg joining. ; 0x000000bb = 187 define i1 @f1(i32 %a) { diff --git a/test/CodeGen/Thumb2/thumb2-tst2.ll b/test/CodeGen/Thumb2/thumb2-tst2.ll index db202dd..405b3bb 100644 --- a/test/CodeGen/Thumb2/thumb2-tst2.ll +++ b/test/CodeGen/Thumb2/thumb2-tst2.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2 -join-physregs | FileCheck %s + +; These tests implicitly depend on 'movs r0, #0' being rematerialized below the +; tst as 'mov.w r0, #0'. So far, that requires physreg joining. define i1 @f1(i32 %a, i32 %b) { ; CHECK: f1: diff --git a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll index b8e4381..03189aa 100644 --- a/test/CodeGen/Thumb2/thumb2-uxt_rot.ll +++ b/test/CodeGen/Thumb2/thumb2-uxt_rot.ll @@ -1,13 +1,13 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s -define i8 @test1(i32 %A.u) zeroext { +define zeroext i8 @test1(i32 %A.u) { ; CHECK: test1 ; CHECK: uxtb r0, r0 %B.u = trunc i32 %A.u to i8 ret i8 %B.u } -define i32 @test2(i32 %A.u, i32 %B.u) zeroext { +define zeroext i32 @test2(i32 %A.u, i32 %B.u) { ; CHECK: test2 ; CHECK: uxtab r0, r0, r1 %C.u = trunc i32 %B.u to i8 @@ -16,7 +16,7 @@ define i32 @test2(i32 %A.u, i32 %B.u) zeroext { ret i32 %E.u } -define i32 @test3(i32 %A.u) zeroext { +define zeroext i32 @test3(i32 %A.u) { ; CHECK: test3 ; CHECK: uxth.w r0, r0, ror #8 %B.u = lshr i32 %A.u, 8 diff --git a/test/CodeGen/Thumb2/thumb2-uxtb.ll b/test/CodeGen/Thumb2/thumb2-uxtb.ll index 2074f98..35914b1 100644 --- a/test/CodeGen/Thumb2/thumb2-uxtb.ll +++ b/test/CodeGen/Thumb2/thumb2-uxtb.ll @@ -128,9 +128,9 @@ define i32 @test10(i32 %p0) { ; ARMv7M: test10 ; ARMv7M: mov.w r1, #16253176 +; ARMv7M: mov.w r2, #458759 ; ARMv7M: and.w r0, r1, r0, lsr #7 -; ARMv7M: mov.w r1, #458759 -; ARMv7M: and.w r1, r1, r0, lsr #5 +; ARMv7M: and.w r1, r2, r0, lsr #5 ; ARMv7M: orrs r0, r1 %tmp1 = lshr i32 %p0, 7 ; <i32> [#uses=1] %tmp2 = and i32 %tmp1, 16253176 ; <i32> [#uses=2] diff --git a/test/CodeGen/X86/2006-05-22-FPSetEQ.ll b/test/CodeGen/X86/2006-05-22-FPSetEQ.ll index 35b0159..6c5a4fb 100644 --- a/test/CodeGen/X86/2006-05-22-FPSetEQ.ll +++ b/test/CodeGen/X86/2006-05-22-FPSetEQ.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 | grep setnp -; RUN: llc < %s -march=x86 -enable-unsafe-fp-math -enable-no-nans-fp-math | \ +; RUN: llc < %s -march=x86 -mattr=-sse | grep setnp +; RUN: llc < %s -march=x86 -mattr=-sse -enable-unsafe-fp-math -enable-no-nans-fp-math | \ ; RUN: not grep setnp define i32 @test(float %f) { diff --git a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll index a662dd5..11c0bf9 100644 --- a/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll +++ b/test/CodeGen/X86/2007-04-25-MMX-PADDQ.ll @@ -8,8 +8,8 @@ entry: bb26: ; preds = %bb26, %entry -; CHECK: addl %e -; CHECK: adcl %e +; CHECK: addl +; CHECK: adcl %i.037.0 = phi i32 [ 0, %entry ], [ %tmp25, %bb26 ] ; <i32> [#uses=3] %sum.035.0 = phi <1 x i64> [ zeroinitializer, %entry ], [ %tmp22, %bb26 ] ; <<1 x i64>> [#uses=1] diff --git a/test/CodeGen/X86/2007-05-05-Personality.ll b/test/CodeGen/X86/2007-05-05-Personality.ll index a9b17d3..0f49d2e 100644 --- a/test/CodeGen/X86/2007-05-05-Personality.ll +++ b/test/CodeGen/X86/2007-05-05-Personality.ll @@ -1,4 +1,7 @@ -; RUN: llc < %s -mtriple=i686-pc-linux-gnu -o - | grep zPL +; RUN: llc < %s -mtriple=i686-pc-linux-gnu -o - | FileCheck %s + +; CHECK: .cfi_personality 0, __gnat_eh_personality +; CHECK: .cfi_lsda 0, .Lexception0 @error = external global i8 ; <i8*> [#uses=2] diff --git a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll index ae49bd0..22e2750 100644 --- a/test/CodeGen/X86/2007-05-07-InvokeSRet.ll +++ b/test/CodeGen/X86/2007-05-07-InvokeSRet.ll @@ -7,7 +7,7 @@ declare void @invokee(%struct.S* sret ) define void @invoker(%struct.S* %name.0.0) { entry: - invoke void @invokee( %struct.S* %name.0.0 sret ) + invoke void @invokee( %struct.S* sret %name.0.0 ) to label %return unwind label %return return: ; preds = %entry, %entry diff --git a/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll b/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll index 8ef2538..ecc5835 100644 --- a/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll +++ b/test/CodeGen/X86/2007-05-14-LiveIntervalAssert.ll @@ -3,7 +3,7 @@ %struct.XDesc = type <{ i32, %struct.OpaqueXDataStorageType** }> %struct.OpaqueXDataStorageType = type opaque -declare i16 @GetParamDesc(%struct.XDesc*, i32, i32, %struct.XDesc*) signext +declare signext i16 @GetParamDesc(%struct.XDesc*, i32, i32, %struct.XDesc*) declare void @r_raise(i64, i8*, ...) @@ -18,7 +18,7 @@ cond_true109: ; preds = %entry br i1 false, label %cond_next164, label %cond_true239 cond_next164: ; preds = %cond_true109 - %tmp176 = call i16 @GetParamDesc( %struct.XDesc* null, i32 1701999219, i32 1413830740, %struct.XDesc* null ) signext ; <i16> [#uses=0] + %tmp176 = call signext i16 @GetParamDesc( %struct.XDesc* null, i32 1701999219, i32 1413830740, %struct.XDesc* null ) call void (i64, i8*, ...)* @r_raise( i64 0, i8* null ) unreachable diff --git a/test/CodeGen/X86/2007-06-04-tailmerge4.ll b/test/CodeGen/X86/2007-06-04-tailmerge4.ll deleted file mode 100644 index d5ec089..0000000 --- a/test/CodeGen/X86/2007-06-04-tailmerge4.ll +++ /dev/null @@ -1,454 +0,0 @@ -; RUN: llc < %s -asm-verbose | grep invcont131 -; PR 1496: tail merge was incorrectly removing this block - -; ModuleID = 'report.1.bc' -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" -target triple = "i686-pc-linux-gnu" - %struct.ALLOC = type { %struct.string___XUB, [2 x i8] } - %struct.RETURN = type { i32, i32, i32, i64 } - %struct.ada__streams__root_stream_type = type { %struct.ada__tags__dispatch_table* } - %struct.ada__tags__dispatch_table = type { [1 x i8*] } - %struct.ada__text_io__text_afcb = type { %struct.system__file_control_block__afcb, i32, i32, i32, i32, i32, %struct.ada__text_io__text_afcb*, i8, i8 } - %struct.string___XUB = type { i32, i32 } - %struct.string___XUP = type { i8*, %struct.string___XUB* } - %struct.system__file_control_block__afcb = type { %struct.ada__streams__root_stream_type, i32, %struct.string___XUP, i32, %struct.string___XUP, i8, i8, i8, i8, i8, i8, i8, %struct.system__file_control_block__afcb*, %struct.system__file_control_block__afcb* } - %struct.system__secondary_stack__mark_id = type { i8*, i32 } - %struct.wide_string___XUP = type { i16*, %struct.string___XUB* } -@report_E = global i8 0 ; <i8*> [#uses=0] -@report__test_status = internal global i8 1 ; <i8*> [#uses=8] -@report__test_name = internal global [15 x i8] zeroinitializer ; <[15 x i8]*> [#uses=10] -@report__test_name_len = internal global i32 0 ; <i32*> [#uses=15] -@.str = internal constant [12 x i8] c"report.adb\00\00" ; <[12 x i8]*> [#uses=1] -@C.26.599 = internal constant %struct.string___XUB { i32 1, i32 1 } ; <%struct.string___XUB*> [#uses=1] -@.str1 = internal constant [1 x i8] c":" ; <[1 x i8]*> [#uses=1] -@.str2 = internal constant [1 x i8] c" " ; <[1 x i8]*> [#uses=1] -@.str3 = internal constant [1 x i8] c"-" ; <[1 x i8]*> [#uses=1] -@.str5 = internal constant [10 x i8] c"0123456789" ; <[10 x i8]*> [#uses=12] -@C.59.855 = internal constant %struct.string___XUB { i32 1, i32 0 } ; <%struct.string___XUB*> [#uses=1] -@C.69.876 = internal constant %struct.string___XUB { i32 1, i32 3 } ; <%struct.string___XUB*> [#uses=1] -@C.70.879 = internal constant %struct.string___XUB { i32 1, i32 6 } ; <%struct.string___XUB*> [#uses=1] -@C.81.900 = internal constant %struct.string___XUB { i32 1, i32 5 } ; <%struct.string___XUB*> [#uses=1] -@.str6 = internal constant [0 x i8] zeroinitializer ; <[0 x i8]*> [#uses=1] -@.str7 = internal constant [3 x i8] c"2.5" ; <[3 x i8]*> [#uses=1] -@.str8 = internal constant [6 x i8] c"ACATS " ; <[6 x i8]*> [#uses=1] -@.str9 = internal constant [5 x i8] c",.,. " ; <[5 x i8]*> [#uses=1] -@.str10 = internal constant [1 x i8] c"." ; <[1 x i8]*> [#uses=1] -@.str11 = internal constant [5 x i8] c"---- " ; <[5 x i8]*> [#uses=1] -@.str12 = internal constant [5 x i8] c" - " ; <[5 x i8]*> [#uses=1] -@.str13 = internal constant [5 x i8] c" * " ; <[5 x i8]*> [#uses=1] -@.str14 = internal constant [5 x i8] c" + " ; <[5 x i8]*> [#uses=1] -@.str15 = internal constant [5 x i8] c" ! " ; <[5 x i8]*> [#uses=1] -@C.209.1380 = internal constant %struct.string___XUB { i32 1, i32 37 } ; <%struct.string___XUB*> [#uses=1] -@.str16 = internal constant [37 x i8] c" PASSED ============================." ; <[37 x i8]*> [#uses=1] -@.str17 = internal constant [5 x i8] c"==== " ; <[5 x i8]*> [#uses=1] -@.str18 = internal constant [37 x i8] c" NOT-APPLICABLE ++++++++++++++++++++." ; <[37 x i8]*> [#uses=1] -@.str19 = internal constant [5 x i8] c"++++ " ; <[5 x i8]*> [#uses=1] -@.str20 = internal constant [37 x i8] c" TENTATIVELY PASSED !!!!!!!!!!!!!!!!." ; <[37 x i8]*> [#uses=1] -@.str21 = internal constant [5 x i8] c"!!!! " ; <[5 x i8]*> [#uses=1] -@.str22 = internal constant [37 x i8] c" SEE '!' COMMENTS FOR SPECIAL NOTES!!" ; <[37 x i8]*> [#uses=1] -@.str23 = internal constant [37 x i8] c" FAILED ****************************." ; <[37 x i8]*> [#uses=1] -@.str24 = internal constant [5 x i8] c"**** " ; <[5 x i8]*> [#uses=1] -@__gnat_others_value = external constant i32 ; <i32*> [#uses=2] -@system__soft_links__abort_undefer = external global void ()* ; <void ()**> [#uses=1] -@C.320.1854 = internal constant %struct.string___XUB { i32 2, i32 6 } ; <%struct.string___XUB*> [#uses=1] - -declare void @report__put_msg(i64 %msg.0.0) - -declare void @__gnat_rcheck_05(i8*, i32) - -declare void @__gnat_rcheck_12(i8*, i32) - -declare %struct.ada__text_io__text_afcb* @ada__text_io__standard_output() - -declare void @ada__text_io__set_col(%struct.ada__text_io__text_afcb*, i32) - -declare void @ada__text_io__put_line(%struct.ada__text_io__text_afcb*, i64) - -declare void @report__time_stamp(%struct.string___XUP* sret %agg.result) - -declare i64 @ada__calendar__clock() - -declare void @ada__calendar__split(%struct.RETURN* sret , i64) - -declare void @system__string_ops_concat_5__str_concat_5(%struct.string___XUP* sret , i64, i64, i64, i64, i64) - -declare void @system__string_ops_concat_3__str_concat_3(%struct.string___XUP* sret , i64, i64, i64) - -declare i8* @system__secondary_stack__ss_allocate(i32) - -declare void @report__test(i64 %name.0.0, i64 %descr.0.0) - -declare void @system__secondary_stack__ss_mark(%struct.system__secondary_stack__mark_id* sret ) - -declare i8* @llvm.eh.exception() - -declare i32 @llvm.eh.selector(i8*, i8*, ...) - -declare i32 @llvm.eh.typeid.for(i8*) - -declare i32 @__gnat_eh_personality(...) - -declare i32 @_Unwind_Resume(...) - -declare void @__gnat_rcheck_07(i8*, i32) - -declare void @system__secondary_stack__ss_release(i64) - -declare void @report__comment(i64 %descr.0.0) - -declare void @report__failed(i64 %descr.0.0) - -declare void @report__not_applicable(i64 %descr.0.0) - -declare void @report__special_action(i64 %descr.0.0) - -define void @report__result() { -entry: - %tmp = alloca %struct.system__secondary_stack__mark_id, align 8 ; <%struct.system__secondary_stack__mark_id*> [#uses=3] - %A.210 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3] - %tmp5 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3] - %A.229 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3] - %tmp10 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3] - %A.248 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3] - %tmp15 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3] - %A.270 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3] - %tmp20 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3] - %A.284 = alloca %struct.string___XUB, align 8 ; <%struct.string___XUB*> [#uses=3] - %tmp25 = alloca %struct.string___XUP, align 8 ; <%struct.string___XUP*> [#uses=3] - call void @system__secondary_stack__ss_mark( %struct.system__secondary_stack__mark_id* %tmp sret ) - %tmp28 = getelementptr %struct.system__secondary_stack__mark_id* %tmp, i32 0, i32 0 ; <i8**> [#uses=1] - %tmp29 = load i8** %tmp28 ; <i8*> [#uses=2] - %tmp31 = getelementptr %struct.system__secondary_stack__mark_id* %tmp, i32 0, i32 1 ; <i32*> [#uses=1] - %tmp32 = load i32* %tmp31 ; <i32> [#uses=2] - %tmp33 = load i8* @report__test_status ; <i8> [#uses=1] - switch i8 %tmp33, label %bb483 [ - i8 0, label %bb - i8 2, label %bb143 - i8 3, label %bb261 - ] - -bb: ; preds = %entry - %tmp34 = load i32* @report__test_name_len ; <i32> [#uses=4] - %tmp35 = icmp sgt i32 %tmp34, 0 ; <i1> [#uses=2] - %tmp40 = icmp sgt i32 %tmp34, 15 ; <i1> [#uses=1] - %bothcond139 = and i1 %tmp35, %tmp40 ; <i1> [#uses=1] - br i1 %bothcond139, label %cond_true43, label %cond_next44 - -cond_true43: ; preds = %bb - invoke void @__gnat_rcheck_12( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 212 ) - to label %UnifiedUnreachableBlock unwind label %unwind - -unwind: ; preds = %invcont589, %cond_next567, %bb555, %cond_true497, %invcont249, %cond_next227, %bb215, %cond_true157, %invcont131, %cond_next109, %bb97, %cond_true43 - %eh_ptr = call i8* @llvm.eh.exception( ) ; <i8*> [#uses=1] - br label %cleanup717 - -cond_next44: ; preds = %bb - %tmp72 = getelementptr %struct.string___XUB* %A.210, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 1, i32* %tmp72 - %tmp73 = getelementptr %struct.string___XUB* %A.210, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %tmp34, i32* %tmp73 - br i1 %tmp35, label %cond_true80, label %cond_next109 - -cond_true80: ; preds = %cond_next44 - %tmp45.off = add i32 %tmp34, -1 ; <i32> [#uses=1] - %bothcond = icmp ugt i32 %tmp45.off, 14 ; <i1> [#uses=1] - br i1 %bothcond, label %bb97, label %cond_next109 - -bb97: ; preds = %cond_true80 - invoke void @__gnat_rcheck_05( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 212 ) - to label %UnifiedUnreachableBlock unwind label %unwind - -cond_next109: ; preds = %cond_true80, %cond_next44 - %A.210128 = ptrtoint %struct.string___XUB* %A.210 to i32 ; <i32> [#uses=1] - %A.210128129 = zext i32 %A.210128 to i64 ; <i64> [#uses=1] - %A.210128129130 = shl i64 %A.210128129, 32 ; <i64> [#uses=1] - %A.210128129130.ins = or i64 %A.210128129130, zext (i32 ptrtoint ([15 x i8]* @report__test_name to i32) to i64) ; <i64> [#uses=1] - invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp5 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str17 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.210128129130.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str16 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) ) - to label %invcont131 unwind label %unwind - -invcont131: ; preds = %cond_next109 - %tmp133 = getelementptr %struct.string___XUP* %tmp5, i32 0, i32 0 ; <i8**> [#uses=1] - %tmp134 = load i8** %tmp133 ; <i8*> [#uses=1] - %tmp134120 = ptrtoint i8* %tmp134 to i32 ; <i32> [#uses=1] - %tmp134120121 = zext i32 %tmp134120 to i64 ; <i64> [#uses=1] - %tmp136 = getelementptr %struct.string___XUP* %tmp5, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1] - %tmp137 = load %struct.string___XUB** %tmp136 ; <%struct.string___XUB*> [#uses=1] - %tmp137116 = ptrtoint %struct.string___XUB* %tmp137 to i32 ; <i32> [#uses=1] - %tmp137116117 = zext i32 %tmp137116 to i64 ; <i64> [#uses=1] - %tmp137116117118 = shl i64 %tmp137116117, 32 ; <i64> [#uses=1] - %tmp137116117118.ins = or i64 %tmp137116117118, %tmp134120121 ; <i64> [#uses=1] - invoke fastcc void @report__put_msg( i64 %tmp137116117118.ins ) - to label %cond_next618 unwind label %unwind - -bb143: ; preds = %entry - %tmp144 = load i32* @report__test_name_len ; <i32> [#uses=4] - %tmp147 = icmp sgt i32 %tmp144, 0 ; <i1> [#uses=2] - %tmp154 = icmp sgt i32 %tmp144, 15 ; <i1> [#uses=1] - %bothcond140 = and i1 %tmp147, %tmp154 ; <i1> [#uses=1] - br i1 %bothcond140, label %cond_true157, label %cond_next160 - -cond_true157: ; preds = %bb143 - invoke void @__gnat_rcheck_12( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 215 ) - to label %UnifiedUnreachableBlock unwind label %unwind - -cond_next160: ; preds = %bb143 - %tmp189 = getelementptr %struct.string___XUB* %A.229, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 1, i32* %tmp189 - %tmp190 = getelementptr %struct.string___XUB* %A.229, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %tmp144, i32* %tmp190 - br i1 %tmp147, label %cond_true197, label %cond_next227 - -cond_true197: ; preds = %cond_next160 - %tmp161.off = add i32 %tmp144, -1 ; <i32> [#uses=1] - %bothcond1 = icmp ugt i32 %tmp161.off, 14 ; <i1> [#uses=1] - br i1 %bothcond1, label %bb215, label %cond_next227 - -bb215: ; preds = %cond_true197 - invoke void @__gnat_rcheck_05( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 215 ) - to label %UnifiedUnreachableBlock unwind label %unwind - -cond_next227: ; preds = %cond_true197, %cond_next160 - %A.229105 = ptrtoint %struct.string___XUB* %A.229 to i32 ; <i32> [#uses=1] - %A.229105106 = zext i32 %A.229105 to i64 ; <i64> [#uses=1] - %A.229105106107 = shl i64 %A.229105106, 32 ; <i64> [#uses=1] - %A.229105106107.ins = or i64 %A.229105106107, zext (i32 ptrtoint ([15 x i8]* @report__test_name to i32) to i64) ; <i64> [#uses=1] - invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp10 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str19 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.229105106107.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str18 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) ) - to label %invcont249 unwind label %unwind - -invcont249: ; preds = %cond_next227 - %tmp251 = getelementptr %struct.string___XUP* %tmp10, i32 0, i32 0 ; <i8**> [#uses=1] - %tmp252 = load i8** %tmp251 ; <i8*> [#uses=1] - %tmp25297 = ptrtoint i8* %tmp252 to i32 ; <i32> [#uses=1] - %tmp2529798 = zext i32 %tmp25297 to i64 ; <i64> [#uses=1] - %tmp254 = getelementptr %struct.string___XUP* %tmp10, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1] - %tmp255 = load %struct.string___XUB** %tmp254 ; <%struct.string___XUB*> [#uses=1] - %tmp25593 = ptrtoint %struct.string___XUB* %tmp255 to i32 ; <i32> [#uses=1] - %tmp2559394 = zext i32 %tmp25593 to i64 ; <i64> [#uses=1] - %tmp255939495 = shl i64 %tmp2559394, 32 ; <i64> [#uses=1] - %tmp255939495.ins = or i64 %tmp255939495, %tmp2529798 ; <i64> [#uses=1] - invoke fastcc void @report__put_msg( i64 %tmp255939495.ins ) - to label %cond_next618 unwind label %unwind - -bb261: ; preds = %entry - %tmp262 = call i8* @llvm.stacksave( ) ; <i8*> [#uses=2] - %tmp263 = load i32* @report__test_name_len ; <i32> [#uses=4] - %tmp266 = icmp sgt i32 %tmp263, 0 ; <i1> [#uses=2] - %tmp273 = icmp sgt i32 %tmp263, 15 ; <i1> [#uses=1] - %bothcond141 = and i1 %tmp266, %tmp273 ; <i1> [#uses=1] - br i1 %bothcond141, label %cond_true276, label %cond_next281 - -cond_true276: ; preds = %bb261 - invoke void @__gnat_rcheck_12( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 218 ) - to label %UnifiedUnreachableBlock unwind label %unwind277 - -unwind277: ; preds = %invcont467, %cond_next442, %invcont370, %cond_next348, %bb336, %cond_true276 - %eh_ptr278 = call i8* @llvm.eh.exception( ) ; <i8*> [#uses=1] - call void @llvm.stackrestore( i8* %tmp262 ) - br label %cleanup717 - -cond_next281: ; preds = %bb261 - %tmp310 = getelementptr %struct.string___XUB* %A.248, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 1, i32* %tmp310 - %tmp311 = getelementptr %struct.string___XUB* %A.248, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %tmp263, i32* %tmp311 - br i1 %tmp266, label %cond_true318, label %cond_next348 - -cond_true318: ; preds = %cond_next281 - %tmp282.off = add i32 %tmp263, -1 ; <i32> [#uses=1] - %bothcond2 = icmp ugt i32 %tmp282.off, 14 ; <i1> [#uses=1] - br i1 %bothcond2, label %bb336, label %cond_next348 - -bb336: ; preds = %cond_true318 - invoke void @__gnat_rcheck_05( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 218 ) - to label %UnifiedUnreachableBlock unwind label %unwind277 - -cond_next348: ; preds = %cond_true318, %cond_next281 - %A.24882 = ptrtoint %struct.string___XUB* %A.248 to i32 ; <i32> [#uses=1] - %A.2488283 = zext i32 %A.24882 to i64 ; <i64> [#uses=1] - %A.248828384 = shl i64 %A.2488283, 32 ; <i64> [#uses=1] - %A.248828384.ins = or i64 %A.248828384, zext (i32 ptrtoint ([15 x i8]* @report__test_name to i32) to i64) ; <i64> [#uses=1] - invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp15 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str21 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.248828384.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str20 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) ) - to label %invcont370 unwind label %unwind277 - -invcont370: ; preds = %cond_next348 - %tmp372 = getelementptr %struct.string___XUP* %tmp15, i32 0, i32 0 ; <i8**> [#uses=1] - %tmp373 = load i8** %tmp372 ; <i8*> [#uses=1] - %tmp37374 = ptrtoint i8* %tmp373 to i32 ; <i32> [#uses=1] - %tmp3737475 = zext i32 %tmp37374 to i64 ; <i64> [#uses=1] - %tmp375 = getelementptr %struct.string___XUP* %tmp15, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1] - %tmp376 = load %struct.string___XUB** %tmp375 ; <%struct.string___XUB*> [#uses=1] - %tmp37670 = ptrtoint %struct.string___XUB* %tmp376 to i32 ; <i32> [#uses=1] - %tmp3767071 = zext i32 %tmp37670 to i64 ; <i64> [#uses=1] - %tmp376707172 = shl i64 %tmp3767071, 32 ; <i64> [#uses=1] - %tmp376707172.ins = or i64 %tmp376707172, %tmp3737475 ; <i64> [#uses=1] - invoke fastcc void @report__put_msg( i64 %tmp376707172.ins ) - to label %invcont381 unwind label %unwind277 - -invcont381: ; preds = %invcont370 - %tmp382 = load i32* @report__test_name_len ; <i32> [#uses=6] - %tmp415 = icmp sgt i32 %tmp382, -1 ; <i1> [#uses=1] - %max416 = select i1 %tmp415, i32 %tmp382, i32 0 ; <i32> [#uses=1] - %tmp417 = alloca i8, i32 %max416 ; <i8*> [#uses=3] - %tmp423 = icmp sgt i32 %tmp382, 0 ; <i1> [#uses=1] - br i1 %tmp423, label %bb427, label %cond_next442 - -bb427: ; preds = %invcont381 - store i8 32, i8* %tmp417 - %tmp434 = icmp eq i32 %tmp382, 1 ; <i1> [#uses=1] - br i1 %tmp434, label %cond_next442, label %cond_next438.preheader - -cond_next438.preheader: ; preds = %bb427 - %tmp. = add i32 %tmp382, -1 ; <i32> [#uses=1] - br label %cond_next438 - -cond_next438: ; preds = %cond_next438, %cond_next438.preheader - %indvar = phi i32 [ 0, %cond_next438.preheader ], [ %J130b.513.5, %cond_next438 ] ; <i32> [#uses=1] - %J130b.513.5 = add i32 %indvar, 1 ; <i32> [#uses=3] - %tmp43118 = getelementptr i8* %tmp417, i32 %J130b.513.5 ; <i8*> [#uses=1] - store i8 32, i8* %tmp43118 - %exitcond = icmp eq i32 %J130b.513.5, %tmp. ; <i1> [#uses=1] - br i1 %exitcond, label %cond_next442, label %cond_next438 - -cond_next442: ; preds = %cond_next438, %bb427, %invcont381 - %tmp448 = getelementptr %struct.string___XUB* %A.270, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 1, i32* %tmp448 - %tmp449 = getelementptr %struct.string___XUB* %A.270, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %tmp382, i32* %tmp449 - %tmp41762 = ptrtoint i8* %tmp417 to i32 ; <i32> [#uses=1] - %tmp4176263 = zext i32 %tmp41762 to i64 ; <i64> [#uses=1] - %A.27058 = ptrtoint %struct.string___XUB* %A.270 to i32 ; <i32> [#uses=1] - %A.2705859 = zext i32 %A.27058 to i64 ; <i64> [#uses=1] - %A.270585960 = shl i64 %A.2705859, 32 ; <i64> [#uses=1] - %A.270585960.ins = or i64 %tmp4176263, %A.270585960 ; <i64> [#uses=1] - invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp20 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str21 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.270585960.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str22 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) ) - to label %invcont467 unwind label %unwind277 - -invcont467: ; preds = %cond_next442 - %tmp469 = getelementptr %struct.string___XUP* %tmp20, i32 0, i32 0 ; <i8**> [#uses=1] - %tmp470 = load i8** %tmp469 ; <i8*> [#uses=1] - %tmp47050 = ptrtoint i8* %tmp470 to i32 ; <i32> [#uses=1] - %tmp4705051 = zext i32 %tmp47050 to i64 ; <i64> [#uses=1] - %tmp472 = getelementptr %struct.string___XUP* %tmp20, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1] - %tmp473 = load %struct.string___XUB** %tmp472 ; <%struct.string___XUB*> [#uses=1] - %tmp47346 = ptrtoint %struct.string___XUB* %tmp473 to i32 ; <i32> [#uses=1] - %tmp4734647 = zext i32 %tmp47346 to i64 ; <i64> [#uses=1] - %tmp473464748 = shl i64 %tmp4734647, 32 ; <i64> [#uses=1] - %tmp473464748.ins = or i64 %tmp473464748, %tmp4705051 ; <i64> [#uses=1] - invoke fastcc void @report__put_msg( i64 %tmp473464748.ins ) - to label %cleanup unwind label %unwind277 - -cleanup: ; preds = %invcont467 - call void @llvm.stackrestore( i8* %tmp262 ) - br label %cond_next618 - -bb483: ; preds = %entry - %tmp484 = load i32* @report__test_name_len ; <i32> [#uses=4] - %tmp487 = icmp sgt i32 %tmp484, 0 ; <i1> [#uses=2] - %tmp494 = icmp sgt i32 %tmp484, 15 ; <i1> [#uses=1] - %bothcond142 = and i1 %tmp487, %tmp494 ; <i1> [#uses=1] - br i1 %bothcond142, label %cond_true497, label %cond_next500 - -cond_true497: ; preds = %bb483 - invoke void @__gnat_rcheck_12( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 223 ) - to label %UnifiedUnreachableBlock unwind label %unwind - -cond_next500: ; preds = %bb483 - %tmp529 = getelementptr %struct.string___XUB* %A.284, i32 0, i32 0 ; <i32*> [#uses=1] - store i32 1, i32* %tmp529 - %tmp530 = getelementptr %struct.string___XUB* %A.284, i32 0, i32 1 ; <i32*> [#uses=1] - store i32 %tmp484, i32* %tmp530 - br i1 %tmp487, label %cond_true537, label %cond_next567 - -cond_true537: ; preds = %cond_next500 - %tmp501.off = add i32 %tmp484, -1 ; <i32> [#uses=1] - %bothcond3 = icmp ugt i32 %tmp501.off, 14 ; <i1> [#uses=1] - br i1 %bothcond3, label %bb555, label %cond_next567 - -bb555: ; preds = %cond_true537 - invoke void @__gnat_rcheck_05( i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0), i32 223 ) - to label %UnifiedUnreachableBlock unwind label %unwind - -cond_next567: ; preds = %cond_true537, %cond_next500 - %A.28435 = ptrtoint %struct.string___XUB* %A.284 to i32 ; <i32> [#uses=1] - %A.2843536 = zext i32 %A.28435 to i64 ; <i64> [#uses=1] - %A.284353637 = shl i64 %A.2843536, 32 ; <i64> [#uses=1] - %A.284353637.ins = or i64 %A.284353637, zext (i32 ptrtoint ([15 x i8]* @report__test_name to i32) to i64) ; <i64> [#uses=1] - invoke void @system__string_ops_concat_3__str_concat_3( %struct.string___XUP* %tmp25 sret , i64 or (i64 zext (i32 ptrtoint ([5 x i8]* @.str24 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.81.900 to i32) to i64), i64 32)), i64 %A.284353637.ins, i64 or (i64 zext (i32 ptrtoint ([37 x i8]* @.str23 to i32) to i64), i64 shl (i64 zext (i32 ptrtoint (%struct.string___XUB* @C.209.1380 to i32) to i64), i64 32)) ) - to label %invcont589 unwind label %unwind - -invcont589: ; preds = %cond_next567 - %tmp591 = getelementptr %struct.string___XUP* %tmp25, i32 0, i32 0 ; <i8**> [#uses=1] - %tmp592 = load i8** %tmp591 ; <i8*> [#uses=1] - %tmp59228 = ptrtoint i8* %tmp592 to i32 ; <i32> [#uses=1] - %tmp5922829 = zext i32 %tmp59228 to i64 ; <i64> [#uses=1] - %tmp594 = getelementptr %struct.string___XUP* %tmp25, i32 0, i32 1 ; <%struct.string___XUB**> [#uses=1] - %tmp595 = load %struct.string___XUB** %tmp594 ; <%struct.string___XUB*> [#uses=1] - %tmp59524 = ptrtoint %struct.string___XUB* %tmp595 to i32 ; <i32> [#uses=1] - %tmp5952425 = zext i32 %tmp59524 to i64 ; <i64> [#uses=1] - %tmp595242526 = shl i64 %tmp5952425, 32 ; <i64> [#uses=1] - %tmp595242526.ins = or i64 %tmp595242526, %tmp5922829 ; <i64> [#uses=1] - invoke fastcc void @report__put_msg( i64 %tmp595242526.ins ) - to label %cond_next618 unwind label %unwind - -cond_next618: ; preds = %invcont589, %cleanup, %invcont249, %invcont131 - store i8 1, i8* @report__test_status - store i32 7, i32* @report__test_name_len - store i8 78, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 0) - store i8 79, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 1) - store i8 95, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 2) - store i8 78, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 3) - store i8 65, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 4) - store i8 77, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 5) - store i8 69, i8* getelementptr ([15 x i8]* @report__test_name, i32 0, i32 6) - %CHAIN.310.0.0.0.val5.i = ptrtoint i8* %tmp29 to i32 ; <i32> [#uses=1] - %CHAIN.310.0.0.0.val56.i = zext i32 %CHAIN.310.0.0.0.val5.i to i64 ; <i64> [#uses=1] - %CHAIN.310.0.0.1.val2.i = zext i32 %tmp32 to i64 ; <i64> [#uses=1] - %CHAIN.310.0.0.1.val23.i = shl i64 %CHAIN.310.0.0.1.val2.i, 32 ; <i64> [#uses=1] - %CHAIN.310.0.0.1.val23.ins.i = or i64 %CHAIN.310.0.0.1.val23.i, %CHAIN.310.0.0.0.val56.i ; <i64> [#uses=1] - call void @system__secondary_stack__ss_release( i64 %CHAIN.310.0.0.1.val23.ins.i ) - ret void - -cleanup717: ; preds = %unwind277, %unwind - %eh_exception.0 = phi i8* [ %eh_ptr278, %unwind277 ], [ %eh_ptr, %unwind ] ; <i8*> [#uses=1] - %CHAIN.310.0.0.0.val5.i8 = ptrtoint i8* %tmp29 to i32 ; <i32> [#uses=1] - %CHAIN.310.0.0.0.val56.i9 = zext i32 %CHAIN.310.0.0.0.val5.i8 to i64 ; <i64> [#uses=1] - %CHAIN.310.0.0.1.val2.i10 = zext i32 %tmp32 to i64 ; <i64> [#uses=1] - %CHAIN.310.0.0.1.val23.i11 = shl i64 %CHAIN.310.0.0.1.val2.i10, 32 ; <i64> [#uses=1] - %CHAIN.310.0.0.1.val23.ins.i12 = or i64 %CHAIN.310.0.0.1.val23.i11, %CHAIN.310.0.0.0.val56.i9 ; <i64> [#uses=1] - call void @system__secondary_stack__ss_release( i64 %CHAIN.310.0.0.1.val23.ins.i12 ) - call i32 (...)* @_Unwind_Resume( i8* %eh_exception.0 ) ; <i32>:0 [#uses=0] - unreachable - -UnifiedUnreachableBlock: ; preds = %bb555, %cond_true497, %bb336, %cond_true276, %bb215, %cond_true157, %bb97, %cond_true43 - unreachable -} - -declare i8* @llvm.stacksave() - -declare void @llvm.stackrestore(i8*) - -declare i32 @report__ident_int(i32 %x) - -declare i8 @report__equal(i32 %x, i32 %y) - -declare i8 @report__ident_char(i8 zeroext %x) - -declare i16 @report__ident_wide_char(i16 zeroext %x) - -declare i8 @report__ident_bool(i8 %x) - -declare void @report__ident_str(%struct.string___XUP* sret %agg.result, i64 %x.0.0) - -declare void @llvm.memcpy.i32(i8*, i8*, i32, i32) - -declare void @report__ident_wide_str(%struct.wide_string___XUP* sret %agg.result, i64 %x.0.0) - -declare void @__gnat_begin_handler(i8*) - -declare void @__gnat_end_handler(i8*) - -declare void @report__legal_file_name(%struct.string___XUP* sret %agg.result, i32 %x, i64 %nam.0.0) - -declare void @__gnat_rcheck_06(i8*, i32) - -declare void @system__string_ops__str_concat_cs(%struct.string___XUP* sret , i8 zeroext , i64) diff --git a/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll b/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll index 3cd8052..62624a7 100644 --- a/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll +++ b/test/CodeGen/X86/2007-08-01-LiveVariablesBug.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 | not grep movl -define i8 @t(i8 zeroext %x, i8 zeroext %y) zeroext { +define zeroext i8 @t(i8 zeroext %x, i8 zeroext %y) { %tmp2 = add i8 %x, 2 %tmp4 = add i8 %y, -2 %tmp5 = mul i8 %tmp4, %tmp2 diff --git a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll index e93092f..77291f0 100644 --- a/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll +++ b/test/CodeGen/X86/2007-08-10-SignExtSubreg.ll @@ -2,7 +2,7 @@ @X = global i32 0 ; <i32*> [#uses=1] -define i8 @_Z3fooi(i32 %x) signext { +define signext i8 @_Z3fooi(i32 %x) { entry: store i32 %x, i32* @X, align 4 %retval67 = trunc i32 %x to i8 ; <i8> [#uses=1] diff --git a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll index c3403a0..8518d4c 100644 --- a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll +++ b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll @@ -1,4 +1,6 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin | grep {isNullOrNil].eh"} | count 2 +; RUN: llc < %s -disable-cfi -march=x86 -mtriple=i686-apple-darwin | grep {isNullOrNil].eh"} | FileCheck %s + +; CHECK: "_-[NSString(local) isNullOrNil].eh": %struct.NSString = type { } %struct._objc__method_prototype_list = type opaque @@ -24,7 +26,7 @@ [1 x %struct._objc_method] [ %struct._objc_method { %struct.objc_selector* bitcast ([12 x i8]* @"\01L_OBJC_METH_VAR_NAME_0" to %struct.objc_selector*), i8* getelementptr ([7 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0), - i8* bitcast (i8 (%struct.NSString*, %struct.objc_selector*) signext * @"-[NSString(local) isNullOrNil]" to i8*) } ] }, section "__OBJC,__cat_inst_meth,regular,no_dead_strip" ; <{ i32, i32, [1 x %struct._objc_method] }*> [#uses=3] + i8* bitcast (i8 (%struct.NSString*, %struct.objc_selector*) * @"-[NSString(local) isNullOrNil]" to i8*) } ] }, section "__OBJC,__cat_inst_meth,regular,no_dead_strip" ; <{ i32, i32, [1 x %struct._objc_method] }*> [#uses=3] @"\01L_OBJC_CATEGORY_NSString_local" = internal global { i8*, i8*, %struct._objc_method_list*, i32, i32, i32, i32 } { i8* getelementptr ([6 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* getelementptr ([9 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), @@ -49,7 +51,7 @@ @"\01L_OBJC_METH_VAR_TYPE_0" = internal global [7 x i8] c"c8@0:4\00", section "__TEXT,__cstring,cstring_literals" ; <[7 x i8]*> [#uses=2] @llvm.used = appending global [11 x i8*] [ i8* bitcast ({ i32, i32, i16, i16, [1 x %struct._objc_category*] }* @"\01L_OBJC_SYMBOLS" to i8*), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01L_OBJC_CATEGORY_INSTANCE_METHODS_NSString_local" to i8*), i8* bitcast ({ i8*, i8*, %struct._objc_method_list*, i32, i32, i32, i32 }* @"\01L_OBJC_CATEGORY_NSString_local" to i8*), i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*), i8* bitcast (i32* @"\01.objc_category_name_NSString_local" to i8*), i8* getelementptr ([1 x i8]* @"\01L_OBJC_CLASS_NAME_2", i32 0, i32 0), i8* getelementptr ([9 x i8]* @"\01L_OBJC_CLASS_NAME_1", i32 0, i32 0), i8* getelementptr ([6 x i8]* @"\01L_OBJC_CLASS_NAME_0", i32 0, i32 0), i8* getelementptr ([12 x i8]* @"\01L_OBJC_METH_VAR_NAME_0", i32 0, i32 0), i8* getelementptr ([7 x i8]* @"\01L_OBJC_METH_VAR_TYPE_0", i32 0, i32 0) ], section "llvm.metadata" ; <[11 x i8*]*> [#uses=0] -define internal i8 @"-[NSString(local) isNullOrNil]"(%struct.NSString* %self, %struct.objc_selector* %_cmd) signext { +define internal signext i8 @"-[NSString(local) isNullOrNil]"(%struct.NSString* %self, %struct.objc_selector* %_cmd) { entry: %self_addr = alloca %struct.NSString* ; <%struct.NSString**> [#uses=1] %_cmd_addr = alloca %struct.objc_selector* ; <%struct.objc_selector**> [#uses=1] diff --git a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll index 4d69715..f7ffb93 100644 --- a/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll +++ b/test/CodeGen/X86/2007-09-27-LDIntrinsics.ll @@ -23,7 +23,7 @@ entry: ; CHECK: fldt 4(%esp) ; CHECK-NEXT: fld %st(0) ; CHECK-NEXT: fmul %st(1) -; CHECK-NEXT: fmulp %st(1) +; CHECK-NEXT: fmulp ; CHECK-NEXT: ret } diff --git a/test/CodeGen/X86/2007-10-05-3AddrConvert.ll b/test/CodeGen/X86/2007-10-05-3AddrConvert.ll deleted file mode 100644 index 2c2706d..0000000 --- a/test/CodeGen/X86/2007-10-05-3AddrConvert.ll +++ /dev/null @@ -1,48 +0,0 @@ -; RUN: llc < %s -march=x86 | grep lea - - %struct.anon = type { [3 x double], double, %struct.node*, [64 x %struct.bnode*], [64 x %struct.bnode*] } - %struct.bnode = type { i16, double, [3 x double], i32, i32, [3 x double], [3 x double], [3 x double], double, %struct.bnode*, %struct.bnode* } - %struct.node = type { i16, double, [3 x double], i32, i32 } - -define i32 @main(i32 %argc, i8** nocapture %argv) nounwind { -entry: - %0 = malloc %struct.anon ; <%struct.anon*> [#uses=2] - %1 = getelementptr %struct.anon* %0, i32 0, i32 2 ; <%struct.node**> [#uses=1] - br label %bb14.i - -bb14.i: ; preds = %bb14.i, %entry - %i8.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %2, %bb14.i ] ; <i32> [#uses=1] - %2 = add i32 %i8.0.reg2mem.0.i, 1 ; <i32> [#uses=2] - %exitcond74.i = icmp eq i32 %2, 32 ; <i1> [#uses=1] - br i1 %exitcond74.i, label %bb32.i, label %bb14.i - -bb32.i: ; preds = %bb32.i, %bb14.i - %tmp.0.reg2mem.0.i = phi i32 [ %indvar.next63.i, %bb32.i ], [ 0, %bb14.i ] ; <i32> [#uses=1] - %indvar.next63.i = add i32 %tmp.0.reg2mem.0.i, 1 ; <i32> [#uses=2] - %exitcond64.i = icmp eq i32 %indvar.next63.i, 64 ; <i1> [#uses=1] - br i1 %exitcond64.i, label %bb47.loopexit.i, label %bb32.i - -bb.i.i: ; preds = %bb47.loopexit.i - unreachable - -stepsystem.exit.i: ; preds = %bb47.loopexit.i - store %struct.node* null, %struct.node** %1, align 4 - br label %bb.i6.i - -bb.i6.i: ; preds = %bb.i6.i, %stepsystem.exit.i - %tmp.0.i.i = add i32 0, -1 ; <i32> [#uses=1] - %3 = icmp slt i32 %tmp.0.i.i, 0 ; <i1> [#uses=1] - br i1 %3, label %bb107.i.i, label %bb.i6.i - -bb107.i.i: ; preds = %bb107.i.i, %bb.i6.i - %q_addr.0.i.i.in = phi %struct.bnode** [ null, %bb107.i.i ], [ %4, %bb.i6.i ] ; <%struct.bnode**> [#uses=1] - %q_addr.0.i.i = load %struct.bnode** %q_addr.0.i.i.in ; <%struct.bnode*> [#uses=1] - %q_addr.1 = getelementptr %struct.anon* %0, i32 0, i32 4, i32 1 - store %struct.bnode* %q_addr.0.i.i, %struct.bnode** %q_addr.1, align 4 - br label %bb107.i.i - -bb47.loopexit.i: ; preds = %bb32.i - %4 = getelementptr %struct.anon* %0, i32 0, i32 4, i32 0 ; <%struct.bnode**> [#uses=1] - %5 = icmp eq %struct.node* null, null ; <i1> [#uses=1] - br i1 %5, label %stepsystem.exit.i, label %bb.i.i -} diff --git a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll index db13fde..8091bd1 100644 --- a/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll +++ b/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 | not grep movb -define i16 @f(i32* %bp, i32* %ss) signext { +define signext i16 @f(i32* %bp, i32* %ss) { entry: br label %cond_next127 diff --git a/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll b/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll index a3872ad..7a3d72d 100644 --- a/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll +++ b/test/CodeGen/X86/2007-10-12-SpillerUnfold2.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 | grep sarl | not grep esp -define i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) signext { +define signext i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) { entry: br label %cond_next127 diff --git a/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll b/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll index 1e4ae84..c68628d 100644 --- a/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll +++ b/test/CodeGen/X86/2007-10-15-CoalescerCrash.ll @@ -362,7 +362,7 @@ bb1159: ; preds = %cond_next1150 cond_true1169: ; preds = %bb1159 %tmp11741175 = trunc i64 %lsum.11225.0 to i32 ; <i32> [#uses=1] - %tmp1178 = tail call i32 (%struct._IO_FILE* noalias , i8* noalias , ...)* @fprintf( %struct._IO_FILE* %file noalias , i8* getelementptr ([49 x i8]* @.str32, i32 0, i64 0) noalias , i32 %tmp11741175, i32 0 ) ; <i32> [#uses=0] + %tmp1178 = tail call i32 (%struct._IO_FILE* noalias , i8* noalias , ...)* @fprintf( %struct._IO_FILE* noalias %file , i8* getelementptr ([49 x i8]* @.str32, i32 0, i64 0) , i32 %tmp11741175, i32 0 ) ; <i32> [#uses=0] ret void UnifiedReturnBlock: ; preds = %bb1159 @@ -379,9 +379,9 @@ declare i32 @reg_preferred_class(i32) declare i32 @reg_alternate_class(i32) -declare i8 @maybe_hot_bb_p(%struct.basic_block_def*) zeroext +declare zeroext i8 @maybe_hot_bb_p(%struct.basic_block_def*) -declare i8 @probably_never_executed_bb_p(%struct.basic_block_def*) zeroext +declare zeroext i8 @probably_never_executed_bb_p(%struct.basic_block_def*) declare void @dump_regset(%struct.bitmap_head_def*, %struct._IO_FILE*) diff --git a/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll b/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll index 600bd1f..d3120f3 100644 --- a/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll +++ b/test/CodeGen/X86/2007-10-19-SpillerUnfold.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 -x86-asm-syntax=intel | grep inc | not grep PTR -define i16 @t(i32* %bitptr, i32* %source, i8** %byteptr, i32 %scale, i32 %round) signext { +define signext i16 @t(i32* %bitptr, i32* %source, i8** %byteptr, i32 %scale, i32 %round) { entry: br label %bb diff --git a/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll b/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll index 86d3bbf..573a217 100644 --- a/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll +++ b/test/CodeGen/X86/2007-10-29-ExtendSetCC.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 | grep mov | count 1 -define i16 @t() signext { +define signext i16 @t() { entry: %tmp180 = load i16* null, align 2 ; <i16> [#uses=3] %tmp180181 = sext i16 %tmp180 to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/2007-11-02-BadAsm.ll b/test/CodeGen/X86/2007-11-02-BadAsm.ll deleted file mode 100644 index 4e11cda..0000000 --- a/test/CodeGen/X86/2007-11-02-BadAsm.ll +++ /dev/null @@ -1,144 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movl | not grep rax - - %struct.color_sample = type { i64 } - %struct.gs_matrix = type { float, i64, float, i64, float, i64, float, i64, float, i64, float, i64 } - %struct.ref = type { %struct.color_sample, i16, i16 } - %struct.status = type { %struct.gs_matrix, i8*, i32, i32, i8*, i32, i32, i32, i32, i32, i32, i32 } - -define i32 @ztype1imagepath(%struct.ref* %op) { -entry: - br i1 false, label %cond_next, label %UnifiedReturnBlock - -cond_next: ; preds = %entry - br i1 false, label %cond_next68, label %UnifiedReturnBlock - -cond_next68: ; preds = %cond_next - %tmp5.i.i = malloc i8, i32 0 ; <i8*> [#uses=2] - br i1 false, label %bb81.outer.i, label %xit.i - -bb81.outer.i: ; preds = %bb87.i, %cond_next68 - %tmp67.i = add i32 0, 1 ; <i32> [#uses=1] - br label %bb81.i - -bb61.i: ; preds = %bb81.i - %tmp71.i = getelementptr i8* %tmp5.i.i, i64 0 ; <i8*> [#uses=1] - %tmp72.i = load i8* %tmp71.i, align 1 ; <i8> [#uses=1] - %tmp73.i = icmp eq i8 %tmp72.i, 0 ; <i1> [#uses=1] - br i1 %tmp73.i, label %bb81.i, label %xit.i - -bb81.i: ; preds = %bb61.i, %bb81.outer.i - br i1 false, label %bb87.i, label %bb61.i - -bb87.i: ; preds = %bb81.i - br i1 false, label %bb81.outer.i, label %xit.i - -xit.i: ; preds = %bb87.i, %bb61.i, %cond_next68 - %lsbx.0.reg2mem.1.i = phi i32 [ 0, %cond_next68 ], [ 0, %bb61.i ], [ %tmp67.i, %bb87.i ] ; <i32> [#uses=1] - %tmp6162.i.i = fptrunc double 0.000000e+00 to float ; <float> [#uses=1] - %tmp67.i15.i = fptrunc double 0.000000e+00 to float ; <float> [#uses=1] - %tmp24.i27.i = icmp eq i64 0, 0 ; <i1> [#uses=1] - br i1 %tmp24.i27.i, label %cond_next.i79.i, label %cond_true.i34.i - -cond_true.i34.i: ; preds = %xit.i - ret i32 0 - -cond_next.i79.i: ; preds = %xit.i - %phitmp167.i = fptosi double 0.000000e+00 to i64 ; <i64> [#uses=1] - %tmp142143.i = fpext float %tmp6162.i.i to double ; <double> [#uses=1] - %tmp2.i139.i = fadd double %tmp142143.i, 5.000000e-01 ; <double> [#uses=1] - %tmp23.i140.i = fptosi double %tmp2.i139.i to i64 ; <i64> [#uses=1] - br i1 false, label %cond_true.i143.i, label %round_coord.exit148.i - -cond_true.i143.i: ; preds = %cond_next.i79.i - %tmp8.i142.i = icmp sgt i64 %tmp23.i140.i, -32768 ; <i1> [#uses=1] - br i1 %tmp8.i142.i, label %cond_true11.i145.i, label %round_coord.exit148.i - -cond_true11.i145.i: ; preds = %cond_true.i143.i - ret i32 0 - -round_coord.exit148.i: ; preds = %cond_true.i143.i, %cond_next.i79.i - %tmp144149.i = phi i32 [ 32767, %cond_next.i79.i ], [ -32767, %cond_true.i143.i ] ; <i32> [#uses=1] - store i32 %tmp144149.i, i32* null, align 8 - %tmp147148.i = fpext float %tmp67.i15.i to double ; <double> [#uses=1] - %tmp2.i128.i = fadd double %tmp147148.i, 5.000000e-01 ; <double> [#uses=1] - %tmp23.i129.i = fptosi double %tmp2.i128.i to i64 ; <i64> [#uses=2] - %tmp5.i130.i = icmp slt i64 %tmp23.i129.i, 32768 ; <i1> [#uses=1] - br i1 %tmp5.i130.i, label %cond_true.i132.i, label %round_coord.exit137.i - -cond_true.i132.i: ; preds = %round_coord.exit148.i - %tmp8.i131.i = icmp sgt i64 %tmp23.i129.i, -32768 ; <i1> [#uses=1] - br i1 %tmp8.i131.i, label %cond_true11.i134.i, label %round_coord.exit137.i - -cond_true11.i134.i: ; preds = %cond_true.i132.i - br label %round_coord.exit137.i - -round_coord.exit137.i: ; preds = %cond_true11.i134.i, %cond_true.i132.i, %round_coord.exit148.i - %tmp149138.i = phi i32 [ 0, %cond_true11.i134.i ], [ 32767, %round_coord.exit148.i ], [ -32767, %cond_true.i132.i ] ; <i32> [#uses=1] - br i1 false, label %cond_true.i121.i, label %round_coord.exit126.i - -cond_true.i121.i: ; preds = %round_coord.exit137.i - br i1 false, label %cond_true11.i123.i, label %round_coord.exit126.i - -cond_true11.i123.i: ; preds = %cond_true.i121.i - br label %round_coord.exit126.i - -round_coord.exit126.i: ; preds = %cond_true11.i123.i, %cond_true.i121.i, %round_coord.exit137.i - %tmp153127.i = phi i32 [ 0, %cond_true11.i123.i ], [ 32767, %round_coord.exit137.i ], [ -32767, %cond_true.i121.i ] ; <i32> [#uses=1] - br i1 false, label %cond_true.i110.i, label %round_coord.exit115.i - -cond_true.i110.i: ; preds = %round_coord.exit126.i - br i1 false, label %cond_true11.i112.i, label %round_coord.exit115.i - -cond_true11.i112.i: ; preds = %cond_true.i110.i - br label %round_coord.exit115.i - -round_coord.exit115.i: ; preds = %cond_true11.i112.i, %cond_true.i110.i, %round_coord.exit126.i - %tmp157116.i = phi i32 [ 0, %cond_true11.i112.i ], [ 32767, %round_coord.exit126.i ], [ -32767, %cond_true.i110.i ] ; <i32> [#uses=2] - br i1 false, label %cond_true.i99.i, label %round_coord.exit104.i - -cond_true.i99.i: ; preds = %round_coord.exit115.i - br i1 false, label %cond_true11.i101.i, label %round_coord.exit104.i - -cond_true11.i101.i: ; preds = %cond_true.i99.i - %tmp1213.i100.i = trunc i64 %phitmp167.i to i32 ; <i32> [#uses=1] - br label %cond_next172.i - -round_coord.exit104.i: ; preds = %cond_true.i99.i, %round_coord.exit115.i - %UnifiedRetVal.i102.i = phi i32 [ 32767, %round_coord.exit115.i ], [ -32767, %cond_true.i99.i ] ; <i32> [#uses=1] - %tmp164.i = call fastcc i32 @put_int( %struct.status* null, i32 %tmp157116.i ) ; <i32> [#uses=0] - br label %cond_next172.i - -cond_next172.i: ; preds = %round_coord.exit104.i, %cond_true11.i101.i - %tmp161105.reg2mem.0.i = phi i32 [ %tmp1213.i100.i, %cond_true11.i101.i ], [ %UnifiedRetVal.i102.i, %round_coord.exit104.i ] ; <i32> [#uses=1] - %tmp174.i = icmp eq i32 %tmp153127.i, 0 ; <i1> [#uses=1] - %bothcond.i = and i1 false, %tmp174.i ; <i1> [#uses=1] - %tmp235.i = call fastcc i32 @put_int( %struct.status* null, i32 %tmp149138.i ) ; <i32> [#uses=0] - %tmp245.i = load i8** null, align 8 ; <i8*> [#uses=2] - %tmp246.i = getelementptr i8* %tmp245.i, i64 1 ; <i8*> [#uses=1] - br i1 %bothcond.i, label %cond_next254.i, label %bb259.i - -cond_next254.i: ; preds = %cond_next172.i - store i8 13, i8* %tmp245.i, align 1 - br label %bb259.i - -bb259.i: ; preds = %cond_next254.i, %cond_next172.i - %storemerge.i = phi i8* [ %tmp246.i, %cond_next254.i ], [ null, %cond_next172.i ] ; <i8*> [#uses=0] - %tmp261.i = shl i32 %lsbx.0.reg2mem.1.i, 2 ; <i32> [#uses=1] - store i32 %tmp261.i, i32* null, align 8 - %tmp270.i = add i32 0, %tmp157116.i ; <i32> [#uses=1] - store i32 %tmp270.i, i32* null, align 8 - %tmp275.i = add i32 0, %tmp161105.reg2mem.0.i ; <i32> [#uses=0] - br i1 false, label %trace_cells.exit.i, label %bb.preheader.i.i - -bb.preheader.i.i: ; preds = %bb259.i - ret i32 0 - -trace_cells.exit.i: ; preds = %bb259.i - free i8* %tmp5.i.i - ret i32 0 - -UnifiedReturnBlock: ; preds = %cond_next, %entry - ret i32 -20 -} - -declare fastcc i32 @put_int(%struct.status*, i32) diff --git a/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll b/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll deleted file mode 100644 index ca995cc..0000000 --- a/test/CodeGen/X86/2007-12-11-FoldImpDefSpill.ll +++ /dev/null @@ -1,680 +0,0 @@ -; RUN: llc < %s -mtriple=i686-apple-darwin | not grep IMPLICIT_DEF - - %struct.__sbuf = type { i8*, i32 } - %struct.ggBRDF = type { i32 (...)** } - %"struct.ggBST<ggMaterial>" = type { %"struct.ggBSTNode<ggMaterial>"*, i32 } - %"struct.ggBST<ggRasterSurfaceTexture>" = type { %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, i32 } - %"struct.ggBST<ggSolidTexture>" = type { %"struct.ggBSTNode<ggSolidTexture>"*, i32 } - %"struct.ggBST<ggSpectrum>" = type { %"struct.ggBSTNode<ggSpectrum>"*, i32 } - %"struct.ggBST<mrObjectRecord>" = type { %"struct.ggBSTNode<mrObjectRecord>"*, i32 } - %"struct.ggBSTNode<ggMaterial>" = type { %"struct.ggBSTNode<ggMaterial>"*, %"struct.ggBSTNode<ggMaterial>"*, %struct.ggString, %struct.ggMaterial* } - %"struct.ggBSTNode<ggRasterSurfaceTexture>" = type { %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, %"struct.ggBSTNode<ggRasterSurfaceTexture>"*, %struct.ggString, %struct.ggRasterSurfaceTexture* } - %"struct.ggBSTNode<ggSolidTexture>" = type { %"struct.ggBSTNode<ggSolidTexture>"*, %"struct.ggBSTNode<ggSolidTexture>"*, %struct.ggString, %struct.ggBRDF* } - %"struct.ggBSTNode<ggSpectrum>" = type { %"struct.ggBSTNode<ggSpectrum>"*, %"struct.ggBSTNode<ggSpectrum>"*, %struct.ggString, %struct.ggSpectrum* } - %"struct.ggBSTNode<mrObjectRecord>" = type { %"struct.ggBSTNode<mrObjectRecord>"*, %"struct.ggBSTNode<mrObjectRecord>"*, %struct.ggString, %struct.mrObjectRecord* } - %"struct.ggDictionary<ggMaterial>" = type { %"struct.ggBST<ggMaterial>" } - %"struct.ggDictionary<ggRasterSurfaceTexture>" = type { %"struct.ggBST<ggRasterSurfaceTexture>" } - %"struct.ggDictionary<ggSolidTexture>" = type { %"struct.ggBST<ggSolidTexture>" } - %"struct.ggDictionary<ggSpectrum>" = type { %"struct.ggBST<ggSpectrum>" } - %"struct.ggDictionary<mrObjectRecord>" = type { %"struct.ggBST<mrObjectRecord>" } - %struct.ggHAffineMatrix3 = type { %struct.ggHMatrix3 } - %struct.ggHBoxMatrix3 = type { %struct.ggHAffineMatrix3 } - %struct.ggHMatrix3 = type { [4 x [4 x double]] } - %struct.ggMaterial = type { i32 (...)**, %struct.ggBRDF* } - %struct.ggPoint3 = type { [3 x double] } - %"struct.ggRGBPixel<char>" = type { [3 x i8], i8 } - %"struct.ggRaster<ggRGBPixel<unsigned char> >" = type { i32, i32, %"struct.ggRGBPixel<char>"* } - %struct.ggRasterSurfaceTexture = type { %"struct.ggRaster<ggRGBPixel<unsigned char> >"* } - %struct.ggSolidNoise3 = type { i32, [256 x %struct.ggPoint3], [256 x i32] } - %struct.ggSpectrum = type { [8 x float] } - %struct.ggString = type { %"struct.ggString::StringRep"* } - %"struct.ggString::StringRep" = type { i32, i32, [1 x i8] } - %"struct.ggTrain<mrPixelRenderer*>" = type { %struct.ggBRDF**, i32, i32 } - %struct.mrObjectRecord = type { %struct.ggHBoxMatrix3, %struct.ggHBoxMatrix3, %struct.mrSurfaceList, %struct.ggMaterial*, i32, %struct.ggRasterSurfaceTexture*, %struct.ggBRDF*, i32, i32 } - %struct.mrScene = type { %struct.ggSpectrum, %struct.ggSpectrum, %struct.ggBRDF*, %struct.ggBRDF*, %struct.ggBRDF*, i32, double, %"struct.ggDictionary<mrObjectRecord>", %"struct.ggDictionary<ggRasterSurfaceTexture>", %"struct.ggDictionary<ggSolidTexture>", %"struct.ggDictionary<ggSpectrum>", %"struct.ggDictionary<ggMaterial>" } - %struct.mrSurfaceList = type { %struct.ggBRDF, %"struct.ggTrain<mrPixelRenderer*>" } - %"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>" = type { %"struct.std::locale::facet" } - %"struct.std::basic_ios<char,std::char_traits<char> >" = type { %"struct.std::ios_base", %"struct.std::basic_ostream<char,std::char_traits<char> >"*, i8, i8, %"struct.std::basic_streambuf<char,std::char_traits<char> >"*, %"struct.std::ctype<char>"*, %"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>"*, %"struct.std::__codecvt_abstract_base<char,char,__mbstate_t>"* } - %"struct.std::basic_istream<char,std::char_traits<char> >" = type { i32 (...)**, i32, %"struct.std::basic_ios<char,std::char_traits<char> >" } - %"struct.std::basic_ostream<char,std::char_traits<char> >" = type { i32 (...)**, %"struct.std::basic_ios<char,std::char_traits<char> >" } - %"struct.std::basic_streambuf<char,std::char_traits<char> >" = type { i32 (...)**, i8*, i8*, i8*, i8*, i8*, i8*, %"struct.std::locale" } - %"struct.std::ctype<char>" = type { %"struct.std::locale::facet", i32*, i8, i32*, i32*, i32*, i8, [256 x i8], [256 x i8], i8 } - %"struct.std::ios_base" = type { i32 (...)**, i32, i32, i32, i32, i32, %"struct.std::ios_base::_Callback_list"*, %struct.__sbuf, [8 x %struct.__sbuf], i32, %struct.__sbuf*, %"struct.std::locale" } - %"struct.std::ios_base::_Callback_list" = type { %"struct.std::ios_base::_Callback_list"*, void (i32, %"struct.std::ios_base"*, i32)*, i32, i32 } - %"struct.std::locale" = type { %"struct.std::locale::_Impl"* } - %"struct.std::locale::_Impl" = type { i32, %"struct.std::locale::facet"**, i32, %"struct.std::locale::facet"**, i8** } - %"struct.std::locale::facet" = type { i32 (...)**, i32 } -@.str80 = external constant [7 x i8] ; <[7 x i8]*> [#uses=1] -@.str81 = external constant [11 x i8] ; <[11 x i8]*> [#uses=1] - -define fastcc void @_ZN7mrScene4ReadERSi(%struct.mrScene* %this, %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces) { -entry: - %tmp6.i.i8288 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit unwind label %lpad ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit: ; preds = %entry - %tmp6.i.i8995 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit96 unwind label %lpad3825 ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit96: ; preds = %_ZN8ggStringC1Ei.exit - %tmp6.i.i97103 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit104 unwind label %lpad3829 ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit104: ; preds = %_ZN8ggStringC1Ei.exit96 - %tmp6.i.i105111 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit112 unwind label %lpad3833 ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit112: ; preds = %_ZN8ggStringC1Ei.exit104 - %tmp6.i.i122128 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit129 unwind label %lpad3837 ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit129: ; preds = %_ZN8ggStringC1Ei.exit112 - %tmp6.i.i132138 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit139 unwind label %lpad3841 ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit139: ; preds = %_ZN8ggStringC1Ei.exit129 - %tmp295 = invoke i8* @_Znwm( i32 16 ) - to label %invcont294 unwind label %lpad3845 ; <i8*> [#uses=0] - -invcont294: ; preds = %_ZN8ggStringC1Ei.exit139 - %tmp10.i.i141 = invoke i8* @_Znam( i32 16 ) - to label %_ZN13mrSurfaceListC1Ev.exit unwind label %lpad3849 ; <i8*> [#uses=0] - -_ZN13mrSurfaceListC1Ev.exit: ; preds = %invcont294 - %tmp3.i148 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i.noexc: ; preds = %_ZN13mrSurfaceListC1Ev.exit - %tmp15.i149 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i.noexc unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i.noexc: ; preds = %tmp3.i.noexc - br i1 false, label %bb308, label %bb.i - -bb.i: ; preds = %tmp15.i.noexc - ret void - -bb308: ; preds = %tmp15.i.noexc - br i1 false, label %bb3743.preheader, label %bb315 - -bb3743.preheader: ; preds = %bb308 - %tmp16.i3862 = getelementptr %struct.ggPoint3* null, i32 0, i32 0, i32 0 ; <double*> [#uses=1] - %tmp16.i3859 = getelementptr %struct.ggPoint3* null, i32 0, i32 0, i32 0 ; <double*> [#uses=3] - br label %bb3743 - -bb315: ; preds = %bb308 - ret void - -bb333: ; preds = %invcont3758, %invcont335 - %tmp3.i167180 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i167.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i167.noexc: ; preds = %bb333 - %tmp15.i182 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i.noexc181 unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i.noexc181: ; preds = %tmp3.i167.noexc - br i1 false, label %invcont335, label %bb.i178 - -bb.i178: ; preds = %tmp15.i.noexc181 - ret void - -invcont335: ; preds = %tmp15.i.noexc181 - br i1 false, label %bb3743, label %bb333 - -bb345: ; preds = %invcont3758 - br i1 false, label %bb353, label %bb360 - -bb353: ; preds = %bb345 - %tmp356 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null ) - to label %bb3743 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -bb360: ; preds = %bb345 - br i1 false, label %bb368, label %bb374 - -bb368: ; preds = %bb360 - %tmp373 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null ) - to label %bb3743 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -bb374: ; preds = %bb360 - br i1 false, label %bb396, label %bb421 - -bb396: ; preds = %bb374 - ret void - -bb421: ; preds = %bb374 - br i1 false, label %bb429, label %bb530 - -bb429: ; preds = %bb421 - ret void - -bb530: ; preds = %bb421 - br i1 false, label %bb538, label %bb673 - -bb538: ; preds = %bb530 - ret void - -bb673: ; preds = %bb530 - br i1 false, label %bb681, label %bb778 - -bb681: ; preds = %bb673 - ret void - -bb778: ; preds = %bb673 - br i1 false, label %bb786, label %bb891 - -bb786: ; preds = %bb778 - ret void - -bb891: ; preds = %bb778 - br i1 false, label %bb899, label %bb998 - -bb899: ; preds = %bb891 - ret void - -bb998: ; preds = %bb891 - br i1 false, label %bb1168, label %bb1190 - -bb1168: ; preds = %bb998 - ret void - -bb1190: ; preds = %bb998 - br i1 false, label %bb1198, label %bb1220 - -bb1198: ; preds = %bb1190 - ret void - -bb1220: ; preds = %bb1190 - br i1 false, label %bb1228, label %bb1250 - -bb1228: ; preds = %bb1220 - ret void - -bb1250: ; preds = %bb1220 - br i1 false, label %bb1258, label %bb1303 - -bb1258: ; preds = %bb1250 - ret void - -bb1303: ; preds = %bb1250 - br i1 false, label %bb1311, label %bb1366 - -bb1311: ; preds = %bb1303 - ret void - -bb1366: ; preds = %bb1303 - br i1 false, label %bb1374, label %bb1432 - -bb1374: ; preds = %bb1366 - ret void - -bb1432: ; preds = %bb1366 - br i1 false, label %bb1440, label %bb1495 - -bb1440: ; preds = %bb1432 - ret void - -bb1495: ; preds = %bb1432 - br i1 false, label %bb1503, label %bb1561 - -bb1503: ; preds = %bb1495 - ret void - -bb1561: ; preds = %bb1495 - br i1 false, label %bb1569, label %bb1624 - -bb1569: ; preds = %bb1561 - ret void - -bb1624: ; preds = %bb1561 - br i1 false, label %bb1632, label %bb1654 - -bb1632: ; preds = %bb1624 - store double 0.000000e+00, double* %tmp16.i3859, align 8 - %tmp3.i38383852 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3838.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3838.noexc: ; preds = %bb1632 - %tmp15.i38473853 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i3847.noexc unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i3847.noexc: ; preds = %tmp3.i3838.noexc - br i1 false, label %invcont1634, label %bb.i3850 - -bb.i3850: ; preds = %tmp15.i3847.noexc - ret void - -invcont1634: ; preds = %tmp15.i3847.noexc - %tmp3.i38173831 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3817.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3817.noexc: ; preds = %invcont1634 - %tmp15.i38263832 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i3826.noexc unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i3826.noexc: ; preds = %tmp3.i3817.noexc - br i1 false, label %invcont1636, label %bb.i3829 - -bb.i3829: ; preds = %tmp15.i3826.noexc - ret void - -invcont1636: ; preds = %tmp15.i3826.noexc - %tmp8.i38083811 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* %tmp16.i3862 ) - to label %tmp8.i3808.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -tmp8.i3808.noexc: ; preds = %invcont1636 - %tmp9.i38093812 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp8.i38083811, double* null ) - to label %tmp9.i3809.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -tmp9.i3809.noexc: ; preds = %tmp8.i3808.noexc - %tmp10.i38103813 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp9.i38093812, double* null ) - to label %invcont1638 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -invcont1638: ; preds = %tmp9.i3809.noexc - %tmp8.i37983801 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* %tmp16.i3859 ) - to label %tmp8.i3798.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -tmp8.i3798.noexc: ; preds = %invcont1638 - %tmp9.i37993802 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp8.i37983801, double* null ) - to label %tmp9.i3799.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -tmp9.i3799.noexc: ; preds = %tmp8.i3798.noexc - %tmp10.i38003803 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp9.i37993802, double* null ) - to label %invcont1640 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -invcont1640: ; preds = %tmp9.i3799.noexc - %tmp3.i3778 = load double* %tmp16.i3859, align 8 ; <double> [#uses=1] - %tmp1643 = invoke i8* @_Znwm( i32 76 ) - to label %invcont1642 unwind label %lpad3845 ; <i8*> [#uses=0] - -invcont1642: ; preds = %invcont1640 - %tmp18.i3770 = fsub double %tmp3.i3778, 0.000000e+00 ; <double> [#uses=0] - invoke fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i( %struct.mrScene* %this, %struct.ggBRDF* null, %struct.ggString* null, %struct.ggString* null, i32 0 ) - to label %bb3743 unwind label %lpad3845 - -bb1654: ; preds = %bb1624 - br i1 false, label %bb1662, label %bb1693 - -bb1662: ; preds = %bb1654 - %tmp3.i37143728 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3714.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3714.noexc: ; preds = %bb1662 - %tmp15.i37233729 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i3723.noexc unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i3723.noexc: ; preds = %tmp3.i3714.noexc - ret void - -bb1693: ; preds = %bb1654 - br i1 false, label %bb1701, label %bb1745 - -bb1701: ; preds = %bb1693 - %tmp3.i36493663 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3649.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3649.noexc: ; preds = %bb1701 - ret void - -bb1745: ; preds = %bb1693 - br i1 false, label %bb1753, label %bb1797 - -bb1753: ; preds = %bb1745 - ret void - -bb1797: ; preds = %bb1745 - br i1 false, label %bb1805, label %bb1847 - -bb1805: ; preds = %bb1797 - ret void - -bb1847: ; preds = %bb1797 - br i1 false, label %bb1855, label %bb1897 - -bb1855: ; preds = %bb1847 - %tmp3.i34633477 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3463.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3463.noexc: ; preds = %bb1855 - %tmp15.i34723478 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i3472.noexc unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i3472.noexc: ; preds = %tmp3.i3463.noexc - br i1 false, label %invcont1857, label %bb.i3475 - -bb.i3475: ; preds = %tmp15.i3472.noexc - invoke fastcc void @_ZN8ggStringaSEPKc( %struct.ggString* null, i8* null ) - to label %invcont1857 unwind label %lpad3845 - -invcont1857: ; preds = %bb.i3475, %tmp15.i3472.noexc - %tmp1860 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null ) - to label %invcont1859 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -invcont1859: ; preds = %invcont1857 - %tmp1862 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1860, double* null ) - to label %invcont1861 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -invcont1861: ; preds = %invcont1859 - %tmp1864 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1862, double* null ) - to label %invcont1863 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -invcont1863: ; preds = %invcont1861 - %tmp1866 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1864, double* null ) - to label %invcont1865 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -invcont1865: ; preds = %invcont1863 - %tmp1868 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp1866, double* null ) - to label %invcont1867 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -invcont1867: ; preds = %invcont1865 - %tmp1881 = invoke i8 @_ZNKSt9basic_iosIcSt11char_traitsIcEE4goodEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) zeroext - to label %invcont1880 unwind label %lpad3845 ; <i8> [#uses=0] - -invcont1880: ; preds = %invcont1867 - %tmp1883 = invoke i8* @_Znwm( i32 24 ) - to label %invcont1882 unwind label %lpad3845 ; <i8*> [#uses=0] - -invcont1882: ; preds = %invcont1880 - invoke fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i( %struct.mrScene* %this, %struct.ggBRDF* null, %struct.ggString* null, %struct.ggString* null, i32 0 ) - to label %bb3743 unwind label %lpad3845 - -bb1897: ; preds = %bb1847 - br i1 false, label %bb1905, label %bb1947 - -bb1905: ; preds = %bb1897 - ret void - -bb1947: ; preds = %bb1897 - br i1 false, label %bb1955, label %bb2000 - -bb1955: ; preds = %bb1947 - ret void - -bb2000: ; preds = %bb1947 - br i1 false, label %bb2008, label %bb2053 - -bb2008: ; preds = %bb2000 - ret void - -bb2053: ; preds = %bb2000 - br i1 false, label %bb2061, label %bb2106 - -bb2061: ; preds = %bb2053 - %tmp3.i32433257 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3243.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3243.noexc: ; preds = %bb2061 - %tmp15.i32523258 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %bb.i3255 unwind label %lpad3845 ; <i8*> [#uses=0] - -bb.i3255: ; preds = %tmp3.i3243.noexc - invoke fastcc void @_ZN8ggStringaSEPKc( %struct.ggString* null, i8* null ) - to label %invcont2063 unwind label %lpad3845 - -invcont2063: ; preds = %bb.i3255 - ret void - -bb2106: ; preds = %bb2053 - %tmp7.i3214 = call i32 @strcmp( i8* %tmp5.i161, i8* getelementptr ([7 x i8]* @.str80, i32 0, i32 0) ) nounwind readonly ; <i32> [#uses=0] - br i1 false, label %bb2114, label %bb2136 - -bb2114: ; preds = %bb2106 - %tmp3.i31923206 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3192.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3192.noexc: ; preds = %bb2114 - %tmp15.i32013207 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i3201.noexc unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i3201.noexc: ; preds = %tmp3.i3192.noexc - br i1 false, label %invcont2116, label %bb.i3204 - -bb.i3204: ; preds = %tmp15.i3201.noexc - ret void - -invcont2116: ; preds = %tmp15.i3201.noexc - %tmp3.i31713185 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3171.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3171.noexc: ; preds = %invcont2116 - %tmp15.i31803186 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i3180.noexc unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i3180.noexc: ; preds = %tmp3.i3171.noexc - br i1 false, label %invcont2118, label %bb.i3183 - -bb.i3183: ; preds = %tmp15.i3180.noexc - ret void - -invcont2118: ; preds = %tmp15.i3180.noexc - %tmp8.i31623165 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null ) - to label %tmp8.i3162.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -tmp8.i3162.noexc: ; preds = %invcont2118 - %tmp9.i31633166 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp8.i31623165, double* null ) - to label %tmp9.i3163.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -tmp9.i3163.noexc: ; preds = %tmp8.i3162.noexc - %tmp10.i31643167 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp9.i31633166, double* null ) - to label %invcont2120 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -invcont2120: ; preds = %tmp9.i3163.noexc - %tmp2123 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null ) - to label %invcont2122 unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -invcont2122: ; preds = %invcont2120 - %tmp2125 = invoke i8* @_Znwm( i32 36 ) - to label %invcont2124 unwind label %lpad3845 ; <i8*> [#uses=0] - -invcont2124: ; preds = %invcont2122 - invoke fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i( %struct.mrScene* %this, %struct.ggBRDF* null, %struct.ggString* null, %struct.ggString* null, i32 0 ) - to label %bb3743 unwind label %lpad3845 - -bb2136: ; preds = %bb2106 - %tmp7.i3128 = call i32 @strcmp( i8* %tmp5.i161, i8* getelementptr ([11 x i8]* @.str81, i32 0, i32 0) ) nounwind readonly ; <i32> [#uses=0] - br i1 false, label %bb2144, label %bb3336 - -bb2144: ; preds = %bb2136 - %tmp6.i.i31173123 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit3124 unwind label %lpad3845 ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit3124: ; preds = %bb2144 - %tmp3.i30983112 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i3098.noexc unwind label %lpad3921 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i3098.noexc: ; preds = %_ZN8ggStringC1Ei.exit3124 - %tmp15.i31073113 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i3107.noexc unwind label %lpad3921 ; <i8*> [#uses=0] - -tmp15.i3107.noexc: ; preds = %tmp3.i3098.noexc - br i1 false, label %invcont2147, label %bb.i3110 - -bb.i3110: ; preds = %tmp15.i3107.noexc - ret void - -invcont2147: ; preds = %tmp15.i3107.noexc - %tmp2161 = invoke i8 @_ZNKSt9basic_iosIcSt11char_traitsIcEE4goodEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) zeroext - to label %invcont2160 unwind label %lpad3921 ; <i8> [#uses=0] - -invcont2160: ; preds = %invcont2147 - %tmp4.i30933094 = invoke fastcc %struct.ggSpectrum* @_ZN5ggBSTI10ggSpectrumE4findERK8ggString3( %"struct.ggBSTNode<ggSpectrum>"* null, %struct.ggString* null ) - to label %invcont2164 unwind label %lpad3921 ; <%struct.ggSpectrum*> [#uses=0] - -invcont2164: ; preds = %invcont2160 - br i1 false, label %bb2170, label %bb2181 - -bb2170: ; preds = %invcont2164 - ret void - -bb2181: ; preds = %invcont2164 - invoke fastcc void @_ZN8ggStringD1Ev( %struct.ggString* null ) - to label %bb3743 unwind label %lpad3845 - -bb3336: ; preds = %bb2136 - br i1 false, label %bb3344, label %bb3734 - -bb3344: ; preds = %bb3336 - %tmp6.i.i773779 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit780 unwind label %lpad3845 ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit780: ; preds = %bb3344 - %tmp6.i.i765771 = invoke i8* @_Znam( i32 12 ) - to label %_ZN8ggStringC1Ei.exit772 unwind label %lpad4025 ; <i8*> [#uses=0] - -_ZN8ggStringC1Ei.exit772: ; preds = %_ZN8ggStringC1Ei.exit780 - %tmp3.i746760 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i746.noexc unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i746.noexc: ; preds = %_ZN8ggStringC1Ei.exit772 - %tmp15.i755761 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i755.noexc unwind label %lpad4029 ; <i8*> [#uses=0] - -tmp15.i755.noexc: ; preds = %tmp3.i746.noexc - br i1 false, label %invcont3348, label %bb.i758 - -bb.i758: ; preds = %tmp15.i755.noexc - ret void - -invcont3348: ; preds = %tmp15.i755.noexc - %tmp3.i726740 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i726.noexc unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i726.noexc: ; preds = %invcont3348 - %tmp15.i735741 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i735.noexc unwind label %lpad4029 ; <i8*> [#uses=0] - -tmp15.i735.noexc: ; preds = %tmp3.i726.noexc - br i1 false, label %bb3458, label %bb.i738 - -bb.i738: ; preds = %tmp15.i735.noexc - ret void - -bb3458: ; preds = %tmp15.i735.noexc - br i1 false, label %bb3466, label %bb3491 - -bb3466: ; preds = %bb3458 - %tmp3469 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, double* null ) - to label %invcont3468 unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -invcont3468: ; preds = %bb3466 - %tmp3471 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp3469, double* null ) - to label %invcont3470 unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=1] - -invcont3470: ; preds = %invcont3468 - %tmp3473 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERi( %"struct.std::basic_istream<char,std::char_traits<char> >"* %tmp3471, i32* null ) - to label %invcont3472 unwind label %lpad4029 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -invcont3472: ; preds = %invcont3470 - %tmp3475 = invoke i8* @_Znwm( i32 7196 ) - to label %invcont3474 unwind label %lpad4029 ; <i8*> [#uses=1] - -invcont3474: ; preds = %invcont3472 - invoke fastcc void @_ZN13ggSolidNoise3C1Ev( %struct.ggSolidNoise3* null ) - to label %_ZN22ggCoverageSolidTextureC1Eddi.exit unwind label %lpad4045 - -_ZN22ggCoverageSolidTextureC1Eddi.exit: ; preds = %invcont3474 - %tmp34823483 = bitcast i8* %tmp3475 to %struct.ggBRDF* ; <%struct.ggBRDF*> [#uses=2] - invoke fastcc void @_ZN5ggBSTI14ggSolidTextureE17InsertIntoSubtreeERK8ggStringPS0_RP9ggBSTNodeIS0_E( %"struct.ggBST<ggSolidTexture>"* null, %struct.ggString* null, %struct.ggBRDF* %tmp34823483, %"struct.ggBSTNode<ggSolidTexture>"** null ) - to label %bb3662 unwind label %lpad4029 - -bb3491: ; preds = %bb3458 - ret void - -bb3662: ; preds = %_ZN22ggCoverageSolidTextureC1Eddi.exit - invoke fastcc void @_ZN8ggStringD1Ev( %struct.ggString* null ) - to label %invcont3663 unwind label %lpad4025 - -invcont3663: ; preds = %bb3662 - invoke fastcc void @_ZN8ggStringD1Ev( %struct.ggString* null ) - to label %bb3743 unwind label %lpad3845 - -bb3734: ; preds = %bb3336 - ret void - -bb3743: ; preds = %invcont3663, %bb2181, %invcont2124, %invcont1882, %invcont1642, %bb368, %bb353, %invcont335, %bb3743.preheader - %tex1.3 = phi %struct.ggBRDF* [ undef, %bb3743.preheader ], [ %tex1.3, %bb368 ], [ %tex1.3, %invcont1642 ], [ %tex1.3, %invcont1882 ], [ %tex1.3, %invcont2124 ], [ %tex1.3, %bb2181 ], [ %tex1.3, %invcont335 ], [ %tmp34823483, %invcont3663 ], [ %tex1.3, %bb353 ] ; <%struct.ggBRDF*> [#uses=7] - %tmp3.i312325 = invoke %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_( %"struct.std::basic_istream<char,std::char_traits<char> >"* %surfaces, i8* null ) - to label %tmp3.i312.noexc unwind label %lpad3845 ; <%"struct.std::basic_istream<char,std::char_traits<char> >"*> [#uses=0] - -tmp3.i312.noexc: ; preds = %bb3743 - %tmp15.i327 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %tmp15.i.noexc326 unwind label %lpad3845 ; <i8*> [#uses=0] - -tmp15.i.noexc326: ; preds = %tmp3.i312.noexc - br i1 false, label %invcont3745, label %bb.i323 - -bb.i323: ; preds = %tmp15.i.noexc326 - ret void - -invcont3745: ; preds = %tmp15.i.noexc326 - %tmp3759 = invoke i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv( %"struct.std::basic_ios<char,std::char_traits<char> >"* null ) - to label %invcont3758 unwind label %lpad3845 ; <i8*> [#uses=0] - -invcont3758: ; preds = %invcont3745 - %tmp5.i161 = getelementptr %"struct.ggString::StringRep"* null, i32 0, i32 2, i32 0 ; <i8*> [#uses=2] - br i1 false, label %bb333, label %bb345 - -lpad: ; preds = %entry - ret void - -lpad3825: ; preds = %_ZN8ggStringC1Ei.exit - ret void - -lpad3829: ; preds = %_ZN8ggStringC1Ei.exit96 - ret void - -lpad3833: ; preds = %_ZN8ggStringC1Ei.exit104 - ret void - -lpad3837: ; preds = %_ZN8ggStringC1Ei.exit112 - ret void - -lpad3841: ; preds = %_ZN8ggStringC1Ei.exit129 - ret void - -lpad3845: ; preds = %invcont3745, %tmp3.i312.noexc, %bb3743, %invcont3663, %bb3344, %bb2181, %bb2144, %invcont2124, %invcont2122, %invcont2120, %tmp9.i3163.noexc, %tmp8.i3162.noexc, %invcont2118, %tmp3.i3171.noexc, %invcont2116, %tmp3.i3192.noexc, %bb2114, %bb.i3255, %tmp3.i3243.noexc, %bb2061, %invcont1882, %invcont1880, %invcont1867, %invcont1865, %invcont1863, %invcont1861, %invcont1859, %invcont1857, %bb.i3475, %tmp3.i3463.noexc, %bb1855, %bb1701, %tmp3.i3714.noexc, %bb1662, %invcont1642, %invcont1640, %tmp9.i3799.noexc, %tmp8.i3798.noexc, %invcont1638, %tmp9.i3809.noexc, %tmp8.i3808.noexc, %invcont1636, %tmp3.i3817.noexc, %invcont1634, %tmp3.i3838.noexc, %bb1632, %bb368, %bb353, %tmp3.i167.noexc, %bb333, %tmp3.i.noexc, %_ZN13mrSurfaceListC1Ev.exit, %_ZN8ggStringC1Ei.exit139 - ret void - -lpad3849: ; preds = %invcont294 - ret void - -lpad3921: ; preds = %invcont2160, %invcont2147, %tmp3.i3098.noexc, %_ZN8ggStringC1Ei.exit3124 - ret void - -lpad4025: ; preds = %bb3662, %_ZN8ggStringC1Ei.exit780 - ret void - -lpad4029: ; preds = %_ZN22ggCoverageSolidTextureC1Eddi.exit, %invcont3472, %invcont3470, %invcont3468, %bb3466, %tmp3.i726.noexc, %invcont3348, %tmp3.i746.noexc, %_ZN8ggStringC1Ei.exit772 - ret void - -lpad4045: ; preds = %invcont3474 - ret void -} - -declare fastcc void @_ZN8ggStringD1Ev(%struct.ggString*) - -declare i8* @_Znam(i32) - -declare fastcc void @_ZN8ggStringaSEPKc(%struct.ggString*, i8*) - -declare i32 @strcmp(i8*, i8*) nounwind readonly - -declare %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERi(%"struct.std::basic_istream<char,std::char_traits<char> >"*, i32*) - -declare i8* @_Znwm(i32) - -declare i8* @_ZNKSt9basic_iosIcSt11char_traitsIcEEcvPvEv(%"struct.std::basic_ios<char,std::char_traits<char> >"*) - -declare %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZNSirsERd(%"struct.std::basic_istream<char,std::char_traits<char> >"*, double*) - -declare %"struct.std::basic_istream<char,std::char_traits<char> >"* @_ZStrsIcSt11char_traitsIcEERSt13basic_istreamIT_T0_ES6_PS3_(%"struct.std::basic_istream<char,std::char_traits<char> >"*, i8*) - -declare fastcc void @_ZN13ggSolidNoise3C1Ev(%struct.ggSolidNoise3*) - -declare i8 @_ZNKSt9basic_iosIcSt11char_traitsIcEE4goodEv(%"struct.std::basic_ios<char,std::char_traits<char> >"*) zeroext - -declare fastcc %struct.ggSpectrum* @_ZN5ggBSTI10ggSpectrumE4findERK8ggString3(%"struct.ggBSTNode<ggSpectrum>"*, %struct.ggString*) - -declare fastcc void @_ZN5ggBSTI14ggSolidTextureE17InsertIntoSubtreeERK8ggStringPS0_RP9ggBSTNodeIS0_E(%"struct.ggBST<ggSolidTexture>"*, %struct.ggString*, %struct.ggBRDF*, %"struct.ggBSTNode<ggSolidTexture>"**) - -declare fastcc void @_ZN7mrScene9AddObjectEP9mrSurfaceRK8ggStringS4_i(%struct.mrScene*, %struct.ggBRDF*, %struct.ggString*, %struct.ggString*, i32) diff --git a/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll b/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll index 6615b8c..fd9c35e 100644 --- a/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-02-25-X86-64-CoalescerBug.ll @@ -4,7 +4,7 @@ %struct.YY = type { i64 } %struct.ZZ = type opaque -define i8 @f(%struct.XX*** %fontMap, %struct.XX* %uen) signext { +define signext i8 @f(%struct.XX*** %fontMap, %struct.XX* %uen) { entry: %tmp45 = add i16 0, 1 ; <i16> [#uses=2] br i1 false, label %bb124, label %bb53 diff --git a/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll b/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll index c6ba22e..19d49b2 100644 --- a/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll +++ b/test/CodeGen/X86/2008-03-13-TwoAddrPassCrash.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 -define i16 @t(i32 %depth) signext nounwind { +define signext i16 @t(i32 %depth) nounwind { entry: br i1 false, label %bb74, label %bb bb: ; preds = %entry diff --git a/test/CodeGen/X86/2008-04-02-unnamedEH.ll b/test/CodeGen/X86/2008-04-02-unnamedEH.ll index 27bbbaa..ab8ec80 100644 --- a/test/CodeGen/X86/2008-04-02-unnamedEH.ll +++ b/test/CodeGen/X86/2008-04-02-unnamedEH.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | FileCheck %s +; RUN: llc < %s -disable-cfi | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" diff --git a/test/CodeGen/X86/2008-04-16-ReMatBug.ll b/test/CodeGen/X86/2008-04-16-ReMatBug.ll index bfe8ef5..109069e 100644 --- a/test/CodeGen/X86/2008-04-16-ReMatBug.ll +++ b/test/CodeGen/X86/2008-04-16-ReMatBug.ll @@ -6,7 +6,7 @@ %struct.pthread_mutex_t = type { i32, [40 x i8] } @iodbcdm_global_lock = external global %struct.pthread_mutex_t ; <%struct.pthread_mutex_t*> [#uses=1] -define i16 @SQLDriversW(i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* %pcbDrvDesc, i32* %szDrvAttr, i16 signext %cbDrvAttrMax, i16* %pcbDrvAttr) signext nounwind { +define i16 @SQLDriversW(i8* %henv, i16 zeroext %fDir, i32* %szDrvDesc, i16 signext %cbDrvDescMax, i16* %pcbDrvDesc, i32* %szDrvAttr, i16 signext %cbDrvAttrMax, i16* %pcbDrvAttr) nounwind { entry: %tmp12 = bitcast i8* %henv to %struct.GENV_t* ; <%struct.GENV_t*> [#uses=1] br i1 true, label %bb28, label %bb @@ -23,7 +23,7 @@ bb74: ; preds = %bb37 bb92: ; preds = %bb74, %bb37 %tmp95180 = shl i16 %cbDrvAttrMax, 2 ; <i16> [#uses=1] %tmp100178 = shl i16 %cbDrvDescMax, 2 ; <i16> [#uses=1] - %tmp113 = tail call i16 @SQLDrivers_Internal( i8* %henv, i16 zeroext %fDir, i8* null, i16 signext %tmp100178, i16* %pcbDrvDesc, i8* null, i16 signext %tmp95180, i16* %pcbDrvAttr, i8 zeroext 87 ) signext nounwind ; <i16> [#uses=1] + %tmp113 = tail call i16 @SQLDrivers_Internal( i8* %henv, i16 zeroext %fDir, i8* null, i16 signext %tmp100178, i16* %pcbDrvDesc, i8* null, i16 signext %tmp95180, i16* %pcbDrvAttr, i8 zeroext 87 ) nounwind ; <i16> [#uses=1] br i1 false, label %done, label %bb137 bb137: ; preds = %bb92 ret i16 0 @@ -41,6 +41,6 @@ bb167: ; preds = %done declare i32 @pthread_mutex_unlock(%struct.pthread_mutex_t*) -declare i16 @SQLDrivers_Internal(i8*, i16 zeroext , i8*, i16 signext , i16*, i8*, i16 signext , i16*, i8 zeroext ) signext nounwind +declare i16 @SQLDrivers_Internal(i8*, i16 zeroext , i8*, i16 signext , i16*, i8*, i16 signext , i16*, i8 zeroext ) nounwind declare void @trace_SQLDriversW(i32, i32, i8*, i16 zeroext , i32*, i16 signext , i16*, i32*, i16 signext , i16*) diff --git a/test/CodeGen/X86/2008-04-17-CoalescerBug.ll b/test/CodeGen/X86/2008-04-17-CoalescerBug.ll index ac48285..77720aa 100644 --- a/test/CodeGen/X86/2008-04-17-CoalescerBug.ll +++ b/test/CodeGen/X86/2008-04-17-CoalescerBug.ll @@ -75,7 +75,7 @@ bb5334: ; preds = %bb3314 bb5484: ; preds = %bb3314 ret void bb5657: ; preds = %bb3314 - %tmp5661 = invoke i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE( %struct.wxDateTime* %this, %"struct.wxDateTime::TimeZone"* %tz ) zeroext + %tmp5661 = invoke zeroext i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE( %struct.wxDateTime* %this, %"struct.wxDateTime::TimeZone"* %tz ) to label %invcont5660 unwind label %lpad ; <i16> [#uses=0] invcont5660: ; preds = %bb5657 ret void @@ -120,7 +120,7 @@ invcont5814: ; preds = %bb448.i8694, %bb265.i8606 invoke void (%struct.wxString*, i32*, ...)* @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 %tmp58165817 ) to label %invcont5831 unwind label %lpad invcont5831: ; preds = %invcont5814 - %tmp5862 = invoke i8 @_ZN12wxStringBase10ConcatSelfEmPKwm( %struct.wxStringBase* null, i32 0, i32* null, i32 0 ) zeroext + %tmp5862 = invoke zeroext i8 @_ZN12wxStringBase10ConcatSelfEmPKwm( %struct.wxStringBase* null, i32 0, i32* null, i32 0 ) to label %bb7834 unwind label %lpad8185 ; <i8> [#uses=0] bb5968: ; preds = %bb3314 invoke void (%struct.wxString*, i32*, ...)* @_ZN8wxString6FormatEPKwz( %struct.wxString* noalias sret null, i32* null, i32 0 ) @@ -158,11 +158,11 @@ lpad8185: ; preds = %invcont5831 declare void @_Z10wxOnAssertPKwiPKcS0_S0_(i32*, i32, i8*, i32*, i32*) -declare i8 @_ZN12wxStringBase10ConcatSelfEmPKwm(%struct.wxStringBase*, i32, i32*, i32) zeroext +declare zeroext i8 @_ZN12wxStringBase10ConcatSelfEmPKwm(%struct.wxStringBase*, i32, i32*, i32) declare %struct.tm* @gmtime_r(i32*, %struct.tm*) -declare i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE(%struct.wxDateTime*, %"struct.wxDateTime::TimeZone"*) zeroext +declare zeroext i16 @_ZNK10wxDateTime12GetDayOfYearERKNS_8TimeZoneE(%struct.wxDateTime*, %"struct.wxDateTime::TimeZone"*) declare %struct.wxStringBase* @_ZN12wxStringBase6appendEmw(%struct.wxStringBase*, i32, i32) diff --git a/test/CodeGen/X86/2008-07-11-SpillerBug.ll b/test/CodeGen/X86/2008-07-11-SpillerBug.ll deleted file mode 100644 index dee7415..0000000 --- a/test/CodeGen/X86/2008-07-11-SpillerBug.ll +++ /dev/null @@ -1,52 +0,0 @@ -; RUN: llc < %s -march=x86 -relocation-model=static -disable-fp-elim -post-RA-scheduler=false -asm-verbose=0 | FileCheck %s -; PR2536 - -; CHECK: andl $65534, % -; CHECK-NEXT: movl % -; CHECK-NEXT: movzwl - -@g_5 = external global i16 ; <i16*> [#uses=2] -@g_107 = external global i16 ; <i16*> [#uses=1] -@g_229 = external global i32 ; <i32*> [#uses=1] -@g_227 = external global i16 ; <i16*> [#uses=1] - -define i32 @func_54(i32 %p_55, i16 zeroext %p_56) nounwind { -entry: - load i16* @g_5, align 2 ; <i16>:0 [#uses=1] - zext i16 %0 to i32 ; <i32>:1 [#uses=1] - %.mask = and i32 %1, 65534 ; <i32> [#uses=1] - icmp eq i32 %.mask, 0 ; <i1>:2 [#uses=1] - load i32* @g_229, align 4 ; <i32>:3 [#uses=1] - load i16* @g_227, align 2 ; <i16>:4 [#uses=1] - icmp eq i16 %4, 0 ; <i1>:5 [#uses=1] - load i16* @g_5, align 2 ; <i16>:6 [#uses=1] - br label %bb - -bb: ; preds = %bb7.preheader, %entry - %indvar4 = phi i32 [ 0, %entry ], [ %indvar.next5, %bb7.preheader ] ; <i32> [#uses=1] - %p_56_addr.1.reg2mem.0 = phi i16 [ %p_56, %entry ], [ %p_56_addr.0, %bb7.preheader ] ; <i16> [#uses=2] - br i1 %2, label %bb7.preheader, label %bb5 - -bb5: ; preds = %bb - store i16 %6, i16* @g_107, align 2 - br label %bb7.preheader - -bb7.preheader: ; preds = %bb5, %bb - icmp eq i16 %p_56_addr.1.reg2mem.0, 0 ; <i1>:7 [#uses=1] - %.0 = select i1 %7, i32 1, i32 %3 ; <i32> [#uses=1] - urem i32 1, %.0 ; <i32>:8 [#uses=1] - icmp eq i32 %8, 0 ; <i1>:9 [#uses=1] - %.not = xor i1 %9, true ; <i1> [#uses=1] - %.not1 = xor i1 %5, true ; <i1> [#uses=1] - %brmerge = or i1 %.not, %.not1 ; <i1> [#uses=1] - %iftmp.6.0 = select i1 %brmerge, i32 3, i32 0 ; <i32> [#uses=1] - mul i32 %iftmp.6.0, %3 ; <i32>:10 [#uses=1] - icmp eq i32 %10, 0 ; <i1>:11 [#uses=1] - %p_56_addr.0 = select i1 %11, i16 %p_56_addr.1.reg2mem.0, i16 1 ; <i16> [#uses=1] - %indvar.next5 = add i32 %indvar4, 1 ; <i32> [#uses=2] - %exitcond6 = icmp eq i32 %indvar.next5, 17 ; <i1> [#uses=1] - br i1 %exitcond6, label %bb25, label %bb - -bb25: ; preds = %bb7.preheader - ret i32 1 -} diff --git a/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll b/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll deleted file mode 100644 index ce9e389..0000000 --- a/test/CodeGen/X86/2008-08-23-X86-64AsmBug.ll +++ /dev/null @@ -1,59 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movd | count 1 -; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep movq -; PR2677 - - - %struct.Bigint = type { %struct.Bigint*, i32, i32, i32, i32, [1 x i32] } - -define double @_Z7qstrtodPKcPS0_Pb(i8* %s00, i8** %se, i8* %ok) nounwind { -entry: - br label %bb163 - -bb151: ; preds = %entry - br label %bb163 - -bb163: ; preds = %bb151, %entry - %tmp366 = load double* null, align 8 ; <double> [#uses=1] - %tmp368 = fmul double %tmp366, 0.000000e+00 ; <double> [#uses=1] - %tmp368226 = bitcast double %tmp368 to i64 ; <i64> [#uses=1] - br label %bb5.i - -bb5.i: ; preds = %bb5.i57.i, %bb163 - %b.0.i = phi %struct.Bigint* [ null, %bb163 ] ; <%struct.Bigint*> [#uses=1] - %tmp3.i7.i728 = load i32* null, align 4 ; <i32> [#uses=1] - br label %bb.i27.i - -bb.i27.i: ; preds = %bb.i27.i, %bb5.i - %tmp23.i20.i = lshr i32 0, 16 ; <i32> [#uses=1] - br label %bb5.i57.i - -bb5.i57.i: ; preds = %bb.i27.i - %tmp50.i35.i = load i32* null, align 4 ; <i32> [#uses=1] - %tmp51.i36.i = add i32 %tmp50.i35.i, 1 ; <i32> [#uses=2] - %tmp2.i.i37.i = shl i32 1, %tmp51.i36.i ; <i32> [#uses=2] - %tmp4.i.i38.i = shl i32 %tmp2.i.i37.i, 2 ; <i32> [#uses=1] - %tmp7.i.i39.i = add i32 %tmp4.i.i38.i, 28 ; <i32> [#uses=1] - %tmp8.i.i40.i = malloc i8, i32 %tmp7.i.i39.i ; <i8*> [#uses=1] - %tmp9.i.i41.i = bitcast i8* %tmp8.i.i40.i to %struct.Bigint* ; <%struct.Bigint*> [#uses=2] - store i32 %tmp51.i36.i, i32* null, align 8 - store i32 %tmp2.i.i37.i, i32* null, align 4 - free %struct.Bigint* %b.0.i - store i32 %tmp23.i20.i, i32* null, align 4 - %tmp74.i61.i = add i32 %tmp3.i7.i728, 1 ; <i32> [#uses=1] - store i32 %tmp74.i61.i, i32* null, align 4 - br label %bb7.i - -bb7.i: ; preds = %bb5.i57.i - %tmp514 = load i32* null, align 4 ; <i32> [#uses=1] - %tmp515 = sext i32 %tmp514 to i64 ; <i64> [#uses=1] - %tmp516 = shl i64 %tmp515, 2 ; <i64> [#uses=1] - %tmp517 = add i64 %tmp516, 8 ; <i64> [#uses=1] - %tmp519 = getelementptr %struct.Bigint* %tmp9.i.i41.i, i32 0, i32 3 ; <i32*> [#uses=1] - %tmp523 = bitcast i32* %tmp519 to i8* ; <i8*> [#uses=1] - call void @llvm.memcpy.i64( i8* null, i8* %tmp523, i64 %tmp517, i32 1 ) - %tmp524136 = bitcast i64 %tmp368226 to double ; <double> [#uses=1] - store double %tmp524136, double* null - unreachable -} - -declare void @llvm.memcpy.i64(i8*, i8*, i64, i32) nounwind diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll index b92c789..1d27fc5 100644 --- a/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll +++ b/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll @@ -1,5 +1,5 @@ ; Check that eh_return & unwind_init were properly lowered -; RUN: llc < %s | grep %ebp | count 7 +; RUN: llc < %s | grep %ebp | count 9 ; RUN: llc < %s | grep %ecx | count 5 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" diff --git a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll index 00ab735..d423bfc 100644 --- a/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll +++ b/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll @@ -1,5 +1,5 @@ ; Check that eh_return & unwind_init were properly lowered -; RUN: llc < %s | grep %rbp | count 5 +; RUN: llc < %s | grep %rbp | count 7 ; RUN: llc < %s | grep %rcx | count 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" diff --git a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll index 947a1f1..dfd165c 100644 --- a/test/CodeGen/X86/2008-09-18-inline-asm-2.ll +++ b/test/CodeGen/X86/2008-09-18-inline-asm-2.ll @@ -1,12 +1,32 @@ -; RUN: llc < %s -march=x86 -regalloc=linearscan | grep "#%ebp %edi %ebx 8(%esi) %eax %dl" -; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%ebx %esi %edi 8(%ebp) %eax %dl" -; RUN: llc < %s -march=x86 -regalloc=basic | grep "#%ebp %esi %edx 8(%edi) %eax %bl" -; RUN: llc < %s -march=x86 -regalloc=greedy | grep "#%edx %edi %ebp 8(%esi) %eax %bl" +; RUN: llc < %s -march=x86 -regalloc=linearscan | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=fast | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=basic | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=greedy | FileCheck %s -; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers +; The 1st, 2nd, 3rd and 5th registers must all be different. The registers ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th -; operand. There are many combinations that work; this is what llc puts out now. -; ModuleID = '<stdin>' +; operand. +; +; CHECK: 1st=[[A1:%...]] +; CHECK-NOT: [[A1]] +; CHECK: 2nd=[[A2:%...]] +; CHECK-NOT: [[A1]] +; CHECK-NOT: [[A2]] +; CHECK: 3rd=[[A3:%...]] +; CHECK-NOT: [[A1]] +; CHECK-NOT: [[A2]] +; CHECK-NOT: [[A3]] +; CHECK: 5th=[[A5:%...]] +; CHECK-NOT: [[A1]] +; CHECK-NOT; [[A5]] +; CHECK: =4th + +; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th. +; CHECK: 1%e[[S1:.]]x +; CHECK: 5%e[[S5:.]]x +; CHECK-NOT: %[[S1]] +; CHECK-NOT: %[[S5]] + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" %struct.foo = type { i32, i32, i8* } @@ -19,7 +39,7 @@ entry: %3 = load i32* %0, align 4 ; <i32> [#uses=1] %4 = load i32* %1, align 4 ; <i32> [#uses=1] %5 = load i8* %state, align 1 ; <i8> [#uses=1] - %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3] + %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#1st=$0 $1 2nd=$1 $2 3rd=$2 $4 5th=$4 $3=4th 1$0 1%eXx 5$4 5%eXx 6th=$5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3] %asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; <i32> [#uses=1] %asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; <i32> [#uses=1] store i32 %asmresult1, i32* %0 diff --git a/test/CodeGen/X86/2008-09-25-sseregparm-1.ll b/test/CodeGen/X86/2008-09-25-sseregparm-1.ll index c92a8f4..fc3e35e 100644 --- a/test/CodeGen/X86/2008-09-25-sseregparm-1.ll +++ b/test/CodeGen/X86/2008-09-25-sseregparm-1.ll @@ -2,11 +2,11 @@ ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep fld | count 2 ; check 'inreg' attribute for sse_regparm -define double @foo1() inreg nounwind { +define inreg double @foo1() nounwind { ret double 1.0 } -define float @foo2() inreg nounwind { +define inreg float @foo2() nounwind { ret float 1.0 } diff --git a/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll b/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll index e97b63d..2e27811 100644 --- a/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll +++ b/test/CodeGen/X86/2008-12-12-PrivateEHSymbol.ll @@ -1,7 +1,5 @@ -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu | grep ^.L_Z1fv.eh -; RUN: llc < %s -march=x86 -mtriple=i686-unknown-linux-gnu | grep ^.L_Z1fv.eh -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin9 | grep ^__Z1fv.eh -; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin9 | grep ^__Z1fv.eh +; RUN: llc < %s -disable-cfi -march=x86-64 -mtriple=x86_64-apple-darwin9 | grep ^__Z1fv.eh +; RUN: llc < %s -disable-cfi -march=x86 -mtriple=i386-apple-darwin9 | grep ^__Z1fv.eh define void @_Z1fv() { entry: diff --git a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll index 5eba9b9..75e0b8a 100644 --- a/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll +++ b/test/CodeGen/X86/2008-12-19-EarlyClobberBug.ll @@ -4,7 +4,7 @@ ; CHECK: ## InlineAsm End ; CHECK-NEXT: BB0_2: -; CHECK-NEXT: movl %esi, %eax +; CHECK-NEXT: {{movl %esi, %eax|addl %edi, %esi}} @"\01LC" = internal constant [7 x i8] c"n0=%d\0A\00" ; <[7 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll b/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll deleted file mode 100644 index 35fac0c..0000000 --- a/test/CodeGen/X86/2009-01-29-LocalRegAllocBug.ll +++ /dev/null @@ -1,38 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9.6 -regalloc=fast -disable-fp-elim -; rdar://6538384 - - %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } - %struct.Lit = type { i32 } - %struct.StreamBuffer = type { %struct.FILE*, [1048576 x i8], i32, i32 } - %struct.__sFILEX = type opaque - %struct.__sbuf = type { i8*, i32 } - -declare fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer*) - -declare i8* @llvm.eh.exception() nounwind - -define i32 @main(i32 %argc, i8** nocapture %argv) noreturn { -entry: - %0 = invoke fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer* null) - to label %bb1.i16.i.i unwind label %lpad.i.i ; <i32> [#uses=0] - -bb1.i16.i.i: ; preds = %entry - br i1 false, label %bb.i.i.i.i, label %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i - -bb.i.i.i.i: ; preds = %bb1.i16.i.i - br label %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i - -_ZN3vecI3LitE4pushERKS0_.exit.i.i.i: ; preds = %bb.i.i.i.i, %bb1.i16.i.i - %lits.i.i.0.0 = phi %struct.Lit* [ null, %bb1.i16.i.i ], [ null, %bb.i.i.i.i ] ; <%struct.Lit*> [#uses=1] - %1 = invoke fastcc i32 @_Z8parseIntI12StreamBufferEiRT_(%struct.StreamBuffer* null) - to label %.noexc21.i.i unwind label %lpad.i.i ; <i32> [#uses=0] - -.noexc21.i.i: ; preds = %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i - unreachable - -lpad.i.i: ; preds = %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i, %entry - %lits.i.i.0.3 = phi %struct.Lit* [ %lits.i.i.0.0, %_ZN3vecI3LitE4pushERKS0_.exit.i.i.i ], [ null, %entry ] ; <%struct.Lit*> [#uses=1] - %eh_ptr.i.i = call i8* @llvm.eh.exception() ; <i8*> [#uses=0] - free %struct.Lit* %lits.i.i.0.3 - unreachable -} diff --git a/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll b/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll deleted file mode 100644 index aba4bfc..0000000 --- a/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll +++ /dev/null @@ -1,71 +0,0 @@ -; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8 -pre-alloc-split -regalloc=linearscan - -define i32 @main() nounwind { -bb4.i.thread: - br label %bb5.i4 - -bb16: ; preds = %bb111.i - %phitmp = add i32 %indvar.reg2mem.4, 1 ; <i32> [#uses=2] - switch i32 %indvar.reg2mem.4, label %bb100.i [ - i32 0, label %bb5.i4 - i32 1, label %bb5.i4 - i32 2, label %bb5.i4 - i32 5, label %bb.i14.i - i32 6, label %bb.i14.i - i32 7, label %bb.i14.i - ] - -bb5.i4: ; preds = %bb16, %bb16, %bb16, %bb4.i.thread - br i1 false, label %bb102.i, label %bb103.i - -bb.i14.i: ; preds = %bb16, %bb16, %bb16 - %0 = malloc [600 x i32] ; <[600 x i32]*> [#uses=0] - %1 = icmp eq i32 %phitmp, 7 ; <i1> [#uses=1] - %tl.0.i = select i1 %1, float 1.000000e+02, float 1.000000e+00 ; <float> [#uses=1] - %2 = icmp eq i32 %phitmp, 8 ; <i1> [#uses=1] - %tu.0.i = select i1 %2, float 1.000000e+02, float 1.000000e+00 ; <float> [#uses=1] - br label %bb30.i - -bb30.i: ; preds = %bb36.i, %bb.i14.i - %i.1173.i = phi i32 [ 0, %bb.i14.i ], [ %indvar.next240.i, %bb36.i ] ; <i32> [#uses=3] - %3 = icmp eq i32 0, %i.1173.i ; <i1> [#uses=1] - br i1 %3, label %bb33.i, label %bb34.i - -bb33.i: ; preds = %bb30.i - store float %tl.0.i, float* null, align 4 - br label %bb36.i - -bb34.i: ; preds = %bb30.i - %4 = icmp eq i32 0, %i.1173.i ; <i1> [#uses=1] - br i1 %4, label %bb35.i, label %bb36.i - -bb35.i: ; preds = %bb34.i - store float %tu.0.i, float* null, align 4 - br label %bb36.i - -bb36.i: ; preds = %bb35.i, %bb34.i, %bb33.i - %indvar.next240.i = add i32 %i.1173.i, 1 ; <i32> [#uses=1] - br label %bb30.i - -bb100.i: ; preds = %bb16 - ret i32 0 - -bb102.i: ; preds = %bb5.i4 - br label %bb103.i - -bb103.i: ; preds = %bb102.i, %bb5.i4 - %indvar.reg2mem.4 = phi i32 [ 0, %bb5.i4 ], [ 0, %bb102.i ] ; <i32> [#uses=2] - %n.0.reg2mem.1.i = phi i32 [ 0, %bb102.i ], [ 0, %bb5.i4 ] ; <i32> [#uses=1] - %5 = icmp eq i32 0, 0 ; <i1> [#uses=1] - br i1 %5, label %bb111.i, label %bb108.i - -bb108.i: ; preds = %bb103.i - ret i32 0 - -bb111.i: ; preds = %bb103.i - %6 = icmp sgt i32 %n.0.reg2mem.1.i, 7 ; <i1> [#uses=1] - br i1 %6, label %bb16, label %bb112.i - -bb112.i: ; preds = %bb111.i - unreachable -} diff --git a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll index 2853930..45fc269 100644 --- a/test/CodeGen/X86/2009-03-13-PHIElimBug.ll +++ b/test/CodeGen/X86/2009-03-13-PHIElimBug.ll @@ -28,5 +28,5 @@ lpad: ; preds = %cont, %entry } ; CHECK: call{{.*}}f -; CHECK-NEXT: Ltmp0: -; CHECK-NEXT: movl %eax, %esi +; CHECK: movl %eax, %esi +; CHECK: call{{.*}}g diff --git a/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll b/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll deleted file mode 100644 index 91c5440..0000000 --- a/test/CodeGen/X86/2009-10-08-MachineLICMBug.ll +++ /dev/null @@ -1,264 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic -stats |& grep {machine-licm} | grep 2 -; rdar://7274692 - -%0 = type { [125 x i32] } -%1 = type { i32 } -%struct..5sPragmaType = type { i8*, i32 } -%struct.AggInfo = type { i8, i8, i32, %struct.ExprList*, i32, %struct.AggInfo_col*, i32, i32, i32, %struct.AggInfo_func*, i32, i32 } -%struct.AggInfo_col = type { %struct.Table*, i32, i32, i32, i32, %struct.Expr* } -%struct.AggInfo_func = type { %struct.Expr*, %struct.FuncDef*, i32, i32 } -%struct.AuxData = type { i8*, void (i8*)* } -%struct.Bitvec = type { i32, i32, i32, %0 } -%struct.BtCursor = type { %struct.Btree*, %struct.BtShared*, %struct.BtCursor*, %struct.BtCursor*, i32 (i8*, i32, i8*, i32, i8*)*, i8*, i32, %struct.MemPage*, i32, %struct.CellInfo, i8, i8, i8*, i64, i32, i8, i32* } -%struct.BtLock = type { %struct.Btree*, i32, i8, %struct.BtLock* } -%struct.BtShared = type { %struct.Pager*, %struct.sqlite3*, %struct.BtCursor*, %struct.MemPage*, i8, i8, i8, i8, i8, i8, i8, i8, i32, i16, i16, i32, i32, i32, i32, i8, i32, i8*, void (i8*)*, %struct.sqlite3_mutex*, %struct.BusyHandler, i32, %struct.BtShared*, %struct.BtLock*, %struct.Btree* } -%struct.Btree = type { %struct.sqlite3*, %struct.BtShared*, i8, i8, i8, i32, %struct.Btree*, %struct.Btree* } -%struct.BtreeMutexArray = type { i32, [11 x %struct.Btree*] } -%struct.BusyHandler = type { i32 (i8*, i32)*, i8*, i32 } -%struct.CellInfo = type { i8*, i64, i32, i32, i16, i16, i16, i16 } -%struct.CollSeq = type { i8*, i8, i8, i8*, i32 (i8*, i32, i8*, i32, i8*)*, void (i8*)* } -%struct.Column = type { i8*, %struct.Expr*, i8*, i8*, i8, i8, i8, i8 } -%struct.Context = type { i64, i32, %struct.Fifo } -%struct.CountCtx = type { i64 } -%struct.Cursor = type { %struct.BtCursor*, i32, i64, i64, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i64, %struct.Btree*, i32, i8*, i64, i8*, %struct.KeyInfo*, i32, i64, %struct.sqlite3_vtab_cursor*, %struct.sqlite3_module*, i32, i32, i32*, i32*, i8* } -%struct.Db = type { i8*, %struct.Btree*, i8, i8, i8*, void (i8*)*, %struct.Schema* } -%struct.DbPage = type { %struct.Pager*, i32, %struct.DbPage*, %struct.DbPage*, %struct.PagerLruLink, %struct.DbPage*, i8, i8, i8, i8, i8, i16, %struct.DbPage*, %struct.DbPage*, i8* } -%struct.Expr = type { i8, i8, i16, %struct.CollSeq*, %struct.Expr*, %struct.Expr*, %struct.ExprList*, %struct..5sPragmaType, %struct..5sPragmaType, i32, i32, %struct.AggInfo*, i32, i32, %struct.Select*, %struct.Table*, i32 } -%struct.ExprList = type { i32, i32, i32, %struct.ExprList_item* } -%struct.ExprList_item = type { %struct.Expr*, i8*, i8, i8, i8 } -%struct.FILE = type { i8*, i32, i32, i16, i16, %struct..5sPragmaType, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct..5sPragmaType, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct..5sPragmaType, i32, i64 } -%struct.FKey = type { %struct.Table*, %struct.FKey*, i8*, %struct.FKey*, i32, %struct.sColMap*, i8, i8, i8, i8 } -%struct.Fifo = type { i32, %struct.FifoPage*, %struct.FifoPage* } -%struct.FifoPage = type { i32, i32, i32, %struct.FifoPage*, [1 x i64] } -%struct.FuncDef = type { i16, i8, i8, i8, i8*, %struct.FuncDef*, void (%struct.sqlite3_context*, i32, %struct.Mem**)*, void (%struct.sqlite3_context*, i32, %struct.Mem**)*, void (%struct.sqlite3_context*)*, [1 x i8] } -%struct.Hash = type { i8, i8, i32, i32, %struct.HashElem*, %struct._ht* } -%struct.HashElem = type { %struct.HashElem*, %struct.HashElem*, i8*, i8*, i32 } -%struct.IdList = type { %struct..5sPragmaType*, i32, i32 } -%struct.Index = type { i8*, i32, i32*, i32*, %struct.Table*, i32, i8, i8, i8*, %struct.Index*, %struct.Schema*, i8*, i8** } -%struct.KeyInfo = type { %struct.sqlite3*, i8, i8, i8, i32, i8*, [1 x %struct.CollSeq*] } -%struct.Mem = type { %struct.CountCtx, double, %struct.sqlite3*, i8*, i32, i16, i8, i8, void (i8*)* } -%struct.MemPage = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i16, i16, i16, i16, i16, i16, [5 x %struct._OvflCell], %struct.BtShared*, i8*, %struct.DbPage*, i32, %struct.MemPage* } -%struct.Module = type { %struct.sqlite3_module*, i8*, i8*, void (i8*)* } -%struct.Op = type { i8, i8, i8, i8, i32, i32, i32, %1 } -%struct.Pager = type { %struct.sqlite3_vfs*, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.Bitvec*, %struct.Bitvec*, i8*, i8*, i8*, i8*, %struct.sqlite3_file*, %struct.sqlite3_file*, %struct.sqlite3_file*, %struct.BusyHandler*, %struct.PagerLruList, %struct.DbPage*, %struct.DbPage*, %struct.DbPage*, i64, i64, i64, i64, i64, i32, void (%struct.DbPage*, i32)*, void (%struct.DbPage*, i32)*, i32, %struct.DbPage**, i8*, [16 x i8] } -%struct.PagerLruLink = type { %struct.DbPage*, %struct.DbPage* } -%struct.PagerLruList = type { %struct.DbPage*, %struct.DbPage*, %struct.DbPage* } -%struct.Schema = type { i32, %struct.Hash, %struct.Hash, %struct.Hash, %struct.Hash, %struct.Table*, i8, i8, i16, i32, %struct.sqlite3* } -%struct.Select = type { %struct.ExprList*, i8, i8, i8, i8, i8, i8, i8, %struct.SrcList*, %struct.Expr*, %struct.ExprList*, %struct.Expr*, %struct.ExprList*, %struct.Select*, %struct.Select*, %struct.Select*, %struct.Expr*, %struct.Expr*, i32, i32, [3 x i32] } -%struct.SrcList = type { i16, i16, [1 x %struct.SrcList_item] } -%struct.SrcList_item = type { i8*, i8*, i8*, %struct.Table*, %struct.Select*, i8, i8, i32, %struct.Expr*, %struct.IdList*, i64 } -%struct.Table = type { i8*, i32, %struct.Column*, i32, %struct.Index*, i32, %struct.Select*, i32, %struct.Trigger*, %struct.FKey*, i8*, %struct.Expr*, i32, i8, i8, i8, i8, i8, i8, i8, %struct.Module*, %struct.sqlite3_vtab*, i32, i8**, %struct.Schema* } -%struct.Trigger = type { i8*, i8*, i8, i8, %struct.Expr*, %struct.IdList*, %struct..5sPragmaType, %struct.Schema*, %struct.Schema*, %struct.TriggerStep*, %struct.Trigger* } -%struct.TriggerStep = type { i32, i32, %struct.Trigger*, %struct.Select*, %struct..5sPragmaType, %struct.Expr*, %struct.ExprList*, %struct.IdList*, %struct.TriggerStep*, %struct.TriggerStep* } -%struct.Vdbe = type { %struct.sqlite3*, %struct.Vdbe*, %struct.Vdbe*, i32, i32, %struct.Op*, i32, i32, i32*, %struct.Mem**, %struct.Mem*, i32, %struct.Cursor**, i32, %struct.Mem*, i8**, i32, i32, i32, %struct.Mem*, i32, i32, %struct.Fifo, i32, i32, %struct.Context*, i32, i32, i32, i32, i32, [25 x i32], i32, i32, i8**, i8*, %struct.Mem*, i8, i8, i8, i8, i8, i8, i32, i64, i32, %struct.BtreeMutexArray, i32, i8*, i32 } -%struct.VdbeFunc = type { %struct.FuncDef*, i32, [1 x %struct.AuxData] } -%struct._OvflCell = type { i8*, i16 } -%struct._RuneCharClass = type { [14 x i8], i32 } -%struct._RuneEntry = type { i32, i32, i32, i32* } -%struct._RuneLocale = type { [8 x i8], [32 x i8], i32 (i8*, i32, i8**)*, i32 (i32, i8*, i32, i8**)*, i32, [256 x i32], [256 x i32], [256 x i32], %struct._RuneRange, %struct._RuneRange, %struct._RuneRange, i8*, i32, i32, %struct._RuneCharClass* } -%struct._RuneRange = type { i32, %struct._RuneEntry* } -%struct.__sFILEX = type opaque -%struct._ht = type { i32, %struct.HashElem* } -%struct.callback_data = type { %struct.sqlite3*, i32, i32, %struct.FILE*, i32, i32, i32, i8*, [20 x i8], [100 x i32], [100 x i32], [20 x i8], %struct.previous_mode_data, [1024 x i8], i8* } -%struct.previous_mode_data = type { i32, i32, i32, [100 x i32] } -%struct.sColMap = type { i32, i8* } -%struct.sqlite3 = type { %struct.sqlite3_vfs*, i32, %struct.Db*, i32, i32, i32, i32, i8, i8, i8, i8, i32, %struct.CollSeq*, i64, i64, i32, i32, i32, %struct.sqlite3_mutex*, %struct.sqlite3InitInfo, i32, i8**, %struct.Vdbe*, i32, void (i8*, i8*)*, i8*, void (i8*, i8*, i64)*, i8*, i8*, i32 (i8*)*, i8*, void (i8*)*, i8*, void (i8*, i32, i8*, i8*, i64)*, void (i8*, %struct.sqlite3*, i32, i8*)*, void (i8*, %struct.sqlite3*, i32, i8*)*, i8*, %struct.Mem*, i8*, i8*, %union.anon, i32 (i8*, i32, i8*, i8*, i8*, i8*)*, i8*, i32 (i8*)*, i8*, i32, %struct.Hash, %struct.Table*, %struct.sqlite3_vtab**, i32, %struct.Hash, %struct.Hash, %struct.BusyHandler, i32, [2 x %struct.Db], i8 } -%struct.sqlite3InitInfo = type { i32, i32, i8 } -%struct.sqlite3_context = type { %struct.FuncDef*, %struct.VdbeFunc*, %struct.Mem, %struct.Mem*, i32, %struct.CollSeq* } -%struct.sqlite3_file = type { %struct.sqlite3_io_methods* } -%struct.sqlite3_index_constraint = type { i32, i8, i8, i32 } -%struct.sqlite3_index_constraint_usage = type { i32, i8 } -%struct.sqlite3_index_info = type { i32, %struct.sqlite3_index_constraint*, i32, %struct.sqlite3_index_constraint_usage*, %struct.sqlite3_index_constraint_usage*, i32, i8*, i32, i32, double } -%struct.sqlite3_io_methods = type { i32, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*, i8*, i32, i64)*, i32 (%struct.sqlite3_file*, i8*, i32, i64)*, i32 (%struct.sqlite3_file*, i64)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*, i64*)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*, i32)*, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*, i32, i8*)*, i32 (%struct.sqlite3_file*)*, i32 (%struct.sqlite3_file*)* } -%struct.sqlite3_module = type { i32, i32 (%struct.sqlite3*, i8*, i32, i8**, %struct.sqlite3_vtab**, i8**)*, i32 (%struct.sqlite3*, i8*, i32, i8**, %struct.sqlite3_vtab**, i8**)*, i32 (%struct.sqlite3_vtab*, %struct.sqlite3_index_info*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*, %struct.sqlite3_vtab_cursor**)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*, i32, i8*, i32, %struct.Mem**)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*)*, i32 (%struct.sqlite3_vtab_cursor*, %struct.sqlite3_context*, i32)*, i32 (%struct.sqlite3_vtab_cursor*, i64*)*, i32 (%struct.sqlite3_vtab*, i32, %struct.Mem**, i64*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*)*, i32 (%struct.sqlite3_vtab*, i32, i8*, void (%struct.sqlite3_context*, i32, %struct.Mem**)**, i8**)*, i32 (%struct.sqlite3_vtab*, i8*)* } -%struct.sqlite3_mutex = type opaque -%struct.sqlite3_vfs = type { i32, i32, i32, %struct.sqlite3_vfs*, i8*, i8*, i32 (%struct.sqlite3_vfs*, i8*, %struct.sqlite3_file*, i32, i32*)*, i32 (%struct.sqlite3_vfs*, i8*, i32)*, i32 (%struct.sqlite3_vfs*, i8*, i32)*, i32 (%struct.sqlite3_vfs*, i32, i8*)*, i32 (%struct.sqlite3_vfs*, i8*, i32, i8*)*, i8* (%struct.sqlite3_vfs*, i8*)*, void (%struct.sqlite3_vfs*, i32, i8*)*, i8* (%struct.sqlite3_vfs*, i8*, i8*)*, void (%struct.sqlite3_vfs*, i8*)*, i32 (%struct.sqlite3_vfs*, i32, i8*)*, i32 (%struct.sqlite3_vfs*, i32)*, i32 (%struct.sqlite3_vfs*, double*)* } -%struct.sqlite3_vtab = type { %struct.sqlite3_module*, i32, i8* } -%struct.sqlite3_vtab_cursor = type { %struct.sqlite3_vtab* } -%union.anon = type { double } - -@_DefaultRuneLocale = external global %struct._RuneLocale ; <%struct._RuneLocale*> [#uses=2] -@__stderrp = external global %struct.FILE* ; <%struct.FILE**> [#uses=1] -@.str10 = internal constant [16 x i8] c"Out of memory!\0A\00", align 1 ; <[16 x i8]*> [#uses=1] -@llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.callback_data*, i8*)* @set_table_name to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define fastcc void @set_table_name(%struct.callback_data* nocapture %p, i8* %zName) nounwind ssp { -entry: - %0 = getelementptr inbounds %struct.callback_data* %p, i32 0, i32 7 ; <i8**> [#uses=3] - %1 = load i8** %0, align 4 ; <i8*> [#uses=2] - %2 = icmp eq i8* %1, null ; <i1> [#uses=1] - br i1 %2, label %bb1, label %bb - -bb: ; preds = %entry - free i8* %1 - store i8* null, i8** %0, align 4 - br label %bb1 - -bb1: ; preds = %bb, %entry - %3 = icmp eq i8* %zName, null ; <i1> [#uses=1] - br i1 %3, label %return, label %bb2 - -bb2: ; preds = %bb1 - %4 = load i8* %zName, align 1 ; <i8> [#uses=2] - %5 = zext i8 %4 to i32 ; <i32> [#uses=2] - %6 = icmp sgt i8 %4, -1 ; <i1> [#uses=1] - br i1 %6, label %bb.i.i, label %bb1.i.i - -bb.i.i: ; preds = %bb2 - %7 = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i32 0, i32 5, i32 %5 ; <i32*> [#uses=1] - %8 = load i32* %7, align 4 ; <i32> [#uses=1] - %9 = and i32 %8, 256 ; <i32> [#uses=1] - br label %isalpha.exit - -bb1.i.i: ; preds = %bb2 - %10 = tail call i32 @__maskrune(i32 %5, i32 256) nounwind ; <i32> [#uses=1] - br label %isalpha.exit - -isalpha.exit: ; preds = %bb1.i.i, %bb.i.i - %storemerge.in.in.i.i = phi i32 [ %9, %bb.i.i ], [ %10, %bb1.i.i ] ; <i32> [#uses=1] - %storemerge.in.i.i = icmp eq i32 %storemerge.in.in.i.i, 0 ; <i1> [#uses=1] - br i1 %storemerge.in.i.i, label %bb3, label %bb5 - -bb3: ; preds = %isalpha.exit - %11 = load i8* %zName, align 1 ; <i8> [#uses=2] - %12 = icmp eq i8 %11, 95 ; <i1> [#uses=1] - br i1 %12, label %bb5, label %bb12.preheader - -bb5: ; preds = %bb3, %isalpha.exit - %.pre = load i8* %zName, align 1 ; <i8> [#uses=1] - br label %bb12.preheader - -bb12.preheader: ; preds = %bb5, %bb3 - %13 = phi i8 [ %.pre, %bb5 ], [ %11, %bb3 ] ; <i8> [#uses=1] - %needQuote.1.ph = phi i32 [ 0, %bb5 ], [ 1, %bb3 ] ; <i32> [#uses=2] - %14 = icmp eq i8 %13, 0 ; <i1> [#uses=1] - br i1 %14, label %bb13, label %bb7 - -bb7: ; preds = %bb11, %bb12.preheader - %i.011 = phi i32 [ %tmp17, %bb11 ], [ 0, %bb12.preheader ] ; <i32> [#uses=2] - %n.110 = phi i32 [ %26, %bb11 ], [ 0, %bb12.preheader ] ; <i32> [#uses=3] - %needQuote.19 = phi i32 [ %needQuote.0, %bb11 ], [ %needQuote.1.ph, %bb12.preheader ] ; <i32> [#uses=2] - %scevgep16 = getelementptr i8* %zName, i32 %i.011 ; <i8*> [#uses=2] - %tmp17 = add i32 %i.011, 1 ; <i32> [#uses=2] - %scevgep18 = getelementptr i8* %zName, i32 %tmp17 ; <i8*> [#uses=1] - %15 = load i8* %scevgep16, align 1 ; <i8> [#uses=2] - %16 = zext i8 %15 to i32 ; <i32> [#uses=2] - %17 = icmp sgt i8 %15, -1 ; <i1> [#uses=1] - br i1 %17, label %bb.i.i2, label %bb1.i.i3 - -bb.i.i2: ; preds = %bb7 - %18 = getelementptr inbounds %struct._RuneLocale* @_DefaultRuneLocale, i32 0, i32 5, i32 %16 ; <i32*> [#uses=1] - %19 = load i32* %18, align 4 ; <i32> [#uses=1] - %20 = and i32 %19, 1280 ; <i32> [#uses=1] - br label %isalnum.exit - -bb1.i.i3: ; preds = %bb7 - %21 = tail call i32 @__maskrune(i32 %16, i32 1280) nounwind ; <i32> [#uses=1] - br label %isalnum.exit - -isalnum.exit: ; preds = %bb1.i.i3, %bb.i.i2 - %storemerge.in.in.i.i4 = phi i32 [ %20, %bb.i.i2 ], [ %21, %bb1.i.i3 ] ; <i32> [#uses=1] - %storemerge.in.i.i5 = icmp eq i32 %storemerge.in.in.i.i4, 0 ; <i1> [#uses=1] - br i1 %storemerge.in.i.i5, label %bb8, label %bb11 - -bb8: ; preds = %isalnum.exit - %22 = load i8* %scevgep16, align 1 ; <i8> [#uses=2] - %23 = icmp eq i8 %22, 95 ; <i1> [#uses=1] - br i1 %23, label %bb11, label %bb9 - -bb9: ; preds = %bb8 - %24 = icmp eq i8 %22, 39 ; <i1> [#uses=1] - %25 = zext i1 %24 to i32 ; <i32> [#uses=1] - %.n.1 = add i32 %n.110, %25 ; <i32> [#uses=1] - br label %bb11 - -bb11: ; preds = %bb9, %bb8, %isalnum.exit - %needQuote.0 = phi i32 [ 1, %bb9 ], [ %needQuote.19, %isalnum.exit ], [ %needQuote.19, %bb8 ] ; <i32> [#uses=2] - %n.0 = phi i32 [ %.n.1, %bb9 ], [ %n.110, %isalnum.exit ], [ %n.110, %bb8 ] ; <i32> [#uses=1] - %26 = add nsw i32 %n.0, 1 ; <i32> [#uses=2] - %27 = load i8* %scevgep18, align 1 ; <i8> [#uses=1] - %28 = icmp eq i8 %27, 0 ; <i1> [#uses=1] - br i1 %28, label %bb13, label %bb7 - -bb13: ; preds = %bb11, %bb12.preheader - %n.1.lcssa = phi i32 [ 0, %bb12.preheader ], [ %26, %bb11 ] ; <i32> [#uses=2] - %needQuote.1.lcssa = phi i32 [ %needQuote.1.ph, %bb12.preheader ], [ %needQuote.0, %bb11 ] ; <i32> [#uses=1] - %29 = add nsw i32 %n.1.lcssa, 2 ; <i32> [#uses=1] - %30 = icmp eq i32 %needQuote.1.lcssa, 0 ; <i1> [#uses=3] - %n.1. = select i1 %30, i32 %n.1.lcssa, i32 %29 ; <i32> [#uses=1] - %31 = add nsw i32 %n.1., 1 ; <i32> [#uses=1] - %32 = malloc i8, i32 %31 ; <i8*> [#uses=7] - store i8* %32, i8** %0, align 4 - %33 = icmp eq i8* %32, null ; <i1> [#uses=1] - br i1 %33, label %bb16, label %bb17 - -bb16: ; preds = %bb13 - %34 = load %struct.FILE** @__stderrp, align 4 ; <%struct.FILE*> [#uses=1] - %35 = bitcast %struct.FILE* %34 to i8* ; <i8*> [#uses=1] - %36 = tail call i32 @"\01_fwrite$UNIX2003"(i8* getelementptr inbounds ([16 x i8]* @.str10, i32 0, i32 0), i32 1, i32 15, i8* %35) nounwind ; <i32> [#uses=0] - tail call void @exit(i32 1) noreturn nounwind - unreachable - -bb17: ; preds = %bb13 - br i1 %30, label %bb23.preheader, label %bb18 - -bb18: ; preds = %bb17 - store i8 39, i8* %32, align 4 - br label %bb23.preheader - -bb23.preheader: ; preds = %bb18, %bb17 - %n.3.ph = phi i32 [ 1, %bb18 ], [ 0, %bb17 ] ; <i32> [#uses=2] - %37 = load i8* %zName, align 1 ; <i8> [#uses=1] - %38 = icmp eq i8 %37, 0 ; <i1> [#uses=1] - br i1 %38, label %bb24, label %bb20 - -bb20: ; preds = %bb22, %bb23.preheader - %storemerge18 = phi i32 [ %tmp, %bb22 ], [ 0, %bb23.preheader ] ; <i32> [#uses=2] - %n.37 = phi i32 [ %n.4, %bb22 ], [ %n.3.ph, %bb23.preheader ] ; <i32> [#uses=3] - %scevgep = getelementptr i8* %zName, i32 %storemerge18 ; <i8*> [#uses=1] - %tmp = add i32 %storemerge18, 1 ; <i32> [#uses=2] - %scevgep15 = getelementptr i8* %zName, i32 %tmp ; <i8*> [#uses=1] - %39 = load i8* %scevgep, align 1 ; <i8> [#uses=2] - %40 = getelementptr inbounds i8* %32, i32 %n.37 ; <i8*> [#uses=1] - store i8 %39, i8* %40, align 1 - %41 = add nsw i32 %n.37, 1 ; <i32> [#uses=2] - %42 = icmp eq i8 %39, 39 ; <i1> [#uses=1] - br i1 %42, label %bb21, label %bb22 - -bb21: ; preds = %bb20 - %43 = getelementptr inbounds i8* %32, i32 %41 ; <i8*> [#uses=1] - store i8 39, i8* %43, align 1 - %44 = add nsw i32 %n.37, 2 ; <i32> [#uses=1] - br label %bb22 - -bb22: ; preds = %bb21, %bb20 - %n.4 = phi i32 [ %44, %bb21 ], [ %41, %bb20 ] ; <i32> [#uses=2] - %45 = load i8* %scevgep15, align 1 ; <i8> [#uses=1] - %46 = icmp eq i8 %45, 0 ; <i1> [#uses=1] - br i1 %46, label %bb24, label %bb20 - -bb24: ; preds = %bb22, %bb23.preheader - %n.3.lcssa = phi i32 [ %n.3.ph, %bb23.preheader ], [ %n.4, %bb22 ] ; <i32> [#uses=3] - br i1 %30, label %bb26, label %bb25 - -bb25: ; preds = %bb24 - %47 = getelementptr inbounds i8* %32, i32 %n.3.lcssa ; <i8*> [#uses=1] - store i8 39, i8* %47, align 1 - %48 = add nsw i32 %n.3.lcssa, 1 ; <i32> [#uses=1] - br label %bb26 - -bb26: ; preds = %bb25, %bb24 - %n.5 = phi i32 [ %48, %bb25 ], [ %n.3.lcssa, %bb24 ] ; <i32> [#uses=1] - %49 = getelementptr inbounds i8* %32, i32 %n.5 ; <i8*> [#uses=1] - store i8 0, i8* %49, align 1 - ret void - -return: ; preds = %bb1 - ret void -} - -declare i32 @"\01_fwrite$UNIX2003"(i8*, i32, i32, i8*) - -declare void @exit(i32) noreturn nounwind - -declare i32 @__maskrune(i32, i32) diff --git a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll index 848af82..2fceab6 100644 --- a/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll @@ -1,8 +1,10 @@ -; RUN: llc -march=x86-64 -O2 < %s | FileCheck %s -; RUN: llc -march=x86-64 -O2 -regalloc=basic < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-linux -O2 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-pc-linux -O2 -regalloc=basic < %s | FileCheck %s ; Test to check .debug_loc support. This test case emits many debug_loc entries. ; CHECK: Loc expr size +; CHECK-NEXT: .short +; CHECK-NEXT: .Ltmp ; CHECK-NEXT: DW_OP_reg %0 = type { double } diff --git a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll index ac26def..7909d27 100644 --- a/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll +++ b/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll @@ -1,7 +1,7 @@ ; RUN: llc -O2 < %s | FileCheck %s ; RUN: llc -O2 -regalloc=basic < %s | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-apple-darwin" +target triple = "x86_64-apple-darwin10" %struct.a = type { i32, %struct.a* } @@ -68,9 +68,15 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone ; CHECK: Ldebug_loc0: ; CHECK-NEXT: .quad Lfunc_begin0 ; CHECK-NEXT: .quad [[LABEL]] -; CHECK-NEXT: .short 1 +; CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}} ## Loc expr size +; CHECK-NEXT: .short Lset{{.*}} +; CHECK-NEXT: Ltmp{{.*}}: ; CHECK-NEXT: .byte 85 +; CHECK-NEXT: Ltmp{{.*}}: ; CHECK-NEXT: .quad [[LABEL]] ; CHECK-NEXT: .quad [[CLOBBER]] -; CHECK-NEXT: .short 1 +; CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}} ## Loc expr size +; CHECK-NEXT: .short Lset{{.*}} +; CHECK-NEXT: Ltmp{{.*}}: ; CHECK-NEXT: .byte 83 +; CHECK-NEXT: Ltmp{{.*}}:
\ No newline at end of file diff --git a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll index 6db3ce1..bb1db59 100644 --- a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll +++ b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll @@ -22,7 +22,7 @@ bb: ; it is. ; ; CHECK: # %bb -; CHECK: addq $64036, %rdi +; CHECK: leaq 64036(%rdx), %rdi ; CHECK: rep;stosl %tmp5 = bitcast i32* %tmp4 to i8* diff --git a/test/CodeGen/X86/2010-08-04-StackVariable.ll b/test/CodeGen/X86/2010-08-04-StackVariable.ll index edfd1b8..ba36fe7 100644 --- a/test/CodeGen/X86/2010-08-04-StackVariable.ll +++ b/test/CodeGen/X86/2010-08-04-StackVariable.ll @@ -1,5 +1,5 @@ -; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_fbreg -; Use DW_OP_fbreg in variable's location expression if the variable is in a stack slot. +; RUN: llc -O0 -mtriple=x86_64-apple-darwin < %s | grep DW_OP_breg7 +; Use DW_OP_breg7 in variable's location expression if the variable is in a stack slot. %struct.SVal = type { i8*, i32 } diff --git a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll index f12001c..eaede30 100644 --- a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll +++ b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll @@ -18,7 +18,7 @@ entry: ret i32 0 } -; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip), %rax +; CHECK: movq ___stack_chk_guard@GOTPCREL(%rip) ; CHECK: movb 38(%rsp), [[R0:%.+]] ; CHECK: movb 8(%rsp), [[R1:%.+]] ; CHECK: movb [[R1]], 8(%rsp) diff --git a/test/CodeGen/Generic/2011-02-12-shuffle.ll b/test/CodeGen/X86/2011-02-12-shuffle.ll index b4d56d1..b4d56d1 100644 --- a/test/CodeGen/Generic/2011-02-12-shuffle.ll +++ b/test/CodeGen/X86/2011-02-12-shuffle.ll diff --git a/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll new file mode 100644 index 0000000..07b1971 --- /dev/null +++ b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll @@ -0,0 +1,65 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=yonah | FileCheck %s +; Reduced from JavaScriptCore + +%"class.JSC::CodeLocationCall" = type { [8 x i8] } +%"class.JSC::JSGlobalData" = type { [4 x i8] } +%"class.JSC::FunctionPtr" = type { i8* } +%"class.JSC::Structure" = type { [4 x i8] } +%"class.JSC::UString" = type { i8* } +%"class.JSC::JSString" = type { [16 x i8], i32, %"class.JSC::UString", i32 } + +declare hidden fastcc void @_ZN3JSCL23returnToThrowTrampolineEPNS_12JSGlobalDataENS_16ReturnAddressPtrERS2_(%"class.JSC::JSGlobalData"* nocapture, i8*, %"class.JSC::FunctionPtr"* nocapture) nounwind noinline ssp + +; Avoid hoisting the test above loads or copies +; CHECK: %entry +; CHECK: cmpq +; CHECK-NOT: mov +; CHECK: jb +define i32 @cti_op_eq(i8** nocapture %args) nounwind ssp { +entry: + %0 = load i8** null, align 8 + %tmp13 = bitcast i8* %0 to %"class.JSC::CodeLocationCall"* + %tobool.i.i.i = icmp ugt i8* undef, inttoptr (i64 281474976710655 to i8*) + %or.cond.i = and i1 %tobool.i.i.i, undef + br i1 %or.cond.i, label %if.then.i, label %if.end.i + +if.then.i: ; preds = %entry + br i1 undef, label %if.then.i.i.i, label %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit + +if.then.i.i.i: ; preds = %if.then.i + %conv.i.i.i.i = trunc i64 undef to i32 + br label %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit + +if.end.i: ; preds = %entry + br i1 undef, label %land.rhs.i121.i, label %_ZNK3JSC7JSValue8isStringEv.exit122.i + +land.rhs.i121.i: ; preds = %if.end.i + %tmp.i.i117.i = load %"class.JSC::Structure"** undef, align 8 + br label %_ZNK3JSC7JSValue8isStringEv.exit122.i + +_ZNK3JSC7JSValue8isStringEv.exit122.i: ; preds = %land.rhs.i121.i, %if.end.i + %brmerge.i = or i1 undef, false + %or.cond = or i1 false, %brmerge.i + br i1 %or.cond, label %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit, label %if.then.i92.i + +if.then.i92.i: ; preds = %_ZNK3JSC7JSValue8isStringEv.exit122.i + tail call void @_ZNK3JSC8JSString11resolveRopeEPNS_9ExecStateE(%"class.JSC::JSString"* undef, %"class.JSC::CodeLocationCall"* %tmp13) nounwind + unreachable + +_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit: ; preds = %_ZNK3JSC7JSValue8isStringEv.exit122.i, %if.then.i.i.i, %if.then.i + + %1 = load i8** undef, align 8 + br i1 undef, label %do.end39, label %do.body27 + +do.body27: ; preds = %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit + %tmp30 = bitcast i8* %1 to %"class.JSC::JSGlobalData"* + %2 = getelementptr inbounds i8** %args, i64 -1 + %3 = bitcast i8** %2 to %"class.JSC::FunctionPtr"* + tail call fastcc void @_ZN3JSCL23returnToThrowTrampolineEPNS_12JSGlobalDataENS_16ReturnAddressPtrERS2_(%"class.JSC::JSGlobalData"* %tmp30, i8* undef, %"class.JSC::FunctionPtr"* %3) + unreachable + +do.end39: ; preds = %_ZN3JSC7JSValue19equalSlowCaseInlineEPNS_9ExecStateES0_S0_.exit + ret i32 undef +} + +declare void @_ZNK3JSC8JSString11resolveRopeEPNS_9ExecStateE(%"class.JSC::JSString"*, %"class.JSC::CodeLocationCall"*) diff --git a/test/CodeGen/X86/2011-05-09-loaduse.ll b/test/CodeGen/X86/2011-05-09-loaduse.ll new file mode 100644 index 0000000..8673d74 --- /dev/null +++ b/test/CodeGen/X86/2011-05-09-loaduse.ll @@ -0,0 +1,13 @@ +; RUN: llc < %s -march=x86 -mcpu=corei7 | FileCheck %s + +;CHECK: test +;CHECK-not: pshufd +;CHECK: ret +define float @test(<4 x float>* %A) nounwind { +entry: + %T = load <4 x float>* %A + %R = extractelement <4 x float> %T, i32 3 + store <4 x float><float 0.0, float 0.0, float 0.0, float 0.0>, <4 x float>* %A + ret float %R +} + diff --git a/test/CodeGen/X86/2011-05-26-UnreachableBlockElim.ll b/test/CodeGen/X86/2011-05-26-UnreachableBlockElim.ll new file mode 100644 index 0000000..0f18f09 --- /dev/null +++ b/test/CodeGen/X86/2011-05-26-UnreachableBlockElim.ll @@ -0,0 +1,53 @@ +; RUN: llc < %s -verify-coalescing +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.0" + +%struct.attrib = type { i32, i32 } +%struct.dfa = type { [80 x i8], i32, %struct.state*, i32, i32, %struct.attrib*, i32, i32 } +%struct.state = type { i32, [4 x i32] } + +@aux_temp = external global %struct.dfa, align 8 + +declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone + +declare void @__memset_chk() nounwind + +define void @dfa_add_string() nounwind uwtable ssp { +entry: + br label %if.end.i + +if.end.i: ; preds = %entry + %idxprom.i = add i64 0, 1 + br i1 undef, label %land.end.thread.i, label %land.end.i + +land.end.thread.i: ; preds = %if.end.i + %0 = call i64 @llvm.objectsize.i64(i8* undef, i1 false) nounwind + %cmp1710.i = icmp eq i64 %0, -1 + br i1 %cmp1710.i, label %cond.false156.i, label %cond.true138.i + +land.end.i: ; preds = %if.end.i + %1 = call i64 @llvm.objectsize.i64(i8* undef, i1 false) nounwind + %cmp17.i = icmp eq i64 %1, -1 + br i1 %cmp17.i, label %cond.false156.i, label %cond.true138.i + +cond.true138.i: ; preds = %for.end.i, %land.end.thread.i + call void @__memset_chk() nounwind + br label %cond.end166.i + +cond.false156.i: ; preds = %for.end.i, %land.end.thread.i + %idxprom1114.i = phi i64 [ undef, %land.end.thread.i ], [ %idxprom.i, %land.end.i ] + call void @__memset_chk() nounwind + br label %cond.end166.i + +cond.end166.i: ; preds = %cond.false156.i, %cond.true138.i + %idxprom1113.i = phi i64 [ %idxprom1114.i, %cond.false156.i ], [ undef, %cond.true138.i ] + %tmp235.i = load %struct.state** getelementptr inbounds (%struct.dfa* @aux_temp, i64 0, i32 2), align 8, !tbaa !0 + %att.i = getelementptr inbounds %struct.state* %tmp235.i, i64 %idxprom1113.i, i32 0 + store i32 0, i32* %att.i, align 4, !tbaa !3 + ret void +} + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} +!3 = metadata !{metadata !"int", metadata !1} diff --git a/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll b/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll new file mode 100644 index 0000000..c595bba --- /dev/null +++ b/test/CodeGen/X86/2011-05-27-CrossClassCoalescing.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -verify-coalescing +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.0" + +@bit_count = external constant [256 x i32], align 16 + +define fastcc void @unate_intersect() nounwind uwtable ssp { +entry: + br label %for.body + +for.body: ; preds = %entry, %for.inc.i + br label %do.body.i + +do.body.i: ; preds = %do.body.i, %for.body + %exitcond149 = icmp eq i64 undef, undef + br i1 %exitcond149, label %land.lhs.true, label %do.body.i + +land.lhs.true: ; preds = %do.body.i + br label %for.body.i + +for.body.i: ; preds = %for.inc.i, %if.then + %tmp3524.i = phi i32 [ 0, %land.lhs.true ], [ %tmp351.i, %for.inc.i ] + %tmp6.i12 = load i32* undef, align 4 + br i1 undef, label %for.inc.i, label %if.then.i17 + +if.then.i17: ; preds = %for.body.i + %shr.i14 = lshr i32 %tmp6.i12, 8 + %and14.i = and i32 %shr.i14, 255 + %idxprom15.i = zext i32 %and14.i to i64 + %arrayidx16.i = getelementptr inbounds [256 x i32]* @bit_count, i64 0, i64 %idxprom15.i + %tmp17.i15 = load i32* %arrayidx16.i, align 4 + %add.i = add i32 0, %tmp3524.i + %add24.i = add i32 %add.i, %tmp17.i15 + %add31.i = add i32 %add24.i, 0 + %add33.i = add i32 %add31.i, 0 + br label %for.inc.i + +for.inc.i: ; preds = %if.then.i17, %for.body.i + %tmp351.i = phi i32 [ %add33.i, %if.then.i17 ], [ %tmp3524.i, %for.body.i ] + br label %for.body.i +} diff --git a/test/CodeGen/X86/2011-05-31-movmsk.ll b/test/CodeGen/X86/2011-05-31-movmsk.ll new file mode 100644 index 0000000..2b54d5c --- /dev/null +++ b/test/CodeGen/X86/2011-05-31-movmsk.ll @@ -0,0 +1,79 @@ +; RUN: llc -mcpu=core2 < %s | FileCheck %s +; ModuleID = '<stdin>' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.6" + +%0 = type { double } +%union.anon = type { float } + +define i32 @double_signbit(double %d1) nounwind uwtable readnone ssp { +entry: + %__x.addr.i = alloca double, align 8 + %__u.i = alloca %0, align 8 + %0 = bitcast double* %__x.addr.i to i8* + %1 = bitcast %0* %__u.i to i8* + store double %d1, double* %__x.addr.i, align 8 + %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 + store double %d1, double* %__f.i, align 8 + %tmp = bitcast double %d1 to i64 +; CHECK-NOT: shr +; CHECK: movmskpd +; CHECK-NEXT: and + %tmp1 = lshr i64 %tmp, 63 + %shr.i = trunc i64 %tmp1 to i32 + ret i32 %shr.i +} + +define i32 @double_add_signbit(double %d1, double %d2) nounwind uwtable readnone ssp { +entry: + %__x.addr.i = alloca double, align 8 + %__u.i = alloca %0, align 8 + %add = fadd double %d1, %d2 + %0 = bitcast double* %__x.addr.i to i8* + %1 = bitcast %0* %__u.i to i8* + store double %add, double* %__x.addr.i, align 8 + %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 + store double %add, double* %__f.i, align 8 + %tmp = bitcast double %add to i64 +; CHECK-NOT: shr +; CHECK: movmskpd +; CHECK-NEXT: and + %tmp1 = lshr i64 %tmp, 63 + %shr.i = trunc i64 %tmp1 to i32 + ret i32 %shr.i +} + +define i32 @float_signbit(float %f1) nounwind uwtable readnone ssp { +entry: + %__x.addr.i = alloca float, align 4 + %__u.i = alloca %union.anon, align 4 + %0 = bitcast float* %__x.addr.i to i8* + %1 = bitcast %union.anon* %__u.i to i8* + store float %f1, float* %__x.addr.i, align 4 + %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 + store float %f1, float* %__f.i, align 4 + %2 = bitcast float %f1 to i32 +; CHECK-NOT: shr +; CHECK: movmskps +; CHECK-NEXT: and + %shr.i = lshr i32 %2, 31 + ret i32 %shr.i +} + +define i32 @float_add_signbit(float %f1, float %f2) nounwind uwtable readnone ssp { +entry: + %__x.addr.i = alloca float, align 4 + %__u.i = alloca %union.anon, align 4 + %add = fadd float %f1, %f2 + %0 = bitcast float* %__x.addr.i to i8* + %1 = bitcast %union.anon* %__u.i to i8* + store float %add, float* %__x.addr.i, align 4 + %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 + store float %add, float* %__f.i, align 4 + %2 = bitcast float %add to i32 +; CHECK-NOT: shr +; CHECK: movmskps +; CHECK-NEXT: and + %shr.i = lshr i32 %2, 31 + ret i32 %shr.i +} diff --git a/test/CodeGen/X86/2011-06-01-fildll.ll b/test/CodeGen/X86/2011-06-01-fildll.ll new file mode 100644 index 0000000..3a0b05f --- /dev/null +++ b/test/CodeGen/X86/2011-06-01-fildll.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86 | FileCheck %s +; ModuleID = '<stdin>' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-macosx10.6.6" + +define float @f(i64* nocapture %x) nounwind readonly ssp { +entry: +; CHECK: movl +; CHECK-NOT: movl + %tmp1 = load i64* %x, align 4 +; CHECK: fildll + %conv = sitofp i64 %tmp1 to float + %add = fadd float %conv, 1.000000e+00 + ret float %add +} diff --git a/test/CodeGen/X86/2011-06-03-x87chain.ll b/test/CodeGen/X86/2011-06-03-x87chain.ll new file mode 100644 index 0000000..bf7f583 --- /dev/null +++ b/test/CodeGen/X86/2011-06-03-x87chain.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -march=x86 -mattr=+sse | FileCheck %s + +define float @chainfail1(i64* nocapture %a, i64* nocapture %b, i32 %x, i32 %y, float* nocapture %f) nounwind uwtable noinline ssp { +entry: + %tmp1 = load i64* %a, align 8 +; Insure x87 ops are properly chained, order preserved. +; CHECK: fildll + %conv = sitofp i64 %tmp1 to float +; CHECK: fstps + store float %conv, float* %f, align 4 +; CHECK: idivl + %div = sdiv i32 %x, %y + %conv5 = sext i32 %div to i64 + store i64 %conv5, i64* %b, align 8 + ret float %conv +} + +define float @chainfail2(i64* nocapture %a, i64* nocapture %b, i32 %x, i32 %y, float* nocapture %f) nounwind uwtable noinline ssp { +entry: +; CHECK: movl $0, + store i64 0, i64* %b, align 8 + %mul = mul nsw i32 %y, %x + %sub = add nsw i32 %mul, -1 + %idxprom = sext i32 %sub to i64 + %arrayidx = getelementptr inbounds i64* %a, i64 %idxprom + %tmp4 = load i64* %arrayidx, align 8 +; CHECK: fildll + %conv = sitofp i64 %tmp4 to float + store float %conv, float* %f, align 4 + ret float %conv +} diff --git a/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll b/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll new file mode 100644 index 0000000..d934148 --- /dev/null +++ b/test/CodeGen/X86/2011-06-06-fgetsign80bit.ll @@ -0,0 +1,8 @@ +; RUN: llc -march=x86-64 < %s +define i32 @signbitl(x86_fp80 %x) nounwind uwtable readnone { +entry: + %tmp4 = bitcast x86_fp80 %x to i80 + %tmp4.lobit = lshr i80 %tmp4, 79 + %tmp = trunc i80 %tmp4.lobit to i32 + ret i32 %tmp +} diff --git a/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll b/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll new file mode 100644 index 0000000..a51dad0 --- /dev/null +++ b/test/CodeGen/X86/2011-06-12-FastAllocSpill.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -O0 -disable-fp-elim -relocation-model=pic -stats |& FileCheck %s +; +; This test should not cause any spilling with RAFast. +; +; CHECK: Number of copies coalesced +; CHECK-NOT: Number of stores added +; +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +%0 = type { i64, i64, i8*, i8* } +%1 = type opaque +%2 = type opaque +%3 = type <{ i8*, i32, i32, void (%4*)*, i8*, i64 }> +%4 = type { i8**, i32, i32, i8**, %5*, i64 } +%5 = type { i64, i64 } +%6 = type { i8*, i32, i32, i8*, %5* } + +@0 = external hidden constant %0 + +define hidden void @f() ssp { +bb: + %tmp5 = alloca i64, align 8 + %tmp6 = alloca void ()*, align 8 + %tmp7 = alloca %3, align 8 + store i64 0, i64* %tmp5, align 8 + br label %bb8 + +bb8: ; preds = %bb23, %bb + %tmp15 = getelementptr inbounds %3* %tmp7, i32 0, i32 4 + store i8* bitcast (%0* @0 to i8*), i8** %tmp15 + %tmp16 = bitcast %3* %tmp7 to void ()* + store void ()* %tmp16, void ()** %tmp6, align 8 + %tmp17 = load void ()** %tmp6, align 8 + %tmp18 = bitcast void ()* %tmp17 to %6* + %tmp19 = getelementptr inbounds %6* %tmp18, i32 0, i32 3 + %tmp20 = bitcast %6* %tmp18 to i8* + %tmp21 = load i8** %tmp19 + %tmp22 = bitcast i8* %tmp21 to void (i8*)* + call void %tmp22(i8* %tmp20) + br label %bb23 + +bb23: ; preds = %bb8 + %tmp24 = load i64* %tmp5, align 8 + %tmp25 = add i64 %tmp24, 1 + store i64 %tmp25, i64* %tmp5, align 8 + %tmp26 = icmp ult i64 %tmp25, 10 + br i1 %tmp26, label %bb8, label %bb27 + +bb27: ; preds = %bb23 + ret void +} diff --git a/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll b/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll new file mode 100644 index 0000000..0532375 --- /dev/null +++ b/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=x86-64 -stress-sched | FileCheck %s +; REQUIRES: Asserts +; Test interference between physreg aliases during preRAsched. +; mul wants an operand in AL, but call clobbers it. + +define i8 @f(i8 %v1, i8 %v2) nounwind { +entry: +; CHECK: callq +; CHECK: movb %{{.*}}, %al +; CHECK: mulb +; CHECK: mulb + %rval = tail call i8 @bar() nounwind + %m1 = mul i8 %v1, %v2 + %m2 = mul i8 %m1, %rval + ret i8 %m2 +} + +declare i8 @bar() diff --git a/test/CodeGen/X86/2011-06-14-mmx-inlineasm.ll b/test/CodeGen/X86/2011-06-14-mmx-inlineasm.ll new file mode 100644 index 0000000..445fc01 --- /dev/null +++ b/test/CodeGen/X86/2011-06-14-mmx-inlineasm.ll @@ -0,0 +1,45 @@ +; RUN: llc -mcpu=i686 -mattr=+mmx < %s | FileCheck %s +; ModuleID = 'tq.c' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-macosx10.6.6" + +%0 = type { x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx, x86_mmx } + +define i32 @pixman_fill_mmx(i32* nocapture %bits, i32 %stride, i32 %bpp, i32 %x, i32 %y, i32 %width, i32 %height, i32 %xor) nounwind ssp { +entry: + %conv = zext i32 %xor to i64 + %shl = shl nuw i64 %conv, 32 + %or = or i64 %shl, %conv + %0 = bitcast i64 %or to x86_mmx +; CHECK: movq [[MMXR:%mm[0-7],]] {{%mm[0-7]}} +; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}} +; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}} +; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}} +; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}} +; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}} +; CHECK-NEXT: movq [[MMXR]] {{%mm[0-7]}} + %1 = tail call %0 asm "movq\09\09$7,\09$0\0Amovq\09\09$7,\09$1\0Amovq\09\09$7,\09$2\0Amovq\09\09$7,\09$3\0Amovq\09\09$7,\09$4\0Amovq\09\09$7,\09$5\0Amovq\09\09$7,\09$6\0A", "=&y,=&y,=&y,=&y,=&y,=&y,=y,y,~{dirflag},~{fpsr},~{flags}"(x86_mmx %0) nounwind, !srcloc !0 + %asmresult = extractvalue %0 %1, 0 + %asmresult6 = extractvalue %0 %1, 1 + %asmresult7 = extractvalue %0 %1, 2 + %asmresult8 = extractvalue %0 %1, 3 + %asmresult9 = extractvalue %0 %1, 4 + %asmresult10 = extractvalue %0 %1, 5 + %asmresult11 = extractvalue %0 %1, 6 +; CHECK: movq {{%mm[0-7]}}, +; CHECK-NEXT: movq {{%mm[0-7]}}, +; CHECK-NEXT: movq {{%mm[0-7]}}, +; CHECK-NEXT: movq {{%mm[0-7]}}, +; CHECK-NEXT: movq {{%mm[0-7]}}, +; CHECK-NEXT: movq {{%mm[0-7]}}, +; CHECK-NEXT: movq {{%mm[0-7]}}, +; CHECK-NEXT: movq {{%mm[0-7]}}, + tail call void asm sideeffect "movq\09$1,\09 ($0)\0Amovq\09$2,\09 8($0)\0Amovq\09$3,\0916($0)\0Amovq\09$4,\0924($0)\0Amovq\09$5,\0932($0)\0Amovq\09$6,\0940($0)\0Amovq\09$7,\0948($0)\0Amovq\09$8,\0956($0)\0A", "r,y,y,y,y,y,y,y,y,~{memory},~{dirflag},~{fpsr},~{flags}"(i8* undef, x86_mmx %0, x86_mmx %asmresult, x86_mmx %asmresult6, x86_mmx %asmresult7, x86_mmx %asmresult8, x86_mmx %asmresult9, x86_mmx %asmresult10, x86_mmx %asmresult11) nounwind, !srcloc !1 + tail call void @llvm.x86.mmx.emms() nounwind + ret i32 1 +} + +declare void @llvm.x86.mmx.emms() nounwind + +!0 = metadata !{i32 888, i32 917, i32 945, i32 973, i32 1001, i32 1029, i32 1057} +!1 = metadata !{i32 1390, i32 1430, i32 1469, i32 1508, i32 1547, i32 1586, i32 1625, i32 1664} diff --git a/test/CodeGen/X86/2011-06-19-QuicksortCoalescerBug.ll b/test/CodeGen/X86/2011-06-19-QuicksortCoalescerBug.ll new file mode 100644 index 0000000..08178a3 --- /dev/null +++ b/test/CodeGen/X86/2011-06-19-QuicksortCoalescerBug.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -verify-coalescing +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.7.0" + +define void @Quicksort(i32* %a, i32 %l, i32 %r) nounwind ssp { +entry: + br label %tailrecurse + +tailrecurse: ; preds = %do.cond, %entry + %l.tr = phi i32 [ %l, %entry ], [ %i.1, %do.cond ] + %r.tr = phi i32 [ %r, %entry ], [ %l.tr, %do.cond ] + %idxprom12 = sext i32 %r.tr to i64 + %arrayidx14 = getelementptr inbounds i32* %a, i64 %idxprom12 + br label %do.body + +do.body: ; preds = %do.cond, %tailrecurse + %i.0 = phi i32 [ %l.tr, %tailrecurse ], [ %i.1, %do.cond ] + %add7 = add nsw i32 %i.0, 1 + %cmp = icmp sgt i32 %add7, %r.tr + br i1 %cmp, label %do.cond, label %if.then + +if.then: ; preds = %do.body + store i32 %add7, i32* %arrayidx14, align 4 + %add16 = add i32 %i.0, 2 + br label %do.cond + +do.cond: ; preds = %do.body, %if.then + %i.1 = phi i32 [ %add16, %if.then ], [ %add7, %do.body ] + %cmp19 = icmp sgt i32 %i.1, %r.tr + br i1 %cmp19, label %tailrecurse, label %do.body +} diff --git a/test/CodeGen/X86/3dnow-intrinsics.ll b/test/CodeGen/X86/3dnow-intrinsics.ll new file mode 100644 index 0000000..0b27bf2 --- /dev/null +++ b/test/CodeGen/X86/3dnow-intrinsics.ll @@ -0,0 +1,297 @@ +; RUN: llc < %s -march=x86 -mattr=+3dnow | FileCheck %s + +define <8 x i8> @test_pavgusb(x86_mmx %a.coerce, x86_mmx %b.coerce) nounwind readnone { +; CHECK: pavgusb +entry: + %0 = bitcast x86_mmx %a.coerce to <8 x i8> + %1 = bitcast x86_mmx %b.coerce to <8 x i8> + %2 = bitcast <8 x i8> %0 to x86_mmx + %3 = bitcast <8 x i8> %1 to x86_mmx + %4 = call x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx %2, x86_mmx %3) + %5 = bitcast x86_mmx %4 to <8 x i8> + ret <8 x i8> %5 +} + +declare x86_mmx @llvm.x86.3dnow.pavgusb(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pf2id(<2 x float> %a) nounwind readnone { +; CHECK: pf2id +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x i32> + ret <2 x i32> %2 +} + +declare x86_mmx @llvm.x86.3dnow.pf2id(x86_mmx) nounwind readnone + +define <2 x float> @test_pfacc(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfacc +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfacc(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfadd(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfadd +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfadd(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pfcmpeq(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfcmpeq +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x i32> + ret <2 x i32> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfcmpeq(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pfcmpge(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfcmpge +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x i32> + ret <2 x i32> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfcmpge(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pfcmpgt(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfcmpgt +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x i32> + ret <2 x i32> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfcmpgt(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfmax(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfmax +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfmax(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfmin(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfmin +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfmin(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfmul(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfmul +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfmul(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfrcp(<2 x float> %a) nounwind readnone { +; CHECK: pfrcp +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x float> + ret <2 x float> %2 +} + +declare x86_mmx @llvm.x86.3dnow.pfrcp(x86_mmx) nounwind readnone + +define <2 x float> @test_pfrcpit1(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfrcpit1 +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfrcpit1(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfrcpit1(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfrcpit2(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfrcpit2 +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfrcpit2(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfrcpit2(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfrsqrt(<2 x float> %a) nounwind readnone { +; CHECK: pfrsqrt +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnow.pfrsqrt(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x float> + ret <2 x float> %2 +} + +declare x86_mmx @llvm.x86.3dnow.pfrsqrt(x86_mmx) nounwind readnone + +define <2 x float> @test_pfrsqit1(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfrsqit1 +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfrsqit1(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfrsqit1(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfsub(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfsub +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfsub(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfsub(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfsubr(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfsubr +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnow.pfsubr(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pfsubr(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pi2fd(x86_mmx %a.coerce) nounwind readnone { +; CHECK: pi2fd +entry: + %0 = bitcast x86_mmx %a.coerce to <2 x i32> + %1 = bitcast <2 x i32> %0 to x86_mmx + %2 = call x86_mmx @llvm.x86.3dnow.pi2fd(x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnow.pi2fd(x86_mmx) nounwind readnone + +define <4 x i16> @test_pmulhrw(x86_mmx %a.coerce, x86_mmx %b.coerce) nounwind readnone { +; CHECK: pmulhrw +entry: + %0 = bitcast x86_mmx %a.coerce to <4 x i16> + %1 = bitcast x86_mmx %b.coerce to <4 x i16> + %2 = bitcast <4 x i16> %0 to x86_mmx + %3 = bitcast <4 x i16> %1 to x86_mmx + %4 = call x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx %2, x86_mmx %3) + %5 = bitcast x86_mmx %4 to <4 x i16> + ret <4 x i16> %5 +} + +declare x86_mmx @llvm.x86.3dnow.pmulhrw(x86_mmx, x86_mmx) nounwind readnone + +define <2 x i32> @test_pf2iw(<2 x float> %a) nounwind readnone { +; CHECK: pf2iw +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnowa.pf2iw(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x i32> + ret <2 x i32> %2 +} + +declare x86_mmx @llvm.x86.3dnowa.pf2iw(x86_mmx) nounwind readnone + +define <2 x float> @test_pfnacc(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfnacc +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnowa.pfnacc(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnowa.pfnacc(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pfpnacc(<2 x float> %a, <2 x float> %b) nounwind readnone { +; CHECK: pfpnacc +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = bitcast <2 x float> %b to x86_mmx + %2 = tail call x86_mmx @llvm.x86.3dnowa.pfpnacc(x86_mmx %0, x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnowa.pfpnacc(x86_mmx, x86_mmx) nounwind readnone + +define <2 x float> @test_pi2fw(x86_mmx %a.coerce) nounwind readnone { +; CHECK: pi2fw +entry: + %0 = bitcast x86_mmx %a.coerce to <2 x i32> + %1 = bitcast <2 x i32> %0 to x86_mmx + %2 = call x86_mmx @llvm.x86.3dnowa.pi2fw(x86_mmx %1) + %3 = bitcast x86_mmx %2 to <2 x float> + ret <2 x float> %3 +} + +declare x86_mmx @llvm.x86.3dnowa.pi2fw(x86_mmx) nounwind readnone + +define <2 x float> @test_pswapdsf(<2 x float> %a) nounwind readnone { +; CHECK: pswapd +entry: + %0 = bitcast <2 x float> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x float> + ret <2 x float> %2 +} + +define <2 x i32> @test_pswapdsi(<2 x i32> %a) nounwind readnone { +; CHECK: pswapd +entry: + %0 = bitcast <2 x i32> %a to x86_mmx + %1 = tail call x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx %0) + %2 = bitcast x86_mmx %1 to <2 x i32> + ret <2 x i32> %2 +} + +declare x86_mmx @llvm.x86.3dnowa.pswapd(x86_mmx) nounwind readnone diff --git a/test/CodeGen/X86/4char-promote.ll b/test/CodeGen/X86/4char-promote.ll new file mode 100644 index 0000000..386057f --- /dev/null +++ b/test/CodeGen/X86/4char-promote.ll @@ -0,0 +1,17 @@ +; A test for checking PR 9623 +;RUN: llc -march=x86-64 -mcpu=corei7 -promote-elements < %s | FileCheck %s + +target triple = "x86_64-apple-darwin" + +; CHECK: pmulld +; CHECK: paddd +; CHECK: movdqa + +define <4 x i8> @foo(<4 x i8> %x, <4 x i8> %y) { +entry: + %binop = mul <4 x i8> %x, %y + %binop6 = add <4 x i8> %binop, %x + ret <4 x i8> %binop6 +} + + diff --git a/test/CodeGen/X86/9601.ll b/test/CodeGen/X86/9601.ll new file mode 100644 index 0000000..cd65a03 --- /dev/null +++ b/test/CodeGen/X86/9601.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu +; PR9601 +; Previously we'd crash trying to put a 32-bit float into a constraint +; for a normal 'r' register. +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +define void @test() { +entry: + %0 = call float asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* undef, float 2.000000e+00) nounwind + unreachable +} diff --git a/test/CodeGen/X86/GC/simple_ocaml.ll b/test/CodeGen/X86/GC/simple_ocaml.ll deleted file mode 100644 index f765dc0..0000000 --- a/test/CodeGen/X86/GC/simple_ocaml.ll +++ /dev/null @@ -1,42 +0,0 @@ -; RUN: llc < %s | grep caml.*__frametable -; RUN: llc < %s -march=x86 | grep {movl .0} - -%struct.obj = type { i8*, %struct.obj* } - -define %struct.obj* @fun(%struct.obj* %head) gc "ocaml" { -entry: - %gcroot.0 = alloca i8* - %gcroot.1 = alloca i8* - - call void @llvm.gcroot(i8** %gcroot.0, i8* null) - call void @llvm.gcroot(i8** %gcroot.1, i8* null) - - %local.0 = bitcast i8** %gcroot.0 to %struct.obj** - %local.1 = bitcast i8** %gcroot.1 to %struct.obj** - - store %struct.obj* %head, %struct.obj** %local.0 - br label %bb.loop -bb.loop: - %t0 = load %struct.obj** %local.0 - %t1 = getelementptr %struct.obj* %t0, i32 0, i32 1 - %t2 = bitcast %struct.obj* %t0 to i8* - %t3 = bitcast %struct.obj** %t1 to i8** - %t4 = call i8* @llvm.gcread(i8* %t2, i8** %t3) - %t5 = bitcast i8* %t4 to %struct.obj* - %t6 = icmp eq %struct.obj* %t5, null - br i1 %t6, label %bb.loop, label %bb.end -bb.end: - %t7 = malloc %struct.obj - store %struct.obj* %t7, %struct.obj** %local.1 - %t8 = bitcast %struct.obj* %t7 to i8* - %t9 = load %struct.obj** %local.0 - %t10 = getelementptr %struct.obj* %t9, i32 0, i32 1 - %t11 = bitcast %struct.obj* %t9 to i8* - %t12 = bitcast %struct.obj** %t10 to i8** - call void @llvm.gcwrite(i8* %t8, i8* %t11, i8** %t12) - ret %struct.obj* %t7 -} - -declare void @llvm.gcroot(i8** %value, i8* %tag) -declare void @llvm.gcwrite(i8* %value, i8* %obj, i8** %field) -declare i8* @llvm.gcread(i8* %obj, i8** %field) diff --git a/test/CodeGen/X86/abi-isel.ll b/test/CodeGen/X86/abi-isel.ll index 7535e07..5068d29 100644 --- a/test/CodeGen/X86/abi-isel.ll +++ b/test/CodeGen/X86/abi-isel.ll @@ -12,17 +12,6 @@ ; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC ; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC - @src = external global [131072 x i32] @dst = external global [131072 x i32] @xsrc = external global [32 x i32] diff --git a/test/CodeGen/X86/add-of-carry.ll b/test/CodeGen/X86/add-of-carry.ll index f924ec8..a4abccb 100644 --- a/test/CodeGen/X86/add-of-carry.ll +++ b/test/CodeGen/X86/add-of-carry.ll @@ -4,9 +4,9 @@ define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp { entry: ; CHECK: test1: -; CHECK: sbbl %ecx, %ecx +; CHECK: cmpl %ecx, %eax ; CHECK-NOT: addl -; CHECK: subl %ecx, %eax +; CHECK: adcl $0, %eax %add4 = add i32 %x, %sum %cmp = icmp ult i32 %add4, %x %inc = zext i1 %cmp to i32 @@ -18,8 +18,7 @@ entry: ; CHECK: test2: ; CHECK: movl ; CHECK-NEXT: addl -; CHECK-NEXT: sbbl -; CHECK-NEXT: subl +; CHECK-NEXT: adcl $0 ; CHECK-NEXT: ret define i32 @test2(i32 %sum, i32 %x) nounwind readnone ssp { entry: diff --git a/test/CodeGen/X86/add.ll b/test/CodeGen/X86/add.ll index b95e5b5..7bf527a 100644 --- a/test/CodeGen/X86/add.ll +++ b/test/CodeGen/X86/add.ll @@ -1,6 +1,8 @@ ; RUN: llc < %s -march=x86 | FileCheck %s -check-prefix=X32 -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=X64 -; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-linux -join-physregs | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-win32 -join-physregs | FileCheck %s -check-prefix=X64 + +; Some of these tests depend on -join-physregs to commute instructions. ; The immediate can be encoded in a smaller way if the ; instruction is a sub instead of an add. diff --git a/test/CodeGen/X86/aliases.ll b/test/CodeGen/X86/aliases.ll index 3ed3bd6..f920279 100644 --- a/test/CodeGen/X86/aliases.ll +++ b/test/CodeGen/X86/aliases.ll @@ -1,6 +1,4 @@ ; RUN: llc < %s -mtriple=i686-pc-linux-gnu -asm-verbose=false -o %t -; RUN: grep { = } %t | count 16 -; RUN: grep set %t | count 18 ; RUN: grep globl %t | count 6 ; RUN: grep weak %t | count 1 ; RUN: grep hidden %t | count 1 diff --git a/test/CodeGen/X86/alignment.ll b/test/CodeGen/X86/alignment.ll index 9678e6d..7e91115 100644 --- a/test/CodeGen/X86/alignment.ll +++ b/test/CodeGen/X86/alignment.ll @@ -6,7 +6,7 @@ ; CHECK: .bss ; CHECK: .globl GlobalA -; CHECK: .align 16 +; CHECK: .align 8 ; CHECK: GlobalA: ; CHECK: .zero 384 @@ -15,12 +15,12 @@ ; PR6921 @GlobalB = common global { [384 x i8] } zeroinitializer, align 8 -; CHECK: .comm GlobalB,384,16 +; CHECK: .comm GlobalB,384,8 @GlobalC = common global { [384 x i8] } zeroinitializer, align 2 -; CHECK: .comm GlobalC,384,16 +; CHECK: .comm GlobalC,384,2 diff --git a/test/CodeGen/X86/andimm8.ll b/test/CodeGen/X86/andimm8.ll index 640237d..a3dc85f 100644 --- a/test/CodeGen/X86/andimm8.ll +++ b/test/CodeGen/X86/andimm8.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mtriple=x86_64-pc-linux-gnu -show-mc-encoding | FileCheck %s +; RUN: llc < %s -march=x86-64 -mtriple=x86_64-pc-linux-gnu -show-mc-encoding -join-physregs | FileCheck %s ; PR8365 ; CHECK: andl $-64, %edi # encoding: [0x83,0xe7,0xc0] diff --git a/test/CodeGen/X86/asm-label.ll b/test/CodeGen/X86/asm-label.ll new file mode 100644 index 0000000..1fc6e2e --- /dev/null +++ b/test/CodeGen/X86/asm-label.ll @@ -0,0 +1,40 @@ +; RUN: llc -mtriple=x86_64-apple-darwin10 -O0 < %s | FileCheck %s + +; test that we print a label that we use. We had a bug where +; we would print the jump, but not the label because it was considered +; a fall through. + +; CHECK: jmp LBB0_9 +; CHECK: LBB0_9: ## %cleanup + +define void @foo() { +entry: + br i1 undef, label %land.lhs.true, label %if.end11 + +land.lhs.true: ; preds = %entry + br i1 undef, label %if.then, label %if.end11 + +if.then: ; preds = %land.lhs.true + br i1 undef, label %if.then9, label %if.end + +if.then9: ; preds = %if.then + br label %cleanup + +if.end: ; preds = %if.then + br label %cleanup + +cleanup: ; preds = %if.end, %if.then9 + switch i32 undef, label %unreachable [ + i32 0, label %cleanup.cont + i32 1, label %if.end11 + ] + +cleanup.cont: ; preds = %cleanup + br label %if.end11 + +if.end11: ; preds = %cleanup.cont, %cleanup, %land.lhs.true, %entry + ret void + +unreachable: ; preds = %cleanup + unreachable +} diff --git a/test/CodeGen/X86/asm-label2.ll b/test/CodeGen/X86/asm-label2.ll new file mode 100644 index 0000000..0b5de34 --- /dev/null +++ b/test/CodeGen/X86/asm-label2.ll @@ -0,0 +1,22 @@ +; RUN: llc -mtriple=x86_64-apple-darwin10 -O0 < %s | FileCheck %s + +; test that we print a label that we use. We had a bug where +; we would print the jump, but not the label because it was considered +; a fall through. + +; CHECK: jmp LBB0_1 +; CHECK: LBB0_1: + +define void @foobar() { +entry: + invoke void @_zed() + to label %invoke.cont unwind label %lpad + +invoke.cont: ; preds = %entry + ret void + +lpad: ; preds = %entry + unreachable +} + +declare void @_zed() ssp align 2 diff --git a/test/CodeGen/X86/avx-128.ll b/test/CodeGen/X86/avx-128.ll index 2bd3b5d..c29cb5d 100644 --- a/test/CodeGen/X86/avx-128.ll +++ b/test/CodeGen/X86/avx-128.ll @@ -10,3 +10,13 @@ entry: ret void } +define void @fpext() nounwind uwtable { +entry: + %f = alloca float, align 4 + %d = alloca double, align 8 + %tmp = load float* %f, align 4 + ; CHECK: vcvtss2sd + %conv = fpext float %tmp to double + store double %conv, double* %d, align 8 + ret void +} diff --git a/test/CodeGen/X86/avx-intrinsics-x86.ll b/test/CodeGen/X86/avx-intrinsics-x86.ll index 6c32396..5201688 100644 --- a/test/CodeGen/X86/avx-intrinsics-x86.ll +++ b/test/CodeGen/X86/avx-intrinsics-x86.ll @@ -247,7 +247,7 @@ declare <2 x double> @llvm.x86.sse2.div.sd(<2 x double>, <2 x double>) nounwind define <16 x i8> @test_x86_sse2_loadu_dq(i8* %a0) { ; CHECK: movl - ; CHECK: vmovdqu + ; CHECK: vmovups %res = call <16 x i8> @llvm.x86.sse2.loadu.dq(i8* %a0) ; <<16 x i8>> [#uses=1] ret <16 x i8> %res } @@ -256,7 +256,7 @@ declare <16 x i8> @llvm.x86.sse2.loadu.dq(i8*) nounwind readonly define <2 x double> @test_x86_sse2_loadu_pd(i8* %a0) { ; CHECK: movl - ; CHECK: vmovupd + ; CHECK: vmovups %res = call <2 x double> @llvm.x86.sse2.loadu.pd(i8* %a0) ; <<2 x double>> [#uses=1] ret <2 x double> %res } diff --git a/test/CodeGen/X86/basic-promote-integers.ll b/test/CodeGen/X86/basic-promote-integers.ll new file mode 100644 index 0000000..c80f2b0 --- /dev/null +++ b/test/CodeGen/X86/basic-promote-integers.ll @@ -0,0 +1,98 @@ +; Test that vectors are scalarized/lowered correctly +; (with both legalization methods). +; RUN: llc -march=x86 -promote-elements < %s +; RUN: llc -march=x86 < %s + +; A simple test to check copyToParts and copyFromParts. + +define <4 x i64> @test_param_0(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + ret <4 x i64> %A +} + +define <2 x i32> @test_param_1(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + ret <2 x i32> %B +} + +define <4 x i8> @test_param_2(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + ret <4 x i8> %C +} + +; Simple tests to check arithmetic and vector operations on types which need to +; be legalized (no loads/stores to/from memory here). + +define <4 x i64> @test_arith_0(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %K = add <4 x i64> %A, <i64 0, i64 1, i64 3, i64 9> + ret <4 x i64> %K +} + +define <2 x i32> @test_arith_1(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %K = add <2 x i32> %B, <i32 0, i32 1> + ret <2 x i32> %K +} + +define <4 x i8> @test_arith_2(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %K = add <4 x i8> %C, <i8 0, i8 1, i8 3, i8 9> + ret <4 x i8> %K +} + +define i8 @test_arith_3(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %K = add <4 x i8> %C, <i8 0, i8 1, i8 3, i8 9> + %Y = extractelement <4 x i8> %K, i32 1 + ret i8 %Y +} + +define <4 x i8> @test_arith_4(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + %Y = insertelement <4 x i8> %C, i8 1, i32 0 + ret <4 x i8> %Y +} + +define <4 x i32> @test_arith_5(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %Y = insertelement <4 x i32> %C, i32 1, i32 0 + ret <4 x i32> %Y +} + +define <4 x i32> @test_arith_6(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = extractelement <2 x i32> %B, i32 1 + %Y = insertelement <4 x i32> %C, i32 %F, i32 0 + ret <4 x i32> %Y +} + +define <4 x i64> @test_arith_7(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = extractelement <2 x i32> %B, i32 1 + %W = zext i32 %F to i64 + %Y = insertelement <4 x i64> %A, i64 %W, i32 0 + ret <4 x i64> %Y +} + +define i64 @test_arith_8(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = extractelement <2 x i32> %B, i32 1 + %W = zext i32 %F to i64 + %T = add i64 %W , 11 + ret i64 %T +} + +define <4 x i64> @test_arith_9(<4 x i64> %A, <2 x i32> %B, <4 x i16> %C) { + %T = add <4 x i16> %C, %C + %F0 = extractelement <4 x i16> %T, i32 0 + %F1 = extractelement <4 x i16> %T, i32 1 + %W0 = zext i16 %F0 to i64 + %W1 = zext i16 %F1 to i64 + %Y0 = insertelement <4 x i64> %A, i64 %W0, i32 0 + %Y1 = insertelement <4 x i64> %Y0, i64 %W1, i32 2 + ret <4 x i64> %Y1 +} + +define <4 x i16> @test_arith_10(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = bitcast <2 x i32> %B to <4 x i16> + %T = add <4 x i16> %F , <i16 0, i16 1, i16 2, i16 3> + ret <4 x i16> %T +} + + +; Simple tests to check saving/loading from memory +define <4 x i16> @test_mem_0(<4 x i64> %A, <2 x i32> %B, <4 x i32> %C) { + %F = bitcast <2 x i32> %B to <4 x i16> + %T = add <4 x i16> %F , <i16 0, i16 1, i16 2, i16 3> + ret <4 x i16> %T +} + diff --git a/test/CodeGen/X86/bool-zext.ll b/test/CodeGen/X86/bool-zext.ll index d2c30c6..3558376 100644 --- a/test/CodeGen/X86/bool-zext.ll +++ b/test/CodeGen/X86/bool-zext.ll @@ -1,8 +1,12 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=WIN64 -; CHECK: @bar1 -; CHECK: movzbl -; CHECK: callq +; X64: @bar1 +; X64: movzbl +; X64: jmp +; WIN64: @bar1 +; WIN64: movzbl +; WIN64: callq define void @bar1(i1 zeroext %v1) nounwind ssp { entry: %conv = zext i1 %v1 to i32 @@ -10,9 +14,12 @@ entry: ret void } -; CHECK: @bar2 -; CHECK-NOT: movzbl -; CHECK: callq +; X64: @bar2 +; X64-NOT: movzbl +; X64: jmp +; WIN64: @bar2 +; WIN64-NOT: movzbl +; WIN64: callq define void @bar2(i8 zeroext %v1) nounwind ssp { entry: %conv = zext i8 %v1 to i32 @@ -20,11 +27,16 @@ entry: ret void } -; CHECK: @bar3 -; CHECK: callq -; CHECK-NOT: movzbl -; CHECK-NOT: and -; CHECK: ret +; X64: @bar3 +; X64: callq +; X64-NOT: movzbl +; X64-NOT: and +; X64: ret +; WIN64: @bar3 +; WIN64: callq +; WIN64-NOT: movzbl +; WIN64-NOT: and +; WIN64: ret define zeroext i1 @bar3() nounwind ssp { entry: %call = call i1 @foo2() nounwind diff --git a/test/CodeGen/X86/byval-align.ll b/test/CodeGen/X86/byval-align.ll new file mode 100644 index 0000000..c62a181 --- /dev/null +++ b/test/CodeGen/X86/byval-align.ll @@ -0,0 +1,59 @@ +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +%struct.S = type { i32} + +@.str = private constant [10 x i8] c"ptr = %p\0A\00", align 1 ; <[10 x i8]*> [#uses=1] +@.str1 = private constant [8 x i8] c"Failed \00", align 1 ; <[8 x i8]*> [#uses=1] +@.str2 = private constant [2 x i8] c"0\00", align 1 ; <[2 x i8]*> [#uses=1] +@.str3 = private constant [7 x i8] c"test.c\00", align 1 ; <[7 x i8]*> [#uses=1] +@__PRETTY_FUNCTION__.2067 = internal constant [13 x i8] c"aligned_func\00" ; <[13 x i8]*> [#uses=1] + +define void @aligned_func(%struct.S* byval align 64 %obj) nounwind { +entry: + %ptr = alloca i8* ; <i8**> [#uses=3] + %p = alloca i64 ; <i64*> [#uses=3] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %obj1 = bitcast %struct.S* %obj to i8* ; <i8*> [#uses=1] + store i8* %obj1, i8** %ptr, align 8 + %0 = load i8** %ptr, align 8 ; <i8*> [#uses=1] + %1 = ptrtoint i8* %0 to i64 ; <i64> [#uses=1] + store i64 %1, i64* %p, align 8 + %2 = load i8** %ptr, align 8 ; <i8*> [#uses=1] + %3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([10 x i8]* @.str, i64 0, i64 0), i8* %2) nounwind ; <i32> [#uses=0] + %4 = load i64* %p, align 8 ; <i64> [#uses=1] + %5 = and i64 %4, 140737488355264 ; <i64> [#uses=1] + %6 = load i64* %p, align 8 ; <i64> [#uses=1] + %7 = icmp ne i64 %5, %6 ; <i1> [#uses=1] + br i1 %7, label %bb, label %bb2 + +bb: ; preds = %entry + %8 = call i32 @puts(i8* getelementptr inbounds ([8 x i8]* @.str1, i64 0, i64 0)) nounwind ; <i32> [#uses=0] + call void @__assert_fail(i8* getelementptr inbounds ([2 x i8]* @.str2, i64 0, i64 0), i8* getelementptr inbounds ([7 x i8]* @.str3, i64 0, i64 0), i32 18, i8* getelementptr inbounds ([13 x i8]* @__PRETTY_FUNCTION__.2067, i64 0, i64 0)) noreturn nounwind + unreachable + +bb2: ; preds = %entry + br label %return + +return: ; preds = %bb2 + ret void +} + +declare i32 @printf(i8*, ...) nounwind + +declare i32 @puts(i8*) + +declare void @__assert_fail(i8*, i8*, i32, i8*) noreturn nounwind + +define void @main() nounwind { +entry: +; CHECK: main +; CHECK: andq $-64, %rsp + %s1 = alloca %struct.S ; <%struct.S*> [#uses=4] + %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] + %0 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; <i32*> [#uses=1] + store i32 1, i32* %0, align 4 + call void @aligned_func(%struct.S* byval align 64 %s1) nounwind + br label %return + +return: ; preds = %entry + ret void +} diff --git a/test/CodeGen/X86/byval2.ll b/test/CodeGen/X86/byval2.ll index 03a9f0f..196efe5 100644 --- a/test/CodeGen/X86/byval2.ll +++ b/test/CodeGen/X86/byval2.ll @@ -37,8 +37,8 @@ entry: store i64 %b, i64* %tmp2, align 16 %tmp4 = getelementptr %struct.s* %d, i32 0, i32 2 store i64 %c, i64* %tmp4, align 16 - call void @f( %struct.s* %d byval) - call void @f( %struct.s* %d byval) + call void @f( %struct.s*byval %d ) + call void @f( %struct.s*byval %d ) ret void } diff --git a/test/CodeGen/X86/byval3.ll b/test/CodeGen/X86/byval3.ll index 8d5bb6d..f3b125c 100644 --- a/test/CodeGen/X86/byval3.ll +++ b/test/CodeGen/X86/byval3.ll @@ -45,8 +45,8 @@ entry: store i32 %a5, i32* %tmp8, align 16 %tmp10 = getelementptr %struct.s* %d, i32 0, i32 5 store i32 %a6, i32* %tmp10, align 16 - call void @f( %struct.s* %d byval) - call void @f( %struct.s* %d byval) + call void @f( %struct.s* byval %d) + call void @f( %struct.s* byval %d) ret void } diff --git a/test/CodeGen/X86/byval4.ll b/test/CodeGen/X86/byval4.ll index ae1a79a..b7a4aa3 100644 --- a/test/CodeGen/X86/byval4.ll +++ b/test/CodeGen/X86/byval4.ll @@ -51,8 +51,8 @@ entry: store i16 %a5, i16* %tmp8, align 16 %tmp10 = getelementptr %struct.s* %a, i32 0, i32 5 store i16 %a6, i16* %tmp10, align 16 - call void @f( %struct.s* %a byval ) - call void @f( %struct.s* %a byval ) + call void @f( %struct.s* byval %a ) + call void @f( %struct.s* byval %a ) ret void } diff --git a/test/CodeGen/X86/byval5.ll b/test/CodeGen/X86/byval5.ll index a376709..dca0936 100644 --- a/test/CodeGen/X86/byval5.ll +++ b/test/CodeGen/X86/byval5.ll @@ -59,8 +59,8 @@ entry: store i8 %a5, i8* %tmp8, align 8 %tmp10 = getelementptr %struct.s* %a, i32 0, i32 5 store i8 %a6, i8* %tmp10, align 8 - call void @f( %struct.s* %a byval ) - call void @f( %struct.s* %a byval ) + call void @f( %struct.s* byval %a ) + call void @f( %struct.s* byval %a ) ret void } diff --git a/test/CodeGen/X86/byval7.ll b/test/CodeGen/X86/byval7.ll index 686ed9c..98a26e4 100644 --- a/test/CodeGen/X86/byval7.ll +++ b/test/CodeGen/X86/byval7.ll @@ -9,7 +9,6 @@ entry: ; CHECK: main: ; CHECK: movl $1, (%esp) ; CHECK: leal 16(%esp), %edi -; CHECK: movl $36, %ecx ; CHECK: leal 160(%esp), %esi ; CHECK: rep;movsl %s = alloca %struct.S ; <%struct.S*> [#uses=2] diff --git a/test/CodeGen/X86/call-push.ll b/test/CodeGen/X86/call-push.ll index 02cbccc..8cca10c 100644 --- a/test/CodeGen/X86/call-push.ll +++ b/test/CodeGen/X86/call-push.ll @@ -27,3 +27,19 @@ UnifiedReturnBlock: ; preds = %entry } declare i32 @f(%struct.decode_t*) + + +; There should be no store for the undef operand. + +; CHECK: _test2: +; CHECK-NOT: 8(%esp) +; CHECK: 4(%esp) +; CHECK-NOT: 8(%esp) +; CHECK: calll +declare i32 @foo(i32, i32, i32) + +define void @test2() nounwind { +entry: + %call = call i32 @foo(i32 8, i32 6, i32 undef) + ret void +} diff --git a/test/CodeGen/X86/clz.ll b/test/CodeGen/X86/clz.ll index 623ac75..d76fab4 100644 --- a/test/CodeGen/X86/clz.ll +++ b/test/CodeGen/X86/clz.ll @@ -31,3 +31,18 @@ entry: } declare i16 @llvm.ctlz.i16(i16) nounwind readnone + +; Don't generate the cmovne when the source is known non-zero (and bsr would +; not set ZF). +; rdar://9490949 + +define i32 @t4(i32 %n) nounwind { +entry: +; CHECK: t4: +; CHECK: bsrl +; CHECK-NOT: cmov +; CHECK: ret + %or = or i32 %n, 1 + %tmp1 = tail call i32 @llvm.ctlz.i32(i32 %or) + ret i32 %tmp1 +} diff --git a/test/CodeGen/X86/coalescer-commute2.ll b/test/CodeGen/X86/coalescer-commute2.ll index 7306920..6e5c1cf 100644 --- a/test/CodeGen/X86/coalescer-commute2.ll +++ b/test/CodeGen/X86/coalescer-commute2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -join-physregs | FileCheck %s ; CHECK-NOT: mov ; CHECK: paddw ; CHECK-NOT: mov diff --git a/test/CodeGen/X86/dbg-const-int.ll b/test/CodeGen/X86/dbg-const-int.ll new file mode 100644 index 0000000..bfc96f1 --- /dev/null +++ b/test/CodeGen/X86/dbg-const-int.ll @@ -0,0 +1,29 @@ +; RUN: llc < %s - | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.7" +; Radar 9511391 + +;CHECK: .byte 4 ## DW_AT_const_value +define i32 @foo() nounwind uwtable readnone optsize ssp { +entry: + tail call void @llvm.dbg.value(metadata !8, i64 0, metadata !6), !dbg !9 + ret i32 42, !dbg !10 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} +!llvm.dbg.sp = !{!1} +!llvm.dbg.lv.foo = !{!6} + +!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 132191)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, i32 ()* @foo, null, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 589865, metadata !"a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 590080, metadata !7, metadata !"i", metadata !2, i32 2, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!7 = metadata !{i32 589835, metadata !1, i32 1, i32 11, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!8 = metadata !{i32 42} +!9 = metadata !{i32 2, i32 12, metadata !7, null} +!10 = metadata !{i32 3, i32 2, metadata !7, null} diff --git a/test/CodeGen/X86/dbg-const.ll b/test/CodeGen/X86/dbg-const.ll new file mode 100644 index 0000000..5a51eb8 --- /dev/null +++ b/test/CodeGen/X86/dbg-const.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s - | FileCheck %s +target triple = "x86_64-apple-darwin10.0.0" + +;CHECK: ## DW_OP_constu +;CHECK-NEXT: .byte 42 +define i32 @foobar() nounwind readonly noinline ssp { +entry: + %call = tail call i32 @bar(), !dbg !11 + tail call void @llvm.dbg.value(metadata !8, i64 0, metadata !6), !dbg !9 + %call2 = tail call i32 @bar(), !dbg !11 + tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !6), !dbg !11 + %add = add nsw i32 %call2, %call, !dbg !12 + ret i32 %add, !dbg !10 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare i32 @bar() nounwind readnone + +!llvm.dbg.sp = !{!0} +!llvm.dbg.lv.foobar = !{!6} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar} +!1 = metadata !{i32 524329, metadata !"mu.c", metadata !"/private/tmp", metadata !2} +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"mu.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 114183)", i1 true, i1 true, metadata !"", i32 0} +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} +!6 = metadata !{i32 524544, metadata !7, metadata !"j", metadata !1, i32 15, metadata !5} +!7 = metadata !{i32 524299, metadata !0, i32 12, i32 52, metadata !1, i32 0} +!8 = metadata !{i32 42} +!9 = metadata !{i32 15, i32 12, metadata !7, null} +!10 = metadata !{i32 23, i32 3, metadata !7, null} +!11 = metadata !{i32 17, i32 3, metadata !7, null} +!12 = metadata !{i32 18, i32 3, metadata !7, null} diff --git a/test/CodeGen/X86/dbg-declare-arg.ll b/test/CodeGen/X86/dbg-declare-arg.ll new file mode 100644 index 0000000..367c1ef --- /dev/null +++ b/test/CodeGen/X86/dbg-declare-arg.ll @@ -0,0 +1,123 @@ +; RUN: llc -O0 -fast-isel=false < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.7" +;Radar 9321650 + +;CHECK: ##DEBUG_VALUE: my_a + +%class.A = type { i32, i32, i32, i32 } + +define void @_Z3fooi(%class.A* sret %agg.result, i32 %i) ssp { +entry: + %i.addr = alloca i32, align 4 + %j = alloca i32, align 4 + %nrvo = alloca i1 + %cleanup.dest.slot = alloca i32 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !26), !dbg !27 + call void @llvm.dbg.declare(metadata !{i32* %j}, metadata !28), !dbg !30 + store i32 0, i32* %j, align 4, !dbg !31 + %tmp = load i32* %i.addr, align 4, !dbg !32 + %cmp = icmp eq i32 %tmp, 42, !dbg !32 + br i1 %cmp, label %if.then, label %if.end, !dbg !32 + +if.then: ; preds = %entry + %tmp1 = load i32* %i.addr, align 4, !dbg !33 + %add = add nsw i32 %tmp1, 1, !dbg !33 + store i32 %add, i32* %j, align 4, !dbg !33 + br label %if.end, !dbg !35 + +if.end: ; preds = %if.then, %entry + store i1 false, i1* %nrvo, !dbg !36 + call void @llvm.dbg.declare(metadata !{%class.A* %agg.result}, metadata !37), !dbg !39 + %tmp2 = load i32* %j, align 4, !dbg !40 + %x = getelementptr inbounds %class.A* %agg.result, i32 0, i32 0, !dbg !40 + store i32 %tmp2, i32* %x, align 4, !dbg !40 + store i1 true, i1* %nrvo, !dbg !41 + store i32 1, i32* %cleanup.dest.slot + %nrvo.val = load i1* %nrvo, !dbg !42 + br i1 %nrvo.val, label %nrvo.skipdtor, label %nrvo.unused, !dbg !42 + +nrvo.unused: ; preds = %if.end + call void @_ZN1AD1Ev(%class.A* %agg.result), !dbg !42 + br label %nrvo.skipdtor, !dbg !42 + +nrvo.skipdtor: ; preds = %nrvo.unused, %if.end + ret void, !dbg !42 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define linkonce_odr void @_ZN1AD1Ev(%class.A* %this) unnamed_addr ssp align 2 { +entry: + %this.addr = alloca %class.A*, align 8 + store %class.A* %this, %class.A** %this.addr, align 8 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !43), !dbg !44 + %this1 = load %class.A** %this.addr + call void @_ZN1AD2Ev(%class.A* %this1) + ret void, !dbg !45 +} + +define linkonce_odr void @_ZN1AD2Ev(%class.A* %this) unnamed_addr nounwind ssp align 2 { +entry: + %this.addr = alloca %class.A*, align 8 + store %class.A* %this, %class.A** %this.addr, align 8 + call void @llvm.dbg.declare(metadata !{%class.A** %this.addr}, metadata !46), !dbg !47 + %this1 = load %class.A** %this.addr + %x = getelementptr inbounds %class.A* %this1, i32 0, i32 0, !dbg !48 + store i32 1, i32* %x, align 4, !dbg !48 + ret void, !dbg !48 +} + +!llvm.dbg.sp = !{!0, !10, !14, !19, !22, !25} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"~A", metadata !"~A", metadata !"", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589826, metadata !2, metadata !"A", metadata !3, i32 2, i64 128, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ] +!2 = metadata !{i32 589841, i32 0, i32 4, metadata !"a.cc", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 130127)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589865, metadata !"a.cc", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!4 = metadata !{metadata !5, metadata !7, metadata !8, metadata !9, metadata !0, metadata !10, metadata !14} +!5 = metadata !{i32 589837, metadata !3, metadata !"x", metadata !3, i32 2, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 589837, metadata !3, metadata !"y", metadata !3, i32 2, i64 32, i64 32, i64 32, i32 0, metadata !6} ; [ DW_TAG_member ] +!8 = metadata !{i32 589837, metadata !3, metadata !"z", metadata !3, i32 2, i64 32, i64 32, i64 64, i32 0, metadata !6} ; [ DW_TAG_member ] +!9 = metadata !{i32 589837, metadata !3, metadata !"o", metadata !3, i32 2, i64 32, i64 32, i64 96, i32 0, metadata !6} ; [ DW_TAG_member ] +!10 = metadata !{i32 589870, i32 0, metadata !1, metadata !"A", metadata !"A", metadata !"", metadata !3, i32 2, metadata !11, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] +!11 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !12, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!12 = metadata !{null, metadata !13} +!13 = metadata !{i32 589839, metadata !2, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !1} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 589870, i32 0, metadata !1, metadata !"A", metadata !"A", metadata !"", metadata !3, i32 2, metadata !15, i1 false, i1 false, i32 0, i32 0, null, i32 320, i1 false, null, null} ; [ DW_TAG_subprogram ] +!15 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!16 = metadata !{null, metadata !13, metadata !17} +!17 = metadata !{i32 589840, metadata !2, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !18} ; [ DW_TAG_reference_type ] +!18 = metadata !{i32 589862, metadata !2, metadata !"", null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_const_type ] +!19 = metadata !{i32 589870, i32 0, metadata !3, metadata !"foo", metadata !"foo", metadata !"_Z3fooi", metadata !3, i32 4, metadata !20, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*, i32)* @_Z3fooi, null, null} ; [ DW_TAG_subprogram ] +!20 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!21 = metadata !{metadata !1} +!22 = metadata !{i32 589870, i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD1Ev", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD1Ev, null, null} ; [ DW_TAG_subprogram ] +!23 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !24, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!24 = metadata !{null} +!25 = metadata !{i32 589870, i32 0, metadata !3, metadata !"~A", metadata !"~A", metadata !"_ZN1AD2Ev", metadata !3, i32 2, metadata !23, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (%class.A*)* @_ZN1AD2Ev, null, null} ; [ DW_TAG_subprogram ] +!26 = metadata !{i32 590081, metadata !19, metadata !"i", metadata !3, i32 16777220, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!27 = metadata !{i32 4, i32 11, metadata !19, null} +!28 = metadata !{i32 590080, metadata !29, metadata !"j", metadata !3, i32 5, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!29 = metadata !{i32 589835, metadata !19, i32 4, i32 14, metadata !3, i32 0} ; [ DW_TAG_lexical_block ] +!30 = metadata !{i32 5, i32 7, metadata !29, null} +!31 = metadata !{i32 5, i32 12, metadata !29, null} +!32 = metadata !{i32 6, i32 3, metadata !29, null} +!33 = metadata !{i32 7, i32 5, metadata !34, null} +!34 = metadata !{i32 589835, metadata !29, i32 6, i32 16, metadata !3, i32 1} ; [ DW_TAG_lexical_block ] +!35 = metadata !{i32 8, i32 3, metadata !34, null} +!36 = metadata !{i32 9, i32 9, metadata !29, null} +!37 = metadata !{i32 590080, metadata !29, metadata !"my_a", metadata !3, i32 9, metadata !38, i32 0} ; [ DW_TAG_auto_variable ] +!38 = metadata !{i32 589840, metadata !2, null, null, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !1} ; [ DW_TAG_reference_type ] +!39 = metadata !{i32 9, i32 5, metadata !29, null} +!40 = metadata !{i32 10, i32 3, metadata !29, null} +!41 = metadata !{i32 11, i32 3, metadata !29, null} +!42 = metadata !{i32 12, i32 1, metadata !29, null} +!43 = metadata !{i32 590081, metadata !22, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64} ; [ DW_TAG_arg_variable ] +!44 = metadata !{i32 2, i32 47, metadata !22, null} +!45 = metadata !{i32 2, i32 61, metadata !22, null} +!46 = metadata !{i32 590081, metadata !25, metadata !"this", metadata !3, i32 16777218, metadata !13, i32 64} ; [ DW_TAG_arg_variable ] +!47 = metadata !{i32 2, i32 47, metadata !25, null} +!48 = metadata !{i32 2, i32 54, metadata !49, null} +!49 = metadata !{i32 589835, metadata !25, i32 2, i32 52, metadata !3, i32 2} ; [ DW_TAG_lexical_block ] diff --git a/test/CodeGen/X86/dbg-file-name.ll b/test/CodeGen/X86/dbg-file-name.ll index e7d5f92..3a849aa 100644 --- a/test/CodeGen/X86/dbg-file-name.ll +++ b/test/CodeGen/X86/dbg-file-name.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple x86_64-apple-darwin10.0.0 < %s | FileCheck %s ; Radar 8884898 -; CHECK: file 1 "/Users/manav/one/two/simple.c" +; CHECK: file 1 "/Users/manav/one/two{{/|\\\\}}simple.c" declare i32 @printf(i8*, ...) nounwind diff --git a/test/CodeGen/X86/dbg-merge-loc-entry.ll b/test/CodeGen/X86/dbg-merge-loc-entry.ll index 76b93dd..afe1729 100644 --- a/test/CodeGen/X86/dbg-merge-loc-entry.ll +++ b/test/CodeGen/X86/dbg-merge-loc-entry.ll @@ -6,8 +6,11 @@ target triple = "x86_64-apple-darwin8" ;CHECK: Ldebug_loc0: ;CHECK-NEXT: .quad Lfunc_begin0 ;CHECK-NEXT: .quad L -;CHECK-NEXT: .short 1 ## Loc expr size +;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}} ## Loc expr size +;CHECK-NEXT: .short Lset +;CHECK-NEXT: Ltmp ;CHECK-NEXT: .byte 85 ## DW_OP_reg5 +;CHECK-NEXT: Ltmp7 ;CHECK-NEXT: .quad 0 ;CHECK-NEXT: .quad 0 diff --git a/test/CodeGen/X86/dbg-prolog-end.ll b/test/CodeGen/X86/dbg-prolog-end.ll new file mode 100644 index 0000000..81303bb --- /dev/null +++ b/test/CodeGen/X86/dbg-prolog-end.ll @@ -0,0 +1,55 @@ +; RUN: llc -O0 < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.7" + +;CHECK: .loc 1 2 11 prologue_end +define i32 @foo(i32 %i) nounwind ssp { +entry: + %i.addr = alloca i32, align 4 + %j = alloca i32, align 4 + store i32 %i, i32* %i.addr, align 4 + call void @llvm.dbg.declare(metadata !{i32* %i.addr}, metadata !7), !dbg !8 + call void @llvm.dbg.declare(metadata !{i32* %j}, metadata !9), !dbg !11 + store i32 2, i32* %j, align 4, !dbg !12 + %tmp = load i32* %j, align 4, !dbg !13 + %inc = add nsw i32 %tmp, 1, !dbg !13 + store i32 %inc, i32* %j, align 4, !dbg !13 + %tmp1 = load i32* %j, align 4, !dbg !14 + %tmp2 = load i32* %i.addr, align 4, !dbg !14 + %add = add nsw i32 %tmp1, %tmp2, !dbg !14 + store i32 %add, i32* %j, align 4, !dbg !14 + %tmp3 = load i32* %j, align 4, !dbg !15 + ret i32 %tmp3, !dbg !15 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define i32 @main() nounwind ssp { +entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval + %call = call i32 @foo(i32 21), !dbg !16 + ret i32 %call, !dbg !16 +} + +!llvm.dbg.cu = !{!0} +!llvm.dbg.sp = !{!1, !6} + +!0 = metadata !{i32 589841, i32 0, i32 12, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 131100)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"foo", metadata !"foo", metadata !"", metadata !2, i32 1, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i32 (i32)* @foo, null, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 589865, metadata !"/tmp/a.c", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589870, i32 0, metadata !2, metadata !"main", metadata !"main", metadata !"", metadata !2, i32 7, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, i32 ()* @main, null, null} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 590081, metadata !1, metadata !"i", metadata !2, i32 16777217, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!8 = metadata !{i32 1, i32 13, metadata !1, null} +!9 = metadata !{i32 590080, metadata !10, metadata !"j", metadata !2, i32 2, metadata !5, i32 0} ; [ DW_TAG_auto_variable ] +!10 = metadata !{i32 589835, metadata !1, i32 1, i32 16, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 2, i32 6, metadata !10, null} +!12 = metadata !{i32 2, i32 11, metadata !10, null} +!13 = metadata !{i32 3, i32 2, metadata !10, null} +!14 = metadata !{i32 4, i32 2, metadata !10, null} +!15 = metadata !{i32 5, i32 2, metadata !10, null} +!16 = metadata !{i32 8, i32 2, metadata !17, null} +!17 = metadata !{i32 589835, metadata !6, i32 7, i32 12, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] diff --git a/test/CodeGen/X86/dbg-value-dag-combine.ll b/test/CodeGen/X86/dbg-value-dag-combine.ll new file mode 100644 index 0000000..b115bf4 --- /dev/null +++ b/test/CodeGen/X86/dbg-value-dag-combine.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" +; PR 9817 + + +declare <4 x i32> @__amdil_get_global_id_int() +declare void @llvm.dbg.value(metadata , i64 , metadata ) +define void @__OpenCL_test_kernel(i32 addrspace(1)* %ip) nounwind { +entry: + call void @llvm.dbg.value(metadata !{i32 addrspace(1)* %ip}, i64 0, metadata +!7), !dbg !8 + %0 = call <4 x i32> @__amdil_get_global_id_int() nounwind + %1 = extractelement <4 x i32> %0, i32 0 + call void @llvm.dbg.value(metadata !{i32 %1}, i64 0, metadata !9), !dbg !11 + call void @llvm.dbg.value(metadata !12, i64 0, metadata !13), !dbg !14 + %tmp2 = load i32 addrspace(1)* %ip, align 4, !dbg !15 + %tmp3 = add i32 0, %tmp2, !dbg !15 +; CHECK: ##DEBUG_VALUE: idx <- EAX+0 + call void @llvm.dbg.value(metadata !{i32 %tmp3}, i64 0, metadata !13), !dbg +!15 + %arrayidx = getelementptr i32 addrspace(1)* %ip, i32 %1, !dbg !16 + store i32 %tmp3, i32 addrspace(1)* %arrayidx, align 4, !dbg !16 + ret void, !dbg !17 +} +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata +!"__OpenCL_test_kernel", metadata !"__OpenCL_test_kernel", metadata +!"__OpenCL_test_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"OCL6368.tmp.cl", metadata !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"OCL6368.tmp.cl", metadata !"E:\5CUsers\5Cmvillmow.AMD\5CAppData\5CLocal\5CTemp", metadata !"clc", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null, metadata !5} +!5 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] +!6 = metadata !{i32 589860, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 590081, metadata !0, metadata !"ip", metadata !1, i32 1, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!8 = metadata !{i32 1, i32 42, metadata !0, null} +!9 = metadata !{i32 590080, metadata !10, metadata !"gid", metadata !1, i32 3, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!10 = metadata !{i32 589835, metadata !0, i32 2, i32 1, metadata !1, i32 0} ; [ DW_TAG_lexical_block ] +!11 = metadata !{i32 3, i32 41, metadata !10, null} +!12 = metadata !{i32 0} +!13 = metadata !{i32 590080, metadata !10, metadata !"idx", metadata !1, i32 4, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!14 = metadata !{i32 4, i32 20, metadata !10, null} +!15 = metadata !{i32 5, i32 15, metadata !10, null} +!16 = metadata !{i32 6, i32 18, metadata !10, null} +!17 = metadata !{i32 7, i32 1, metadata !0, null} + diff --git a/test/CodeGen/X86/dbg-value-isel.ll b/test/CodeGen/X86/dbg-value-isel.ll new file mode 100644 index 0000000..d1a9e57 --- /dev/null +++ b/test/CodeGen/X86/dbg-value-isel.ll @@ -0,0 +1,102 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" +; PR 9879 + +; CHECK: ##DEBUG_VALUE: tid <- +%0 = type { i8*, i8*, i8*, i8*, i32 } + +@sgv = internal addrspace(2) constant [1 x i8] zeroinitializer +@fgv = internal addrspace(2) constant [1 x i8] zeroinitializer +@lvgv = internal constant [0 x i8*] zeroinitializer +@llvm.global.annotations = appending global [1 x %0] [%0 { i8* bitcast (void (i32 addrspace(1)*)* @__OpenCL_nbt02_kernel to i8*), i8* bitcast ([1 x i8] addrspace(2)* @sgv to i8*), i8* bitcast ([1 x i8] addrspace(2)* @fgv to i8*), i8* bitcast ([0 x i8*]* @lvgv to i8*), i32 0 }], section "llvm.metadata" + +define void @__OpenCL_nbt02_kernel(i32 addrspace(1)* %ip) nounwind { +entry: + call void @llvm.dbg.value(metadata !{i32 addrspace(1)* %ip}, i64 0, metadata !8), !dbg !9 + %0 = call <4 x i32> @__amdil_get_local_id_int() nounwind + %1 = extractelement <4 x i32> %0, i32 0 + br label %2 + +; <label>:2 ; preds = %entry + %3 = phi i32 [ %1, %entry ] + br label %4 + +; <label>:4 ; preds = %2 + %5 = phi i32 [ %3, %2 ] + br label %get_local_id.exit + +get_local_id.exit: ; preds = %4 + %6 = phi i32 [ %5, %4 ] + call void @llvm.dbg.value(metadata !{i32 %6}, i64 0, metadata !10), !dbg !12 + %7 = call <4 x i32> @__amdil_get_global_id_int() nounwind + %8 = extractelement <4 x i32> %7, i32 0 + br label %9 + +; <label>:9 ; preds = %get_local_id.exit + %10 = phi i32 [ %8, %get_local_id.exit ] + br label %11 + +; <label>:11 ; preds = %9 + %12 = phi i32 [ %10, %9 ] + br label %get_global_id.exit + +get_global_id.exit: ; preds = %11 + %13 = phi i32 [ %12, %11 ] + call void @llvm.dbg.value(metadata !{i32 %13}, i64 0, metadata !13), !dbg !14 + %14 = call <4 x i32> @__amdil_get_local_size_int() nounwind + %15 = extractelement <4 x i32> %14, i32 0 + br label %16 + +; <label>:16 ; preds = %get_global_id.exit + %17 = phi i32 [ %15, %get_global_id.exit ] + br label %18 + +; <label>:18 ; preds = %16 + %19 = phi i32 [ %17, %16 ] + br label %get_local_size.exit + +get_local_size.exit: ; preds = %18 + %20 = phi i32 [ %19, %18 ] + call void @llvm.dbg.value(metadata !{i32 %20}, i64 0, metadata !15), !dbg !16 + %tmp5 = add i32 %6, %13, !dbg !17 + %tmp7 = add i32 %tmp5, %20, !dbg !17 + store i32 %tmp7, i32 addrspace(1)* %ip, align 4, !dbg !17 + br label %return, !dbg !17 + +return: ; preds = %get_local_size.exit + ret void, !dbg !18 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare <4 x i32> @__amdil_get_local_size_int() nounwind + +declare <4 x i32> @__amdil_get_local_id_int() nounwind + +declare <4 x i32> @__amdil_get_global_id_int() nounwind + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.sp = !{!0} + +!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !"__OpenCL_nbt02_kernel", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 false, null} ; [ DW_TAG_subprogram ] +!1 = metadata !{i32 589865, metadata !"OCLlLwTXZ.cl", metadata !"/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 589841, i32 0, i32 1, metadata !"OCLlLwTXZ.cl", metadata !"/tmp", metadata !"clc", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{null, metadata !5} +!5 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !6} ; [ DW_TAG_pointer_type ] +!6 = metadata !{i32 589846, metadata !2, metadata !"uint", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, metadata !7} ; [ DW_TAG_typedef ] +!7 = metadata !{i32 589860, metadata !2, metadata !"unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ] +!8 = metadata !{i32 590081, metadata !0, metadata !"ip", metadata !1, i32 1, metadata !5, i32 0} ; [ DW_TAG_arg_variable ] +!9 = metadata !{i32 1, i32 32, metadata !0, null} +!10 = metadata !{i32 590080, metadata !11, metadata !"tid", metadata !1, i32 3, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!11 = metadata !{i32 589835, metadata !0, i32 2, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ] +!12 = metadata !{i32 5, i32 24, metadata !11, null} +!13 = metadata !{i32 590080, metadata !11, metadata !"gid", metadata !1, i32 3, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!14 = metadata !{i32 6, i32 25, metadata !11, null} +!15 = metadata !{i32 590080, metadata !11, metadata !"lsz", metadata !1, i32 3, metadata !6, i32 0} ; [ DW_TAG_auto_variable ] +!16 = metadata !{i32 7, i32 26, metadata !11, null} +!17 = metadata !{i32 9, i32 24, metadata !11, null} +!18 = metadata !{i32 10, i32 1, metadata !0, null} + diff --git a/test/CodeGen/X86/dbg-value-range.ll b/test/CodeGen/X86/dbg-value-range.ll index 67e3eee..28d873b 100644 --- a/test/CodeGen/X86/dbg-value-range.ll +++ b/test/CodeGen/X86/dbg-value-range.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s -; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin10 < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-apple-darwin10 -regalloc=basic -join-physregs < %s | FileCheck %s %struct.a = type { i32 } @@ -53,7 +53,10 @@ declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone ;CHECK:Ldebug_loc0: ;CHECK-NEXT: .quad ;CHECK-NEXT: .quad [[CLOBBER]] -;CHECK-NEXT: .short 1 +;CHECK-NEXT: Lset{{.*}} = Ltmp{{.*}}-Ltmp{{.*}} +;CHECK-NEXT: .short Lset +;CHECK-NEXT: Ltmp ;CHECK-NEXT: .byte 85 +;CHECK-NEXT: Ltmp ;CHECK-NEXT: .quad 0 ;CHECK-NEXT: .quad 0 diff --git a/test/CodeGen/X86/div8.ll b/test/CodeGen/X86/div8.ll new file mode 100644 index 0000000..0825f79 --- /dev/null +++ b/test/CodeGen/X86/div8.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s | FileCheck %s +; ModuleID = '8div.c' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.6" + +define signext i8 @test_div(i8 %dividend, i8 %divisor) nounwind ssp { +entry: + %dividend.addr = alloca i8, align 2 + %divisor.addr = alloca i8, align 1 + %quotient = alloca i8, align 1 + store i8 %dividend, i8* %dividend.addr, align 2 + store i8 %divisor, i8* %divisor.addr, align 1 + %tmp = load i8* %dividend.addr, align 2 + %tmp1 = load i8* %divisor.addr, align 1 +; Insist on i8->i32 zero extension, even though divb demands only i16: +; CHECK: movzbl {{.*}}%eax +; CHECK: divb + %div = udiv i8 %tmp, %tmp1 + store i8 %div, i8* %quotient, align 1 + %tmp4 = load i8* %quotient, align 1 + ret i8 %tmp4 +} diff --git a/test/CodeGen/X86/eh_frame.ll b/test/CodeGen/X86/eh_frame.ll new file mode 100644 index 0000000..3b792b2 --- /dev/null +++ b/test/CodeGen/X86/eh_frame.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu | FileCheck -check-prefix=STATIC %s +; RUN: llc < %s -mtriple x86_64-unknown-linux-gnu -relocation-model=pic | FileCheck -check-prefix=PIC %s + +@__FRAME_END__ = constant [1 x i32] zeroinitializer, section ".eh_frame" + +@foo = external global i32 +@bar1 = constant i8* bitcast (i32* @foo to i8*), section "my_bar1", align 8 + + +; STATIC: .section .eh_frame,"a",@progbits +; STATIC: .section my_bar1,"a",@progbits + +; PIC: .section .eh_frame,"a",@progbits +; PIC: .section my_bar1,"aw",@progbits diff --git a/test/CodeGen/X86/empty-functions.ll b/test/CodeGen/X86/empty-functions.ll index b303cd1..874c53a 100644 --- a/test/CodeGen/X86/empty-functions.ll +++ b/test/CodeGen/X86/empty-functions.ll @@ -6,10 +6,24 @@ entry: unreachable } ; CHECK-NO-FP: _func: -; CHECK-NO-FP-NOT: movq %rsp, %rbp +; CHECK-NO-FP-NEXT: : +; CHECK-NO-FP-NEXT: .cfi_startproc ; CHECK-NO-FP: nop +; CHECK-NO-FP-NEXT: : +; CHECK-NO-FP-NEXT: .cfi_endproc ; CHECK-FP: _func: -; CHECK-FP: movq %rsp, %rbp -; CHECK-FP-NEXT: Ltmp1: -; CHECK-FP: nop +; CHECK-FP-NEXT: : +; CHECK-FP-NEXT: .cfi_startproc +; CHECK-FP-NEXT: : +; CHECK-FP-NEXT: pushq %rbp +; CHECK-FP-NEXT: : +; CHECK-FP-NEXT: .cfi_def_cfa_offset 16 +; CHECK-FP-NEXT: : +; CHECK-FP-NEXT: .cfi_offset %rbp, -16 +; CHECK-FP-NEXT: movq %rsp, %rbp +; CHECK-FP-NEXT: : +; CHECK-FP-NEXT: .cfi_def_cfa_register %rbp +; CHECK-FP-NEXT: nop +; CHECK-FP-NEXT: : +; CHECK-FP-NEXT: .cfi_endproc diff --git a/test/CodeGen/X86/fast-isel-agg-constant.ll b/test/CodeGen/X86/fast-isel-agg-constant.ll new file mode 100644 index 0000000..ce0dff7 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-agg-constant.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=x86-64 -O0 | FileCheck %s +; Make sure fast-isel doesn't screw up aggregate constants. +; (Failing out is okay, as long as we don't miscompile.) + +%bar = type { i32 } + +define i32 @foo() { + %tmp = extractvalue %bar { i32 3 }, 0 + ret i32 %tmp +; CHECK: movl $3, %eax +} diff --git a/test/CodeGen/X86/fast-isel-call.ll b/test/CodeGen/X86/fast-isel-call.ll index 5fcdbbb..3159741 100644 --- a/test/CodeGen/X86/fast-isel-call.ll +++ b/test/CodeGen/X86/fast-isel-call.ll @@ -1,6 +1,8 @@ -; RUN: llc < %s -fast-isel -march=x86 | grep and +; RUN: llc < %s -O0 -fast-isel-abort -march=x86 | FileCheck %s -define i32 @t() nounwind { +%struct.s = type {i32, i32, i32} + +define i32 @test1() nounwind { tak: %tmp = call i1 @foo() br i1 %tmp, label %BB1, label %BB2 @@ -8,6 +10,46 @@ BB1: ret i32 1 BB2: ret i32 0 +; CHECK: test1: +; CHECK: calll +; CHECK-NEXT: testb $1 } +declare zeroext i1 @foo() nounwind + +declare void @foo2(%struct.s* byval) + +define void @test2(%struct.s* %d) nounwind { + call void @foo2(%struct.s* byval %d ) + ret void +; CHECK: test2: +; CHECK: movl (%eax) +; CHECK: movl {{.*}}, (%esp) +; CHECK: movl 4(%eax) +; CHECK: movl {{.*}}, 4(%esp) +; CHECK: movl 8(%eax) +; CHECK: movl {{.*}}, 8(%esp) +} + +declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind -declare i1 @foo() zeroext nounwind +define void @test3(i8* %a) { + call void @llvm.memset.p0i8.i32(i8* %a, i8 0, i32 100, i32 1, i1 false) + ret void +; CHECK: test3: +; CHECK: movl {{.*}}, (%esp) +; CHECK: movl $0, 4(%esp) +; CHECK: movl $100, 8(%esp) +; CHECK: calll {{.*}}memset +} + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind + +define void @test4(i8* %a, i8* %b) { + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 100, i32 1, i1 false) + ret void +; CHECK: test4: +; CHECK: movl {{.*}}, (%esp) +; CHECK: movl {{.*}}, 4(%esp) +; CHECK: movl $100, 8(%esp) +; CHECK: calll {{.*}}memcpy +} diff --git a/test/CodeGen/X86/fast-isel-extract.ll b/test/CodeGen/X86/fast-isel-extract.ll new file mode 100644 index 0000000..f63396e --- /dev/null +++ b/test/CodeGen/X86/fast-isel-extract.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 -fast-isel-abort | FileCheck %s + +%struct.x = type { i64, i64 } +%addovf = type { i32, i1 } +declare %struct.x @f() + +define void @test1(i64*) nounwind ssp { + %2 = tail call %struct.x @f() nounwind + %3 = extractvalue %struct.x %2, 0 + %4 = add i64 %3, 10 + store i64 %4, i64* %0 + ret void +; CHECK: test1: +; CHECK: callq _f +; CHECK-NEXT: addq $10, %rax +} + +define void @test2(i64*) nounwind ssp { + %2 = tail call %struct.x @f() nounwind + %3 = extractvalue %struct.x %2, 1 + %4 = add i64 %3, 10 + store i64 %4, i64* %0 + ret void +; CHECK: test2: +; CHECK: callq _f +; CHECK-NEXT: addq $10, %rdx +} + +declare %addovf @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone + +define void @test3(i32 %x, i32 %y, i32* %z) { + %r = call %addovf @llvm.sadd.with.overflow.i32(i32 %x, i32 %y) + %sum = extractvalue %addovf %r, 0 + %sum3 = mul i32 %sum, 3 + %bit = extractvalue %addovf %r, 1 + br i1 %bit, label %then, label %end + +then: + store i32 %sum3, i32* %z + br label %end + +end: + ret void +; CHECK: test3 +; CHECK: addl +; CHECK: seto %al +; CHECK: testb $1, %al +} diff --git a/test/CodeGen/X86/fast-isel-fneg.ll b/test/CodeGen/X86/fast-isel-fneg.ll index 5ffd48b..f42a4a2 100644 --- a/test/CodeGen/X86/fast-isel-fneg.ll +++ b/test/CodeGen/X86/fast-isel-fneg.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 | FileCheck %s +; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | grep xor | count 2 ; CHECK: doo: diff --git a/test/CodeGen/X86/fast-isel-gep.ll b/test/CodeGen/X86/fast-isel-gep.ll index 48abfd0..1a2e34e 100644 --- a/test/CodeGen/X86/fast-isel-gep.ll +++ b/test/CodeGen/X86/fast-isel-gep.ll @@ -24,7 +24,7 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind { %t15 = load i32* %t9 ; <i32> [#uses=1] ret i32 %t15 ; X32: test2: -; X32: movl (%edx,%ecx,4), %eax +; X32: movl (%edx,%ecx,4), %e ; X32: ret ; X64: test2: diff --git a/test/CodeGen/X86/fast-isel-i1.ll b/test/CodeGen/X86/fast-isel-i1.ll index d066578..bea18a1 100644 --- a/test/CodeGen/X86/fast-isel-i1.ll +++ b/test/CodeGen/X86/fast-isel-i1.ll @@ -1,19 +1,41 @@ -; RUN: llc < %s -march=x86 -fast-isel | grep {andb \$1, %} +; RUN: llc < %s -mtriple=i686-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -fast-isel -fast-isel-abort | FileCheck %s -declare i64 @bar(i64) +declare i32 @test1a(i32) -define i32 @foo(i64 %x) nounwind { - %y = add i64 %x, -3 ; <i64> [#uses=1] - %t = call i64 @bar(i64 %y) ; <i64> [#uses=1] - %s = mul i64 %t, 77 ; <i64> [#uses=1] - %z = trunc i64 %s to i1 ; <i1> [#uses=1] +define i32 @test1(i32 %x) nounwind { +; CHECK: test1: +; CHECK: andb $1, % + %y = add i32 %x, -3 + %t = call i32 @test1a(i32 %y) + %s = mul i32 %t, 77 + %z = trunc i32 %s to i1 br label %next next: ; preds = %0 - %u = zext i1 %z to i32 ; <i32> [#uses=1] - %v = add i32 %u, 1999 ; <i32> [#uses=1] + %u = zext i1 %z to i32 + %v = add i32 %u, 1999 br label %exit exit: ; preds = %next ret i32 %v } + +define void @test2(i8* %a) nounwind { +entry: +; CHECK: test2: +; CHECK: movb {{.*}} %al +; CHECK-NEXT: xorb $1, %al +; CHECK-NEXT: testb $1 + %tmp = load i8* %a, align 1 + %tobool = trunc i8 %tmp to i1 + %tobool2 = xor i1 %tobool, true + br i1 %tobool2, label %if.then, label %if.end + +if.then: + call void @test2(i8* null) + br label %if.end + +if.end: + ret void +} diff --git a/test/CodeGen/X86/fast-isel-ret-ext.ll b/test/CodeGen/X86/fast-isel-ret-ext.ll new file mode 100644 index 0000000..fd768cb --- /dev/null +++ b/test/CodeGen/X86/fast-isel-ret-ext.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -O0 -fast-isel-abort -mtriple i686-apple-darwin10 | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -mtriple x86_64-apple-darwin10 | FileCheck %s + +define zeroext i8 @test1(i32 %y) nounwind { + %conv = trunc i32 %y to i8 + ret i8 %conv + ; CHECK: test1: + ; CHECK: movzbl {{.*}}, %eax +} + +define signext i8 @test2(i32 %y) nounwind { + %conv = trunc i32 %y to i8 + ret i8 %conv + ; CHECK: test2: + ; CHECK: movsbl {{.*}}, %eax +} + +define zeroext i16 @test3(i32 %y) nounwind { + %conv = trunc i32 %y to i16 + ret i16 %conv + ; CHECK: test3: + ; CHECK: movzwl {{.*}}, %eax +} + +define signext i16 @test4(i32 %y) nounwind { + %conv = trunc i32 %y to i16 + ret i16 %conv + ; CHECK: test4: + ; CHECK: movswl {{.*}}, %eax +} + +define zeroext i1 @test5(i32 %y) nounwind { + %conv = trunc i32 %y to i1 + ret i1 %conv + ; CHECK: test5: + ; CHECK: andb $1 + ; CHECK: movzbl {{.*}}, %eax +} diff --git a/test/CodeGen/X86/fast-isel-shift-imm.ll b/test/CodeGen/X86/fast-isel-shift-imm.ll deleted file mode 100644 index 5c62c18..0000000 --- a/test/CodeGen/X86/fast-isel-shift-imm.ll +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: llc < %s -march=x86 -O0 | grep {sarl \$80, %e} -; PR3242 - -define void @foo(i32 %x, i32* %p) nounwind { - %y = ashr i32 %x, 50000 - store i32 %y, i32* %p - ret void -} diff --git a/test/CodeGen/X86/fast-isel-x86-64.ll b/test/CodeGen/X86/fast-isel-x86-64.ll new file mode 100644 index 0000000..c4afc10 --- /dev/null +++ b/test/CodeGen/X86/fast-isel-x86-64.ll @@ -0,0 +1,262 @@ +; RUN: llc < %s -fast-isel -O0 -regalloc=fast -asm-verbose=0 -fast-isel-abort | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +; Make sure that fast-isel folds the immediate into the binop even though it +; is non-canonical. +define i32 @test1(i32 %i) nounwind ssp { + %and = and i32 8, %i + ret i32 %and +} + +; CHECK: test1: +; CHECK: andl $8, + + +; rdar://9289512 - The load should fold into the compare. +define void @test2(i64 %x) nounwind ssp { +entry: + %x.addr = alloca i64, align 8 + store i64 %x, i64* %x.addr, align 8 + %tmp = load i64* %x.addr, align 8 + %cmp = icmp sgt i64 %tmp, 42 + br i1 %cmp, label %if.then, label %if.end + +if.then: ; preds = %entry + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +; CHECK: test2: +; CHECK: movq %rdi, -8(%rsp) +; CHECK: cmpq $42, -8(%rsp) +} + + + + +@G = external global i32 +define i64 @test3() nounwind { + %A = ptrtoint i32* @G to i64 + ret i64 %A +; CHECK: test3: +; CHECK: movq _G@GOTPCREL(%rip), %rax +; CHECK-NEXT: ret +} + + + +; rdar://9289558 +@rtx_length = external global [153 x i8] + +define i32 @test4(i64 %idxprom9) nounwind { + %arrayidx10 = getelementptr inbounds [153 x i8]* @rtx_length, i32 0, i64 %idxprom9 + %tmp11 = load i8* %arrayidx10, align 1 + %conv = zext i8 %tmp11 to i32 + ret i32 %conv + +; CHECK: test4: +; CHECK: movq _rtx_length@GOTPCREL(%rip), %rax +; CHECK-NEXT: movzbl (%rax,%rdi), %eax +; CHECK-NEXT: ret +} + + +; PR3242 - Out of range shifts should not be folded by fastisel. +define void @test5(i32 %x, i32* %p) nounwind { + %y = ashr i32 %x, 50000 + store i32 %y, i32* %p + ret void + +; CHECK: test5: +; CHECK: movl $50000, %ecx +; CHECK: sarl %cl, %edi +; CHECK: ret +} + +; rdar://9289501 - fast isel should fold trivial multiplies to shifts. +define i64 @test6(i64 %x) nounwind ssp { +entry: + %mul = mul nsw i64 %x, 8 + ret i64 %mul + +; CHECK: test6: +; CHECK: leaq (,%rdi,8), %rax +} + +define i32 @test7(i32 %x) nounwind ssp { +entry: + %mul = mul nsw i32 %x, 8 + ret i32 %mul +; CHECK: test7: +; CHECK: leal (,%rdi,8), %eax +} + + +; rdar://9289507 - folding of immediates into 64-bit operations. +define i64 @test8(i64 %x) nounwind ssp { +entry: + %add = add nsw i64 %x, 7 + ret i64 %add + +; CHECK: test8: +; CHECK: addq $7, %rdi +} + +define i64 @test9(i64 %x) nounwind ssp { +entry: + %add = mul nsw i64 %x, 7 + ret i64 %add +; CHECK: test9: +; CHECK: imulq $7, %rdi, %rax +} + +; rdar://9297011 - Don't reject udiv by a power of 2. +define i32 @test10(i32 %X) nounwind { + %Y = udiv i32 %X, 8 + ret i32 %Y +; CHECK: test10: +; CHECK: shrl $3, +} + +define i32 @test11(i32 %X) nounwind { + %Y = sdiv exact i32 %X, 8 + ret i32 %Y +; CHECK: test11: +; CHECK: sarl $3, +} + + +; rdar://9297006 - Trunc to bool. +define void @test12(i8 %tmp) nounwind ssp noredzone { +entry: + %tobool = trunc i8 %tmp to i1 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + call void @test12(i8 0) noredzone + br label %if.end + +if.end: ; preds = %if.then, %entry + ret void +; CHECK: test12: +; CHECK: testb $1, +; CHECK-NEXT: je L +; CHECK-NEXT: movl $0, %edi +; CHECK-NEXT: callq +} + +declare void @test13f(i1 %X) + +define void @test13() nounwind { + call void @test13f(i1 0) + ret void +; CHECK: test13: +; CHECK: movl $0, %edi +; CHECK-NEXT: callq +} + + + +; rdar://9297003 - fast isel bails out on all functions taking bools +define void @test14(i8 %tmp) nounwind ssp noredzone { +entry: + %tobool = trunc i8 %tmp to i1 + call void @test13f(i1 zeroext %tobool) noredzone + ret void +; CHECK: test14: +; CHECK: andb $1, +; CHECK: callq +} + +declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1) + +; rdar://9289488 - fast-isel shouldn't bail out on llvm.memcpy +define void @test15(i8* %a, i8* %b) nounwind { + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 4, i32 4, i1 false) + ret void +; CHECK: test15: +; CHECK-NEXT: movl (%rsi), %eax +; CHECK-NEXT: movl %eax, (%rdi) +; CHECK-NEXT: ret +} + +; Handling for varargs calls +declare void @test16callee(...) nounwind +define void @test16() nounwind { +; CHECK: test16: +; CHECK: movl $1, %edi +; CHECK: movb $0, %al +; CHECK: callq _test16callee + call void (...)* @test16callee(i32 1) + br label %block2 + +block2: +; CHECK: movabsq $1 +; CHECK: cvtsi2sdq {{.*}} %xmm0 +; CHECK: movb $1, %al +; CHECK: callq _test16callee + call void (...)* @test16callee(double 1.000000e+00) + ret void +} + + +declare void @foo() unnamed_addr ssp align 2 + +; Verify that we don't fold the load into the compare here. That would move it +; w.r.t. the call. +define i32 @test17(i32 *%P) ssp nounwind { +entry: + %tmp = load i32* %P + %cmp = icmp ne i32 %tmp, 5 + call void @foo() + br i1 %cmp, label %if.then, label %if.else + +if.then: ; preds = %entry + ret i32 1 + +if.else: ; preds = %entry + ret i32 2 +; CHECK: test17: +; CHECK: movl (%rdi), %eax +; CHECK: callq _foo +; CHECK: cmpl $5, %eax +; CHECK-NEXT: je +} + +; Check that 0.0 is materialized using pxor +define void @test18(float* %p1) { + store float 0.0, float* %p1 + ret void +; CHECK: test18: +; CHECK: pxor +} +define void @test19(double* %p1) { + store double 0.0, double* %p1 + ret void +; CHECK: test19: +; CHECK: pxor +} + +; Check that we fast-isel sret +%struct.a = type { i64, i64, i64 } +define void @test20() nounwind ssp { +entry: + %tmp = alloca %struct.a, align 8 + call void @test20sret(%struct.a* sret %tmp) + ret void +; CHECK: test20: +; CHECK: leaq (%rsp), %rdi +; CHECK: callq _test20sret +} +declare void @test20sret(%struct.a* sret) + +; Check that -0.0 is not materialized using pxor +define void @test21(double* %p1) { + store double -0.0, double* %p1 + ret void +; CHECK: test21: +; CHECK-NOT: pxor +; CHECK: movsd LCPI +}
\ No newline at end of file diff --git a/test/CodeGen/X86/fast-isel-x86.ll b/test/CodeGen/X86/fast-isel-x86.ll index 56aeb3a..19972f7 100644 --- a/test/CodeGen/X86/fast-isel-x86.ll +++ b/test/CodeGen/X86/fast-isel-x86.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86 -relocation-model=pic < %s +; RUN: llc -fast-isel -O0 -mtriple=i386-apple-darwin10 -relocation-model=pic < %s | FileCheck %s ; This should use flds to set the return value. ; CHECK: test0: @@ -31,3 +31,18 @@ define i32 @test2() nounwind { %t = load i32* @HHH ret i32 %t } + +; Check that we fast-isel sret, and handle the callee-pops behavior correctly. +%struct.a = type { i64, i64, i64 } +define void @test3() nounwind ssp { +entry: + %tmp = alloca %struct.a, align 8 + call void @test3sret(%struct.a* sret %tmp) + ret void +; CHECK: test3: +; CHECK: subl $44 +; CHECK: leal 16(%esp) +; CHECK: calll _test3sret +; CHECK: addl $40 +} +declare void @test3sret(%struct.a* sret) diff --git a/test/CodeGen/X86/fast-isel.ll b/test/CodeGen/X86/fast-isel.ll index 177c06b..8391860 100644 --- a/test/CodeGen/X86/fast-isel.ll +++ b/test/CodeGen/X86/fast-isel.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 -mattr=sse2 -; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 +; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 ; This tests very minimal fast-isel functionality. @@ -20,13 +20,14 @@ fast: %t6 = add i32 %t5, 2 %t7 = getelementptr i32* %y, i32 1 %t8 = getelementptr i32* %t7, i32 %t6 + call void asm sideeffect "hello world", ""() br label %exit exit: ret i32* %t8 } -define double @bar(double* %p, double* %q) nounwind { +define void @bar(double* %p, double* %q) nounwind { entry: %r = load double* %p %s = load double* %q @@ -40,7 +41,8 @@ fast: br label %exit exit: - ret double %t3 + store double %t3, double* %q + ret void } define i32 @cast() nounwind { @@ -67,24 +69,28 @@ define i8* @inttoptr_i32(i32 %p) nounwind { ret i8* %t } -define i8 @trunc_i32_i8(i32 %x) signext nounwind { +define void @trunc_i32_i8(i32 %x, i8* %p) nounwind { %tmp1 = trunc i32 %x to i8 - ret i8 %tmp1 + store i8 %tmp1, i8* %p + ret void } -define i8 @trunc_i16_i8(i16 signext %x) signext nounwind { +define void @trunc_i16_i8(i16 signext %x, i8* %p) nounwind { %tmp1 = trunc i16 %x to i8 - ret i8 %tmp1 + store i8 %tmp1, i8* %p + ret void } -define i8 @shl_i8(i8 %a, i8 %c) nounwind { - %tmp = shl i8 %a, %c - ret i8 %tmp +define void @shl_i8(i8 %a, i8 %c, i8* %p) nounwind { + %tmp = shl i8 %a, %c + store i8 %tmp, i8* %p + ret void } -define i8 @mul_i8(i8 %a) nounwind { - %tmp = mul i8 %a, 17 - ret i8 %tmp +define void @mul_i8(i8 %a, i8* %p) nounwind { + %tmp = mul i8 %a, 17 + store i8 %tmp, i8* %p + ret void } define void @load_store_i1(i1* %p, i1* %q) nounwind { @@ -92,3 +98,13 @@ define void @load_store_i1(i1* %p, i1* %q) nounwind { store i1 %t, i1* %q ret void } + + +@crash_test1x = external global <2 x i32>, align 8 + +define void @crash_test1() nounwind ssp { + %tmp = load <2 x i32>* @crash_test1x, align 8 + %neg = xor <2 x i32> %tmp, <i32 -1, i32 -1> + ret void +} + diff --git a/test/CodeGen/X86/fold-xmm-zero.ll b/test/CodeGen/X86/fold-xmm-zero.ll new file mode 100644 index 0000000..b4eeb40 --- /dev/null +++ b/test/CodeGen/X86/fold-xmm-zero.ll @@ -0,0 +1,34 @@ +; RUN: llc < %s -mtriple=i386-apple-macosx10.6.7 -mattr=+sse2 | FileCheck %s + +; Simple test to make sure folding for special constants (like float zero) +; isn't completely broken. + +; CHECK: divss LCPI0 + +%0 = type { float, float, float, float, float, float, float, float } + +define void @f() nounwind ssp { +entry: + %0 = tail call %0 asm sideeffect "foo", "={xmm0},={xmm1},={xmm2},={xmm3},={xmm4},={xmm5},={xmm6},={xmm7},0,1,2,3,4,5,6,7,~{dirflag},~{fpsr},~{flags}"(float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00, float 5.000000e+00, float 6.000000e+00, float 7.000000e+00, float 8.000000e+00) nounwind + %asmresult = extractvalue %0 %0, 0 + %asmresult8 = extractvalue %0 %0, 1 + %asmresult9 = extractvalue %0 %0, 2 + %asmresult10 = extractvalue %0 %0, 3 + %asmresult11 = extractvalue %0 %0, 4 + %asmresult12 = extractvalue %0 %0, 5 + %asmresult13 = extractvalue %0 %0, 6 + %asmresult14 = extractvalue %0 %0, 7 + %div = fdiv float %asmresult, 0.000000e+00 + %1 = tail call %0 asm sideeffect "bar", "={xmm0},={xmm1},={xmm2},={xmm3},={xmm4},={xmm5},={xmm6},={xmm7},0,1,2,3,4,5,6,7,~{dirflag},~{fpsr},~{flags}"(float %div, float %asmresult8, float %asmresult9, float %asmresult10, float %asmresult11, float %asmresult12, float %asmresult13, float %asmresult14) nounwind + %asmresult24 = extractvalue %0 %1, 0 + %asmresult25 = extractvalue %0 %1, 1 + %asmresult26 = extractvalue %0 %1, 2 + %asmresult27 = extractvalue %0 %1, 3 + %asmresult28 = extractvalue %0 %1, 4 + %asmresult29 = extractvalue %0 %1, 5 + %asmresult30 = extractvalue %0 %1, 6 + %asmresult31 = extractvalue %0 %1, 7 + %div33 = fdiv float %asmresult24, 0.000000e+00 + %2 = tail call %0 asm sideeffect "baz", "={xmm0},={xmm1},={xmm2},={xmm3},={xmm4},={xmm5},={xmm6},={xmm7},0,1,2,3,4,5,6,7,~{dirflag},~{fpsr},~{flags}"(float %div33, float %asmresult25, float %asmresult26, float %asmresult27, float %asmresult28, float %asmresult29, float %asmresult30, float %asmresult31) nounwind + ret void +} diff --git a/test/CodeGen/X86/fold-zext-trunc.ll b/test/CodeGen/X86/fold-zext-trunc.ll new file mode 100644 index 0000000..f901ad2 --- /dev/null +++ b/test/CodeGen/X86/fold-zext-trunc.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s | FileCheck %s +; PR9055 +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i686-pc-linux-gnu" + +%struct.S0 = type { i32, [2 x i8], [2 x i8], [4 x i8] } + +@g_98 = common global %struct.S0 zeroinitializer, align 4 + +define void @foo() nounwind { +; CHECK: movzbl +; CHECK-NOT: movzbl +; CHECK: calll +entry: + %tmp17 = load i8* getelementptr inbounds (%struct.S0* @g_98, i32 0, i32 1, i32 0), align 4 + %tmp54 = zext i8 %tmp17 to i32 + %foo = load i32* bitcast (i8* getelementptr inbounds (%struct.S0* @g_98, i32 0, i32 1, i32 0) to i32*), align 4 + %conv.i = trunc i32 %foo to i8 + tail call void @func_12(i32 %tmp54, i8 zeroext %conv.i) nounwind + ret void +} + +declare void @func_12(i32, i8 zeroext) diff --git a/test/CodeGen/X86/fp-stack-compare.ll b/test/CodeGen/X86/fp-stack-compare.ll index b216914..f3998b6 100644 --- a/test/CodeGen/X86/fp-stack-compare.ll +++ b/test/CodeGen/X86/fp-stack-compare.ll @@ -1,11 +1,11 @@ -; RUN: llc < %s -march=x86 -mcpu=i386 | grep {fucompi.*st.\[12\]} +; RUN: llc < %s -march=x86 -mcpu=i386 | FileCheck %s ; PR1012 define float @foo(float* %col.2.0) { - %tmp = load float* %col.2.0 ; <float> [#uses=3] - %tmp16 = fcmp olt float %tmp, 0.000000e+00 ; <i1> [#uses=1] - %tmp20 = fsub float -0.000000e+00, %tmp ; <float> [#uses=1] - %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp ; <float> [#uses=1] - ret float %iftmp.2.0 +; CHECK: fucompi + %tmp = load float* %col.2.0 + %tmp16 = fcmp olt float %tmp, 0.000000e+00 + %tmp20 = fsub float -0.000000e+00, %tmp + %iftmp.2.0 = select i1 %tmp16, float %tmp20, float %tmp + ret float %iftmp.2.0 } - diff --git a/test/CodeGen/X86/fp-trunc.ll b/test/CodeGen/X86/fp-trunc.ll index 4fe78ec..170637a 100644 --- a/test/CodeGen/X86/fp-trunc.ll +++ b/test/CodeGen/X86/fp-trunc.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2,-avx +; RUN: llc < %s -march=x86 -mattr=+sse2,-avx | FileCheck %s define <1 x float> @test1(<1 x double> %x) nounwind { ; CHECK: cvtsd2ss diff --git a/test/CodeGen/X86/hidden-vis-pic.ll b/test/CodeGen/X86/hidden-vis-pic.ll index ba130a2..67be3d0 100644 --- a/test/CodeGen/X86/hidden-vis-pic.ll +++ b/test/CodeGen/X86/hidden-vis-pic.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9 -relocation-model=pic -disable-fp-elim -unwind-tables | FileCheck %s +; RUN: llc < %s -disable-cfi -mtriple=i386-apple-darwin9 -relocation-model=pic -disable-fp-elim | FileCheck %s @@ -26,7 +26,7 @@ entry: @.str = private constant [12 x i8] c"hello world\00", align 1 ; <[12 x i8]*> [#uses=1] -define hidden void @func() nounwind ssp { +define hidden void @func() nounwind ssp uwtable { entry: %0 = call i32 @puts(i8* getelementptr inbounds ([12 x i8]* @.str, i64 0, i64 0)) nounwind ; <i32> [#uses=0] br label %return @@ -37,7 +37,7 @@ return: ; preds = %entry declare i32 @puts(i8*) -define hidden i32 @main() nounwind ssp { +define hidden i32 @main() nounwind ssp uwtable { entry: %retval = alloca i32 ; <i32*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] diff --git a/test/CodeGen/X86/hoist-common.ll b/test/CodeGen/X86/hoist-common.ll new file mode 100644 index 0000000..72e17c0 --- /dev/null +++ b/test/CodeGen/X86/hoist-common.ll @@ -0,0 +1,28 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s + +; Common "xorb al, al" instruction in the two successor blocks should be +; moved to the entry block above the test + je. + +; rdar://9145558 + +define zeroext i1 @t(i32 %c) nounwind ssp { +entry: +; CHECK: t: +; CHECK: xorb %al, %al +; CHECK: test +; CHECK: je + %tobool = icmp eq i32 %c, 0 + br i1 %tobool, label %return, label %if.then + +if.then: +; CHECK: callq + %call = tail call zeroext i1 (...)* @foo() nounwind + br label %return + +return: +; CHECK: ret + %retval.0 = phi i1 [ %call, %if.then ], [ false, %entry ] + ret i1 %retval.0 +} + +declare zeroext i1 @foo(...) diff --git a/test/CodeGen/X86/inline-asm-error.ll b/test/CodeGen/X86/inline-asm-error.ll new file mode 100644 index 0000000..29c5ae5 --- /dev/null +++ b/test/CodeGen/X86/inline-asm-error.ll @@ -0,0 +1,17 @@ +; RUN: not llc -march x86 -regalloc=fast < %s 2> %t1 +; RUN: not llc -march x86 -regalloc=basic < %s 2> %t2 +; RUN: not llc -march x86 -regalloc=greedy < %s 2> %t3 +; RUN: FileCheck %s < %t1 +; RUN: FileCheck %s < %t2 +; RUN: FileCheck %s < %t3 + +; The register allocator must fail on this function, and it should print the +; inline asm in the diagnostic. +; CHECK: LLVM ERROR: Ran out of registers during register allocation! +; CHECK: INLINEASM <es:hello world> + +define void @f(i32 %x0, i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5, i32 %x6, i32 %x7, i32 %x8, i32 %x9) nounwind ssp { +entry: + tail call void asm sideeffect "hello world", "r,r,r,r,r,r,r,r,r,r,~{dirflag},~{fpsr},~{flags}"(i32 %x0, i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5, i32 %x6, i32 %x7, i32 %x8, i32 %x9) nounwind + ret void +} diff --git a/test/CodeGen/X86/isint.ll b/test/CodeGen/X86/isint.ll index 507a328..4a98e63 100644 --- a/test/CodeGen/X86/isint.ll +++ b/test/CodeGen/X86/isint.ll @@ -1,17 +1,15 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 > %t -; RUN: not grep cmp %t -; RUN: not grep xor %t -; RUN: grep jne %t | count 1 -; RUN: grep jp %t | count 1 -; RUN: grep setnp %t | count 1 -; RUN: grep sete %t | count 1 -; RUN: grep and %t | count 1 -; RUN: grep cvt %t | count 4 +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define i32 @isint_return(double %d) nounwind { +; CHECK-NOT: xor +; CHECK: cvt %i = fptosi double %d to i32 +; CHECK-NEXT: cvt %e = sitofp i32 %i to double +; CHECK: cmpeqsd %c = fcmp oeq double %d, %e +; CHECK-NEXT: movd +; CHECK-NEXT: andl %z = zext i1 %c to i32 ret i32 %z } @@ -19,9 +17,14 @@ define i32 @isint_return(double %d) nounwind { declare void @foo() define void @isint_branch(double %d) nounwind { +; CHECK: cvt %i = fptosi double %d to i32 +; CHECK-NEXT: cvt %e = sitofp i32 %i to double +; CHECK: ucomisd %c = fcmp oeq double %d, %e +; CHECK-NEXT: jne +; CHECK-NEXT: jp br i1 %c, label %true, label %false true: call void @foo() diff --git a/test/CodeGen/X86/lea-3.ll b/test/CodeGen/X86/lea-3.ll index 040c5c2..c439ee1 100644 --- a/test/CodeGen/X86/lea-3.ll +++ b/test/CodeGen/X86/lea-3.ll @@ -14,7 +14,7 @@ define i32 @test(i32 %a) { ret i32 %tmp2 } -;; TODO! LEA instead of shift + copy. +; CHECK: leaq (,[[A0]],8), %rax define i64 @test3(i64 %a) { %tmp2 = shl i64 %a, 3 ret i64 %tmp2 diff --git a/test/CodeGen/X86/lock-inst-encoding.ll b/test/CodeGen/X86/lock-inst-encoding.ll index 03468e2..2d10fbc 100644 --- a/test/CodeGen/X86/lock-inst-encoding.ll +++ b/test/CodeGen/X86/lock-inst-encoding.ll @@ -4,10 +4,9 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin10.0.0" ; CHECK: f0: -; CHECK: addq %rax, (%rdi) -; CHECK: # encoding: [0xf0,0x48,0x01,0x07] +; CHECK: addq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0, ; CHECK: ret -define void @f0(i64* %a0) { +define void @f0(i64* %a0) nounwind { %t0 = and i64 1, 1 call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) nounwind %1 = call i64 @llvm.atomic.load.add.i64.p0i64(i64* %a0, i64 %t0) nounwind diff --git a/test/CodeGen/X86/lsr-interesting-step.ll b/test/CodeGen/X86/lsr-interesting-step.ll index 4b7050b..d1de051 100644 --- a/test/CodeGen/X86/lsr-interesting-step.ll +++ b/test/CodeGen/X86/lsr-interesting-step.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=x86-64 -relocation-model=static -mtriple=x86_64-unknown-linux-gnu +; RUN: llc < %s -march=x86-64 -relocation-model=static -mtriple=x86_64-unknown-linux-gnu -asm-verbose=0 | FileCheck %s ; The inner loop should require only one add (and no leas either). ; rdar://8100380 -; CHECK: BB0_4: +; CHECK: BB0_3: ; CHECK-NEXT: movb $0, flags(%rdx) ; CHECK-NEXT: addq %rcx, %rdx ; CHECK-NEXT: cmpq $8192, %rdx diff --git a/test/CodeGen/X86/lsr-loop-exit-cond.ll b/test/CodeGen/X86/lsr-loop-exit-cond.ll index d33cc3a..938023f 100644 --- a/test/CodeGen/X86/lsr-loop-exit-cond.ll +++ b/test/CodeGen/X86/lsr-loop-exit-cond.ll @@ -1,4 +1,3 @@ -; XFAIL: * ; RUN: llc -march=x86-64 < %s | FileCheck %s ; CHECK: decq diff --git a/test/CodeGen/X86/lsr-overflow.ll b/test/CodeGen/X86/lsr-overflow.ll index 5bc4f7e..09c1c07 100644 --- a/test/CodeGen/X86/lsr-overflow.ll +++ b/test/CodeGen/X86/lsr-overflow.ll @@ -25,3 +25,21 @@ __ABContainsLabel.exit: %cmp = icmp eq i64 %indvar, 9223372036854775807 ret i1 %cmp } + +define void @func_37() noreturn nounwind readonly { +entry: + br label %for.body + +for.body: ; preds = %for.inc8, %entry + %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.inc8 ] + %sub.i = add i64 undef, %indvar + %cmp.i = icmp eq i64 %sub.i, -9223372036854775808 + br i1 undef, label %for.inc8, label %for.cond4 + +for.cond4: ; preds = %for.cond4, %for.body + br label %for.cond4 + +for.inc8: ; preds = %for.body + %indvar.next = add i64 %indvar, 1 + br label %for.body +} diff --git a/test/CodeGen/X86/movntdq-no-avx.ll b/test/CodeGen/X86/movntdq-no-avx.ll new file mode 100644 index 0000000..8b7e6ef --- /dev/null +++ b/test/CodeGen/X86/movntdq-no-avx.ll @@ -0,0 +1,12 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s + +; Test that we produce a movntdq, not a vmovntdq +; CHECK-NOT: vmovntdq + +define void @test(<2 x i64>* nocapture %a, <2 x i64> %b) nounwind optsize { +entry: + store <2 x i64> %b, <2 x i64>* %a, align 16, !nontemporal !0 + ret void +} + +!0 = metadata !{i32 1} diff --git a/test/CodeGen/X86/narrow-shl-cst.ll b/test/CodeGen/X86/narrow-shl-cst.ll new file mode 100644 index 0000000..a404f34 --- /dev/null +++ b/test/CodeGen/X86/narrow-shl-cst.ll @@ -0,0 +1,101 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s +; PR5039 + +define i32 @test1(i32 %x) nounwind { + %and = shl i32 %x, 10 + %shl = and i32 %and, 31744 + ret i32 %shl +; CHECK: test1: +; CHECK: andl $31 +; CHECK: shll $10 +} + +define i32 @test2(i32 %x) nounwind { + %or = shl i32 %x, 10 + %shl = or i32 %or, 31744 + ret i32 %shl +; CHECK: test2: +; CHECK: orl $31 +; CHECK: shll $10 +} + +define i32 @test3(i32 %x) nounwind { + %xor = shl i32 %x, 10 + %shl = xor i32 %xor, 31744 + ret i32 %shl +; CHECK: test3: +; CHECK: xorl $31 +; CHECK: shll $10 +} + +define i64 @test4(i64 %x) nounwind { + %and = shl i64 %x, 40 + %shl = and i64 %and, 264982302294016 + ret i64 %shl +; CHECK: test4: +; CHECK: andq $241 +; CHECK: shlq $40 +} + +define i64 @test5(i64 %x) nounwind { + %and = shl i64 %x, 40 + %shl = and i64 %and, 34084860461056 + ret i64 %shl +; CHECK: test5: +; CHECK: andq $31 +; CHECK: shlq $40 +} + +define i64 @test6(i64 %x) nounwind { + %and = shl i64 %x, 32 + %shl = and i64 %and, -281474976710656 + ret i64 %shl +; CHECK: test6: +; CHECK: andq $-65536 +; CHECK: shlq $32 +} + +define i64 @test7(i64 %x) nounwind { + %or = shl i64 %x, 40 + %shl = or i64 %or, 264982302294016 + ret i64 %shl +; CHECK: test7: +; CHECK: orq $241 +; CHECK: shlq $40 +} + +define i64 @test8(i64 %x) nounwind { + %or = shl i64 %x, 40 + %shl = or i64 %or, 34084860461056 + ret i64 %shl +; CHECK: test8: +; CHECK: orq $31 +; CHECK: shlq $40 +} + +define i64 @test9(i64 %x) nounwind { + %xor = shl i64 %x, 40 + %shl = xor i64 %xor, 264982302294016 + ret i64 %shl +; CHECK: test9: +; CHECK: orq $241 +; CHECK: shlq $40 +} + +define i64 @test10(i64 %x) nounwind { + %xor = shl i64 %x, 40 + %shl = xor i64 %xor, 34084860461056 + ret i64 %shl +; CHECK: test10: +; CHECK: xorq $31 +; CHECK: shlq $40 +} + +define i64 @test11(i64 %x) nounwind { + %xor = shl i64 %x, 33 + %shl = xor i64 %xor, -562949953421312 + ret i64 %shl +; CHECK: test11: +; CHECK: xorq $-65536 +; CHECK: shlq $33 +} diff --git a/test/CodeGen/X86/no-cfi.ll b/test/CodeGen/X86/no-cfi.ll new file mode 100644 index 0000000..f9985d4 --- /dev/null +++ b/test/CodeGen/X86/no-cfi.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -disable-cfi | FileCheck --check-prefix=STATIC %s +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -disable-cfi -relocation-model=pic | FileCheck --check-prefix=PIC %s + +; STATIC: .ascii "zPLR" +; STATIC: .byte 3 +; STATIC-NEXT: .long __gxx_personality_v0 +; STATIC-NEXT: .byte 3 +; STATIC-NEXT: .byte 3 + +; PIC: .ascii "zPLR" +; PIC: .byte 155 +; PIC-NEXT: .L +; PIC-NEXT: .long DW.ref.__gxx_personality_v0-.L +; PIC-NEXT: .byte 27 +; PIC-NEXT: .byte 27 + + +define void @bar() { +entry: + %call = invoke i32 @foo() + to label %invoke.cont unwind label %lpad + +invoke.cont: + ret void + +lpad: + %exn = call i8* @llvm.eh.exception() nounwind + %eh.selector = call i32 (i8*, i8*, ...)* @llvm.eh.selector(i8* %exn, i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*), i8* null) nounwind + ret void +} + +declare i32 @foo() + +declare i8* @llvm.eh.exception() nounwind readonly + +declare i32 @__gxx_personality_v0(...) + +declare i32 @llvm.eh.selector(i8*, i8*, ...) nounwind diff --git a/test/CodeGen/X86/non-lazy-bind.ll b/test/CodeGen/X86/non-lazy-bind.ll new file mode 100644 index 0000000..f729658 --- /dev/null +++ b/test/CodeGen/X86/non-lazy-bind.ll @@ -0,0 +1,27 @@ +; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s + +declare void @lazy() nonlazybind +declare void @not() + +; CHECK: foo: +; CHECK: callq _not +; CHECK: callq *_lazy@GOTPCREL(%rip) +define void @foo() nounwind { + call void @not() + call void @lazy() + ret void +} + +; CHECK: tail_call_regular: +; CHECK: jmp _not +define void @tail_call_regular() nounwind { + tail call void @not() + ret void +} + +; CHECK: tail_call_eager: +; CHECK: jmpq *_lazy@GOTPCREL(%rip) +define void @tail_call_eager() nounwind { + tail call void @lazy() + ret void +} diff --git a/test/CodeGen/X86/nontemporal.ll b/test/CodeGen/X86/nontemporal.ll new file mode 100644 index 0000000..1d09535 --- /dev/null +++ b/test/CodeGen/X86/nontemporal.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s + +define void @f(<4 x float> %A, i8* %B, <2 x double> %C, i32 %D, <2 x i64> %E) { +; CHECK: movntps + %cast = bitcast i8* %B to <4 x float>* + store <4 x float> %A, <4 x float>* %cast, align 16, !nontemporal !0 +; CHECK: movntdq + %cast1 = bitcast i8* %B to <2 x i64>* + store <2 x i64> %E, <2 x i64>* %cast1, align 16, !nontemporal !0 +; CHECK: movntpd + %cast2 = bitcast i8* %B to <2 x double>* + store <2 x double> %C, <2 x double>* %cast2, align 16, !nontemporal !0 +; CHECK: movnti + %cast3 = bitcast i8* %B to i32* + store i32 %D, i32* %cast3, align 16, !nontemporal !0 + ret void +} + +!0 = metadata !{i32 1} diff --git a/test/CodeGen/X86/opt-ext-uses.ll b/test/CodeGen/X86/opt-ext-uses.ll index fa2aef5..72fb38b 100644 --- a/test/CodeGen/X86/opt-ext-uses.ll +++ b/test/CodeGen/X86/opt-ext-uses.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=x86 | grep movw | count 1 -define i16 @t() signext { +define signext i16 @t() { entry: %tmp180 = load i16* null, align 2 ; <i16> [#uses=3] %tmp180181 = sext i16 %tmp180 to i32 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/optimize-max-3.ll b/test/CodeGen/X86/optimize-max-3.ll index e35eb70..e42aa9d 100644 --- a/test/CodeGen/X86/optimize-max-3.ll +++ b/test/CodeGen/X86/optimize-max-3.ll @@ -41,14 +41,13 @@ for.end: ; preds = %for.body, %entry ; CHECK: jle ; CHECK-NOT: cmov -; CHECK: xorl {{%edi, %edi|%ecx, %ecx}} +; CHECK: xorl {{%edi, %edi|%ecx, %ecx|%eax, %eax}} ; CHECK-NEXT: align ; CHECK-NEXT: BB1_2: -; CHECK-NEXT: callq +; CHECK: callq ; CHECK-NEXT: incl [[BX:%[a-z0-9]+]] ; CHECK-NEXT: cmpl [[R14:%[a-z0-9]+]], [[BX]] -; CHECK-NEXT: movq %rax, %r{{di|cx}} -; CHECK-NEXT: jl +; CHECK: jl define void @_Z18GenerateStatusPagei(i32 %jobs_to_display) nounwind { entry: diff --git a/test/CodeGen/X86/peep-setb.ll b/test/CodeGen/X86/peep-setb.ll new file mode 100644 index 0000000..0bab789 --- /dev/null +++ b/test/CodeGen/X86/peep-setb.ll @@ -0,0 +1,82 @@ +; RUN: llc -march=x86-64 < %s | FileCheck %s + +define i8 @test1(i8 %a, i8 %b) nounwind { + %cmp = icmp ult i8 %a, %b + %cond = zext i1 %cmp to i8 + %add = add i8 %cond, %b + ret i8 %add +; CHECK: test1: +; CHECK: adcb $0 +} + +define i32 @test2(i32 %a, i32 %b) nounwind { + %cmp = icmp ult i32 %a, %b + %cond = zext i1 %cmp to i32 + %add = add i32 %cond, %b + ret i32 %add +; CHECK: test2: +; CHECK: adcl $0 +} + +define i64 @test3(i64 %a, i64 %b) nounwind { + %cmp = icmp ult i64 %a, %b + %conv = zext i1 %cmp to i64 + %add = add i64 %conv, %b + ret i64 %add +; CHECK: test3: +; CHECK: adcq $0 +} + +define i8 @test4(i8 %a, i8 %b) nounwind { + %cmp = icmp ult i8 %a, %b + %cond = zext i1 %cmp to i8 + %sub = sub i8 %b, %cond + ret i8 %sub +; CHECK: test4: +; CHECK: sbbb $0 +} + +define i32 @test5(i32 %a, i32 %b) nounwind { + %cmp = icmp ult i32 %a, %b + %cond = zext i1 %cmp to i32 + %sub = sub i32 %b, %cond + ret i32 %sub +; CHECK: test5: +; CHECK: sbbl $0 +} + +define i64 @test6(i64 %a, i64 %b) nounwind { + %cmp = icmp ult i64 %a, %b + %conv = zext i1 %cmp to i64 + %sub = sub i64 %b, %conv + ret i64 %sub +; CHECK: test6: +; CHECK: sbbq $0 +} + +define i8 @test7(i8 %a, i8 %b) nounwind { + %cmp = icmp ult i8 %a, %b + %cond = sext i1 %cmp to i8 + %sub = sub i8 %b, %cond + ret i8 %sub +; CHECK: test7: +; CHECK: adcb $0 +} + +define i32 @test8(i32 %a, i32 %b) nounwind { + %cmp = icmp ult i32 %a, %b + %cond = sext i1 %cmp to i32 + %sub = sub i32 %b, %cond + ret i32 %sub +; CHECK: test8: +; CHECK: adcl $0 +} + +define i64 @test9(i64 %a, i64 %b) nounwind { + %cmp = icmp ult i64 %a, %b + %conv = sext i1 %cmp to i64 + %sub = sub i64 %b, %conv + ret i64 %sub +; CHECK: test9: +; CHECK: adcq $0 +} diff --git a/test/CodeGen/X86/personality.ll b/test/CodeGen/X86/personality.ll index 705e489..e952a9b 100644 --- a/test/CodeGen/X86/personality.ll +++ b/test/CodeGen/X86/personality.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X64 -; RUN: llc < %s -mtriple=i386-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X32 +; RUN: llc < %s -disable-cfi -mtriple=x86_64-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -disable-cfi -mtriple=i386-apple-darwin9 -disable-cgp-branch-opts | FileCheck %s -check-prefix=X32 ; PR1632 define void @_Z1fv() { @@ -38,13 +38,15 @@ declare void @__gxx_personality_v0() declare void @__cxa_end_catch() -; X64: Leh_frame_common_begin0: -; X64: .long ___gxx_personality_v0@GOTPCREL+4 +; X64: zPLR +; X64: .byte 155 +; X64-NEXT: .long ___gxx_personality_v0@GOTPCREL+4 -; X32: Leh_frame_common_begin0: -; X32: .long L___gxx_personality_v0$non_lazy_ptr- -; .... +; X32: .section __IMPORT,__pointers,non_lazy_symbol_pointers +; X32-NEXT: L___gxx_personality_v0$non_lazy_ptr: +; X32-NEXT: .indirect_symbol ___gxx_personality_v0 -; X32: .section __IMPORT,__pointers,non_lazy_symbol_pointers -; X32: L___gxx_personality_v0$non_lazy_ptr: -; X32: .indirect_symbol ___gxx_personality_v0 +; X32: zPLR +; X32: .byte 155 +; X32-NEXT: : +; X32-NEXT: .long L___gxx_personality_v0$non_lazy_ptr- diff --git a/test/CodeGen/X86/phys_subreg_coalesce-2.ll b/test/CodeGen/X86/phys_subreg_coalesce-2.ll index 13e804d..02c519f 100644 --- a/test/CodeGen/X86/phys_subreg_coalesce-2.ll +++ b/test/CodeGen/X86/phys_subreg_coalesce-2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | grep mov | count 4 +; RUN: llc < %s -march=x86 | FileCheck %s ; PR2659 define i32 @binomial(i32 %n, i32 %k) nounwind { @@ -12,7 +12,8 @@ forcond.preheader: ; preds = %entry ifthen: ; preds = %entry ret i32 0 - +; CHECK: forbody +; CHECK-NOT: mov forbody: ; preds = %forbody, %forcond.preheader %indvar = phi i32 [ 0, %forcond.preheader ], [ %divisor.02, %forbody ] ; <i32> [#uses=3] %accumulator.01 = phi i32 [ 1, %forcond.preheader ], [ %div, %forbody ] ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/phys_subreg_coalesce-3.ll b/test/CodeGen/X86/phys_subreg_coalesce-3.ll index f23669e..4162015 100644 --- a/test/CodeGen/X86/phys_subreg_coalesce-3.ll +++ b/test/CodeGen/X86/phys_subreg_coalesce-3.ll @@ -1,6 +1,11 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=i386-apple-darwin -join-physregs | FileCheck %s ; rdar://5571034 +; This requires physreg joining, %vreg13 is live everywhere: +; 304L %CL<def> = COPY %vreg13:sub_8bit; GR32_ABCD:%vreg13 +; 320L %vreg15<def> = COPY %vreg19; GR32:%vreg15 GR32_NOSP:%vreg19 +; 336L %vreg15<def> = SAR32rCL %vreg15, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg15 + define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp { ; CHECK: foo: entry: diff --git a/test/CodeGen/X86/pic.ll b/test/CodeGen/X86/pic.ll index dc5fcd7..fb60ac2 100644 --- a/test/CodeGen/X86/pic.ll +++ b/test/CodeGen/X86/pic.ll @@ -79,8 +79,8 @@ entry: ; LINUX-NEXT: .L3$pb: ; LINUX: popl ; LINUX: addl $_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L3$pb), %[[REG3:e..]] -; LINUX: movl pfoo@GOT(%[[REG3]]), ; LINUX: calll afoo@PLT +; LINUX: movl pfoo@GOT(%[[REG3]]), ; LINUX: calll * } diff --git a/test/CodeGen/X86/pmul.ll b/test/CodeGen/X86/pmul.ll index bf5229a..d8ed4c0 100644 --- a/test/CodeGen/X86/pmul.ll +++ b/test/CodeGen/X86/pmul.ll @@ -1,7 +1,9 @@ -; RUN: llc < %s -march=x86 -mattr=sse41 -stack-alignment=16 > %t +; RUN: llc < %s -march=x86 -mattr=sse41 -stack-alignment=16 -join-physregs > %t ; RUN: grep pmul %t | count 12 ; RUN: grep mov %t | count 11 +; The f() arguments in %xmm0 and %xmm1 cause an extra movdqa without -join-physregs. + define <4 x i32> @a(<4 x i32> %i) nounwind { %A = mul <4 x i32> %i, < i32 117, i32 117, i32 117, i32 117 > ret <4 x i32> %A diff --git a/test/CodeGen/X86/pr10068.ll b/test/CodeGen/X86/pr10068.ll new file mode 100644 index 0000000..8829c5d --- /dev/null +++ b/test/CodeGen/X86/pr10068.ll @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=x86 + +define void @foobar() { +entry: + %sub.i = trunc i64 undef to i32 + %shr80.i = ashr i32 %sub.i, 16 + %add82.i = add nsw i32 %shr80.i, 1 + %notlhs.i = icmp slt i32 %shr80.i, undef + %notrhs.i = icmp sgt i32 %add82.i, -1 + %or.cond.not.i = and i1 %notrhs.i, %notlhs.i + %cmp154.i = icmp slt i32 0, undef + %or.cond406.i = and i1 %or.cond.not.i, %cmp154.i + %or.cond406.not.i = xor i1 %or.cond406.i, true + %or.cond407.i = or i1 undef, %or.cond406.not.i + br i1 %or.cond407.i, label %if.then158.i, label %if.end163.i + +if.then158.i: + ret void + +if.end163.i: ; preds = %if.end67.i + ret void +} diff --git a/test/CodeGen/X86/pr2659.ll b/test/CodeGen/X86/pr2659.ll index 54d043d..5dab5c9 100644 --- a/test/CodeGen/X86/pr2659.ll +++ b/test/CodeGen/X86/pr2659.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | grep movl | count 4 -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 | FileCheck %s +; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin9.4.0 -disable-branch-fold | FileCheck %s ; PR2659 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" @@ -18,7 +17,12 @@ forcond.preheader: ; preds = %entry ; CHECK: movl $1 ; CHECK-NOT: xorl ; CHECK-NOT: movl -; CHECK-NEXT: je +; CHECK-NOT: LBB +; CHECK: jne + +; There should be no moves required in the for loop body. +; CHECK: %forbody +; CHECK-NOT: mov ifthen: ; preds = %entry ret i32 0 diff --git a/test/CodeGen/X86/pr9127.ll b/test/CodeGen/X86/pr9127.ll index 9b251f5..ba92c77 100644 --- a/test/CodeGen/X86/pr9127.ll +++ b/test/CodeGen/X86/pr9127.ll @@ -10,4 +10,4 @@ entry: } ; test that the load is folded. -; CHECK: ucomisd (%{{rdi|rdx}}), %xmm0 +; CHECK: cmpeqsd (%{{rdi|rdx}}), %xmm0 diff --git a/test/CodeGen/X86/pr9743.ll b/test/CodeGen/X86/pr9743.ll new file mode 100644 index 0000000..6597c23 --- /dev/null +++ b/test/CodeGen/X86/pr9743.ll @@ -0,0 +1,17 @@ +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -disable-fp-elim -asm-verbose=0 | FileCheck %s + +define void @f() { + ret void +} + +; CHECK: .cfi_startproc +; CHECK-NEXT: pushq +; CHECK-NEXT: : +; CHECK-NEXT: .cfi_def_cfa_offset 16 +; CHECK-NEXT: : +; CHECK-NEXT: .cfi_offset %rbp, -16 +; CHECK-NEXT: movq %rsp, %rbp +; CHECK-NEXT: : +; CHECK-NEXT: .cfi_def_cfa_register %rbp +; CHECK-NEXT: popq %rbp +; CHECK-NEXT: ret diff --git a/test/CodeGen/X86/prefetch.ll b/test/CodeGen/X86/prefetch.ll index 48d2673..ebe11a5 100644 --- a/test/CodeGen/X86/prefetch.ll +++ b/test/CodeGen/X86/prefetch.ll @@ -6,11 +6,11 @@ entry: ; CHECK: prefetcht1 ; CHECK: prefetcht0 ; CHECK: prefetchnta - tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 ) - tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 ) - tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 ) - tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 ) + tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 ) ret void } -declare void @llvm.prefetch(i8*, i32, i32) nounwind +declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind diff --git a/test/CodeGen/X86/promote-i16.ll b/test/CodeGen/X86/promote-i16.ll index 101bb29..3c91d74 100644 --- a/test/CodeGen/X86/promote-i16.ll +++ b/test/CodeGen/X86/promote-i16.ll @@ -3,9 +3,19 @@ define signext i16 @foo(i16 signext %x) nounwind { entry: ; CHECK: foo: -; CHECK: movzwl 4(%esp), %eax +; CHECK-NOT: movzwl +; CHECK: movswl 4(%esp), %eax ; CHECK: xorl $21998, %eax -; CHECK: movswl %ax, %eax %0 = xor i16 %x, 21998 ret i16 %0 } + +define signext i16 @bar(i16 signext %x) nounwind { +entry: +; CHECK: bar: +; CHECK-NOT: movzwl +; CHECK: movswl 4(%esp), %eax +; CHECK: xorl $-10770, %eax + %0 = xor i16 %x, 54766 + ret i16 %0 +} diff --git a/test/CodeGen/X86/ret-mmx.ll b/test/CodeGen/X86/ret-mmx.ll index 04b57dd..865e147 100644 --- a/test/CodeGen/X86/ret-mmx.ll +++ b/test/CodeGen/X86/ret-mmx.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 +; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mattr=+mmx,+sse2 | FileCheck %s ; rdar://6602459 @g_v1di = external global <1 x i64> @@ -8,19 +8,32 @@ entry: %call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0] store <1 x i64> %call, <1 x i64>* @g_v1di ret void +; CHECK: t1: +; CHECK: callq +; CHECK-NEXT: movq _g_v1di +; CHECK-NEXT: movq %rax, } declare <1 x i64> @return_v1di() define <1 x i64> @t2() nounwind { ret <1 x i64> <i64 1> +; CHECK: t2: +; CHECK: movl $1 +; CHECK-NEXT: ret } define <2 x i32> @t3() nounwind { ret <2 x i32> <i32 1, i32 0> +; CHECK: t3: +; CHECK: movl $1 +; CHECK: movd {{.*}}, %xmm0 } define double @t4() nounwind { ret double bitcast (<2 x i32> <i32 1, i32 0> to double) +; CHECK: t4: +; CHECK: movl $1 +; CHECK: movd {{.*}}, %xmm0 } diff --git a/test/CodeGen/X86/setoeq.ll b/test/CodeGen/X86/setoeq.ll index 4a9c1ba..aa2f0af 100644 --- a/test/CodeGen/X86/setoeq.ll +++ b/test/CodeGen/X86/setoeq.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 | grep set | count 2 -; RUN: llc < %s -march=x86 | grep and +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define zeroext i8 @t(double %x) nounwind readnone { entry: @@ -7,5 +6,16 @@ entry: %1 = sitofp i32 %0 to double ; <double> [#uses=1] %2 = fcmp oeq double %1, %x ; <i1> [#uses=1] %retval12 = zext i1 %2 to i8 ; <i8> [#uses=1] +; CHECK: cmpeqsd + ret i8 %retval12 +} + +define zeroext i8 @u(double %x) nounwind readnone { +entry: + %0 = fptosi double %x to i32 ; <i32> [#uses=1] + %1 = sitofp i32 %0 to double ; <double> [#uses=1] + %2 = fcmp une double %1, %x ; <i1> [#uses=1] + %retval12 = zext i1 %2 to i8 ; <i8> [#uses=1] +; CHECK: cmpneqsd ret i8 %retval12 } diff --git a/test/CodeGen/X86/sext-trunc.ll b/test/CodeGen/X86/sext-trunc.ll index 2eaf425..22b3791 100644 --- a/test/CodeGen/X86/sext-trunc.ll +++ b/test/CodeGen/X86/sext-trunc.ll @@ -3,7 +3,7 @@ ; RUN: not grep movz %t ; RUN: not grep and %t -define i8 @foo(i16 signext %x) signext nounwind { +define signext i8 @foo(i16 signext %x) nounwind { %retval56 = trunc i16 %x to i8 ret i8 %retval56 } diff --git a/test/CodeGen/X86/shift-pair.ll b/test/CodeGen/X86/shift-pair.ll new file mode 100644 index 0000000..24ba1fc --- /dev/null +++ b/test/CodeGen/X86/shift-pair.ll @@ -0,0 +1,11 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +define i64 @test(i64 %A) { +; CHECK: @test +; CHECK: shrq $54 +; CHECK: andq $1020 +; CHECK: ret + %B = lshr i64 %A, 56 + %C = shl i64 %B, 2 + ret i64 %C +} diff --git a/test/CodeGen/X86/shl_undef.ll b/test/CodeGen/X86/shl_undef.ll new file mode 100644 index 0000000..54b74cc --- /dev/null +++ b/test/CodeGen/X86/shl_undef.ll @@ -0,0 +1,53 @@ +; RUN: llc < %s -O1 -mtriple=i386-apple-darwin | FileCheck %s +; +; Interesting test case where %tmp1220 = xor i32 %tmp862, %tmp592 and +; %tmp1676 = xor i32 %tmp1634, %tmp1530 have zero demanded bits after +; DAGCombiner optimization pass. These are changed to undef and in turn +; the successor shl(s) become shl undef, 1. This pattern then matches +; shl x, 1 -> add x, x. add undef, undef doesn't guarentee the low +; order bit is zero and is incorrect. +; +; See rdar://9453156 and rdar://9487392. +; + +; CHECK-NOT: shl +define i32 @foo(i8* %a0, i32* %a2) nounwind { +entry: + %tmp0 = alloca i8 + %tmp1 = alloca i32 + store i8 1, i8* %tmp0 + %tmp921.i7845 = load i8* %a0, align 1 + %tmp309 = xor i8 %tmp921.i7845, 104 + %tmp592 = zext i8 %tmp309 to i32 + %tmp862 = xor i32 1293461297, %tmp592 + %tmp1220 = xor i32 %tmp862, %tmp592 + %tmp1506 = shl i32 %tmp1220, 1 + %tmp1530 = sub i32 %tmp592, %tmp1506 + %tmp1557 = sub i32 %tmp1530, 542767629 + %tmp1607 = and i32 %tmp1557, 1 + store i32 %tmp1607, i32* %tmp1 + %tmp1634 = and i32 %tmp1607, 2080309246 + %tmp1676 = xor i32 %tmp1634, %tmp1530 + %tmp1618 = shl i32 %tmp1676, 1 + %tmp1645 = sub i32 %tmp862, %tmp1618 + %tmp1697 = and i32 %tmp1645, 1 + store i32 %tmp1697, i32* %a2 + ret i32 %tmp1607 +} + +; CHECK-NOT: shl +; shl undef, 0 -> undef +define i32 @foo2_undef() nounwind { +entry: + %tmp2 = shl i32 undef, 0; + ret i32 %tmp2 +} + +; CHECK-NOT: shl +; shl undef, x -> 0 +define i32 @foo1_undef(i32* %a0) nounwind { +entry: + %tmp1 = load i32* %a0, align 1 + %tmp2 = shl i32 undef, %tmp1; + ret i32 %tmp2 +} diff --git a/test/CodeGen/X86/shrink-compare.ll b/test/CodeGen/X86/shrink-compare.ll new file mode 100644 index 0000000..8d4b07f --- /dev/null +++ b/test/CodeGen/X86/shrink-compare.ll @@ -0,0 +1,36 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +declare void @bar() + +define void @test1(i32* nocapture %X) nounwind { +entry: + %tmp1 = load i32* %X, align 4 + %and = and i32 %tmp1, 255 + %cmp = icmp eq i32 %and, 47 + br i1 %cmp, label %if.then, label %if.end + +if.then: + tail call void @bar() nounwind + br label %if.end + +if.end: + ret void +; CHECK: test1: +; CHECK: cmpb $47, (%{{rdi|rcx}}) +} + +define void @test2(i32 %X) nounwind { +entry: + %and = and i32 %X, 255 + %cmp = icmp eq i32 %and, 47 + br i1 %cmp, label %if.then, label %if.end + +if.then: + tail call void @bar() nounwind + br label %if.end + +if.end: + ret void +; CHECK: test2: +; CHECK: cmpb $47, %{{dil|cl}} +} diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index de2a81e..4a98efb 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -198,7 +198,7 @@ declare i32 @foo6(i32, i32, %struct.t* byval align 4) ; rdar://r7717598 %struct.ns = type { i32, i32 } -%struct.cp = type { float, float } +%struct.cp = type { float, float, float, float, float } define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp { ; 32: t13: @@ -229,7 +229,7 @@ entry: ; 64: t14: ; 64: movq 32(%rdi) ; 64-NOT: movq 16(%rdi) -; 64: jmpq *16(%rdi) +; 64: jmpq *16({{%rdi|%rax}}) %0 = getelementptr inbounds %struct.__block_literal_2* %.block_descriptor, i64 0, i32 5 ; <void ()**> [#uses=1] %1 = load void ()** %0, align 8 ; <void ()*> [#uses=2] %2 = bitcast void ()* %1 to %struct.__block_literal_1* ; <%struct.__block_literal_1*> [#uses=1] diff --git a/test/CodeGen/X86/smul-with-overflow-2.ll b/test/CodeGen/X86/smul-with-overflow-2.ll deleted file mode 100644 index 7c23adb..0000000 --- a/test/CodeGen/X86/smul-with-overflow-2.ll +++ /dev/null @@ -1,20 +0,0 @@ -; RUN: llc < %s -march=x86 | grep mul | count 1 -; RUN: llc < %s -march=x86 | grep add | count 3 - -define i32 @t1(i32 %a, i32 %b) nounwind readnone { -entry: - %tmp0 = add i32 %b, %a - %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2) - %tmp2 = extractvalue { i32, i1 } %tmp1, 0 - ret i32 %tmp2 -} - -define i32 @t2(i32 %a, i32 %b) nounwind readnone { -entry: - %tmp0 = add i32 %b, %a - %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4) - %tmp2 = extractvalue { i32, i1 } %tmp1, 0 - ret i32 %tmp2 -} - -declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32) nounwind diff --git a/test/CodeGen/X86/smul-with-overflow-3.ll b/test/CodeGen/X86/smul-with-overflow-3.ll deleted file mode 100644 index 49c31f5..0000000 --- a/test/CodeGen/X86/smul-with-overflow-3.ll +++ /dev/null @@ -1,23 +0,0 @@ -; RUN: llc < %s -march=x86 | grep {jno} | count 1 - -@ok = internal constant [4 x i8] c"%d\0A\00" -@no = internal constant [4 x i8] c"no\0A\00" - -define i1 @func1(i32 %v1, i32 %v2) nounwind { -entry: - %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2) - %sum = extractvalue {i32, i1} %t, 0 - %obit = extractvalue {i32, i1} %t, 1 - br i1 %obit, label %overflow, label %normal - -overflow: - %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind - ret i1 false - -normal: - %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind - ret i1 true -} - -declare i32 @printf(i8*, ...) nounwind -declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) diff --git a/test/CodeGen/X86/smul-with-overflow.ll b/test/CodeGen/X86/smul-with-overflow.ll index 6d125e4..7c2e247 100644 --- a/test/CodeGen/X86/smul-with-overflow.ll +++ b/test/CodeGen/X86/smul-with-overflow.ll @@ -1,9 +1,9 @@ -; RUN: llc < %s -march=x86 | grep {jo} | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s @ok = internal constant [4 x i8] c"%d\0A\00" @no = internal constant [4 x i8] c"no\0A\00" -define i1 @func1(i32 %v1, i32 %v2) nounwind { +define i1 @test1(i32 %v1, i32 %v2) nounwind { entry: %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2) %sum = extractvalue {i32, i1} %t, 0 @@ -17,7 +17,53 @@ normal: overflow: %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind ret i1 false +; CHECK: test1: +; CHECK: imull +; CHECK-NEXT: jo +} + +define i1 @test2(i32 %v1, i32 %v2) nounwind { +entry: + %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2) + %sum = extractvalue {i32, i1} %t, 0 + %obit = extractvalue {i32, i1} %t, 1 + br i1 %obit, label %overflow, label %normal + +overflow: + %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind + ret i1 false + +normal: + %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + ret i1 true +; CHECK: test2: +; CHECK: imull +; CHECK-NEXT: jno } declare i32 @printf(i8*, ...) nounwind declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) + +define i32 @test3(i32 %a, i32 %b) nounwind readnone { +entry: + %tmp0 = add i32 %b, %a + %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2) + %tmp2 = extractvalue { i32, i1 } %tmp1, 0 + ret i32 %tmp2 +; CHECK: test3: +; CHECK: addl +; CHECK-NEXT: addl +; CHECK-NEXT: ret +} + +define i32 @test4(i32 %a, i32 %b) nounwind readnone { +entry: + %tmp0 = add i32 %b, %a + %tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4) + %tmp2 = extractvalue { i32, i1 } %tmp1, 0 + ret i32 %tmp2 +; CHECK: test4: +; CHECK: addl +; CHECK: mull +; CHECK-NEXT: ret +} diff --git a/test/CodeGen/X86/sse-minmax.ll b/test/CodeGen/X86/sse-minmax.ll index 348121a..ff0af25 100644 --- a/test/CodeGen/X86/sse-minmax.ll +++ b/test/CodeGen/X86/sse-minmax.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=x86-64 -asm-verbose=false | FileCheck %s -; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s -; RUN: llc < %s -march=x86-64 -asm-verbose=false -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs | FileCheck %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s +; RUN: llc < %s -march=x86-64 -asm-verbose=false -join-physregs -enable-no-nans-fp-math | FileCheck -check-prefix=FINITE %s ; Some of these patterns can be matched as SSE min or max. Some of ; then can be matched provided that the operands are swapped. @@ -12,6 +12,9 @@ ; y_ : use -0.0 instead of %y ; _inverse : swap the arms of the select. +; Some of these tests depend on -join-physregs commuting instructions to +; eliminate copies. + ; CHECK: ogt: ; CHECK-NEXT: maxsd %xmm1, %xmm0 ; CHECK-NEXT: ret diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 8e72f13..8c2e58d 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -62,11 +62,10 @@ define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind { %tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 > ret <8 x i16> %tmp ; X64: t4: -; X64: pextrw $7, %xmm0, %eax -; X64: pshufhw $100, %xmm0, %xmm1 -; X64: pinsrw $1, %eax, %xmm1 -; X64: pextrw $1, %xmm0, %eax -; X64: movdqa %xmm1, %xmm0 +; X64: pextrw $7, [[XMM0:%xmm[0-9]+]], %eax +; X64: pshufhw $100, [[XMM0]], [[XMM1:%xmm[0-9]+]] +; X64: pinsrw $1, %eax, [[XMM1]] +; X64: pextrw $1, [[XMM0]], %eax ; X64: pinsrw $4, %eax, %xmm0 ; X64: ret } @@ -251,13 +250,13 @@ entry: %tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef > ret <16 x i8> %tmp9 ; X64: t16: -; X64: pinsrw $0, %eax, %xmm1 -; X64: pextrw $8, %xmm0, %eax -; X64: pinsrw $1, %eax, %xmm1 -; X64: pextrw $1, %xmm1, %ecx -; X64: movd %xmm1, %edx -; X64: pinsrw $0, %edx, %xmm1 -; X64: pinsrw $1, %eax, %xmm0 +; X64: pinsrw $0, %eax, [[X1:%xmm[0-9]+]] +; X64: pextrw $8, [[X0:%xmm[0-9]+]], %eax +; X64: pinsrw $1, %eax, [[X1]] +; X64: pextrw $1, [[X1]], %ecx +; X64: movd [[X1]], %edx +; X64: pinsrw $0, %edx, %xmm +; X64: pinsrw $1, %eax, %xmm ; X64: ret } diff --git a/test/CodeGen/X86/sse42.ll b/test/CodeGen/X86/sse42.ll index 1723909..c787523 100644 --- a/test/CodeGen/X86/sse42.ll +++ b/test/CodeGen/X86/sse42.ll @@ -1,38 +1,39 @@ ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X32 ; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64 -declare i32 @llvm.x86.sse42.crc32.8(i32, i8) nounwind -declare i32 @llvm.x86.sse42.crc32.16(i32, i16) nounwind -declare i32 @llvm.x86.sse42.crc32.32(i32, i32) nounwind +declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind +declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind +declare i32 @llvm.x86.sse42.crc32.32.32(i32, i32) nounwind -define i32 @crc32_8(i32 %a, i8 %b) nounwind { - %tmp = call i32 @llvm.x86.sse42.crc32.8(i32 %a, i8 %b) +define i32 @crc32_32_8(i32 %a, i8 %b) nounwind { + %tmp = call i32 @llvm.x86.sse42.crc32.32.8(i32 %a, i8 %b) ret i32 %tmp -; X32: _crc32_8: +; X32: _crc32_32_8: ; X32: crc32b 8(%esp), %eax -; X64: _crc32_8: -; X64: crc32b %sil, %eax +; X64: _crc32_32_8: +; X64: crc32b %sil, } -define i32 @crc32_16(i32 %a, i16 %b) nounwind { - %tmp = call i32 @llvm.x86.sse42.crc32.16(i32 %a, i16 %b) +define i32 @crc32_32_16(i32 %a, i16 %b) nounwind { + %tmp = call i32 @llvm.x86.sse42.crc32.32.16(i32 %a, i16 %b) ret i32 %tmp -; X32: _crc32_16: +; X32: _crc32_32_16: ; X32: crc32w 8(%esp), %eax -; X64: _crc32_16: -; X64: crc32w %si, %eax +; X64: _crc32_32_16: +; X64: crc32w %si, } -define i32 @crc32_32(i32 %a, i32 %b) nounwind { - %tmp = call i32 @llvm.x86.sse42.crc32.32(i32 %a, i32 %b) +define i32 @crc32_32_32(i32 %a, i32 %b) nounwind { + %tmp = call i32 @llvm.x86.sse42.crc32.32.32(i32 %a, i32 %b) ret i32 %tmp -; X32: _crc32_32: +; X32: _crc32_32_32: ; X32: crc32l 8(%esp), %eax -; X64: _crc32_32: -; X64: crc32l %esi, %eax +; X64: _crc32_32_32: +; X64: crc32l %esi, } + diff --git a/test/CodeGen/X86/sse42_64.ll b/test/CodeGen/X86/sse42_64.ll new file mode 100644 index 0000000..8b3a69b --- /dev/null +++ b/test/CodeGen/X86/sse42_64.ll @@ -0,0 +1,21 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin9 -mattr=sse42 | FileCheck %s -check-prefix=X64 + +declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind +declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind + +define i64 @crc32_64_8(i64 %a, i8 %b) nounwind { + %tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b) + ret i64 %tmp + +; X64: _crc32_64_8: +; X64: crc32b %sil, +} + +define i64 @crc32_64_64(i64 %a, i64 %b) nounwind { + %tmp = call i64 @llvm.x86.sse42.crc32.64.64(i64 %a, i64 %b) + ret i64 %tmp + +; X64: _crc32_64_64: +; X64: crc32q %rsi, +} + diff --git a/test/CodeGen/X86/sse_reload_fold.ll b/test/CodeGen/X86/sse_reload_fold.ll index 02399c4..a57fa58 100644 --- a/test/CodeGen/X86/sse_reload_fold.ll +++ b/test/CodeGen/X86/sse_reload_fold.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates |& FileCheck %s +; RUN: llc < %s -mtriple=x86_64-linux -mattr=+64bit,+sse3 -print-failed-fuse-candidates -regalloc=basic |& FileCheck %s ; CHECK: fail ; CHECK-NOT: fail @@ -117,7 +117,16 @@ define <2 x double> @d8(<2 x double> %f) { ret <2 x double> %t } -; This one should fail to fuse. +; This one should fail to fuse, but -regalloc=greedy isn't even trying. Instead +; it produces: +; callq test_vd +; movapd (%rsp), %xmm1 # 16-byte Reload +; hsubpd %xmm0, %xmm1 +; movapd %xmm1, %xmm0 +; addq $24, %rsp +; ret +; RABasic still tries to fold this one. + define <2 x double> @z0(<2 x double> %f) { %y = call <2 x double> @test_vd(<2 x double> %f) %t = call <2 x double> @llvm.x86.sse3.hsub.pd(<2 x double> %f, <2 x double> %y) diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 424bd21..d6c16ca 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -109,15 +109,15 @@ altret: ; CHECK: dont_merge_oddly: ; CHECK-NOT: ret -; CHECK: ucomiss %xmm1, %xmm2 +; CHECK: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} ; CHECK-NEXT: jbe .LBB2_3 -; CHECK-NEXT: ucomiss %xmm0, %xmm1 +; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} ; CHECK-NEXT: ja .LBB2_4 ; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: movb $1, %al ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB2_3: -; CHECK-NEXT: ucomiss %xmm0, %xmm2 +; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} ; CHECK-NEXT: jbe .LBB2_2 ; CHECK-NEXT: .LBB2_4: ; CHECK-NEXT: xorb %al, %al @@ -412,9 +412,9 @@ return: ; can fall-through into the ret and the other side has to branch anyway. ; CHECK: TESTE: -; CHECK: imulq -; CHECK-NEXT: LBB8_2: -; CHECK-NEXT: ret +; CHECK: ret +; CHECK-NOT: ret +; CHECK: size TESTE define i64 @TESTE(i64 %parami, i64 %paraml) nounwind readnone { entry: diff --git a/test/CodeGen/X86/tail-threshold.ll b/test/CodeGen/X86/tail-threshold.ll new file mode 100644 index 0000000..f2296a0 --- /dev/null +++ b/test/CodeGen/X86/tail-threshold.ll @@ -0,0 +1,44 @@ +; RUN: llc -mtriple=x86_64-pc-linux-gnu -tail-merge-threshold 2 < %s | FileCheck %s + +; Test that we still do some merging if a block has more than +; tail-merge-threshold predecessors. + +; CHECK: callq bar +; CHECK: callq bar +; CHECK: callq bar +; CHECK-NOT: callq + +declare void @bar() + +define void @foo(i32 %xxx) { +entry: + switch i32 %xxx, label %bb4 [ + i32 0, label %bb0 + i32 1, label %bb1 + i32 2, label %bb2 + i32 3, label %bb3 + ] + +bb0: + call void @bar() + br label %bb5 + +bb1: + call void @bar() + br label %bb5 + +bb2: + call void @bar() + br label %bb5 + +bb3: + call void @bar() + br label %bb5 + +bb4: + call void @bar() + br label %bb5 + +bb5: + ret void +} diff --git a/test/CodeGen/X86/tailcallbyval.ll b/test/CodeGen/X86/tailcallbyval.ll index 7002560..03d6f94 100644 --- a/test/CodeGen/X86/tailcallbyval.ll +++ b/test/CodeGen/X86/tailcallbyval.ll @@ -13,6 +13,6 @@ entry: define fastcc i32 @tailcaller(%struct.s* byval %a) nounwind { entry: - %tmp4 = tail call fastcc i32 @tailcallee(%struct.s* %a byval) + %tmp4 = tail call fastcc i32 @tailcallee(%struct.s* byval %a ) ret i32 %tmp4 } diff --git a/test/CodeGen/X86/tailcallbyval64.ll b/test/CodeGen/X86/tailcallbyval64.ll index 1b1efe7..7ecf379 100644 --- a/test/CodeGen/X86/tailcallbyval64.ll +++ b/test/CodeGen/X86/tailcallbyval64.ll @@ -37,6 +37,6 @@ define fastcc i64 @tailcaller(i64 %b, %struct.s* byval %a) { entry: %tmp2 = getelementptr %struct.s* %a, i32 0, i32 1 %tmp3 = load i64* %tmp2, align 8 - %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* %a byval, i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) + %tmp4 = tail call fastcc i64 @tailcallee(%struct.s* byval %a , i64 %tmp3, i64 %b, i64 7, i64 13, i64 17) ret i64 %tmp4 } diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 060ce0f..c18c7aa 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -tailcallopt -mtriple=x86_64-win32 -post-RA-scheduler=true | FileCheck %s ; FIXME: Redundant unused stack allocation could be eliminated. -; CHECK: subq ${{24|72}}, %rsp +; CHECK: subq ${{24|72|80}}, %rsp ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). diff --git a/test/CodeGen/X86/test-nofold.ll b/test/CodeGen/X86/test-nofold.ll index f1063dc..97db1b3 100644 --- a/test/CodeGen/X86/test-nofold.ll +++ b/test/CodeGen/X86/test-nofold.ll @@ -2,10 +2,10 @@ ; rdar://5752025 ; We want: -; CHECK: movl 4(%esp), %ecx -; CHECK-NEXT: andl $15, %ecx -; CHECK-NEXT: movl $42, %eax -; CHECK-NEXT: cmovel %ecx, %eax +; CHECK: movl $42, %ecx +; CHECK-NEXT: movl 4(%esp), %eax +; CHECK-NEXT: andl $15, %eax +; CHECK-NEXT: cmovnel %ecx, %eax ; CHECK-NEXT: ret ; ; We don't want: diff --git a/test/CodeGen/X86/trunc-to-bool.ll b/test/CodeGen/X86/trunc-to-bool.ll index 6062084..92b6859 100644 --- a/test/CodeGen/X86/trunc-to-bool.ll +++ b/test/CodeGen/X86/trunc-to-bool.ll @@ -3,7 +3,7 @@ ; value and as the operand of a branch. ; RUN: llc < %s -march=x86 | FileCheck %s -define i1 @test1(i32 %X) zeroext nounwind { +define zeroext i1 @test1(i32 %X) nounwind { %Y = trunc i32 %X to i1 ret i1 %Y } diff --git a/test/CodeGen/X86/umul-with-overflow.ll b/test/CodeGen/X86/umul-with-overflow.ll index c997661..e5858de 100644 --- a/test/CodeGen/X86/umul-with-overflow.ll +++ b/test/CodeGen/X86/umul-with-overflow.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=x86 | FileCheck %s declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) -define i1 @a(i32 %x) zeroext nounwind { +define zeroext i1 @a(i32 %x) nounwind { %res = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %x, i32 3) %obil = extractvalue {i32, i1} %res, 1 ret i1 %obil @@ -12,3 +12,27 @@ define i1 @a(i32 %x) zeroext nounwind { ; CHECK: movzbl %al, %eax ; CHECK: ret } + +define i32 @test2(i32 %a, i32 %b) nounwind readnone { +entry: + %tmp0 = add i32 %b, %a + %tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2) + %tmp2 = extractvalue { i32, i1 } %tmp1, 0 + ret i32 %tmp2 +; CHECK: test2: +; CHECK: addl +; CHECK-NEXT: addl +; CHECK-NEXT: ret +} + +define i32 @test3(i32 %a, i32 %b) nounwind readnone { +entry: + %tmp0 = add i32 %b, %a + %tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 4) + %tmp2 = extractvalue { i32, i1 } %tmp1, 0 + ret i32 %tmp2 +; CHECK: test3: +; CHECK: addl +; CHECK: mull +; CHECK-NEXT: ret +} diff --git a/test/CodeGen/X86/unaligned-load.ll b/test/CodeGen/X86/unaligned-load.ll index 6a493c0..9f70489 100644 --- a/test/CodeGen/X86/unaligned-load.ll +++ b/test/CodeGen/X86/unaligned-load.ll @@ -29,8 +29,8 @@ return: declare void @llvm.memcpy.i64(i8* nocapture, i8* nocapture, i64, i32) nounwind ; CORE2: .section -; CORE2: .align 4 +; CORE2: .align 3 ; CORE2-NEXT: _.str1: ; CORE2-NEXT: .asciz "DHRYSTONE PROGRAM, SOME STRING" -; CORE2: .align 4 +; CORE2: .align 3 ; CORE2-NEXT: _.str3: diff --git a/test/CodeGen/X86/undef-label.ll b/test/CodeGen/X86/undef-label.ll new file mode 100644 index 0000000..1afd935 --- /dev/null +++ b/test/CodeGen/X86/undef-label.ll @@ -0,0 +1,19 @@ +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s + +; This is a case where we would incorrectly conclude that LBB0_1 could only +; be reached via fall through and would therefore omit the label. + +; CHECK: jne .LBB0_1 +; CHECK-NEXT: jnp .LBB0_3 +; CHECK-NEXT: .LBB0_1: + +define void @xyz() { +entry: + br i1 fcmp oeq (double fsub (double undef, double undef), double 0.000000e+00), label %bar, label %foo + +foo: + br i1 fcmp ogt (double fdiv (double fsub (double fmul (double undef, double undef), double fsub (double undef, double undef)), double fmul (double undef, double undef)), double 1.0), label %foo, label %bar + +bar: + ret void +} diff --git a/test/CodeGen/X86/use-add-flags.ll b/test/CodeGen/X86/use-add-flags.ll index 8fbbd39..a0448ec 100644 --- a/test/CodeGen/X86/use-add-flags.ll +++ b/test/CodeGen/X86/use-add-flags.ll @@ -7,10 +7,10 @@ ; Use the flags on the add. ; CHECK: test1: -; CHECK: addl (%r[[A0:di|cx]]), {{%esi|%edx}} -; CHECK-NEXT: movl {{%edx|%r8d}}, %eax -; CHECK-NEXT: cmovnsl {{%ecx|%r9d}}, %eax -; CHECK-NEXT: ret +; CHECK: addl +; CHECK-NOT: test +; CHECK: cmovnsl +; CHECK: ret define i32 @test1(i32* %x, i32 %y, i32 %a, i32 %b) nounwind { %tmp2 = load i32* %x, align 4 ; <i32> [#uses=1] @@ -42,7 +42,7 @@ false: ; Do use the flags result of the and here, since the and has another use. ; CHECK: test3: -; CHECK: andl $16, %e[[A0]] +; CHECK: andl $16, %e ; CHECK-NEXT: jne define void @test3(i32 %x) nounwind { diff --git a/test/CodeGen/X86/vararg_tailcall.ll b/test/CodeGen/X86/vararg_tailcall.ll new file mode 100644 index 0000000..73d80eb --- /dev/null +++ b/test/CodeGen/X86/vararg_tailcall.ll @@ -0,0 +1,98 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s -check-prefix=X64 +; RUN: llc < %s -mtriple=x86_64-pc-win32 | FileCheck %s -check-prefix=WIN64 + +@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00" +@sel = external global i8* +@sel3 = external global i8* +@sel4 = external global i8* +@sel5 = external global i8* +@sel6 = external global i8* +@sel7 = external global i8* + +; X64: @foo +; X64: jmp +; WIN64: @foo +; WIN64: callq +define void @foo(i64 %arg) nounwind optsize ssp noredzone { +entry: + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone + ret void +} + +declare i32 @printf(i8*, ...) optsize noredzone + +; X64: @bar +; X64: jmp +; WIN64: @bar +; WIN64: jmp +define void @bar(i64 %arg) nounwind optsize ssp noredzone { +entry: + tail call void @bar2(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone + ret void +} + +declare void @bar2(i8*, i64) optsize noredzone + +; X64: @foo2 +; X64: jmp +; WIN64: @foo2 +; WIN64: callq +define i8* @foo2(i8* %arg) nounwind optsize ssp noredzone { +entry: + %tmp1 = load i8** @sel, align 8, !tbaa !0 + %call = tail call i8* (i8*, i8*, ...)* @x2(i8* %arg, i8* %tmp1) nounwind optsize noredzone + ret i8* %call +} + +declare i8* @x2(i8*, i8*, ...) optsize noredzone + +; X64: @foo6 +; X64: jmp +; WIN64: @foo6 +; WIN64: callq +define i8* @foo6(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { +entry: + %tmp2 = load i8** @sel3, align 8, !tbaa !0 + %tmp3 = load i8** @sel4, align 8, !tbaa !0 + %tmp4 = load i8** @sel5, align 8, !tbaa !0 + %tmp5 = load i8** @sel6, align 8, !tbaa !0 + %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5) nounwind optsize noredzone + ret i8* %call +} + +declare i8* @x3(i8*, i8*, i8*, ...) optsize noredzone + +; X64: @foo7 +; X64: callq +; WIN64: @foo7 +; WIN64: callq +define i8* @foo7(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { +entry: + %tmp2 = load i8** @sel3, align 8, !tbaa !0 + %tmp3 = load i8** @sel4, align 8, !tbaa !0 + %tmp4 = load i8** @sel5, align 8, !tbaa !0 + %tmp5 = load i8** @sel6, align 8, !tbaa !0 + %tmp6 = load i8** @sel7, align 8, !tbaa !0 + %call = tail call i8* (i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...)* @x7(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i8* %tmp6) nounwind optsize noredzone + ret i8* %call +} + +declare i8* @x7(i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...) optsize noredzone + +; X64: @foo8 +; X64: callq +; WIN64: @foo8 +; WIN64: callq +define i8* @foo8(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { +entry: + %tmp2 = load i8** @sel3, align 8, !tbaa !0 + %tmp3 = load i8** @sel4, align 8, !tbaa !0 + %tmp4 = load i8** @sel5, align 8, !tbaa !0 + %tmp5 = load i8** @sel6, align 8, !tbaa !0 + %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i32 48879, i32 48879) nounwind optsize noredzone + ret i8* %call +} + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} diff --git a/test/CodeGen/X86/vec_extract-sse4.ll b/test/CodeGen/X86/vec_extract-sse4.ll index dab5dd1..f487654 100644 --- a/test/CodeGen/X86/vec_extract-sse4.ll +++ b/test/CodeGen/X86/vec_extract-sse4.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=x86 -mattr=+sse41 -o %t -; RUN: grep extractps %t | count 1 -; RUN: grep pextrd %t | count 1 +; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse41 -o %t +; RUN: not grep extractps %t +; RUN: not grep pextrd %t ; RUN: not grep pshufd %t -; RUN: not grep movss %t +; RUN: grep movss %t | count 2 define void @t1(float* %R, <4 x float>* %P1) nounwind { %X = load <4 x float>* %P1 diff --git a/test/CodeGen/X86/vec_extract.ll b/test/CodeGen/X86/vec_extract.ll index b013730..2c8796b 100644 --- a/test/CodeGen/X86/vec_extract.ll +++ b/test/CodeGen/X86/vec_extract.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 -o %t -; RUN: grep movss %t | count 3 +; RUN: llc < %s -mcpu=corei7 -march=x86 -mattr=+sse2,-sse41 -o %t +; RUN: grep movss %t | count 4 ; RUN: grep movhlps %t | count 1 -; RUN: grep pshufd %t | count 1 +; RUN: not grep pshufd %t ; RUN: grep unpckhpd %t | count 1 define void @test1(<4 x float>* %F, float* %f) nounwind { diff --git a/test/CodeGen/X86/vec_shuffle-16.ll b/test/CodeGen/X86/vec_shuffle-16.ll index 2ee87fe..06f38ed 100644 --- a/test/CodeGen/X86/vec_shuffle-16.ll +++ b/test/CodeGen/X86/vec_shuffle-16.ll @@ -1,8 +1,9 @@ ; RUN: llc < %s -march=x86 -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse ; RUN: llc < %s -march=x86 -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2 +; sse: t1: +; sse2: t1: define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind { -; sse: movaps ; sse: shufps ; sse2: pshufd ; sse2-NEXT: ret @@ -10,6 +11,8 @@ define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind { ret <4 x float> %tmp1 } +; sse: t2: +; sse2: t2: define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind { ; sse: shufps ; sse2: pshufd @@ -18,8 +21,9 @@ define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind { ret <4 x float> %tmp } +; sse: t3: +; sse2: t3: define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind { -; sse: movaps ; sse: shufps ; sse2: pshufd ; sse2-NEXT: ret @@ -27,7 +31,10 @@ define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind { ret <4 x float> %tmp } +; sse: t4: +; sse2: t4: define <4 x float> @t4(<4 x float> %A, <4 x float> %B) nounwind { + ; sse: shufps ; sse2: pshufd ; sse2-NEXT: ret diff --git a/test/CodeGen/X86/vec_uint_to_fp.ll b/test/CodeGen/X86/vec_uint_to_fp.ll index 39e7d71..fe7fa2f 100644 --- a/test/CodeGen/X86/vec_uint_to_fp.ll +++ b/test/CodeGen/X86/vec_uint_to_fp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 -mcpu=sandybridge | FileCheck %s +; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s ; Test that we are not lowering uinttofp to scalars define <4 x float> @test1(<4 x i32> %A) nounwind { diff --git a/test/CodeGen/X86/visibility2.ll b/test/CodeGen/X86/visibility2.ll new file mode 100644 index 0000000..72ea733 --- /dev/null +++ b/test/CodeGen/X86/visibility2.ll @@ -0,0 +1,18 @@ +; This test case ensures that when the visibility of a global declaration is +; emitted they are not treated as definitions. Test case for r132825. +; Fixes <rdar://problem/9429892>. +; +; RUN: llc -mtriple=x86_64-apple-darwin %s -o - | FileCheck %s + +@foo_private_extern_str = external hidden global i8* + +define void @foo1() nounwind ssp { +entry: + %tmp = load i8** @foo_private_extern_str, align 8 + call void @foo3(i8* %tmp) + ret void +} + +declare void @foo3(i8*) + +; CHECK-NOT: .private_extern diff --git a/test/CodeGen/X86/widen_load-0.ll b/test/CodeGen/X86/widen_load-0.ll index 82c8252..c91627c 100644 --- a/test/CodeGen/X86/widen_load-0.ll +++ b/test/CodeGen/X86/widen_load-0.ll @@ -4,15 +4,15 @@ ; Both loads should happen before either store. -; CHECK: movl (%rdi), %eax -; CHECK: movl (%rsi), %ecx -; CHECK: movl %ecx, (%rdi) -; CHECK: movl %eax, (%rsi) +; CHECK: movl (%rdi), %[[R1:...]] +; CHECK: movl (%rsi), %[[R2:...]] +; CHECK: movl %[[R2]], (%rdi) +; CHECK: movl %[[R1]], (%rsi) -; WIN64: movl (%rcx), %eax -; WIN64: movl (%rdx), %esi -; WIN64: movl %esi, (%rcx) -; WIN64: movl %eax, (%rdx) +; WIN64: movl (%rcx), %[[R1:...]] +; WIN64: movl (%rdx), %[[R2:...]] +; WIN64: movl %[[R2]], (%rcx) +; WIN64: movl %[[R1]], (%rdx) define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind { entry: diff --git a/test/CodeGen/X86/win64_alloca_dynalloca.ll b/test/CodeGen/X86/win64_alloca_dynalloca.ll index cbd38da..e39d007 100644 --- a/test/CodeGen/X86/win64_alloca_dynalloca.ll +++ b/test/CodeGen/X86/win64_alloca_dynalloca.ll @@ -1,9 +1,12 @@ -; RUN: llc < %s -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64 -; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64 -; RUN: llc < %s -mtriple=x86_64-win32-macho | FileCheck %s -check-prefix=EFI +; RUN: llc < %s -join-physregs -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64 +; RUN: llc < %s -join-physregs -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64 +; RUN: llc < %s -join-physregs -mtriple=x86_64-win32-macho | FileCheck %s -check-prefix=EFI ; PR8777 ; PR8778 +; Passing the same value in two registers creates a false interference that +; only -join-physregs resolves. It could also be handled by a parallel copy. + define i64 @foo(i64 %n, i64 %x) nounwind { entry: @@ -40,9 +43,9 @@ entry: ; W64: subq %rax, %rsp ; W64: movq %rsp, %rax -; EFI: leaq 15(%rcx), [[R1:%r..]] +; EFI: leaq 15(%rcx), [[R1:%r.*]] ; EFI: andq $-16, [[R1]] -; EFI: movq %rsp, [[R64:%r..]] +; EFI: movq %rsp, [[R64:%r.*]] ; EFI: subq [[R1]], [[R64]] ; EFI: movq [[R64]], %rsp diff --git a/test/CodeGen/X86/x86-64-and-mask.ll b/test/CodeGen/X86/x86-64-and-mask.ll index 2465f23..07ccb23 100644 --- a/test/CodeGen/X86/x86-64-and-mask.ll +++ b/test/CodeGen/X86/x86-64-and-mask.ll @@ -39,7 +39,7 @@ define void @ccc(i64 %x) nounwind { ; This requires a mov and a 64-bit and. ; CHECK: ddd: -; CHECK: movabsq $4294967296, %rax +; CHECK: movabsq $4294967296, %r ; CHECK: andq %rax, %rdi define void @ddd(i64 %x) nounwind { diff --git a/test/CodeGen/X86/x86-64-extend-shift.ll b/test/CodeGen/X86/x86-64-extend-shift.ll index 6852785..6ebaeee 100644 --- a/test/CodeGen/X86/x86-64-extend-shift.ll +++ b/test/CodeGen/X86/x86-64-extend-shift.ll @@ -2,7 +2,7 @@ ; Formerly there were two shifts. define i64 @baz(i32 %A) nounwind { -; CHECK: shlq $49, %rax +; CHECK: shlq $49, %r %tmp1 = shl i32 %A, 17 %tmp2 = zext i32 %tmp1 to i64 %tmp3 = shl i64 %tmp2, 32 diff --git a/test/CodeGen/X86/x86-64-malloc.ll b/test/CodeGen/X86/x86-64-malloc.ll deleted file mode 100644 index 4aa0ec3..0000000 --- a/test/CodeGen/X86/x86-64-malloc.ll +++ /dev/null @@ -1,12 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -; CHECK: shll $3, {{%edi|%ecx}} -; PR3829 -; The generated code should multiply by 3 (sizeof i8*) as an i32, -; not as an i64! - -define i8** @test(i32 %sz) { - %sub = add i32 %sz, 536870911 ; <i32> [#uses=1] - %call = malloc i8*, i32 %sub ; <i8**> [#uses=1] - ret i8** %call -} diff --git a/test/CodeGen/X86/x86-64-shortint.ll b/test/CodeGen/X86/x86-64-shortint.ll index 7f96543..cbf6588 100644 --- a/test/CodeGen/X86/x86-64-shortint.ll +++ b/test/CodeGen/X86/x86-64-shortint.ll @@ -5,7 +5,7 @@ target triple = "x86_64-apple-darwin8" define void @bar(i16 zeroext %A) { - tail call void @foo( i16 %A signext ) + tail call void @foo( i16 signext %A ) ret void } declare void @foo(i16 signext ) diff --git a/test/CodeGen/X86/x86-shifts.ll b/test/CodeGen/X86/x86-shifts.ll new file mode 100644 index 0000000..fdf68f9 --- /dev/null +++ b/test/CodeGen/X86/x86-shifts.ll @@ -0,0 +1,142 @@ +; RUN: llc < %s -march=x86-64 -mcpu=corei7 | FileCheck %s + +; Splat patterns below + + +define <4 x i32> @shl4(<4 x i32> %A) nounwind { +entry: +; CHECK: shl4 +; CHECK: pslld +; CHECK-NEXT: pslld + %B = shl <4 x i32> %A, < i32 2, i32 2, i32 2, i32 2> + %C = shl <4 x i32> %A, < i32 1, i32 1, i32 1, i32 1> + %K = xor <4 x i32> %B, %C + ret <4 x i32> %K +} + +define <4 x i32> @shr4(<4 x i32> %A) nounwind { +entry: +; CHECK: shr4 +; CHECK: psrld +; CHECK-NEXT: psrld + %B = lshr <4 x i32> %A, < i32 2, i32 2, i32 2, i32 2> + %C = lshr <4 x i32> %A, < i32 1, i32 1, i32 1, i32 1> + %K = xor <4 x i32> %B, %C + ret <4 x i32> %K +} + +define <4 x i32> @sra4(<4 x i32> %A) nounwind { +entry: +; CHECK: sra4 +; CHECK: psrad +; CHECK-NEXT: psrad + %B = ashr <4 x i32> %A, < i32 2, i32 2, i32 2, i32 2> + %C = ashr <4 x i32> %A, < i32 1, i32 1, i32 1, i32 1> + %K = xor <4 x i32> %B, %C + ret <4 x i32> %K +} + +define <2 x i64> @shl2(<2 x i64> %A) nounwind { +entry: +; CHECK: shl2 +; CHECK: psllq +; CHECK-NEXT: psllq + %B = shl <2 x i64> %A, < i64 2, i64 2> + %C = shl <2 x i64> %A, < i64 9, i64 9> + %K = xor <2 x i64> %B, %C + ret <2 x i64> %K +} + +define <2 x i64> @shr2(<2 x i64> %A) nounwind { +entry: +; CHECK: shr2 +; CHECK: psrlq +; CHECK-NEXT: psrlq + %B = lshr <2 x i64> %A, < i64 8, i64 8> + %C = lshr <2 x i64> %A, < i64 1, i64 1> + %K = xor <2 x i64> %B, %C + ret <2 x i64> %K +} + + +define <8 x i16> @shl8(<8 x i16> %A) nounwind { +entry: +; CHECK: shl8 +; CHECK: psllw +; CHECK-NEXT: psllw + %B = shl <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> + %C = shl <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %K = xor <8 x i16> %B, %C + ret <8 x i16> %K +} + +define <8 x i16> @shr8(<8 x i16> %A) nounwind { +entry: +; CHECK: shr8 +; CHECK: psrlw +; CHECK-NEXT: psrlw + %B = lshr <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> + %C = lshr <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %K = xor <8 x i16> %B, %C + ret <8 x i16> %K +} + +define <8 x i16> @sra8(<8 x i16> %A) nounwind { +entry: +; CHECK: sra8 +; CHECK: psraw +; CHECK-NEXT: psraw + %B = ashr <8 x i16> %A, < i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2, i16 2> + %C = ashr <8 x i16> %A, < i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> + %K = xor <8 x i16> %B, %C + ret <8 x i16> %K +} + +; non splat test + + +define <8 x i16> @sll8_nosplat(<8 x i16> %A) nounwind { +entry: +; CHECK: sll8_nosplat +; CHECK-NOT: psll +; CHECK-NOT: psll + %B = shl <8 x i16> %A, < i16 1, i16 2, i16 3, i16 6, i16 2, i16 2, i16 2, i16 2> + %C = shl <8 x i16> %A, < i16 9, i16 7, i16 5, i16 1, i16 4, i16 1, i16 1, i16 1> + %K = xor <8 x i16> %B, %C + ret <8 x i16> %K +} + + +define <2 x i64> @shr2_nosplat(<2 x i64> %A) nounwind { +entry: +; CHECK: shr2_nosplat +; CHECK-NOT: psrlq +; CHECK-NOT: psrlq + %B = lshr <2 x i64> %A, < i64 8, i64 1> + %C = lshr <2 x i64> %A, < i64 1, i64 0> + %K = xor <2 x i64> %B, %C + ret <2 x i64> %K +} + + +; Other shifts + +define <2 x i32> @shl2_other(<2 x i32> %A) nounwind { +entry: +; CHECK: shl2_other +; CHECK-not: psllq + %B = shl <2 x i32> %A, < i32 2, i32 2> + %C = shl <2 x i32> %A, < i32 9, i32 9> + %K = xor <2 x i32> %B, %C + ret <2 x i32> %K +} + +define <2 x i32> @shr2_other(<2 x i32> %A) nounwind { +entry: +; CHECK: shr2_other +; CHECK-NOT: psrlq + %B = lshr <2 x i32> %A, < i32 8, i32 8> + %C = lshr <2 x i32> %A, < i32 1, i32 1> + %K = xor <2 x i32> %B, %C + ret <2 x i32> %K +} diff --git a/test/CodeGen/X86/xor.ll b/test/CodeGen/X86/xor.ll index b90d81a..178c59d 100644 --- a/test/CodeGen/X86/xor.ll +++ b/test/CodeGen/X86/xor.ll @@ -29,9 +29,8 @@ entry: ret i32 %tmp4 ; X64: test3: -; X64: notl [[A1:%esi|%edx]] -; X64: andl [[A0:%edi|%ecx]], [[A1]] -; X64: movl [[A1]], %eax +; X64: notl +; X64: andl ; X64: shrl %eax ; X64: ret @@ -139,7 +138,7 @@ entry: %t2 = add i32 %t1, -1 ret i32 %t2 ; X64: test8: -; X64: notl %eax +; X64: notl {{%eax|%edi|%ecx}} ; X32: test8: ; X32: notl %eax } diff --git a/test/CodeGen/X86/zext-fold.ll b/test/CodeGen/X86/zext-fold.ll new file mode 100644 index 0000000..b3f5cdb --- /dev/null +++ b/test/CodeGen/X86/zext-fold.ll @@ -0,0 +1,41 @@ +; RUN: llc < %s -march=x86 | FileCheck %s + +;; Simple case +define i32 @test1(i8 %x) nounwind readnone { + %A = and i8 %x, -32 + %B = zext i8 %A to i32 + ret i32 %B +} +; CHECK: test1 +; CHECK: movzbl +; CHECK-NEXT: andl {{.*}}224 + +;; Multiple uses of %x but easily extensible. +define i32 @test2(i8 %x) nounwind readnone { + %A = and i8 %x, -32 + %B = zext i8 %A to i32 + %C = or i8 %x, 63 + %D = zext i8 %C to i32 + %E = add i32 %B, %D + ret i32 %E +} +; CHECK: test2 +; CHECK: movzbl +; CHECK: orl $63 +; CHECK: andl $224 + +declare void @use(i32, i8) + +;; Multiple uses of %x where we shouldn't extend the load. +define void @test3(i8 %x) nounwind readnone { + %A = and i8 %x, -32 + %B = zext i8 %A to i32 + call void @use(i32 %B, i8 %x) + ret void +} +; CHECK: test3 +; CHECK: movzbl 16(%esp), [[REGISTER:%e[a-z]{2}]] +; CHECK-NEXT: movl [[REGISTER]], 4(%esp) +; CHECK-NEXT: andl $224, [[REGISTER]] +; CHECK-NEXT: movl [[REGISTER]], (%esp) +; CHECK-NEXT: call{{.*}}use diff --git a/test/CodeGen/XCore/bitrev.ll b/test/CodeGen/XCore/bitrev.ll deleted file mode 100644 index 09202d3..0000000 --- a/test/CodeGen/XCore/bitrev.ll +++ /dev/null @@ -1,8 +0,0 @@ -; RUN: llc < %s -march=xcore > %t1.s -; RUN: grep bitrev %t1.s | count 1 -declare i32 @llvm.xcore.bitrev(i32) - -define i32 @test(i32 %val) { - %result = call i32 @llvm.xcore.bitrev(i32 %val) - ret i32 %result -} diff --git a/test/CodeGen/XCore/misc-intrinsics.ll b/test/CodeGen/XCore/misc-intrinsics.ll new file mode 100644 index 0000000..f504a2e --- /dev/null +++ b/test/CodeGen/XCore/misc-intrinsics.ll @@ -0,0 +1,27 @@ +; RUN: llc < %s -march=xcore | FileCheck %s +%0 = type { i32, i32 } + +declare i32 @llvm.xcore.bitrev(i32) +declare i32 @llvm.xcore.crc32(i32, i32, i32) +declare %0 @llvm.xcore.crc8(i32, i32, i32) + +define i32 @bitrev(i32 %val) { +; CHECK: bitrev: +; CHECK: bitrev r0, r0 + %result = call i32 @llvm.xcore.bitrev(i32 %val) + ret i32 %result +} + +define i32 @crc32(i32 %crc, i32 %data, i32 %poly) { +; CHECK: crc32: +; CHECK: crc32 r0, r1, r2 + %result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly) + ret i32 %result +} + +define %0 @crc8(i32 %crc, i32 %data, i32 %poly) { +; CHECK: crc8: +; CHECK: crc8 r0, r1, r1, r2 + %result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly) + ret %0 %result +} diff --git a/test/CodeGen/XCore/mul64.ll b/test/CodeGen/XCore/mul64.ll index 77c6b42..3d373b1 100644 --- a/test/CodeGen/XCore/mul64.ll +++ b/test/CodeGen/XCore/mul64.ll @@ -9,7 +9,7 @@ entry: } ; CHECK: umul_lohi: ; CHECK: ldc [[REG:r[0-9]+]], 0 -; CHECK-NEXT: lmul r1, r0, r1, r0, [[REG]], [[REG]] +; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]] ; CHECK-NEXT: retsp 0 define i64 @smul_lohi(i32 %a, i32 %b) { @@ -23,9 +23,7 @@ entry: ; CHECK: ldc ; CHECK-NEXT: mov ; CHECK-NEXT: maccs -; CHECK-NEXT: mov r0, -; CHECK-NEXT: mov r1, -; CHECK-NEXT: retsp 0 +; CHECK: retsp 0 define i64 @mul64(i64 %a, i64 %b) { entry: @@ -37,7 +35,6 @@ entry: ; CHECK-NEXT: lmul ; CHECK-NEXT: mul ; CHECK-NEXT: lmul -; CHECK-NEXT: mov r0, define i64 @mul64_2(i64 %a, i32 %b) { entry: @@ -50,4 +47,4 @@ entry: ; CHECK-NEXT: lmul ; CHECK-NEXT: mul ; CHECK-NEXT: add r1, -; CHECK-NEXT: retsp 0 +; CHECK: retsp 0 |