diff options
Diffstat (limited to 'test/CodeGen')
120 files changed, 1361 insertions, 1770 deletions
diff --git a/test/CodeGen/ARM/2009-10-30.ll b/test/CodeGen/ARM/2009-10-30.ll index 87d1a8b..e46ab1e 100644 --- a/test/CodeGen/ARM/2009-10-30.ll +++ b/test/CodeGen/ARM/2009-10-30.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s ; This test checks that the address of the varg arguments is correctly ; computed when there are 5 or more regular arguments. diff --git a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll index 34f7519..a18a830 100644 --- a/test/CodeGen/ARM/2009-11-01-NeonMoves.ll +++ b/test/CodeGen/ARM/2009-11-01-NeonMoves.ll @@ -19,7 +19,7 @@ entry: %5 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %3, <2 x float> %4) nounwind ; <<2 x float>> [#uses=2] %6 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %5, <2 x float> %5) nounwind ; <<2 x float>> [#uses=2] %7 = shufflevector <2 x float> %6, <2 x float> %6, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=2] -;CHECK: vmov +;CHECK: vorr %8 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %7) nounwind ; <<4 x float>> [#uses=3] %9 = fmul <4 x float> %8, %8 ; <<4 x float>> [#uses=1] %10 = call <4 x float> @llvm.arm.neon.vrsqrts.v4f32(<4 x float> %9, <4 x float> %7) nounwind ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll index ee443fe..99db637 100644 --- a/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll +++ b/test/CodeGen/ARM/2010-10-19-mc-elf-objheader.ll @@ -1,7 +1,7 @@ ; RUN: llc %s -mtriple=arm-linux-gnueabi -filetype=obj -o - | \ ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=BASIC %s ; RUN: llc %s -mtriple=armv7-linux-gnueabi -march=arm -mcpu=cortex-a8 \ -; RUN: -mattr=-neon -mattr=+vfp2 \ +; RUN: -mattr=-neon,-vfp3,+vfp2 \ ; RUN: -arm-reserve-r9 -filetype=obj -o - | \ ; RUN: elf-dump --dump-section-data | FileCheck -check-prefix=CORTEXA8 %s diff --git a/test/CodeGen/ARM/2011-07-10-GlobalMergeBug.ll b/test/CodeGen/ARM/2011-07-10-GlobalMergeBug.ll new file mode 100644 index 0000000..2970cd2 --- /dev/null +++ b/test/CodeGen/ARM/2011-07-10-GlobalMergeBug.ll @@ -0,0 +1,8 @@ +; RUN: llc < %s | FileCheck %s +target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:32-n32" +target triple = "thumbv7-apple-darwin10" + +; CHECK-NOT: MergedGlobals + +@a = internal unnamed_addr global i1 false +@b = internal global [64 x i8] zeroinitializer, align 64 diff --git a/test/CodeGen/ARM/armv4.ll b/test/CodeGen/ARM/armv4.ll index ef722de..6b213d5 100644 --- a/test/CodeGen/ARM/armv4.ll +++ b/test/CodeGen/ARM/armv4.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-unknown-eabi | FileCheck %s -check-prefix=THUMB -; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -mtriple=arm-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB -; RUN: llc < %s -mtriple=arm-unknown-eabi -mattr=+v6 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB diff --git a/test/CodeGen/ARM/bfx.ll b/test/CodeGen/ARM/bfx.ll index fcca191..519c135 100644 --- a/test/CodeGen/ARM/bfx.ll +++ b/test/CodeGen/ARM/bfx.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s define i32 @sbfx1(i32 %a) { ; CHECK: sbfx1 diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index c460f7a..e01750b 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -15,11 +15,11 @@ define void @t1() { define void @t2() { ; CHECKV6: t2: -; CHECKV6: bx r0 @ TAILCALL +; CHECKV6: bx r0 ; CHECKT2D: t2: ; CHECKT2D: ldr ; CHECKT2D-NEXT: ldr -; CHECKT2D-NEXT: bx r0 @ TAILCALL +; CHECKT2D-NEXT: bx r0 %tmp = load i32 ()** @t ; <i32 ()*> [#uses=1] %tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0] ret void @@ -27,11 +27,11 @@ define void @t2() { define void @t3() { ; CHECKV6: t3: -; CHECKV6: b _t2 @ TAILCALL +; CHECKV6: b _t2 ; CHECKELF: t3: -; CHECKELF: b t2(PLT) @ TAILCALL +; CHECKELF: b t2(PLT) ; CHECKT2D: t3: -; CHECKT2D: b.w _t2 @ TAILCALL +; CHECKT2D: b.w _t2 tail call void @t2( ) ; <i32> [#uses=0] ret void @@ -41,9 +41,9 @@ define void @t3() { define double @t4(double %a) nounwind readonly ssp { entry: ; CHECKV6: t4: -; CHECKV6: b _sin @ TAILCALL +; CHECKV6: b _sin ; CHECKELF: t4: -; CHECKELF: b sin(PLT) @ TAILCALL +; CHECKELF: b sin(PLT) %0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1] ret double %0 } @@ -51,9 +51,9 @@ entry: define float @t5(float %a) nounwind readonly ssp { entry: ; CHECKV6: t5: -; CHECKV6: b _sinf @ TAILCALL +; CHECKV6: b _sinf ; CHECKELF: t5: -; CHECKELF: b sinf(PLT) @ TAILCALL +; CHECKELF: b sinf(PLT) %0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1] ret float %0 } @@ -65,9 +65,9 @@ declare double @sin(double) nounwind readonly define i32 @t6(i32 %a, i32 %b) nounwind readnone { entry: ; CHECKV6: t6: -; CHECKV6: b ___divsi3 @ TAILCALL +; CHECKV6: b ___divsi3 ; CHECKELF: t6: -; CHECKELF: b __aeabi_idiv(PLT) @ TAILCALL +; CHECKELF: b __aeabi_idiv(PLT) %0 = sdiv i32 %a, %b ret i32 %0 } diff --git a/test/CodeGen/ARM/call.ll b/test/CodeGen/ARM/call.ll index c020b6f..0f9543f 100644 --- a/test/CodeGen/ARM/call.ll +++ b/test/CodeGen/ARM/call.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm | FileCheck %s -check-prefix=CHECKV4 +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s -check-prefix=CHECKV4 ; RUN: llc < %s -march=arm -mattr=+v5t | FileCheck %s -check-prefix=CHECKV5 -; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi\ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi\ ; RUN: -relocation-model=pic | FileCheck %s -check-prefix=CHECKELF @t = weak global i32 ()* null ; <i32 ()**> [#uses=1] diff --git a/test/CodeGen/ARM/constants.ll b/test/CodeGen/ARM/constants.ll index 7b6c9d4..f4c1b5a 100644 --- a/test/CodeGen/ARM/constants.ll +++ b/test/CodeGen/ARM/constants.ll @@ -14,31 +14,31 @@ define i32 @f2() { define i32 @f3() { ; CHECK: f3 -; CHECK: mov r0, #1, #24 +; CHECK: mov r0, #256 ret i32 256 } define i32 @f4() { ; CHECK: f4 -; CHECK: orr{{.*}}#1, #24 +; CHECK: orr{{.*}}#256 ret i32 257 } define i32 @f5() { ; CHECK: f5 -; CHECK: mov r0, #255, #2 +; CHECK: mov r0, #-1073741761 ret i32 -1073741761 } define i32 @f6() { ; CHECK: f6 -; CHECK: mov r0, #63, #28 +; CHECK: mov r0, #1008 ret i32 1008 } define void @f7(i32 %a) { ; CHECK: f7 -; CHECK: cmp r0, #1, #16 +; CHECK: cmp r0, #65536 %b = icmp ugt i32 %a, 65536 br i1 %b, label %r, label %r r: diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index 499c97f..eb0c5c8 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -43,7 +43,7 @@ b1: br label %b2 ; THUMB: add.w {{.*}} #4096 -; ARM: add {{.*}} #1, #20 +; ARM: add {{.*}} #4096 b2: %b = add i32 %tmp, 4095 diff --git a/test/CodeGen/ARM/fold-const.ll b/test/CodeGen/ARM/fold-const.ll new file mode 100644 index 0000000..227e4e8 --- /dev/null +++ b/test/CodeGen/ARM/fold-const.ll @@ -0,0 +1,14 @@ +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s + +define i32 @f(i32 %a) nounwind readnone optsize ssp { +entry: + %conv = zext i32 %a to i64 + %tmp1 = tail call i64 @llvm.ctlz.i64(i64 %conv) +; CHECK: clz +; CHECK-NOT: adds + %cast = trunc i64 %tmp1 to i32 + %sub = sub nsw i32 63, %cast + ret i32 %sub +} + +declare i64 @llvm.ctlz.i64(i64) nounwind readnone diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll index 8ef45f2..ac023d1 100644 --- a/test/CodeGen/ARM/fp.ll +++ b/test/CodeGen/ARM/fp.ll @@ -42,7 +42,7 @@ entry: define double @h(double* %v) { ;CHECK: h: -;CHECK: vldr.64 +;CHECK: vldr.64 ;CHECK-NEXT: vmov entry: %tmp = load double* %v ; <double> [#uses=1] @@ -51,7 +51,7 @@ entry: define float @h2() { ;CHECK: h2: -;CHECK: mov r0, #254, #10 +;CHECK: mov r0, #1065353216 entry: ret float 1.000000e+00 } diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index ccb1428..5e7e3f2 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -1,7 +1,7 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic -; RUN: llc < %s -mtriple=arm-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC -; RUN: llc < %s -mtriple=arm-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=static | FileCheck %s -check-prefix=DarwinStatic +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=dynamic-no-pic | FileCheck %s -check-prefix=DarwinDynamic +; RUN: llc < %s -mtriple=armv6-apple-darwin -relocation-model=pic | FileCheck %s -check-prefix=DarwinPIC +; RUN: llc < %s -mtriple=armv6-linux-gnueabi -relocation-model=pic | FileCheck %s -check-prefix=LinuxPIC @G = external global i32 diff --git a/test/CodeGen/ARM/hello.ll b/test/CodeGen/ARM/hello.ll index bfed7a6..9f46ae0 100644 --- a/test/CodeGen/ARM/hello.ll +++ b/test/CodeGen/ARM/hello.ll @@ -1,8 +1,8 @@ ; RUN: llc < %s -march=arm -; RUN: llc < %s -mtriple=arm-linux-gnueabi | grep mov | count 1 -; RUN: llc < %s -mtriple=arm-linux-gnu --disable-fp-elim | \ +; RUN: llc < %s -mtriple=armv6-linux-gnueabi | grep mov | count 1 +; RUN: llc < %s -mtriple=armv6-linux-gnu --disable-fp-elim | \ ; RUN: grep mov | count 2 -; RUN: llc < %s -mtriple=arm-apple-darwin | grep mov | count 2 +; RUN: llc < %s -mtriple=armv6-apple-darwin | grep mov | count 2 @str = internal constant [12 x i8] c"Hello World\00" diff --git a/test/CodeGen/ARM/iabs.ll b/test/CodeGen/ARM/iabs.ll index 63808b2..c01c041 100644 --- a/test/CodeGen/ARM/iabs.ll +++ b/test/CodeGen/ARM/iabs.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s ;; Integer absolute value, should produce something as good as: ARM: ;; add r3, r0, r0, asr #31 diff --git a/test/CodeGen/ARM/ifcvt1.ll b/test/CodeGen/ARM/ifcvt1.ll index e6aa044..b073a05 100644 --- a/test/CodeGen/ARM/ifcvt1.ll +++ b/test/CodeGen/ARM/ifcvt1.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep bx | count 1 +; RUN: llc < %s -march=arm -mattr=+v4t +; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 1 define i32 @t1(i32 %a, i32 %b) { %tmp2 = icmp eq i32 %a, 0 diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll index 7b9d0cf..1bca10a 100644 --- a/test/CodeGen/ARM/ifcvt2.ll +++ b/test/CodeGen/ARM/ifcvt2.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | FileCheck %s +; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK: t1: diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll index f7ebac6..3e2c578 100644 --- a/test/CodeGen/ARM/ifcvt3.ll +++ b/test/CodeGen/ARM/ifcvt3.ll @@ -1,6 +1,6 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep cmpne | count 1 -; RUN: llc < %s -march=arm | grep bx | count 2 +; RUN: llc < %s -march=arm -mattr=+v4t +; RUN: llc < %s -march=arm -mattr=+v4t | grep cmpne | count 1 +; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { switch i32 %c, label %cond_next [ diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index f0ab9dd..25a0f93 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -relocation-model=pic -mtriple=arm-apple-darwin | FileCheck %s -check-prefix=ARM -; RUN: llc < %s -relocation-model=pic -mtriple=thumb-apple-darwin | FileCheck %s -check-prefix=THUMB +; RUN: llc < %s -relocation-model=pic -mtriple=armv6-apple-darwin | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -relocation-model=pic -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=THUMB ; RUN: llc < %s -relocation-model=static -mtriple=thumbv7-apple-darwin | FileCheck %s -check-prefix=THUMB2 @nextaddr = global i8* null ; <i8**> [#uses=2] diff --git a/test/CodeGen/ARM/ldr_frame.ll b/test/CodeGen/ARM/ldr_frame.ll index a3abdb6..f071b89 100644 --- a/test/CodeGen/ARM/ldr_frame.ll +++ b/test/CodeGen/ARM/ldr_frame.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm | not grep mov +; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov define i32 @f1() { %buf = alloca [32 x i32], align 4 diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll index e401dca..0f1c7be 100644 --- a/test/CodeGen/ARM/long.ll +++ b/test/CodeGen/ARM/long.ll @@ -14,14 +14,14 @@ entry: define i64 @f3() { ; CHECK: f3: -; CHECK: mvn r0, #2, #2 +; CHECK: mvn r0, #-2147483648 entry: ret i64 2147483647 } define i64 @f4() { ; CHECK: f4: -; CHECK: mov r0, #2, #2 +; CHECK: mov r0, #-2147483648 entry: ret i64 2147483648 } @@ -29,7 +29,7 @@ entry: define i64 @f5() { ; CHECK: f5: ; CHECK: mvn r0, #0 -; CHECK: mvn r1, #2, #2 +; CHECK: mvn r1, #-2147483648 entry: ret i64 9223372036854775807 } diff --git a/test/CodeGen/ARM/lsr-unfolded-offset.ll b/test/CodeGen/ARM/lsr-unfolded-offset.ll index e3e6eae..61b25bb 100644 --- a/test/CodeGen/ARM/lsr-unfolded-offset.ll +++ b/test/CodeGen/ARM/lsr-unfolded-offset.ll @@ -4,12 +4,13 @@ ; register pressure and therefore spilling. There is more room for improvement ; here. -; CHECK: sub sp, #{{32|24}} +; CHECK: sub sp, #{{32|28|24}} -; CHECK: ldr r{{.*}}, [sp, #4] -; CHECK-NEXT: ldr r{{.*}}, [sp, #16] -; CHECK-NEXT: ldr r{{.*}}, [sp, #12] -; CHECK-NEXT: adds +; CHECK: %for.inc +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: ldr{{(.w)?}} r{{.*}}, [sp, # +; CHECK: add target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-macosx10.7.0" diff --git a/test/CodeGen/ARM/phi.ll b/test/CodeGen/ARM/phi.ll index 29e17c0..dc1a95b 100644 --- a/test/CodeGen/ARM/phi.ll +++ b/test/CodeGen/ARM/phi.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=arm < %s | FileCheck %s +; RUN: llc -march=arm -mattr=+v4t < %s | FileCheck %s ; <rdar://problem/8686347> define i32 @test1(i1 %a, i32* %b) { @@ -20,4 +20,4 @@ end: %r = load i32* %gep ; CHECK-NEXT: bx lr ret i32 %r -}
\ No newline at end of file +} diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll index 250a34e..9c8ff2b 100644 --- a/test/CodeGen/ARM/prefetch.ll +++ b/test/CodeGen/ARM/prefetch.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=thumb -mattr=-thumb2 | not grep pld -; RUN: llc < %s -march=thumb -mattr=+v7a | FileCheck %s -check-prefix=THUMB2 -; RUN: llc < %s -march=arm -mattr=+v7a | FileCheck %s -check-prefix=ARM +; RUN: llc < %s -march=thumb -mattr=+v7 | FileCheck %s -check-prefix=THUMB2 +; RUN: llc < %s -march=arm -mattr=+v7 | FileCheck %s -check-prefix=ARM ; RUN: llc < %s -march=arm -mcpu=cortex-a9-mp | FileCheck %s -check-prefix=ARM-MP ; rdar://8601536 diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index d350937..3a19211 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -124,7 +124,7 @@ return1: return2: ; CHECK: %return2 ; CHECK: vadd.i32 -; CHECK: vmov {{q[0-9]+}}, {{q[0-9]+}} +; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}} ; CHECK-NOT: vmov ; CHECK: vst2.32 {d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}, d{{[0-9]+}}} %tmp100 = extractvalue %struct.__neon_int32x4x2_t %tmp2, 0 ; <<4 x i32>> [#uses=1] @@ -139,7 +139,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { ; CHECK: t5: ; CHECK: vldmia ; How can FileCheck match Q and D registers? We need a lisp interpreter. -; CHECK: vmov {{q[0-9]+}}, {{q[0-9]+}} +; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} ; CHECK-NOT: vmov ; CHECK: vld2.16 {d{{[0-9]+}}[1], d{{[0-9]+}}[1]}, [r0] ; CHECK-NOT: vmov @@ -156,7 +156,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ; CHECK: t6: ; CHECK: vldr.64 -; CHECK: vmov d[[D0:[0-9]+]], d[[D1:[0-9]+]] +; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]] ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] %tmp2 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) ; <%struct.__neon_int8x8x2_t> [#uses=2] @@ -172,7 +172,7 @@ entry: ; CHECK: vld2.32 ; CHECK: vst2.32 ; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, -; CHECK: vmov q[[Q0:[0-9]+]], q[[Q1:[0-9]+]] +; CHECK: vorr q[[Q0:[0-9]+]], q[[Q1:[0-9]+]], q[[Q1:[0-9]+]] ; CHECK-NOT: vmov ; CHECK: vuzp.32 q[[Q1]], q[[Q0]] ; CHECK: vst1.32 @@ -272,8 +272,8 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { define arm_aapcs_vfpcc i32 @t10() nounwind { entry: ; CHECK: t10: -; CHECK: vmul.f32 q8, q8, d0[0] ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3F000000 +; CHECK: vmul.f32 q8, q8, d0[0] ; CHECK: vadd.f32 q8, q8, q8 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1] %1 = insertelement <4 x float> %0, float undef, i32 1 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/section.ll b/test/CodeGen/ARM/section.ll index 7a566d4..2762056 100644 --- a/test/CodeGen/ARM/section.ll +++ b/test/CodeGen/ARM/section.ll @@ -1,7 +1,6 @@ -; RUN: llc < %s -mtriple=arm-linux | \ -; RUN: grep {__DTOR_END__:} -; RUN: llc < %s -mtriple=arm-linux | \ -; RUN: grep {\\.section.\\.dtors,"aw",.progbits} +; RUN: llc < %s -mtriple=arm-linux | FileCheck %s +; CHECK: .section .dtors,"aw",%progbits +; CHECK: __DTOR_END__: @__DTOR_END__ = internal global [1 x i32] zeroinitializer, section ".dtors" ; <[1 x i32]*> [#uses=0] diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 43f8a66..f43dde5 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -6,7 +6,7 @@ define i32 @t1(i32 %c) nounwind readnone { entry: ; ARM: t1: ; ARM: mov [[R1:r[0-9]+]], #101 -; ARM: orr [[R1b:r[0-9]+]], [[R1]], #1, #24 +; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256 ; ARM: movgt r0, #123 ; ARMT2: t1: @@ -27,7 +27,7 @@ entry: ; ARM: t2: ; ARM: mov r0, #123 ; ARM: movgt r0, #101 -; ARM: orrgt r0, r0, #1, #24 +; ARM: orrgt r0, r0, #256 ; ARMT2: t2: ; ARMT2: mov r0, #123 @@ -76,3 +76,39 @@ entry: %1 = select i1 %0, i32 4283826005, i32 %x ret i32 %1 } + +; rdar://9758317 +define i32 @t5(i32 %a) nounwind { +entry: +; ARM: t5: +; ARM-NOT: mov +; ARM: cmp r0, #1 +; ARM-NOT: mov +; ARM: movne r0, #0 + +; THUMB2: t5: +; THUMB2-NOT: mov +; THUMB2: cmp r0, #1 +; THUMB2: it ne +; THUMB2: movne r0, #0 + %cmp = icmp eq i32 %a, 1 + %conv = zext i1 %cmp to i32 + ret i32 %conv +} + +define i32 @t6(i32 %a) nounwind { +entry: +; ARM: t6: +; ARM-NOT: mov +; ARM: cmp r0, #0 +; ARM: movne r0, #1 + +; THUMB2: t6: +; THUMB2-NOT: mov +; THUMB2: cmp r0, #0 +; THUMB2: it ne +; THUMB2: movne r0, #1 + %tobool = icmp ne i32 %a, 0 + %lnot.ext = zext i1 %tobool to i32 + ret i32 %lnot.ext +} diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll index 4211797..8a3133a 100644 --- a/test/CodeGen/ARM/select_xform.ll +++ b/test/CodeGen/ARM/select_xform.ll @@ -4,7 +4,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { ; ARM: t1: -; ARM: sub r0, r1, #6, #2 +; ARM: sub r0, r1, #-2147483647 ; ARM: movgt r0, r1 ; T2: t1: diff --git a/test/CodeGen/ARM/sub.ll b/test/CodeGen/ARM/sub.ll index 555b18e..06ea703 100644 --- a/test/CodeGen/ARM/sub.ll +++ b/test/CodeGen/ARM/sub.ll @@ -12,7 +12,7 @@ define i64 @f1(i64 %a) { ; 66846720 = 0x03fc0000 define i64 @f2(i64 %a) { ; CHECK: f2 -; CHECK: subs r0, r0, #255, #14 +; CHECK: subs r0, r0, #66846720 ; CHECK: sbc r1, r1, #0 %tmp = sub i64 %a, 66846720 ret i64 %tmp diff --git a/test/CodeGen/ARM/truncstore-dag-combine.ll b/test/CodeGen/ARM/truncstore-dag-combine.ll index 2da08b6..5665440 100644 --- a/test/CodeGen/ARM/truncstore-dag-combine.ll +++ b/test/CodeGen/ARM/truncstore-dag-combine.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=arm | not grep orr -; RUN: llc < %s -march=arm | not grep mov +; RUN: llc < %s -march=arm -mattr=+v4t | not grep orr +; RUN: llc < %s -march=arm -mattr=+v4t | not grep mov define void @bar(i8* %P, i16* %Q) { entry: diff --git a/test/CodeGen/Blackfin/burg.ll b/test/CodeGen/Blackfin/burg.ll deleted file mode 100644 index 8cc3713..0000000 --- a/test/CodeGen/Blackfin/burg.ll +++ /dev/null @@ -1,19 +0,0 @@ -; RUN: llc < %s -march=bfin -verify-machineinstrs > %t - - %IntList = type %struct.intlist* - %ReadFn = type i32 ()* - %YYSTYPE = type { %IntList } - %struct.intlist = type { i32, %IntList } -@yyval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1] - -define i32 @yyparse() { -bb0: - %reg254 = load i16* null ; <i16> [#uses=1] - %reg254-idxcast = sext i16 %reg254 to i64 ; <i64> [#uses=1] - %reg254-idxcast-scale = mul i64 %reg254-idxcast, -1 ; <i64> [#uses=1] - %reg254-idxcast-scale-offset = add i64 %reg254-idxcast-scale, 1 ; <i64> [#uses=1] - %reg261.idx1 = getelementptr %YYSTYPE* null, i64 %reg254-idxcast-scale-offset, i32 0 ; <%IntList*> [#uses=1] - %reg261 = load %IntList* %reg261.idx1 ; <%IntList> [#uses=1] - store %IntList %reg261, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - unreachable -} diff --git a/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll b/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll deleted file mode 100644 index 3b2085c..0000000 --- a/test/CodeGen/CBackend/2002-08-20-RecursiveTypes.ll +++ /dev/null @@ -1,3 +0,0 @@ -; RUN: llc < %s -march=c - -@MyIntList = external global { \2*, i32 } diff --git a/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll b/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll deleted file mode 100644 index 2563d8c..0000000 --- a/test/CodeGen/CBackend/2002-10-15-OpaqueTypeProblem.ll +++ /dev/null @@ -1,6 +0,0 @@ -; RUN: llc < %s -march=c - -%MPI_Comm = type %struct.Comm* -%struct.Comm = type opaque -@thing = global %MPI_Comm* null ; <%MPI_Comm**> [#uses=0] - diff --git a/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll b/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll deleted file mode 100644 index 54e0aa6..0000000 --- a/test/CodeGen/CBackend/2002-10-30-FunctionPointerAlloca.ll +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: llc < %s -march=c - - %BitField = type i32 - %tokenptr = type i32* - -define void @test() { - %pmf1 = alloca %tokenptr (%tokenptr, i8*)* ; <%tokenptr (%tokenptr, i8*)**> [#uses=0] - ret void -} - diff --git a/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll b/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll deleted file mode 100644 index 1c5f506..0000000 --- a/test/CodeGen/CBackend/2005-03-08-RecursiveTypeCrash.ll +++ /dev/null @@ -1,5 +0,0 @@ -; RUN: llc < %s -march=c - - %JNIEnv = type %struct.JNINa* - %struct.JNINa = type { i8*, i8*, i8*, void (%JNIEnv*)* } - diff --git a/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll b/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll deleted file mode 100644 index 8a5f253..0000000 --- a/test/CodeGen/CBackend/2007-01-15-NamedArrayType.ll +++ /dev/null @@ -1,11 +0,0 @@ -; PR918 -; RUN: llc < %s -march=c | not grep {l_structtype_s l_fixarray_array3} - -%structtype_s = type { i32 } -%fixarray_array3 = type [3 x %structtype_s] - -define i32 @witness(%fixarray_array3* %p) { - %q = getelementptr %fixarray_array3* %p, i32 0, i32 0, i32 0 - %v = load i32* %q - ret i32 %v -} diff --git a/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll b/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll new file mode 100644 index 0000000..cd446d5 --- /dev/null +++ b/test/CodeGen/Generic/2011-07-07-ScheduleDAGCrash.ll @@ -0,0 +1,16 @@ +; RUN: llc < %s +; This caused ScheduleDAG to crash in EmitPhysRegCopy when searching +; the uses of a copy to a physical register without ignoring non-data +; dependence, PR10220. + +define void @f(i256* nocapture %a, i256* nocapture %b, i256* nocapture %cc, i256* nocapture %dd) nounwind uwtable noinline ssp { +entry: + %c = load i256* %cc + %d = load i256* %dd + %add = add nsw i256 %c, %d + store i256 %add, i256* %a, align 8 + %or = or i256 %c, 1606938044258990275541962092341162602522202993782792835301376 + %add6 = add nsw i256 %or, %d + store i256 %add6, i256* %b, align 8 + ret void +} diff --git a/test/CodeGen/Generic/BurgBadRegAlloc.ll b/test/CodeGen/Generic/BurgBadRegAlloc.ll deleted file mode 100644 index 99d856a..0000000 --- a/test/CodeGen/Generic/BurgBadRegAlloc.ll +++ /dev/null @@ -1,829 +0,0 @@ -; RUN: llc < %s - -;; Register allocation is doing a very poor job on this routine from yyparse -;; in Burg: -;; -- at least two long-lived values are being allocated to %o? registers -;; -- even worse, those registers are being saved and restored repeatedly -;; at function calls, even though there are no intervening uses. -;; -- outgoing args of some function calls have to be swapped, causing -;; another write/read from stack to do the exchange (use -dregalloc=y). -;; -%Arity = type %struct.arity* - %Binding = type %struct.binding* - %DeltaCost = type [4 x i16] - %Dimension = type %struct.dimension* - %Index_Map = type { i32, %Item_Set* } - %IntList = type %struct.intlist* - %Item = type { %DeltaCost, %Rule } - %ItemArray = type %Item* - %Item_Set = type %struct.item_set* - %List = type %struct.list* - %Mapping = type %struct.mapping* - %NonTerminal = type %struct.nonterminal* - %Operator = type %struct.operator* - %Pattern = type %struct.pattern* - %PatternAST = type %struct.patternAST* - %Plank = type %struct.plank* - %PlankMap = type %struct.plankMap* - %ReadFn = type i32 ()* - %Rule = type %struct.rule* - %RuleAST = type %struct.ruleAST* - %StateMap = type %struct.stateMap* - %StrTableElement = type %struct.strTableElement* - %Symbol = type %struct.symbol* - %Table = type %struct.table* - %YYSTYPE = type { %IntList } - %struct.arity = type { i32, %List } - %struct.binding = type { i8*, i32 } - %struct.dimension = type { i16*, %Index_Map, %Mapping, i32, %PlankMap } - %struct.index_map = type { i32, %Item_Set* } - %struct.intlist = type { i32, %IntList } - %struct.item = type { %DeltaCost, %Rule } - %struct.item_set = type { i32, i32, %Operator, [2 x %Item_Set], %Item_Set, i16*, %ItemArray, %ItemArray } - %struct.list = type { i8*, %List } - %struct.mapping = type { %List*, i32, i32, i32, %Item_Set* } - %struct.nonterminal = type { i8*, i32, i32, i32, %PlankMap, %Rule } - %struct.operator = type { i8*, i32, i32, i32, i32, i32, %Table } - %struct.pattern = type { %NonTerminal, %Operator, [2 x %NonTerminal] } - %struct.patternAST = type { %Symbol, i8*, %List } - %struct.plank = type { i8*, %List, i32 } - %struct.plankMap = type { %List, i32, %StateMap } - %struct.rule = type { %DeltaCost, i32, i32, i32, %NonTerminal, %Pattern, i32 } - %struct.ruleAST = type { i8*, %PatternAST, i32, %IntList, %Rule, %StrTableElement, %StrTableElement } - %struct.stateMap = type { i8*, %Plank, i32, i16* } - %struct.strTableElement = type { i8*, %IntList, i8* } - %struct.symbol = type { i8*, i32, { %Operator } } - %struct.table = type { %Operator, %List, i16*, [2 x %Dimension], %Item_Set* } -@yylval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1] -@yylhs = external global [25 x i16] ; <[25 x i16]*> [#uses=1] -@yylen = external global [25 x i16] ; <[25 x i16]*> [#uses=1] -@yydefred = external global [43 x i16] ; <[43 x i16]*> [#uses=1] -@yydgoto = external global [12 x i16] ; <[12 x i16]*> [#uses=1] -@yysindex = external global [43 x i16] ; <[43 x i16]*> [#uses=2] -@yyrindex = external global [43 x i16] ; <[43 x i16]*> [#uses=1] -@yygindex = external global [12 x i16] ; <[12 x i16]*> [#uses=1] -@yytable = external global [263 x i16] ; <[263 x i16]*> [#uses=4] -@yycheck = external global [263 x i16] ; <[263 x i16]*> [#uses=4] -@yynerrs = external global i32 ; <i32*> [#uses=3] -@yyerrflag = external global i32 ; <i32*> [#uses=6] -@yychar = external global i32 ; <i32*> [#uses=15] -@yyssp = external global i16* ; <i16**> [#uses=15] -@yyvsp = external global %YYSTYPE* ; <%YYSTYPE**> [#uses=30] -@yyval = external global %YYSTYPE ; <%YYSTYPE*> [#uses=1] -@yyss = external global i16* ; <i16**> [#uses=3] -@yysslim = external global i16* ; <i16**> [#uses=3] -@yyvs = external global %YYSTYPE* ; <%YYSTYPE**> [#uses=1] -@.LC01 = external global [13 x i8] ; <[13 x i8]*> [#uses=1] -@.LC1 = external global [20 x i8] ; <[20 x i8]*> [#uses=1] - -define i32 @yyparse() { -bb0: - store i32 0, i32* @yynerrs - store i32 0, i32* @yyerrflag - store i32 -1, i32* @yychar - %reg113 = load i16** @yyss ; <i16*> [#uses=1] - %cond581 = icmp ne i16* %reg113, null ; <i1> [#uses=1] - br i1 %cond581, label %bb3, label %bb2 - -bb2: ; preds = %bb0 - %reg584 = call i32 @yygrowstack( ) ; <i32> [#uses=1] - %cond584 = icmp ne i32 %reg584, 0 ; <i1> [#uses=1] - br i1 %cond584, label %bb113, label %bb3 - -bb3: ; preds = %bb2, %bb0 - %reg115 = load i16** @yyss ; <i16*> [#uses=1] - store i16* %reg115, i16** @yyssp - %reg116 = load %YYSTYPE** @yyvs ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg116, %YYSTYPE** @yyvsp - %reg117 = load i16** @yyssp ; <i16*> [#uses=1] - store i16 0, i16* %reg117 - br label %bb4 - -bb4: ; preds = %bb112, %bb102, %bb35, %bb31, %bb15, %bb14, %bb3 - %reg458 = phi i32 [ %reg476, %bb112 ], [ 1, %bb102 ], [ %reg458, %bb35 ], [ %cast768, %bb31 ], [ %cast658, %bb15 ], [ %cast658, %bb14 ], [ 0, %bb3 ] ; <i32> [#uses=2] - %reg458-idxcast = zext i32 %reg458 to i64 ; <i64> [#uses=3] - %reg594 = getelementptr [43 x i16]* @yydefred, i64 0, i64 %reg458-idxcast ; <i16*> [#uses=1] - %reg125 = load i16* %reg594 ; <i16> [#uses=1] - %cast599 = sext i16 %reg125 to i32 ; <i32> [#uses=2] - %cond600 = icmp ne i32 %cast599, 0 ; <i1> [#uses=1] - br i1 %cond600, label %bb36, label %bb5 - -bb5: ; preds = %bb4 - %reg127 = load i32* @yychar ; <i32> [#uses=1] - %cond603 = icmp sge i32 %reg127, 0 ; <i1> [#uses=1] - br i1 %cond603, label %bb8, label %bb6 - -bb6: ; preds = %bb5 - %reg607 = call i32 @yylex( ) ; <i32> [#uses=1] - store i32 %reg607, i32* @yychar - %reg129 = load i32* @yychar ; <i32> [#uses=1] - %cond609 = icmp sge i32 %reg129, 0 ; <i1> [#uses=1] - br i1 %cond609, label %bb8, label %bb7 - -bb7: ; preds = %bb6 - store i32 0, i32* @yychar - br label %bb8 - -bb8: ; preds = %bb7, %bb6, %bb5 - %reg615 = getelementptr [43 x i16]* @yysindex, i64 0, i64 %reg458-idxcast ; <i16*> [#uses=1] - %reg137 = load i16* %reg615 ; <i16> [#uses=1] - %cast620 = sext i16 %reg137 to i32 ; <i32> [#uses=2] - %cond621 = icmp eq i32 %cast620, 0 ; <i1> [#uses=1] - br i1 %cond621, label %bb16, label %bb9 - -bb9: ; preds = %bb8 - %reg139 = load i32* @yychar ; <i32> [#uses=2] - %reg460 = add i32 %cast620, %reg139 ; <i32> [#uses=3] - %cond624 = icmp slt i32 %reg460, 0 ; <i1> [#uses=1] - br i1 %cond624, label %bb16, label %bb10 - -bb10: ; preds = %bb9 - %cond627 = icmp sgt i32 %reg460, 262 ; <i1> [#uses=1] - br i1 %cond627, label %bb16, label %bb11 - -bb11: ; preds = %bb10 - %reg460-idxcast = sext i32 %reg460 to i64 ; <i64> [#uses=2] - %reg632 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg460-idxcast ; <i16*> [#uses=1] - %reg148 = load i16* %reg632 ; <i16> [#uses=1] - %cast637 = sext i16 %reg148 to i32 ; <i32> [#uses=1] - %cond639 = icmp ne i32 %cast637, %reg139 ; <i1> [#uses=1] - br i1 %cond639, label %bb16, label %bb12 - -bb12: ; preds = %bb11 - %reg150 = load i16** @yyssp ; <i16*> [#uses=1] - %cast640 = bitcast i16* %reg150 to i8* ; <i8*> [#uses=1] - %reg151 = load i16** @yysslim ; <i16*> [#uses=1] - %cast641 = bitcast i16* %reg151 to i8* ; <i8*> [#uses=1] - %cond642 = icmp ult i8* %cast640, %cast641 ; <i1> [#uses=1] - br i1 %cond642, label %bb14, label %bb13 - -bb13: ; preds = %bb12 - %reg644 = call i32 @yygrowstack( ) ; <i32> [#uses=1] - %cond644 = icmp ne i32 %reg644, 0 ; <i1> [#uses=1] - br i1 %cond644, label %bb113, label %bb14 - -bb14: ; preds = %bb13, %bb12 - %reg153 = load i16** @yyssp ; <i16*> [#uses=1] - %reg647 = getelementptr i16* %reg153, i64 1 ; <i16*> [#uses=2] - store i16* %reg647, i16** @yyssp - %reg653 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg460-idxcast ; <i16*> [#uses=1] - %reg162 = load i16* %reg653 ; <i16> [#uses=2] - %cast658 = sext i16 %reg162 to i32 ; <i32> [#uses=2] - store i16 %reg162, i16* %reg647 - %reg164 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg661 = getelementptr %YYSTYPE* %reg164, i64 1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg661, %YYSTYPE** @yyvsp - %reg167 = load %IntList* getelementptr (%YYSTYPE* @yylval, i64 0, i32 0) ; <%IntList> [#uses=1] - %reg661.idx1 = getelementptr %YYSTYPE* %reg164, i64 1, i32 0 ; <%IntList*> [#uses=1] - store %IntList %reg167, %IntList* %reg661.idx1 - store i32 -1, i32* @yychar - %reg169 = load i32* @yyerrflag ; <i32> [#uses=2] - %cond669 = icmp sle i32 %reg169, 0 ; <i1> [#uses=1] - br i1 %cond669, label %bb4, label %bb15 - -bb15: ; preds = %bb14 - %reg171 = add i32 %reg169, -1 ; <i32> [#uses=1] - store i32 %reg171, i32* @yyerrflag - br label %bb4 - -bb16: ; preds = %bb11, %bb10, %bb9, %bb8 - %reg677 = getelementptr [43 x i16]* @yyrindex, i64 0, i64 %reg458-idxcast ; <i16*> [#uses=1] - %reg178 = load i16* %reg677 ; <i16> [#uses=1] - %cast682 = sext i16 %reg178 to i32 ; <i32> [#uses=2] - %cond683 = icmp eq i32 %cast682, 0 ; <i1> [#uses=1] - br i1 %cond683, label %bb21, label %bb17 - -bb17: ; preds = %bb16 - %reg180 = load i32* @yychar ; <i32> [#uses=2] - %reg463 = add i32 %cast682, %reg180 ; <i32> [#uses=3] - %cond686 = icmp slt i32 %reg463, 0 ; <i1> [#uses=1] - br i1 %cond686, label %bb21, label %bb18 - -bb18: ; preds = %bb17 - %cond689 = icmp sgt i32 %reg463, 262 ; <i1> [#uses=1] - br i1 %cond689, label %bb21, label %bb19 - -bb19: ; preds = %bb18 - %reg463-idxcast = sext i32 %reg463 to i64 ; <i64> [#uses=2] - %reg694 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg463-idxcast ; <i16*> [#uses=1] - %reg189 = load i16* %reg694 ; <i16> [#uses=1] - %cast699 = sext i16 %reg189 to i32 ; <i32> [#uses=1] - %cond701 = icmp ne i32 %cast699, %reg180 ; <i1> [#uses=1] - br i1 %cond701, label %bb21, label %bb20 - -bb20: ; preds = %bb19 - %reg704 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg463-idxcast ; <i16*> [#uses=1] - %reg197 = load i16* %reg704 ; <i16> [#uses=1] - %cast709 = sext i16 %reg197 to i32 ; <i32> [#uses=1] - br label %bb36 - -bb21: ; preds = %bb19, %bb18, %bb17, %bb16 - %reg198 = load i32* @yyerrflag ; <i32> [#uses=1] - %cond711 = icmp ne i32 %reg198, 0 ; <i1> [#uses=1] - br i1 %cond711, label %bb23, label %bb22 - -bb22: ; preds = %bb21 - call void @yyerror( i8* getelementptr ([13 x i8]* @.LC01, i64 0, i64 0) ) - %reg200 = load i32* @yynerrs ; <i32> [#uses=1] - %reg201 = add i32 %reg200, 1 ; <i32> [#uses=1] - store i32 %reg201, i32* @yynerrs - br label %bb23 - -bb23: ; preds = %bb22, %bb21 - %reg202 = load i32* @yyerrflag ; <i32> [#uses=1] - %cond719 = icmp sgt i32 %reg202, 2 ; <i1> [#uses=1] - br i1 %cond719, label %bb34, label %bb24 - -bb24: ; preds = %bb23 - store i32 3, i32* @yyerrflag - %reg241 = load i16** @yyss ; <i16*> [#uses=1] - %cast778 = bitcast i16* %reg241 to i8* ; <i8*> [#uses=1] - br label %bb25 - -bb25: ; preds = %bb33, %bb24 - %reg204 = load i16** @yyssp ; <i16*> [#uses=4] - %reg206 = load i16* %reg204 ; <i16> [#uses=1] - %reg206-idxcast = sext i16 %reg206 to i64 ; <i64> [#uses=1] - %reg727 = getelementptr [43 x i16]* @yysindex, i64 0, i64 %reg206-idxcast ; <i16*> [#uses=1] - %reg212 = load i16* %reg727 ; <i16> [#uses=2] - %cast732 = sext i16 %reg212 to i32 ; <i32> [#uses=2] - %cond733 = icmp eq i32 %cast732, 0 ; <i1> [#uses=1] - br i1 %cond733, label %bb32, label %bb26 - -bb26: ; preds = %bb25 - %reg466 = add i32 %cast732, 256 ; <i32> [#uses=2] - %cond736 = icmp slt i32 %reg466, 0 ; <i1> [#uses=1] - br i1 %cond736, label %bb32, label %bb27 - -bb27: ; preds = %bb26 - %cond739 = icmp sgt i32 %reg466, 262 ; <i1> [#uses=1] - br i1 %cond739, label %bb32, label %bb28 - -bb28: ; preds = %bb27 - %reg212-idxcast = sext i16 %reg212 to i64 ; <i64> [#uses=1] - %reg212-idxcast-offset = add i64 %reg212-idxcast, 256 ; <i64> [#uses=2] - %reg744 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg212-idxcast-offset ; <i16*> [#uses=1] - %reg221 = load i16* %reg744 ; <i16> [#uses=1] - %cond748 = icmp ne i16 %reg221, 256 ; <i1> [#uses=1] - br i1 %cond748, label %bb32, label %bb29 - -bb29: ; preds = %bb28 - %cast750 = bitcast i16* %reg204 to i8* ; <i8*> [#uses=1] - %reg223 = load i16** @yysslim ; <i16*> [#uses=1] - %cast751 = bitcast i16* %reg223 to i8* ; <i8*> [#uses=1] - %cond752 = icmp ult i8* %cast750, %cast751 ; <i1> [#uses=1] - br i1 %cond752, label %bb31, label %bb30 - -bb30: ; preds = %bb29 - %reg754 = call i32 @yygrowstack( ) ; <i32> [#uses=1] - %cond754 = icmp ne i32 %reg754, 0 ; <i1> [#uses=1] - br i1 %cond754, label %bb113, label %bb31 - -bb31: ; preds = %bb30, %bb29 - %reg225 = load i16** @yyssp ; <i16*> [#uses=1] - %reg757 = getelementptr i16* %reg225, i64 1 ; <i16*> [#uses=2] - store i16* %reg757, i16** @yyssp - %reg763 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg212-idxcast-offset ; <i16*> [#uses=1] - %reg234 = load i16* %reg763 ; <i16> [#uses=2] - %cast768 = sext i16 %reg234 to i32 ; <i32> [#uses=1] - store i16 %reg234, i16* %reg757 - %reg236 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg771 = getelementptr %YYSTYPE* %reg236, i64 1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg771, %YYSTYPE** @yyvsp - %reg239 = load %IntList* getelementptr (%YYSTYPE* @yylval, i64 0, i32 0) ; <%IntList> [#uses=1] - %reg771.idx1 = getelementptr %YYSTYPE* %reg236, i64 1, i32 0 ; <%IntList*> [#uses=1] - store %IntList %reg239, %IntList* %reg771.idx1 - br label %bb4 - -bb32: ; preds = %bb28, %bb27, %bb26, %bb25 - %cast777 = bitcast i16* %reg204 to i8* ; <i8*> [#uses=1] - %cond779 = icmp ule i8* %cast777, %cast778 ; <i1> [#uses=1] - br i1 %cond779, label %UnifiedExitNode, label %bb33 - -bb33: ; preds = %bb32 - %reg781 = getelementptr i16* %reg204, i64 -1 ; <i16*> [#uses=1] - store i16* %reg781, i16** @yyssp - %reg244 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %reg786 = getelementptr %YYSTYPE* %reg244, i64 -1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg786, %YYSTYPE** @yyvsp - br label %bb25 - -bb34: ; preds = %bb23 - %reg246 = load i32* @yychar ; <i32> [#uses=1] - %cond791 = icmp eq i32 %reg246, 0 ; <i1> [#uses=1] - br i1 %cond791, label %UnifiedExitNode, label %bb35 - -bb35: ; preds = %bb34 - store i32 -1, i32* @yychar - br label %bb4 - -bb36: ; preds = %bb20, %bb4 - %reg468 = phi i32 [ %cast709, %bb20 ], [ %cast599, %bb4 ] ; <i32> [#uses=31] - %reg468-idxcast = sext i32 %reg468 to i64 ; <i64> [#uses=2] - %reg796 = getelementptr [25 x i16]* @yylen, i64 0, i64 %reg468-idxcast ; <i16*> [#uses=1] - %reg254 = load i16* %reg796 ; <i16> [#uses=2] - %reg259 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %reg254-idxcast = sext i16 %reg254 to i64 ; <i64> [#uses=1] - %reg254-idxcast-scale = mul i64 %reg254-idxcast, -1 ; <i64> [#uses=1] - %reg254-idxcast-scale-offset = add i64 %reg254-idxcast-scale, 1 ; <i64> [#uses=1] - %reg261.idx1 = getelementptr %YYSTYPE* %reg259, i64 %reg254-idxcast-scale-offset, i32 0 ; <%IntList*> [#uses=1] - %reg261 = load %IntList* %reg261.idx1 ; <%IntList> [#uses=1] - store %IntList %reg261, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - %cond812 = icmp eq i32 %reg468, 13 ; <i1> [#uses=1] - br i1 %cond812, label %bb85, label %bb37 - -bb37: ; preds = %bb36 - %cond814 = icmp sgt i32 %reg468, 13 ; <i1> [#uses=1] - br i1 %cond814, label %bb56, label %bb38 - -bb38: ; preds = %bb37 - %cond817 = icmp eq i32 %reg468, 7 ; <i1> [#uses=1] - br i1 %cond817, label %bb79, label %bb39 - -bb39: ; preds = %bb38 - %cond819 = icmp sgt i32 %reg468, 7 ; <i1> [#uses=1] - br i1 %cond819, label %bb48, label %bb40 - -bb40: ; preds = %bb39 - %cond822 = icmp eq i32 %reg468, 4 ; <i1> [#uses=1] - br i1 %cond822, label %bb76, label %bb41 - -bb41: ; preds = %bb40 - %cond824 = icmp sgt i32 %reg468, 4 ; <i1> [#uses=1] - br i1 %cond824, label %bb45, label %bb42 - -bb42: ; preds = %bb41 - %cond827 = icmp eq i32 %reg468, 2 ; <i1> [#uses=1] - br i1 %cond827, label %bb74, label %bb43 - -bb43: ; preds = %bb42 - %cond829 = icmp eq i32 %reg468, 3 ; <i1> [#uses=1] - br i1 %cond829, label %bb75, label %bb97 - -bb45: ; preds = %bb41 - %cond831 = icmp eq i32 %reg468, 5 ; <i1> [#uses=1] - br i1 %cond831, label %bb77, label %bb46 - -bb46: ; preds = %bb45 - %cond833 = icmp eq i32 %reg468, 6 ; <i1> [#uses=1] - br i1 %cond833, label %bb78, label %bb97 - -bb48: ; preds = %bb39 - %cond835 = icmp eq i32 %reg468, 10 ; <i1> [#uses=1] - br i1 %cond835, label %bb82, label %bb49 - -bb49: ; preds = %bb48 - %cond837 = icmp sgt i32 %reg468, 10 ; <i1> [#uses=1] - br i1 %cond837, label %bb53, label %bb50 - -bb50: ; preds = %bb49 - %cond840 = icmp eq i32 %reg468, 8 ; <i1> [#uses=1] - br i1 %cond840, label %bb80, label %bb51 - -bb51: ; preds = %bb50 - %cond842 = icmp eq i32 %reg468, 9 ; <i1> [#uses=1] - br i1 %cond842, label %bb81, label %bb97 - -bb53: ; preds = %bb49 - %cond844 = icmp eq i32 %reg468, 11 ; <i1> [#uses=1] - br i1 %cond844, label %bb83, label %bb54 - -bb54: ; preds = %bb53 - %cond846 = icmp eq i32 %reg468, 12 ; <i1> [#uses=1] - br i1 %cond846, label %bb84, label %bb97 - -bb56: ; preds = %bb37 - %cond848 = icmp eq i32 %reg468, 19 ; <i1> [#uses=1] - br i1 %cond848, label %bb91, label %bb57 - -bb57: ; preds = %bb56 - %cond850 = icmp sgt i32 %reg468, 19 ; <i1> [#uses=1] - br i1 %cond850, label %bb66, label %bb58 - -bb58: ; preds = %bb57 - %cond853 = icmp eq i32 %reg468, 16 ; <i1> [#uses=1] - br i1 %cond853, label %bb88, label %bb59 - -bb59: ; preds = %bb58 - %cond855 = icmp sgt i32 %reg468, 16 ; <i1> [#uses=1] - br i1 %cond855, label %bb63, label %bb60 - -bb60: ; preds = %bb59 - %cond858 = icmp eq i32 %reg468, 14 ; <i1> [#uses=1] - br i1 %cond858, label %bb86, label %bb61 - -bb61: ; preds = %bb60 - %cond860 = icmp eq i32 %reg468, 15 ; <i1> [#uses=1] - br i1 %cond860, label %bb87, label %bb97 - -bb63: ; preds = %bb59 - %cond862 = icmp eq i32 %reg468, 17 ; <i1> [#uses=1] - br i1 %cond862, label %bb89, label %bb64 - -bb64: ; preds = %bb63 - %cond864 = icmp eq i32 %reg468, 18 ; <i1> [#uses=1] - br i1 %cond864, label %bb90, label %bb97 - -bb66: ; preds = %bb57 - %cond866 = icmp eq i32 %reg468, 22 ; <i1> [#uses=1] - br i1 %cond866, label %bb94, label %bb67 - -bb67: ; preds = %bb66 - %cond868 = icmp sgt i32 %reg468, 22 ; <i1> [#uses=1] - br i1 %cond868, label %bb71, label %bb68 - -bb68: ; preds = %bb67 - %cond871 = icmp eq i32 %reg468, 20 ; <i1> [#uses=1] - br i1 %cond871, label %bb92, label %bb69 - -bb69: ; preds = %bb68 - %cond873 = icmp eq i32 %reg468, 21 ; <i1> [#uses=1] - br i1 %cond873, label %bb93, label %bb97 - -bb71: ; preds = %bb67 - %cond875 = icmp eq i32 %reg468, 23 ; <i1> [#uses=1] - br i1 %cond875, label %bb95, label %bb72 - -bb72: ; preds = %bb71 - %cond877 = icmp eq i32 %reg468, 24 ; <i1> [#uses=1] - br i1 %cond877, label %bb96, label %bb97 - -bb74: ; preds = %bb42 - call void @yyfinished( ) - br label %bb97 - -bb75: ; preds = %bb43 - %reg262 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg264.idx1 = getelementptr %YYSTYPE* %reg262, i64 -2, i32 0 ; <%IntList*> [#uses=1] - %reg264 = load %IntList* %reg264.idx1 ; <%IntList> [#uses=1] - %reg265.idx = getelementptr %YYSTYPE* %reg262, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg265 = load %IntList* %reg265.idx ; <%IntList> [#uses=1] - %cast889 = bitcast %IntList %reg265 to %List ; <%List> [#uses=1] - %cast890 = bitcast %IntList %reg264 to %List ; <%List> [#uses=1] - call void @doSpec( %List %cast890, %List %cast889 ) - br label %bb97 - -bb76: ; preds = %bb40 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb77: ; preds = %bb45 - %reg269 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast894 = getelementptr %YYSTYPE* %reg269, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg271 = load %IntList* %cast894 ; <%IntList> [#uses=1] - %reg271.upgrd.1 = bitcast %IntList %reg271 to i8* ; <i8*> [#uses=1] - %reg272.idx1 = getelementptr %YYSTYPE* %reg269, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg272 = load %IntList* %reg272.idx1 ; <%IntList> [#uses=1] - %cast901 = bitcast %IntList %reg272 to %List ; <%List> [#uses=1] - %reg901 = call %List @newList( i8* %reg271.upgrd.1, %List %cast901 ) ; <%List> [#uses=1] - bitcast %List %reg901 to %IntList ; <%IntList>:0 [#uses=1] - store %IntList %0, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb78: ; preds = %bb46 - %reg275 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %reg277.idx = getelementptr %YYSTYPE* %reg275, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg277 = load %IntList* %reg277.idx ; <%IntList> [#uses=1] - %cast907 = bitcast %IntList %reg277 to %List ; <%List> [#uses=1] - %reg907 = call %Arity @newArity( i32 -1, %List %cast907 ) ; <%Arity> [#uses=1] - bitcast %Arity %reg907 to %IntList ; <%IntList>:1 [#uses=1] - store %IntList %1, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb79: ; preds = %bb38 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - %reg281 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %cast912 = getelementptr %YYSTYPE* %reg281, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg282 = load %IntList* %cast912 ; <%IntList> [#uses=1] - %reg282.upgrd.2 = bitcast %IntList %reg282 to %List ; <%List> [#uses=1] - call void @doGram( %List %reg282.upgrd.2 ) - br label %bb97 - -bb80: ; preds = %bb50 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - %reg285 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %cast917 = getelementptr %YYSTYPE* %reg285, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg286 = load %IntList* %cast917 ; <%IntList> [#uses=1] - %reg286.upgrd.3 = bitcast %IntList %reg286 to i8* ; <i8*> [#uses=1] - call void @doStart( i8* %reg286.upgrd.3 ) - br label %bb97 - -bb81: ; preds = %bb51 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb82: ; preds = %bb48 - %reg290 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast923 = getelementptr %YYSTYPE* %reg290, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg292 = load %IntList* %cast923 ; <%IntList> [#uses=1] - %reg292.upgrd.4 = bitcast %IntList %reg292 to i8* ; <i8*> [#uses=1] - %reg293.idx1 = getelementptr %YYSTYPE* %reg290, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg293 = load %IntList* %reg293.idx1 ; <%IntList> [#uses=1] - %cast930 = bitcast %IntList %reg293 to %List ; <%List> [#uses=1] - %reg930 = call %List @newList( i8* %reg292.upgrd.4, %List %cast930 ) ; <%List> [#uses=1] - bitcast %List %reg930 to %IntList ; <%IntList>:2 [#uses=1] - store %IntList %2, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb83: ; preds = %bb53 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb84: ; preds = %bb54 - %reg298 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast936 = getelementptr %YYSTYPE* %reg298, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg300 = load %IntList* %cast936 ; <%IntList> [#uses=1] - %reg300.upgrd.5 = bitcast %IntList %reg300 to i8* ; <i8*> [#uses=1] - %reg301.idx1 = getelementptr %YYSTYPE* %reg298, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg301 = load %IntList* %reg301.idx1 ; <%IntList> [#uses=1] - %cast943 = bitcast %IntList %reg301 to %List ; <%List> [#uses=1] - %reg943 = call %List @newList( i8* %reg300.upgrd.5, %List %cast943 ) ; <%List> [#uses=1] - bitcast %List %reg943 to %IntList ; <%IntList>:3 [#uses=1] - store %IntList %3, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb85: ; preds = %bb36 - %reg304 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast9521 = getelementptr %YYSTYPE* %reg304, i64 -2, i32 0 ; <%IntList*> [#uses=1] - %reg306 = load %IntList* %cast9521 ; <%IntList> [#uses=1] - %reg306.upgrd.6 = bitcast %IntList %reg306 to i8* ; <i8*> [#uses=1] - %cast953 = bitcast %YYSTYPE* %reg304 to i32* ; <i32*> [#uses=1] - %reg307 = load i32* %cast953 ; <i32> [#uses=1] - %reg955 = call %Binding @newBinding( i8* %reg306.upgrd.6, i32 %reg307 ) ; <%Binding> [#uses=1] - bitcast %Binding %reg955 to %IntList ; <%IntList>:4 [#uses=1] - store %IntList %4, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb86: ; preds = %bb60 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb87: ; preds = %bb61 - %reg312 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast961 = getelementptr %YYSTYPE* %reg312, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg314 = load %IntList* %cast961 ; <%IntList> [#uses=1] - %reg314.upgrd.7 = bitcast %IntList %reg314 to i8* ; <i8*> [#uses=1] - %reg315.idx1 = getelementptr %YYSTYPE* %reg312, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg315 = load %IntList* %reg315.idx1 ; <%IntList> [#uses=1] - %cast968 = bitcast %IntList %reg315 to %List ; <%List> [#uses=1] - %reg968 = call %List @newList( i8* %reg314.upgrd.7, %List %cast968 ) ; <%List> [#uses=1] - bitcast %List %reg968 to %IntList ; <%IntList>:5 [#uses=1] - store %IntList %5, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb88: ; preds = %bb58 - %reg318 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=4] - %cast9791 = getelementptr %YYSTYPE* %reg318, i64 -6, i32 0 ; <%IntList*> [#uses=1] - %reg322 = load %IntList* %cast9791 ; <%IntList> [#uses=1] - %reg322.upgrd.8 = bitcast %IntList %reg322 to i8* ; <i8*> [#uses=1] - %reg323.idx1 = getelementptr %YYSTYPE* %reg318, i64 -4, i32 0 ; <%IntList*> [#uses=1] - %reg323 = load %IntList* %reg323.idx1 ; <%IntList> [#uses=1] - %reg987 = getelementptr %YYSTYPE* %reg318, i64 -2 ; <%YYSTYPE*> [#uses=1] - %cast989 = bitcast %YYSTYPE* %reg987 to i32* ; <i32*> [#uses=1] - %reg324 = load i32* %cast989 ; <i32> [#uses=1] - %reg325.idx1 = getelementptr %YYSTYPE* %reg318, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg325 = load %IntList* %reg325.idx1 ; <%IntList> [#uses=1] - %cast998 = bitcast %IntList %reg323 to %PatternAST ; <%PatternAST> [#uses=1] - %reg996 = call %RuleAST @newRuleAST( i8* %reg322.upgrd.8, %PatternAST %cast998, i32 %reg324, %IntList %reg325 ) ; <%RuleAST> [#uses=1] - bitcast %RuleAST %reg996 to %IntList ; <%IntList>:6 [#uses=1] - store %IntList %6, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb89: ; preds = %bb63 - %reg328 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %cast1002 = getelementptr %YYSTYPE* %reg328, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg329 = load %IntList* %cast1002 ; <%IntList> [#uses=1] - %reg329.upgrd.9 = bitcast %IntList %reg329 to i8* ; <i8*> [#uses=1] - %reg1004 = call %PatternAST @newPatternAST( i8* %reg329.upgrd.9, %List null ) ; <%PatternAST> [#uses=1] - bitcast %PatternAST %reg1004 to %IntList ; <%IntList>:7 [#uses=1] - store %IntList %7, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb90: ; preds = %bb64 - %reg333 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %cast10131 = getelementptr %YYSTYPE* %reg333, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg335 = load %IntList* %cast10131 ; <%IntList> [#uses=1] - %reg335.upgrd.10 = bitcast %IntList %reg335 to i8* ; <i8*> [#uses=1] - %reg1015 = call %List @newList( i8* %reg335.upgrd.10, %List null ) ; <%List> [#uses=1] - %cast10211 = getelementptr %YYSTYPE* %reg333, i64 -3, i32 0 ; <%IntList*> [#uses=1] - %reg338 = load %IntList* %cast10211 ; <%IntList> [#uses=1] - %reg338.upgrd.11 = bitcast %IntList %reg338 to i8* ; <i8*> [#uses=1] - %reg1023 = call %PatternAST @newPatternAST( i8* %reg338.upgrd.11, %List %reg1015 ) ; <%PatternAST> [#uses=1] - bitcast %PatternAST %reg1023 to %IntList ; <%IntList>:8 [#uses=1] - store %IntList %8, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb91: ; preds = %bb56 - %reg341 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=3] - %cast10331 = getelementptr %YYSTYPE* %reg341, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg344 = load %IntList* %cast10331 ; <%IntList> [#uses=1] - %reg344.upgrd.12 = bitcast %IntList %reg344 to i8* ; <i8*> [#uses=1] - %reg1035 = call %List @newList( i8* %reg344.upgrd.12, %List null ) ; <%List> [#uses=1] - %cast10411 = getelementptr %YYSTYPE* %reg341, i64 -3, i32 0 ; <%IntList*> [#uses=1] - %reg347 = load %IntList* %cast10411 ; <%IntList> [#uses=1] - %reg347.upgrd.13 = bitcast %IntList %reg347 to i8* ; <i8*> [#uses=1] - %reg1043 = call %List @newList( i8* %reg347.upgrd.13, %List %reg1035 ) ; <%List> [#uses=1] - %cast10491 = getelementptr %YYSTYPE* %reg341, i64 -5, i32 0 ; <%IntList*> [#uses=1] - %reg349 = load %IntList* %cast10491 ; <%IntList> [#uses=1] - %reg349.upgrd.14 = bitcast %IntList %reg349 to i8* ; <i8*> [#uses=1] - %reg1051 = call %PatternAST @newPatternAST( i8* %reg349.upgrd.14, %List %reg1043 ) ; <%PatternAST> [#uses=1] - bitcast %PatternAST %reg1051 to %IntList ; <%IntList>:9 [#uses=1] - store %IntList %9, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb92: ; preds = %bb68 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb93: ; preds = %bb69 - %reg354 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1059 = getelementptr %YYSTYPE* %reg354, i64 -2 ; <%YYSTYPE*> [#uses=1] - %cast1061 = bitcast %YYSTYPE* %reg1059 to i32* ; <i32*> [#uses=1] - %reg356 = load i32* %cast1061 ; <i32> [#uses=1] - %reg357.idx1 = getelementptr %YYSTYPE* %reg354, i64 -1, i32 0 ; <%IntList*> [#uses=1] - %reg357 = load %IntList* %reg357.idx1 ; <%IntList> [#uses=1] - %reg1068 = call %IntList @newIntList( i32 %reg356, %IntList %reg357 ) ; <%IntList> [#uses=1] - store %IntList %reg1068, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb94: ; preds = %bb66 - store %IntList null, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb95: ; preds = %bb71 - %reg362 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1076 = getelementptr %YYSTYPE* %reg362, i64 -1 ; <%YYSTYPE*> [#uses=1] - %cast1078 = bitcast %YYSTYPE* %reg1076 to i32* ; <i32*> [#uses=1] - %reg364 = load i32* %cast1078 ; <i32> [#uses=1] - %reg365.idx = getelementptr %YYSTYPE* %reg362, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg365 = load %IntList* %reg365.idx ; <%IntList> [#uses=1] - %reg1081 = call %IntList @newIntList( i32 %reg364, %IntList %reg365 ) ; <%IntList> [#uses=1] - store %IntList %reg1081, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb96: ; preds = %bb72 - %reg368 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1088 = getelementptr %YYSTYPE* %reg368, i64 -1 ; <%YYSTYPE*> [#uses=1] - %cast1090 = bitcast %YYSTYPE* %reg1088 to i32* ; <i32*> [#uses=1] - %reg370 = load i32* %cast1090 ; <i32> [#uses=1] - %reg371.idx = getelementptr %YYSTYPE* %reg368, i64 0, i32 0 ; <%IntList*> [#uses=1] - %reg371 = load %IntList* %reg371.idx ; <%IntList> [#uses=1] - %reg1093 = call %IntList @newIntList( i32 %reg370, %IntList %reg371 ) ; <%IntList> [#uses=1] - store %IntList %reg1093, %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) - br label %bb97 - -bb97: ; preds = %bb96, %bb95, %bb94, %bb93, %bb92, %bb91, %bb90, %bb89, %bb88, %bb87, %bb86, %bb85, %bb84, %bb83, %bb82, %bb81, %bb80, %bb79, %bb78, %bb77, %bb76, %bb75, %bb74, %bb72, %bb69, %bb64, %bb61, %bb54, %bb51, %bb46, %bb43 - %cast1097 = sext i16 %reg254 to i64 ; <i64> [#uses=3] - %reg375 = add i64 %cast1097, %cast1097 ; <i64> [#uses=1] - %reg377 = load i16** @yyssp ; <i16*> [#uses=1] - %cast379 = ptrtoint i16* %reg377 to i64 ; <i64> [#uses=1] - %reg381 = sub i64 %cast379, %reg375 ; <i64> [#uses=1] - %cast1099 = inttoptr i64 %reg381 to i16* ; <i16*> [#uses=1] - store i16* %cast1099, i16** @yyssp - %reg382 = load i16** @yyssp ; <i16*> [#uses=3] - %reg383 = load i16* %reg382 ; <i16> [#uses=1] - %cast1103 = sext i16 %reg383 to i32 ; <i32> [#uses=3] - %reg385 = mul i64 %cast1097, 8 ; <i64> [#uses=1] - %reg387 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=1] - %cast389 = ptrtoint %YYSTYPE* %reg387 to i64 ; <i64> [#uses=1] - %reg391 = sub i64 %cast389, %reg385 ; <i64> [#uses=1] - %cast1108 = inttoptr i64 %reg391 to %YYSTYPE* ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %cast1108, %YYSTYPE** @yyvsp - %reg1111 = getelementptr [25 x i16]* @yylhs, i64 0, i64 %reg468-idxcast ; <i16*> [#uses=1] - %reg398 = load i16* %reg1111 ; <i16> [#uses=2] - %cast1116 = sext i16 %reg398 to i32 ; <i32> [#uses=1] - %cond1117 = icmp ne i32 %cast1103, 0 ; <i1> [#uses=1] - br i1 %cond1117, label %bb104, label %bb98 - -bb98: ; preds = %bb97 - %cond1119 = icmp ne i32 %cast1116, 0 ; <i1> [#uses=1] - br i1 %cond1119, label %bb104, label %bb99 - -bb99: ; preds = %bb98 - %reg1122 = getelementptr i16* %reg382, i64 1 ; <i16*> [#uses=2] - store i16* %reg1122, i16** @yyssp - store i16 1, i16* %reg1122 - %reg403 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1128 = getelementptr %YYSTYPE* %reg403, i64 1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg1128, %YYSTYPE** @yyvsp - %reg406 = load %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) ; <%IntList> [#uses=1] - %reg1128.idx1 = getelementptr %YYSTYPE* %reg403, i64 1, i32 0 ; <%IntList*> [#uses=1] - store %IntList %reg406, %IntList* %reg1128.idx1 - %reg407 = load i32* @yychar ; <i32> [#uses=1] - %cond1135 = icmp sge i32 %reg407, 0 ; <i1> [#uses=1] - br i1 %cond1135, label %bb102, label %bb100 - -bb100: ; preds = %bb99 - %reg1139 = call i32 @yylex( ) ; <i32> [#uses=1] - store i32 %reg1139, i32* @yychar - %reg409 = load i32* @yychar ; <i32> [#uses=1] - %cond1141 = icmp sge i32 %reg409, 0 ; <i1> [#uses=1] - br i1 %cond1141, label %bb102, label %bb101 - -bb101: ; preds = %bb100 - store i32 0, i32* @yychar - br label %bb102 - -bb102: ; preds = %bb101, %bb100, %bb99 - %reg411 = load i32* @yychar ; <i32> [#uses=1] - %cond1146 = icmp ne i32 %reg411, 0 ; <i1> [#uses=1] - br i1 %cond1146, label %bb4, label %UnifiedExitNode - -bb104: ; preds = %bb98, %bb97 - %reg398-idxcast = sext i16 %reg398 to i64 ; <i64> [#uses=2] - %reg1150 = getelementptr [12 x i16]* @yygindex, i64 0, i64 %reg398-idxcast ; <i16*> [#uses=1] - %reg418 = load i16* %reg1150 ; <i16> [#uses=1] - %cast1155 = sext i16 %reg418 to i32 ; <i32> [#uses=2] - %cond1156 = icmp eq i32 %cast1155, 0 ; <i1> [#uses=1] - br i1 %cond1156, label %bb109, label %bb105 - -bb105: ; preds = %bb104 - %reg473 = add i32 %cast1155, %cast1103 ; <i32> [#uses=3] - %cond1158 = icmp slt i32 %reg473, 0 ; <i1> [#uses=1] - br i1 %cond1158, label %bb109, label %bb106 - -bb106: ; preds = %bb105 - %cond1161 = icmp sgt i32 %reg473, 262 ; <i1> [#uses=1] - br i1 %cond1161, label %bb109, label %bb107 - -bb107: ; preds = %bb106 - %reg473-idxcast = sext i32 %reg473 to i64 ; <i64> [#uses=2] - %reg1166 = getelementptr [263 x i16]* @yycheck, i64 0, i64 %reg473-idxcast ; <i16*> [#uses=1] - %reg428 = load i16* %reg1166 ; <i16> [#uses=1] - %cast1171 = sext i16 %reg428 to i32 ; <i32> [#uses=1] - %cond1172 = icmp ne i32 %cast1171, %cast1103 ; <i1> [#uses=1] - br i1 %cond1172, label %bb109, label %bb108 - -bb108: ; preds = %bb107 - %reg1175 = getelementptr [263 x i16]* @yytable, i64 0, i64 %reg473-idxcast ; <i16*> [#uses=1] - %reg435 = load i16* %reg1175 ; <i16> [#uses=1] - %cast1180 = sext i16 %reg435 to i32 ; <i32> [#uses=1] - br label %bb110 - -bb109: ; preds = %bb107, %bb106, %bb105, %bb104 - %reg1183 = getelementptr [12 x i16]* @yydgoto, i64 0, i64 %reg398-idxcast ; <i16*> [#uses=1] - %reg442 = load i16* %reg1183 ; <i16> [#uses=1] - %cast1188 = sext i16 %reg442 to i32 ; <i32> [#uses=1] - br label %bb110 - -bb110: ; preds = %bb109, %bb108 - %reg476 = phi i32 [ %cast1188, %bb109 ], [ %cast1180, %bb108 ] ; <i32> [#uses=2] - %cast1189 = bitcast i16* %reg382 to i8* ; <i8*> [#uses=1] - %reg444 = load i16** @yysslim ; <i16*> [#uses=1] - %cast1190 = bitcast i16* %reg444 to i8* ; <i8*> [#uses=1] - %cond1191 = icmp ult i8* %cast1189, %cast1190 ; <i1> [#uses=1] - br i1 %cond1191, label %bb112, label %bb111 - -bb111: ; preds = %bb110 - %reg1193 = call i32 @yygrowstack( ) ; <i32> [#uses=1] - %cond1193 = icmp ne i32 %reg1193, 0 ; <i1> [#uses=1] - br i1 %cond1193, label %bb113, label %bb112 - -bb112: ; preds = %bb111, %bb110 - %reg446 = load i16** @yyssp ; <i16*> [#uses=1] - %reg1196 = getelementptr i16* %reg446, i64 1 ; <i16*> [#uses=2] - store i16* %reg1196, i16** @yyssp - %cast1357 = trunc i32 %reg476 to i16 ; <i16> [#uses=1] - store i16 %cast1357, i16* %reg1196 - %reg449 = load %YYSTYPE** @yyvsp ; <%YYSTYPE*> [#uses=2] - %reg1202 = getelementptr %YYSTYPE* %reg449, i64 1 ; <%YYSTYPE*> [#uses=1] - store %YYSTYPE* %reg1202, %YYSTYPE** @yyvsp - %reg452 = load %IntList* getelementptr (%YYSTYPE* @yyval, i64 0, i32 0) ; <%IntList> [#uses=1] - %reg1202.idx1 = getelementptr %YYSTYPE* %reg449, i64 1, i32 0 ; <%IntList*> [#uses=1] - store %IntList %reg452, %IntList* %reg1202.idx1 - br label %bb4 - -bb113: ; preds = %bb111, %bb30, %bb13, %bb2 - call void @yyerror( i8* getelementptr ([20 x i8]* @.LC1, i64 0, i64 0) ) - br label %UnifiedExitNode - -UnifiedExitNode: ; preds = %bb113, %bb102, %bb34, %bb32 - %UnifiedRetVal = phi i32 [ 1, %bb113 ], [ 1, %bb34 ], [ 1, %bb32 ], [ 0, %bb102 ] ; <i32> [#uses=1] - ret i32 %UnifiedRetVal -} - -declare %List @newList(i8*, %List) - -declare %IntList @newIntList(i32, %IntList) - -declare void @doStart(i8*) - -declare void @yyerror(i8*) - -declare void @doSpec(%List, %List) - -declare %Arity @newArity(i32, %List) - -declare %Binding @newBinding(i8*, i32) - -declare %PatternAST @newPatternAST(i8*, %List) - -declare %RuleAST @newRuleAST(i8*, %PatternAST, i32, %IntList) - -declare void @yyfinished() - -declare i32 @yylex() - -declare void @doGram(%List) - -declare i32 @yygrowstack() diff --git a/test/CodeGen/Generic/builtin-expect.ll b/test/CodeGen/Generic/builtin-expect.ll new file mode 100644 index 0000000..e8cd07b --- /dev/null +++ b/test/CodeGen/Generic/builtin-expect.ll @@ -0,0 +1,223 @@ +; RUN: llc < %s + +define i32 @test1(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp sgt i32 %tmp, 1 + %conv = zext i1 %cmp to i32 + %conv1 = sext i32 %conv to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 1) + %tobool = icmp ne i64 %expval, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +declare i64 @llvm.expect.i64(i64, i64) nounwind readnone + +declare i32 @f(...) + +define i32 @test2(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool = icmp ne i64 %expval, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test3(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %tobool = icmp ne i32 %tmp, 0 + %lnot = xor i1 %tobool, true + %lnot.ext = zext i1 %lnot to i32 + %conv = sext i32 %lnot.ext to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool1 = icmp ne i64 %expval, 0 + br i1 %tobool1, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test4(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %tobool = icmp ne i32 %tmp, 0 + %lnot = xor i1 %tobool, true + %lnot1 = xor i1 %lnot, true + %lnot.ext = zext i1 %lnot1 to i32 + %conv = sext i32 %lnot.ext to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + %tobool2 = icmp ne i64 %expval, 0 + br i1 %tobool2, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test5(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp slt i32 %tmp, 0 + %conv = zext i1 %cmp to i32 + %conv1 = sext i32 %conv to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv1, i64 0) + %tobool = icmp ne i64 %expval, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test6(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + switch i64 %expval, label %sw.epilog [ + i64 1, label %sw.bb + i64 2, label %sw.bb + ] + +sw.bb: ; preds = %entry, %entry + store i32 0, i32* %retval + br label %return + +sw.epilog: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %sw.epilog, %sw.bb + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test7(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %conv = sext i32 %tmp to i64 + %expval = call i64 @llvm.expect.i64(i64 %conv, i64 1) + switch i64 %expval, label %sw.epilog [ + i64 2, label %sw.bb + i64 3, label %sw.bb + ] + +sw.bb: ; preds = %entry, %entry + %tmp1 = load i32* %x.addr, align 4 + store i32 %tmp1, i32* %retval + br label %return + +sw.epilog: ; preds = %entry + store i32 0, i32* %retval + br label %return + +return: ; preds = %sw.epilog, %sw.bb + %0 = load i32* %retval + ret i32 %0 +} + +define i32 @test8(i32 %x) nounwind uwtable ssp { +entry: + %retval = alloca i32, align 4 + %x.addr = alloca i32, align 4 + store i32 %x, i32* %x.addr, align 4 + %tmp = load i32* %x.addr, align 4 + %cmp = icmp sgt i32 %tmp, 1 + %conv = zext i1 %cmp to i32 + %expval = call i32 @llvm.expect.i32(i32 %conv, i32 1) + %tobool = icmp ne i32 %expval, 0 + br i1 %tobool, label %if.then, label %if.end + +if.then: ; preds = %entry + %call = call i32 (...)* @f() + store i32 %call, i32* %retval + br label %return + +if.end: ; preds = %entry + store i32 1, i32* %retval + br label %return + +return: ; preds = %if.end, %if.then + %0 = load i32* %retval + ret i32 %0 +} + +declare i32 @llvm.expect.i32(i32, i32) nounwind readnone + diff --git a/test/CodeGen/Generic/crash.ll b/test/CodeGen/Generic/crash.ll index e7cc7e3..d889389 100644 --- a/test/CodeGen/Generic/crash.ll +++ b/test/CodeGen/Generic/crash.ll @@ -1,7 +1,7 @@ ; RUN: llc %s -o - ; PR6332 -%struct.AVCodecTag = type opaque +%struct.AVCodecTag = type {} @ff_codec_bmp_tags = external global [0 x %struct.AVCodecTag] @tags = global [1 x %struct.AVCodecTag*] [%struct.AVCodecTag* getelementptr inbounds ([0 x %struct.AVCodecTag]* @ff_codec_bmp_tags, i32 0, i32 0)] diff --git a/test/CodeGen/Generic/spillccr.ll b/test/CodeGen/Generic/spillccr.ll deleted file mode 100644 index 0a774c6..0000000 --- a/test/CodeGen/Generic/spillccr.ll +++ /dev/null @@ -1,49 +0,0 @@ -; RUN: llc < %s - -; July 6, 2002 -- LLC Regression test -; This test case checks if the integer CC register %xcc (or %ccr) -; is correctly spilled. The code fragment came from function -; MakeGraph in Olden-mst. -; The original code made all comparisons with 0, so that the %xcc -; register is not needed for the branch in the first basic block. -; Replace 0 with 1 in the first comparson so that the -; branch-on-register instruction cannot be used directly, i.e., -; the %xcc register is needed for the first branch. -; - - %Graph = type %struct.graph_st* - %Hash = type %struct.hash* - %HashEntry = type %struct.hash_entry* - %Vertex = type %struct.vert_st* - %struct.graph_st = type { [1 x %Vertex] } - %struct.hash = type { %HashEntry*, i32 (i32)*, i32 } - %struct.hash_entry = type { i32, i8*, %HashEntry } - %struct.vert_st = type { i32, %Vertex, %Hash } -@HashRange = external global i32 ; <i32*> [#uses=0] -@.LC0 = internal global [13 x i8] c"Make phase 2\00" ; <[13 x i8]*> [#uses=0] -@.LC1 = internal global [13 x i8] c"Make phase 3\00" ; <[13 x i8]*> [#uses=0] -@.LC2 = internal global [13 x i8] c"Make phase 4\00" ; <[13 x i8]*> [#uses=0] -@.LC3 = internal global [15 x i8] c"Make returning\00" ; <[15 x i8]*> [#uses=0] - -define %Graph @MakeGraph(i32 %numvert, i32 %numproc) { -bb1: - %reg111 = add i32 %numproc, -1 ; <i32> [#uses=2] - %cond275 = icmp slt i32 %reg111, 1 ; <i1> [#uses=1] - %cond276 = icmp sle i32 %reg111, 0 ; <i1> [#uses=1] - %cond277 = icmp sge i32 %numvert, 0 ; <i1> [#uses=1] - %reg162 = add i32 %numvert, 3 ; <i32> [#uses=0] - br i1 %cond275, label %bb7, label %bb4 - -bb4: ; preds = %bb1 - br i1 %cond276, label %bb7, label %bb5 - -bb5: ; preds = %bb4 - br i1 %cond277, label %bb7, label %bb6 - -bb6: ; preds = %bb5 - ret %Graph null - -bb7: ; preds = %bb5, %bb4, %bb1 - ret %Graph null -} - diff --git a/test/CodeGen/PowerPC/vector.ll b/test/CodeGen/PowerPC/vector.ll index ee4da31..e4c3b0d 100644 --- a/test/CodeGen/PowerPC/vector.ll +++ b/test/CodeGen/PowerPC/vector.ll @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llc < %s -march=ppc32 -mcpu=g5 > %t -; RUN: llc < %s -march=ppc32 -mcpu=g3 > %t +; RUN: llc < %s -march=ppc32 -mcpu=g3 >> %t %d8 = type <8 x double> %f1 = type <1 x float> diff --git a/test/CodeGen/Thumb/barrier.ll b/test/CodeGen/Thumb/barrier.ll index 419c3ba..d39b50f 100644 --- a/test/CodeGen/Thumb/barrier.ll +++ b/test/CodeGen/Thumb/barrier.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s -check-prefix=V6 ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=-db | FileCheck %s -check-prefix=V6 -; RUN: llc < %s -march=thumb -mattr=+v6m | FileCheck %s -check-prefix=V6M +; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M declare void @llvm.memory.barrier(i1 , i1 , i1 , i1 , i1) diff --git a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll index 9ed6a01..01fb0a5 100644 --- a/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll +++ b/test/CodeGen/Thumb2/2010-06-14-NEONCoalescer.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 | FileCheck %s +; RUN: llc < %s -O3 -relocation-model=pic -mattr=+thumb2 -mcpu=cortex-a8 -disable-branch-fold | FileCheck %s target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32" target triple = "thumbv7-apple-darwin10" @@ -26,7 +26,7 @@ entry: ; CHECK: vldr.64 [[LDR:d.*]], ; CHECK: LPC0_0: ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]] -; CHECK: vmov.f64 [[LDR]] +; CHECK-NOT: vmov.f64 [[ADD]] %5 = fadd <2 x double> %3, %3 ; <<2 x double>> [#uses=2] %6 = fadd <2 x double> %4, %4 ; <<2 x double>> [#uses=2] %tmp7 = extractelement <2 x double> %5, i32 0 ; <double> [#uses=1] diff --git a/test/CodeGen/Thumb2/lsr-deficiency.ll b/test/CodeGen/Thumb2/lsr-deficiency.ll index ad957a1..9ff114e 100644 --- a/test/CodeGen/Thumb2/lsr-deficiency.ll +++ b/test/CodeGen/Thumb2/lsr-deficiency.ll @@ -13,16 +13,16 @@ define void @t() nounwind optsize { ; CHECK: t: -; CHECK: mov.w r2, #1000 +; CHECK: mov{{.*}}, #1000 entry: %.pre = load i32* @G, align 4 ; <i32> [#uses=1] br label %bb bb: ; preds = %bb, %entry ; CHECK: LBB0_1: -; CHECK: cmp r2, #0 -; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], r2, #1 -; CHECK: mov r2, [[REGISTER]] +; CHECK: cmp [[R2:r[0-9]+]], #0 +; CHECK: sub{{(.w)?}} [[REGISTER:(r[0-9]+)|(lr)]], [[R2]], #1 +; CHECK: mov [[R2]], [[REGISTER]] %0 = phi i32 [ %.pre, %entry ], [ %3, %bb ] ; <i32> [#uses=1] %indvar = phi i32 [ 0, %entry ], [ %indvar.next, %bb ] ; <i32> [#uses=2] diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index ee054a1..b199d69 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -8,26 +8,25 @@ define void @t1(i32* nocapture %vals, i32 %c) nounwind { entry: ; CHECK: t1: -; CHECK: cbz +; CHECK: bxeq lr + %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1] br i1 %0, label %return, label %bb.nph bb.nph: ; preds = %entry -; CHECK: BB#1 ; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr ; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr ; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] ; CHECK: ldr{{.*}}, [r[[R2b]] -; CHECK: LBB0_2 +; CHECK: LBB0_ ; CHECK-NOT: LCPI0_0: -; PIC: BB#1 ; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) ; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) ; PIC: add r[[R2]], pc ; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] ; PIC: ldr{{.*}}, [r[[R2b]] -; PIC: LBB0_2 +; PIC: LBB0_ ; PIC-NOT: LCPI0_0: ; PIC: .section %.pre = load i32* @GV, align 4 ; <i32> [#uses=1] @@ -52,8 +51,8 @@ return: ; preds = %bb, %entry define void @t2(i8* %ptr1, i8* %ptr2) nounwind { entry: ; CHECK: t2: -; CHECK: mov.w r3, #1065353216 -; CHECK: vdup.32 q{{.*}}, r3 +; CHECK: mov.w [[R3:r[0-9]+]], #1065353216 +; CHECK: vdup.32 q{{.*}}, [[R3]] br i1 undef, label %bb1, label %bb2 bb1: diff --git a/test/CodeGen/Thumb2/thumb2-add.ll b/test/CodeGen/Thumb2/thumb2-add.ll index 5e25cf6..66fca13 100644 --- a/test/CodeGen/Thumb2/thumb2-add.ll +++ b/test/CodeGen/Thumb2/thumb2-add.ll @@ -1,48 +1,81 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #255 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #256 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #257 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4094 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4095 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep #4096 -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add -; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep add | grep lsl | grep #8 +; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s define i32 @t2ADDrc_255(i32 %lhs) { +; CHECK: t2ADDrc_255: +; CHECK-NOT: bx lr +; CHECK: add{{.*}} #255 +; CHECK: bx lr + %Rd = add i32 %lhs, 255 ret i32 %Rd } define i32 @t2ADDrc_256(i32 %lhs) { +; CHECK: t2ADDrc_256: +; CHECK-NOT: bx lr +; CHECK: add{{.*}} #256 +; CHECK: bx lr + %Rd = add i32 %lhs, 256 ret i32 %Rd } define i32 @t2ADDrc_257(i32 %lhs) { +; CHECK: t2ADDrc_257: +; CHECK-NOT: bx lr +; CHECK: add{{.*}} #257 +; CHECK: bx lr + %Rd = add i32 %lhs, 257 ret i32 %Rd } define i32 @t2ADDrc_4094(i32 %lhs) { +; CHECK: t2ADDrc_4094: +; CHECK-NOT: bx lr +; CHECK: add{{.*}} #4094 +; CHECK: bx lr + %Rd = add i32 %lhs, 4094 ret i32 %Rd } define i32 @t2ADDrc_4095(i32 %lhs) { +; CHECK: t2ADDrc_4095: +; CHECK-NOT: bx lr +; CHECK: add{{.*}} #4095 +; CHECK: bx lr + %Rd = add i32 %lhs, 4095 ret i32 %Rd } define i32 @t2ADDrc_4096(i32 %lhs) { +; CHECK: t2ADDrc_4096: +; CHECK-NOT: bx lr +; CHECK: add{{.*}} #4096 +; CHECK: bx lr + %Rd = add i32 %lhs, 4096 ret i32 %Rd } define i32 @t2ADDrr(i32 %lhs, i32 %rhs) { +; CHECK: t2ADDrr: +; CHECK-NOT: bx lr +; CHECK: add +; CHECK: bx lr + %Rd = add i32 %lhs, %rhs ret i32 %Rd } define i32 @t2ADDrs(i32 %lhs, i32 %rhs) { +; CHECK: t2ADDrs: +; CHECK-NOT: bx lr +; CHECK: add{{.*}} lsl #8 +; CHECK: bx lr + %tmp = shl i32 %rhs, 8 %Rd = add i32 %lhs, %tmp ret i32 %Rd diff --git a/test/CodeGen/Thumb2/thumb2-bcc.ll b/test/CodeGen/Thumb2/thumb2-bcc.ll index aae9f5c..70febc0 100644 --- a/test/CodeGen/Thumb2/thumb2-bcc.ll +++ b/test/CodeGen/Thumb2/thumb2-bcc.ll @@ -1,5 +1,8 @@ ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s ; RUN: llc < %s -march=thumb -mattr=+thumb2 | not grep it +; If-conversion defeats the purpose of this test, which is to check CBZ +; generation, so use memory barrier instruction to make sure it doesn't +; happen and we get actual branches. define i32 @t1(i32 %a, i32 %b, i32 %c) { ; CHECK: t1: @@ -8,12 +11,16 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) { br i1 %tmp2, label %cond_false, label %cond_true cond_true: + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) %tmp5 = add i32 %b, 1 %tmp6 = and i32 %tmp5, %c ret i32 %tmp6 cond_false: + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) %tmp7 = add i32 %b, -1 %tmp8 = xor i32 %tmp7, %c ret i32 %tmp8 } + +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind diff --git a/test/CodeGen/Thumb2/thumb2-branch.ll b/test/CodeGen/Thumb2/thumb2-branch.ll index 1d2af7a..4d9eda0 100644 --- a/test/CodeGen/Thumb2/thumb2-branch.ll +++ b/test/CodeGen/Thumb2/thumb2-branch.ll @@ -1,4 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mattr=+thumb2 | FileCheck %s +; If-conversion defeats the purpose of this test, which is to check conditional +; branch generation, so use memory barrier instruction to make sure it doesn't +; happen and we get actual branches. define i32 @f1(i32 %a, i32 %b, i32* %v) { entry: @@ -8,10 +11,12 @@ entry: br i1 %tmp, label %cond_true, label %return cond_true: ; preds = %entry + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) store i32 0, i32* %v ret i32 0 return: ; preds = %entry + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) ret i32 1 } @@ -23,10 +28,12 @@ entry: br i1 %tmp, label %cond_true, label %return cond_true: ; preds = %entry + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) store i32 0, i32* %v ret i32 0 return: ; preds = %entry + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) ret i32 1 } @@ -38,10 +45,12 @@ entry: br i1 %tmp, label %cond_true, label %return cond_true: ; preds = %entry + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) store i32 0, i32* %v ret i32 0 return: ; preds = %entry + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) ret i32 1 } @@ -53,9 +62,13 @@ entry: br i1 %tmp, label %return, label %cond_true cond_true: ; preds = %entry + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) store i32 0, i32* %v ret i32 0 return: ; preds = %entry + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 false) ret i32 1 } + +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind diff --git a/test/CodeGen/Thumb2/thumb2-clz.ll b/test/CodeGen/Thumb2/thumb2-clz.ll index 74728bf..00a54a0 100644 --- a/test/CodeGen/Thumb2/thumb2-clz.ll +++ b/test/CodeGen/Thumb2/thumb2-clz.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s define i32 @f1(i32 %a) { ; CHECK: f1: diff --git a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll index 1533040..a4035bb 100644 --- a/test/CodeGen/Thumb2/thumb2-ifcvt1.ll +++ b/test/CodeGen/Thumb2/thumb2-ifcvt1.ll @@ -2,8 +2,10 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; CHECK: t1: -; CHECK: it ne +; CHECK: ittt ne ; CHECK: cmpne +; CHECK: addne +; CHECK: bxne lr switch i32 %c, label %cond_next [ i32 1, label %cond_true i32 7, label %cond_true diff --git a/test/CodeGen/Thumb2/thumb2-rev.ll b/test/CodeGen/Thumb2/thumb2-rev.ll index 2cee2e3..b469bbd 100644 --- a/test/CodeGen/Thumb2/thumb2-rev.ll +++ b/test/CodeGen/Thumb2/thumb2-rev.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7a,+t2xtpk | FileCheck %s +; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s define i32 @f1(i32 %a) { ; CHECK: f1: diff --git a/test/CodeGen/Thumb2/thumb2-teq.ll b/test/CodeGen/Thumb2/thumb2-teq.ll index 566408a..00c928f 100644 --- a/test/CodeGen/Thumb2/thumb2-teq.ll +++ b/test/CodeGen/Thumb2/thumb2-teq.ll @@ -4,15 +4,6 @@ ; test as 'mov.w r0, #0'. So far, that requires physreg joining. ; 0x000000bb = 187 -define i1 @f1(i32 %a) { - %tmp = xor i32 %a, 187 - %tmp1 = icmp ne i32 %tmp, 0 - ret i1 %tmp1 -} -; CHECK: f1: -; CHECK: teq.w r0, #187 - -; 0x000000bb = 187 define i1 @f2(i32 %a) { %tmp = xor i32 %a, 187 %tmp1 = icmp eq i32 0, %tmp @@ -30,24 +21,6 @@ define i1 @f3(i32 %a) { ; CHECK: f3: ; CHECK: teq.w r0, #11141290 -; 0x00aa00aa = 11141290 -define i1 @f4(i32 %a) { - %tmp = xor i32 %a, 11141290 - %tmp1 = icmp ne i32 0, %tmp - ret i1 %tmp1 -} -; CHECK: f4: -; CHECK: teq.w r0, #11141290 - -; 0xcc00cc00 = 3422604288 -define i1 @f5(i32 %a) { - %tmp = xor i32 %a, 3422604288 - %tmp1 = icmp ne i32 %tmp, 0 - ret i1 %tmp1 -} -; CHECK: f5: -; CHECK: teq.w r0, #-872363008 - ; 0xcc00cc00 = 3422604288 define i1 @f6(i32 %a) { %tmp = xor i32 %a, 3422604288 @@ -72,17 +45,6 @@ define i1 @f8(i32 %a) { %tmp1 = icmp ne i32 0, %tmp ret i1 %tmp1 } -; CHECK: f8: -; CHECK: teq.w r0, #-572662307 - -; 0x00110000 = 1114112 -define i1 @f9(i32 %a) { - %tmp = xor i32 %a, 1114112 - %tmp1 = icmp ne i32 %tmp, 0 - ret i1 %tmp1 -} -; CHECK: f9: -; CHECK: teq.w r0, #1114112 ; 0x00110000 = 1114112 define i1 @f10(i32 %a) { diff --git a/test/CodeGen/Thumb2/thumb2-teq2.ll b/test/CodeGen/Thumb2/thumb2-teq2.ll index cdd3489..8acae90 100644 --- a/test/CodeGen/Thumb2/thumb2-teq2.ll +++ b/test/CodeGen/Thumb2/thumb2-teq2.ll @@ -3,14 +3,6 @@ ; These tests implicitly depend on 'movs r0, #0' being rematerialized below the ; tst as 'mov.w r0, #0'. So far, that requires physreg joining. -define i1 @f1(i32 %a, i32 %b) { -; CHECK: f1 -; CHECK: teq.w r0, r1 - %tmp = xor i32 %a, %b - %tmp1 = icmp ne i32 %tmp, 0 - ret i1 %tmp1 -} - define i1 @f2(i32 %a, i32 %b) { ; CHECK: f2 ; CHECK: teq.w r0, r1 @@ -19,14 +11,6 @@ define i1 @f2(i32 %a, i32 %b) { ret i1 %tmp1 } -define i1 @f3(i32 %a, i32 %b) { -; CHECK: f3 -; CHECK: teq.w r0, r1 - %tmp = xor i32 %a, %b - %tmp1 = icmp ne i32 0, %tmp - ret i1 %tmp1 -} - define i1 @f4(i32 %a, i32 %b) { ; CHECK: f4 ; CHECK: teq.w r0, r1 diff --git a/test/CodeGen/Thumb2/thumb2-tst.ll b/test/CodeGen/Thumb2/thumb2-tst.ll index 47f553f..43e208c 100644 --- a/test/CodeGen/Thumb2/thumb2-tst.ll +++ b/test/CodeGen/Thumb2/thumb2-tst.ll @@ -4,15 +4,6 @@ ; tst as 'mov.w r0, #0'. So far, that requires physreg joining. ; 0x000000bb = 187 -define i1 @f1(i32 %a) { - %tmp = and i32 %a, 187 - %tmp1 = icmp ne i32 %tmp, 0 - ret i1 %tmp1 -} -; CHECK: f1: -; CHECK: tst.w r0, #187 - -; 0x000000bb = 187 define i1 @f2(i32 %a) { %tmp = and i32 %a, 187 %tmp1 = icmp eq i32 0, %tmp @@ -30,24 +21,6 @@ define i1 @f3(i32 %a) { ; CHECK: f3: ; CHECK: tst.w r0, #11141290 -; 0x00aa00aa = 11141290 -define i1 @f4(i32 %a) { - %tmp = and i32 %a, 11141290 - %tmp1 = icmp ne i32 0, %tmp - ret i1 %tmp1 -} -; CHECK: f4: -; CHECK: tst.w r0, #11141290 - -; 0xcc00cc00 = 3422604288 -define i1 @f5(i32 %a) { - %tmp = and i32 %a, 3422604288 - %tmp1 = icmp ne i32 %tmp, 0 - ret i1 %tmp1 -} -; CHECK: f5: -; CHECK: tst.w r0, #-872363008 - ; 0xcc00cc00 = 3422604288 define i1 @f6(i32 %a) { %tmp = and i32 %a, 3422604288 @@ -66,24 +39,6 @@ define i1 @f7(i32 %a) { ; CHECK: f7: ; CHECK: tst.w r0, #-572662307 -; 0xdddddddd = 3722304989 -define i1 @f8(i32 %a) { - %tmp = and i32 %a, 3722304989 - %tmp1 = icmp ne i32 0, %tmp - ret i1 %tmp1 -} -; CHECK: f8: -; CHECK: tst.w r0, #-572662307 - -; 0x00110000 = 1114112 -define i1 @f9(i32 %a) { - %tmp = and i32 %a, 1114112 - %tmp1 = icmp ne i32 %tmp, 0 - ret i1 %tmp1 -} -; CHECK: f9: -; CHECK: tst.w r0, #1114112 - ; 0x00110000 = 1114112 define i1 @f10(i32 %a) { %tmp = and i32 %a, 1114112 diff --git a/test/CodeGen/Thumb2/thumb2-tst2.ll b/test/CodeGen/Thumb2/thumb2-tst2.ll index 405b3bb..bfe016f 100644 --- a/test/CodeGen/Thumb2/thumb2-tst2.ll +++ b/test/CodeGen/Thumb2/thumb2-tst2.ll @@ -3,14 +3,6 @@ ; These tests implicitly depend on 'movs r0, #0' being rematerialized below the ; tst as 'mov.w r0, #0'. So far, that requires physreg joining. -define i1 @f1(i32 %a, i32 %b) { -; CHECK: f1: -; CHECK: tst r0, r1 - %tmp = and i32 %a, %b - %tmp1 = icmp ne i32 %tmp, 0 - ret i1 %tmp1 -} - define i1 @f2(i32 %a, i32 %b) { ; CHECK: f2: ; CHECK: tst r0, r1 @@ -19,14 +11,6 @@ define i1 @f2(i32 %a, i32 %b) { ret i1 %tmp1 } -define i1 @f3(i32 %a, i32 %b) { -; CHECK: f3: -; CHECK: tst r0, r1 - %tmp = and i32 %a, %b - %tmp1 = icmp ne i32 0, %tmp - ret i1 %tmp1 -} - define i1 @f4(i32 %a, i32 %b) { ; CHECK: f4: ; CHECK: tst r0, r1 diff --git a/test/CodeGen/X86/2006-11-12-CSRetCC.ll b/test/CodeGen/X86/2006-11-12-CSRetCC.ll index 91210ea..6ec9a48 100644 --- a/test/CodeGen/X86/2006-11-12-CSRetCC.ll +++ b/test/CodeGen/X86/2006-11-12-CSRetCC.ll @@ -1,9 +1,14 @@ -; RUN: llc < %s -march=x86 | grep {subl \$4, %esp} +; RUN: llc < %s -march=x86 | FileCheck %s target triple = "i686-pc-linux-gnu" @str = internal constant [9 x i8] c"%f+%f*i\0A\00" ; <[9 x i8]*> [#uses=1] define i32 @main() { +; CHECK: main: +; CHECK-NOT: ret +; CHECK: subl $4, %{{.*}} +; CHECK: ret + entry: %retval = alloca i32, align 4 ; <i32*> [#uses=1] %tmp = alloca { double, double }, align 16 ; <{ double, double }*> [#uses=4] diff --git a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll index 10bbe74..b0eb1c5 100644 --- a/test/CodeGen/X86/2007-02-04-OrAddrMode.ll +++ b/test/CodeGen/X86/2007-02-04-OrAddrMode.ll @@ -1,8 +1,12 @@ -; RUN: llc < %s -march=x86 | grep {orl \$1, %eax} -; RUN: llc < %s -march=x86 | grep {leal 3(,%eax,8)} +; RUN: llc < %s -march=x86 | FileCheck %s ;; This example can't fold the or into an LEA. define i32 @test(float ** %tmp2, i32 %tmp12) nounwind { +; CHECK: test: +; CHECK-NOT: ret +; CHECK: orl $1, %{{.*}} +; CHECK: ret + %tmp3 = load float** %tmp2 %tmp132 = shl i32 %tmp12, 2 ; <i32> [#uses=1] %tmp4 = bitcast float* %tmp3 to i8* ; <i8*> [#uses=1] @@ -12,9 +16,13 @@ define i32 @test(float ** %tmp2, i32 %tmp12) nounwind { ret i32 %tmp14 } - ;; This can! define i32 @test2(i32 %a, i32 %b) nounwind { +; CHECK: test2: +; CHECK-NOT: ret +; CHECK: leal 3(,%{{.*}},8) +; CHECK: ret + %c = shl i32 %a, 3 %d = or i32 %c, 3 ret i32 %d diff --git a/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll index a8f0e57..b48ce84 100644 --- a/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll +++ b/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll @@ -1,13 +1,17 @@ ; PR1219 -; RUN: llc < %s -march=x86 | grep {movl \$1, %eax} +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @test(i1 %X) { -old_entry1: - %hvar2 = zext i1 %X to i32 +; CHECK: test: +; CHECK-NOT: ret +; CHECK: movl $1, %eax +; CHECK: ret + + %hvar2 = zext i1 %X to i32 %C = icmp sgt i32 %hvar2, -1 br i1 %C, label %cond_true15, label %cond_true cond_true15: - ret i32 1 + ret i32 1 cond_true: - ret i32 2 + ret i32 2 } diff --git a/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll b/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll index 30453d5..e2cd750 100644 --- a/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll +++ b/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll @@ -1,9 +1,14 @@ -; RUN: llc < %s -march=x86 | grep {psrlw \$8, %xmm0} +; RUN: llc < %s -march=x86 | FileCheck %s target datalayout = "e-p:32:32" target triple = "i686-apple-darwin9" define void @test() { - tail call void asm sideeffect "psrlw $0, %xmm0", "X,~{dirflag},~{fpsr},~{flags}"( i32 8 ) - ret void +; CHECK: test: +; CHECK-NOT: ret +; CHECK: psrlw $8, %xmm0 +; CHECK: ret + + tail call void asm sideeffect "psrlw $0, %xmm0", "X,~{dirflag},~{fpsr},~{flags}"( i32 8 ) + ret void } diff --git a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll index 8518d4c..15466a1 100644 --- a/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll +++ b/test/CodeGen/X86/2007-09-17-ObjcFrameEH.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -disable-cfi -march=x86 -mtriple=i686-apple-darwin | grep {isNullOrNil].eh"} | FileCheck %s +; RUN: llc < %s -disable-cfi -march=x86 -mtriple=i686-apple-darwin | FileCheck %s ; CHECK: "_-[NSString(local) isNullOrNil].eh": diff --git a/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll b/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll index 38d6aa6..6e9a629 100644 --- a/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll +++ b/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll @@ -1,10 +1,14 @@ -; RUN: llc < %s | grep {1 \$2 3} +; RUN: llc < %s | FileCheck %s ; rdar://5720231 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" define void @test() nounwind { -entry: +; CHECK: test: +; CHECK-NOT: ret +; CHECK: 1 $2 3 +; CHECK: ret + tail call void asm sideeffect " ${0:c} $1 ${2:c} ", "imr,imr,i,~{dirflag},~{fpsr},~{flags}"( i32 1, i32 2, i32 3 ) nounwind ret void } diff --git a/test/CodeGen/X86/2008-12-05-SpillerCrash.ll b/test/CodeGen/X86/2008-12-05-SpillerCrash.ll deleted file mode 100644 index 7fd2e6f..0000000 --- a/test/CodeGen/X86/2008-12-05-SpillerCrash.ll +++ /dev/null @@ -1,237 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin9.5 -mattr=+sse41 -relocation-model=pic - - %struct.XXActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 } - %struct.XXAlphaTest = type { float, i16, i8, i8 } - %struct.XXArrayRange = type { i8, i8, i8, i8 } - %struct.XXBlendMode = type { i16, i16, i16, i16, %struct.ZZIColor4, i16, i16, i8, i8, i8, i8 } - %struct.XXBBRec = type opaque - %struct.XXBBstate = type { %struct.ZZGTransformKey, %struct.ZZGTransformKey, %struct.XXProgramLimits, %struct.XXProgramLimits, i8, i8, i8, i8, %struct.ZZSBB, %struct.ZZSBB, [4 x %struct.ZZSBB], %struct.ZZSBB, %struct.ZZSBB, %struct.ZZSBB, [8 x %struct.ZZSBB], %struct.ZZSBB } - %struct.XXClearColor = type { double, %struct.ZZIColor4, %struct.ZZIColor4, float, i32 } - %struct.XXClipPlane = type { i32, [6 x %struct.ZZIColor4] } - %struct.XXColorBB = type { i16, i8, i8, [8 x i16], i8, i8, i8, i8 } - %struct.XXColorMatrix = type { [16 x float]*, %struct.XXImagingColorScale } - %struct.XXConfig = type { i32, float, %struct.ZZGTransformKey, %struct.ZZGTransformKey, i8, i8, i8, i8, i8, i8, i16, i32, i32, i32, %struct.XXPixelFormatInfo, %struct.XXPointLineLimits, %struct.XXPointLineLimits, %struct.XXRenderFeatures, i32, i32, i32, i32, i32, i32, i32, i32, i32, %struct.XXTextureLimits, [3 x %struct.XXPipelineProgramLimits], %struct.XXFragmentProgramLimits, %struct.XXVertexProgramLimits, %struct.XXGeometryShaderLimits, %struct.XXProgramLimits, %struct.XXGeometryShaderLimits, %struct.XXVertexDescriptor*, %struct.XXVertexDescriptor*, [3 x i32], [4 x i32], [0 x i32] } - %struct.XXContextRec = type { float, float, float, float, float, float, float, float, %struct.ZZIColor4, %struct.ZZIColor4, %struct.YYFPContext, [16 x [2 x %struct.PPStreamToken]], %struct.ZZGProcessor, %struct._YYConstants*, void (%struct.XXContextRec*, i32, i32, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, i32)*, %struct._YYFunction*, %struct.PPStreamToken*, void (%struct.XXContextRec*, %struct.XXVertex*)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*, %struct.XXVertex*)*, %struct._YYFunction*, %struct._YYFunction*, %struct._YYFunction*, [4 x i32], [3 x i32], [3 x i32], float, float, float, %struct.PPStreamToken, i32, %struct.ZZSDrawable, %struct.XXFramebufferRec*, %struct.XXFramebufferRec*, %struct.XXRect, %struct.XXFormat, %struct.XXFormat, %struct.XXFormat, %struct.XXConfig*, %struct.XXBBstate, %struct.XXBBstate, %struct.XXSharedRec*, %struct.XXState*, %struct.XXPluginState*, %struct.XXVertex*, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, %struct.XXProgramRec*, %struct.XXPipelineProgramRec*, %struct.YYTextures, %struct.XXStippleData, i8, i16, i8, i32, i32, i32, %struct.XXQueryRec*, %struct.XXQueryRec*, %struct.XXFallback, { void (i8*, i8*, i32, i8*)* } } - %struct.XXConvolution = type { %struct.ZZIColor4, %struct.XXImagingColorScale, i16, i16, [0 x i32], float*, i32, i32 } - %struct.XXCurrent16A = type { [8 x %struct.ZZIColor4], [16 x %struct.ZZIColor4], %struct.ZZIColor4, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, [4 x float], %struct.XXPointLineLimits, float, float, float, float, i8, i8, i8, i8 } - %struct.XXDepthTest = type { i16, i16, i8, i8, i8, i8, double, double } - %struct.XXDrawableWindow = type { i32, i32, i32 } - %struct.XXFallback = type { float*, %struct.XXRenderDispatch*, %struct.XXConfig*, i8*, i8*, i32, i32 } - %struct.XXFenceRec = type opaque - %struct.XXFixedFunction = type { %struct.PPStreamToken* } - %struct.XXFogMode = type { %struct.ZZIColor4, float, float, float, float, float, i16, i16, i16, i8, i8 } - %struct.XXFormat = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8, i32, i32, i32 } - %struct.XXFragmentProgramLimits = type { i32, i32, i32, i16, i16, i32, i32 } - %struct.XXFramebufferAttachment = type { i16, i16, i32, i32, i32 } - %struct.XXFramebufferData = type { [10 x %struct.XXFramebufferAttachment], [8 x i16], i16, i16, i16, i8, i8, i32, i32 } - %struct.XXFramebufferRec = type { %struct.XXFramebufferData*, %struct.XXPluginFramebufferData*, %struct.XXFormat, i8, i8, i8, i8 } - %struct.XXGeometryShaderLimits = type { i32, i32, i32, i32, i32 } - %struct.XXHintMode = type { i16, i16, i16, i16, i16, i16, i16, i16, i16, i16 } - %struct.XXHistogram = type { %struct.XXProgramLimits*, i32, i16, i8, i8 } - %struct.XXImagingColorScale = type { %struct.ZZTCoord2, %struct.ZZTCoord2, %struct.ZZTCoord2, %struct.ZZTCoord2 } - %struct.XXImagingSubset = type { %struct.XXConvolution, %struct.XXConvolution, %struct.XXConvolution, %struct.XXColorMatrix, %struct.XXMinmax, %struct.XXHistogram, %struct.XXImagingColorScale, %struct.XXImagingColorScale, %struct.XXImagingColorScale, %struct.XXImagingColorScale, i32, [0 x i32] } - %struct.XXLight = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.XXPointLineLimits, float, float, float, float, float, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, %struct.XXPointLineLimits, float, float, float, float, float } - %struct.XXLightModel = type { %struct.ZZIColor4, [8 x %struct.XXLight], [2 x %struct.XXMaterial], i32, i16, i16, i16, i8, i8, i8, i8, i8, i8 } - %struct.XXLightProduct = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4 } - %struct.XXLineMode = type { float, i32, i16, i16, i8, i8, i8, i8 } - %struct.XXLogicOp = type { i16, i8, i8 } - %struct.XXMaskMode = type { i32, [3 x i32], i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXMaterial = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, float, float, float, float, [8 x %struct.XXLightProduct], %struct.ZZIColor4, [8 x i32] } - %struct.XXMinmax = type { %struct.XXMinmaxTable*, i16, i8, i8, [0 x i32] } - %struct.XXMinmaxTable = type { %struct.ZZIColor4, %struct.ZZIColor4 } - %struct.XXMipmaplevel = type { [4 x i32], [4 x i32], [4 x float], [4 x i32], i32, i32, float*, i8*, i16, i16, i16, i16, [2 x float] } - %struct.XXMultisample = type { float, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXPipelineProgramData = type { i16, i8, i8, i32, %struct.PPStreamToken*, i64, %struct.ZZIColor4*, i32, [0 x i32] } - %struct.XXPipelineProgramLimits = type { i32, i16, i16, i32, i16, i16, i32, i32 } - %struct.XXPipelineProgramRec = type { %struct.XXPipelineProgramData*, %struct.PPStreamToken*, %struct.XXContextRec*, { %struct._YYFunction*, \2, \2, [20 x i32], [64 x i32], i32, i32, i32 }*, i32, i32 } - %struct.XXPipelineProgramState = type { i8, i8, i8, i8, [0 x i32], %struct.ZZIColor4* } - %struct.XXPixelFormatInfo = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXPixelMap = type { i32*, float*, float*, float*, float*, float*, float*, float*, float*, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } - %struct.XXPixelMode = type { float, float, %struct.XXPixelStore, %struct.XXPixelTransfer, %struct.XXPixelMap, %struct.XXImagingSubset, i32, i32 } - %struct.XXPixelPack = type { i32, i32, i32, i32, i32, i32, i32, i32, i8, i8, i8, i8 } - %struct.XXPixelStore = type { %struct.XXPixelPack, %struct.XXPixelPack } - %struct.XXPixelTransfer = type { float, float, float, float, float, float, float, float, float, float, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float } - %struct.XXPluginFramebufferData = type { [10 x %struct.XXTextureRec*], i8, i8, i8, i8 } - %struct.XXPluginProgramData = type { [3 x %struct.XXPipelineProgramRec*], %struct.XXBBRec**, i32, [0 x i32] } - %struct.XXPluginState = type { [16 x [5 x %struct.XXTextureRec*]], [3 x %struct.XXTextureRec*], [3 x %struct.XXPipelineProgramRec*], [3 x %struct.XXPipelineProgramRec*], %struct.XXProgramRec*, %struct.XXVertexArrayRec*, [16 x %struct.XXBBRec*], %struct.XXFramebufferRec*, %struct.XXFramebufferRec* } - %struct.XXPointLineLimits = type { float, float, float } - %struct.XXPointMode = type { float, float, float, float, %struct.XXPointLineLimits, float, i8, i8, i8, i8, i16, i16, i32, i16, i16 } - %struct.XXPolygonMode = type { [128 x i8], float, float, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXProgramData = type { i32, i32, i32, i32, %struct.PPStreamToken*, i32*, i32, i32, i32, i32, i8, i8, i8, i8, [0 x i32] } - %struct.XXProgramLimits = type { i32, i32, i32, i32 } - %struct.XXProgramRec = type { %struct.XXProgramData*, %struct.XXPluginProgramData*, %struct.ZZIColor4**, i32 } - %struct.XXQueryRec = type { i32, i32, %struct.XXQueryRec* } - %struct.XXRect = type { i32, i32, i32, i32, i32, i32 } - %struct.XXRegisterCombiners = type { i8, i8, i8, i8, i32, [2 x %struct.ZZIColor4], [8 x %struct.XXRegisterCombinersPerStageState], %struct.XXRegisterCombinersFinalStageState } - %struct.XXRegisterCombinersFinalStageState = type { i8, i8, i8, i8, [7 x %struct.XXRegisterCombinersPerVariableState] } - %struct.XXRegisterCombinersPerPortionState = type { [4 x %struct.XXRegisterCombinersPerVariableState], i8, i8, i8, i8, i16, i16, i16, i16, i16, i16 } - %struct.XXRegisterCombinersPerStageState = type { [2 x %struct.XXRegisterCombinersPerPortionState], [2 x %struct.ZZIColor4] } - %struct.XXRegisterCombinersPerVariableState = type { i16, i16, i16, i16 } - %struct.XXRenderDispatch = type { void (%struct.XXContextRec*, i32, float)*, void (%struct.XXContextRec*, i32)*, i32 (%struct.XXContextRec*, i32, i32, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, i32 (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, i32, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32, float, float, i8*, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex*, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32, i32)*, void (%struct.XXContextRec*, %struct.XXVertex**, i32, i32)*, i8* (%struct.XXContextRec*, i32, i32*)*, void (%struct.XXContextRec*, i32, i32, i32)*, i8* (%struct.XXContextRec*, i32, i32, i32, i32, i32)*, void (%struct.XXContextRec*, i32, i32, i32, i32, i32, i8*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*, %struct.XXFenceRec*)*, void (%struct.XXContextRec*, i32, %struct.XXQueryRec*)*, void (%struct.XXContextRec*, %struct.XXQueryRec*)*, i32 (%struct.XXContextRec*, i32, i32, i32, i32, i32, i8*, %struct.ZZIColor4*, %struct.XXCurrent16A*)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i32, %struct.XXBBRec*)*, i32 (%struct.XXContextRec*, %struct.XXTextureRec*, i32)*, i32 (%struct.XXContextRec*, %struct.XXBBRec*, i32, i32, i8*)*, void (%struct.XXContextRec*, i32)*, void (%struct.XXContextRec*)*, void (%struct.XXContextRec*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32)*, i32 (%struct.XXContextRec*, %struct.XXQueryRec*)*, void (%struct.XXContextRec*)* } - %struct.XXRenderFeatures = type { i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8 } - %struct.XXSWRSurfaceRec = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i8*, [4 x i8*], i32 } - %struct.XXScissorTest = type { %struct.XXProgramLimits, i8, i8, i8, i8 } - %struct.XXSharedData = type { } - %struct.XXSharedRec = type { %struct.__ZZarrayelementDrawInfoListType, %struct.XXSharedData*, i32, i8, i8, i8, i8 } - %struct.XXState = type <{ i16, i16, i16, i16, i32, i32, [256 x %struct.ZZIColor4], [128 x %struct.ZZIColor4], %struct.XXViewport, %struct.XXTransform, %struct.XXLightModel, %struct.XXActiveTextureTargets, %struct.XXAlphaTest, %struct.XXBlendMode, %struct.XXClearColor, %struct.XXColorBB, %struct.XXDepthTest, %struct.XXArrayRange, %struct.XXFogMode, %struct.XXHintMode, %struct.XXLineMode, %struct.XXLogicOp, %struct.XXMaskMode, %struct.XXPixelMode, %struct.XXPointMode, %struct.XXPolygonMode, %struct.XXScissorTest, i32, %struct.XXStencilTest, [8 x %struct.XXTextureMode], [16 x %struct.XXTextureImageMode], %struct.XXArrayRange, [8 x %struct.XXTextureCoordGen], %struct.XXClipPlane, %struct.XXMultisample, %struct.XXRegisterCombiners, %struct.XXArrayRange, %struct.XXArrayRange, [3 x %struct.XXPipelineProgramState], %struct.XXArrayRange, %struct.XXTransformFeedback, i32*, %struct.XXFixedFunction, [1 x i32] }> - %struct.XXStencilTest = type { [3 x { i32, i32, i16, i16, i16, i16 }], i32, [4 x i8] } - %struct.XXStippleData = type { i32, i16, i16, [32 x [32 x i8]] } - %struct.XXTextureCoordGen = type { { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, { i16, i16, %struct.ZZIColor4, %struct.ZZIColor4 }, i8, i8, i8, i8 } - %struct.XXTextureGeomState = type { i16, i16, i16, i16, i16, i8, i8, i8, i8, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, i8, [6 x i16], [6 x i16] } - %struct.XXTextureImageMode = type { float } - %struct.XXTextureLevel = type { i32, i32, i16, i16, i16, i8, i8, i16, i16, i16, i16, i8* } - %struct.XXTextureLimits = type { float, float, i16, i16, i16, i16, i16, i16, i16, i16, i16, i8, i8, [16 x i16], i32 } - %struct.XXTextureMode = type { %struct.ZZIColor4, i32, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, i16, float, float, i16, i16, i16, i16, i16, i16, [4 x i16], i8, i8, i8, i8, [3 x float], [4 x float], float, float } - %struct.XXTextureParamState = type { i16, i16, i16, i16, i16, i16, %struct.ZZIColor4, float, float, float, float, i16, i16, i16, i16, float, i16, i8, i8, i32, i8* } - %struct.XXTextureRec = type { [4 x float], %struct.XXTextureState*, %struct.XXMipmaplevel*, %struct.XXMipmaplevel*, float, float, float, float, i8, i8, i8, i8, i16, i16, i16, i16, i32, float, [2 x %struct.PPStreamToken] } - %struct.XXTextureState = type { i16, i8, i8, i16, i16, float, i32, %struct.XXSWRSurfaceRec*, %struct.XXTextureParamState, %struct.XXTextureGeomState, i16, i16, i8*, %struct.XXTextureLevel, [1 x [15 x %struct.XXTextureLevel]] } - %struct.XXTransform = type <{ [24 x [16 x float]], [24 x [16 x float]], [16 x float], float, float, float, float, float, i8, i8, i8, i8, i32, i32, i32, i16, i16, i8, i8, i8, i8, i32 }> - %struct.XXTransformFeedback = type { i8, i8, i8, i8, [0 x i32], [16 x i32], [16 x i32] } - %struct.XXVertex = type { %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.ZZIColor4, %struct.XXPointLineLimits, float, %struct.ZZIColor4, float, i8, i8, i8, i8, float, float, i32, i32, i32, i32, [4 x float], [2 x %struct.XXMaterial*], [2 x i32], [8 x %struct.ZZIColor4] } - %struct.XXVertexArrayRec = type opaque - %struct.XXVertexDescriptor = type { i8, i8, i8, i8, [0 x i32] } - %struct.XXVertexProgramLimits = type { i16, i16, i32, i32 } - %struct.XXViewport = type { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, double, double, i32, i32, i32, i32, float, float, float, float } - %struct.ZZGColorTable = type { i32, i32, i32, i8* } - %struct.ZZGOperation = type { i8*, i8*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, float, %struct.ZZGColorTable, %struct.ZZGColorTable, %struct.ZZGColorTable } - %struct.ZZGProcessor = type { void (%struct.XXPixelMode*, %struct.ZZGOperation*, %struct._ZZGProcessorData*, %union._ZZGFunctionKey*)*, %struct._YYFunction*, %union._ZZGFunctionKey*, %struct._ZZGProcessorData* } - %struct.ZZGTransformKey = type { i32, i32 } - %struct.ZZIColor4 = type { float, float, float, float } - %struct.ZZSBB = type { i8* } - %struct.ZZSDrawable = type { %struct.ZZSWindowRec* } - %struct.ZZSWindowRec = type { %struct.ZZGTransformKey, %struct.ZZGTransformKey, i32, i32, %struct.ZZSDrawable, i8*, i8*, i8*, i8*, i8*, [4 x i8*], i32, i16, i16, i16, i16, i8, i8, i8, i8, i8, i8, i8, i8, %struct.XXDrawableWindow, i32, i32, i8*, i8* } - %struct.ZZTCoord2 = type { float, float } - %struct.YYFPContext = type { float, i32, i32, i32, float, [3 x float] } - %struct.YYFragmentAttrib = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, [8 x <4 x float>] } - %struct.YYTextures = type { [16 x %struct.XXTextureRec*] } - %struct.PPStreamToken = type { { i16, i16, i32 } } - %struct._ZZGProcessorData = type { void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32)*, void (i8*, i8*, i32, i32, i32, i32, i32, i32, i32)*, i8* (i32)*, void (i8*)* } - %struct._YYConstants = type { <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, <4 x float>, float, float, float, float, float, float, float, float, float, float, float, float, [256 x float], [4096 x i8], [8 x float], [48 x float], [128 x float], [528 x i8], { void (i8*, i8*, i32, i8*)*, float (float)*, float (float)*, float (float)*, i32 (float)* } } - %struct._YYFunction = type opaque - %struct.__ZZarrayelementDrawInfoListType = type { i32, [40 x i8] } - %union._ZZGFunctionKey = type opaque -@llvm.used = appending global [1 x i8*] [ i8* bitcast (void (%struct.XXContextRec*, i32, i32, %struct.YYFragmentAttrib*, %struct.YYFragmentAttrib*, i32)* @t to i8*) ], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] - -define void @t(%struct.XXContextRec* %ctx, i32 %x, i32 %y, %struct.YYFragmentAttrib* %start, %struct.YYFragmentAttrib* %deriv, i32 %num_frags) nounwind { -entry: - %tmp7485.i.i.i = xor <4 x i32> zeroinitializer, < i32 -1, i32 -1, i32 -1, i32 -1 > ; <<4 x i32>> [#uses=1] - %tmp8382.i.i.i = extractelement <4 x i32> zeroinitializer, i32 1 ; <i32> [#uses=1] - %tmp8383.i.i.i = extractelement <4 x i32> zeroinitializer, i32 2 ; <i32> [#uses=2] - %tmp8384.i.i.i = extractelement <4 x i32> zeroinitializer, i32 3 ; <i32> [#uses=2] - br label %bb7551.i.i.i - -bb4426.i.i.i: ; preds = %bb7551.i.i.i - %0 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8383.i.i.i, i32 3 ; <[4 x i32]*> [#uses=1] - %1 = bitcast [4 x i32]* %0 to <4 x i32>* ; <<4 x i32>*> [#uses=1] - %2 = load <4 x i32>* %1, align 16 ; <<4 x i32>> [#uses=1] - %3 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8384.i.i.i, i32 3 ; <[4 x i32]*> [#uses=1] - %4 = bitcast [4 x i32]* %3 to <4 x i32>* ; <<4 x i32>*> [#uses=1] - %5 = load <4 x i32>* %4, align 16 ; <<4 x i32>> [#uses=1] - %6 = shufflevector <4 x i32> %2, <4 x i32> %5, <4 x i32> < i32 0, i32 4, i32 1, i32 5 > ; <<4 x i32>> [#uses=1] - %7 = bitcast <4 x i32> %6 to <2 x i64> ; <<2 x i64>> [#uses=1] - %8 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %7, <2 x i32> < i32 1, i32 3 > ; <<2 x i64>> [#uses=1] - %9 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8382.i.i.i, i32 6 ; <float**> [#uses=1] - %10 = load float** %9, align 4 ; <float*> [#uses=1] - %11 = bitcast float* %10 to i8* ; <i8*> [#uses=1] - %12 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8383.i.i.i, i32 6 ; <float**> [#uses=1] - %13 = load float** %12, align 4 ; <float*> [#uses=1] - %14 = bitcast float* %13 to i8* ; <i8*> [#uses=1] - %15 = getelementptr %struct.XXMipmaplevel* null, i32 %tmp8384.i.i.i, i32 6 ; <float**> [#uses=1] - %16 = load float** %15, align 4 ; <float*> [#uses=1] - %17 = bitcast float* %16 to i8* ; <i8*> [#uses=1] - %tmp7308.i.i.i = and <2 x i64> zeroinitializer, %8 ; <<2 x i64>> [#uses=1] - %18 = bitcast <2 x i64> %tmp7308.i.i.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %19 = mul <4 x i32> %18, zeroinitializer ; <<4 x i32>> [#uses=1] - %20 = add <4 x i32> %19, zeroinitializer ; <<4 x i32>> [#uses=3] - %21 = load i32* null, align 4 ; <i32> [#uses=0] - %22 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> zeroinitializer) nounwind readnone ; <<4 x float>> [#uses=1] - %23 = fmul <4 x float> %22, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2114.i119.i.i = extractelement <4 x i32> %20, i32 1 ; <i32> [#uses=1] - %24 = shl i32 %tmp2114.i119.i.i, 2 ; <i32> [#uses=1] - %25 = getelementptr i8* %11, i32 %24 ; <i8*> [#uses=1] - %26 = bitcast i8* %25 to i32* ; <i32*> [#uses=1] - %27 = load i32* %26, align 4 ; <i32> [#uses=1] - %28 = or i32 %27, -16777216 ; <i32> [#uses=1] - %tmp1927.i120.i.i = insertelement <4 x i32> undef, i32 %28, i32 0 ; <<4 x i32>> [#uses=1] - %29 = bitcast <4 x i32> %tmp1927.i120.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %30 = shufflevector <16 x i8> %29, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %31 = bitcast <16 x i8> %30 to <8 x i16> ; <<8 x i16>> [#uses=1] - %32 = shufflevector <8 x i16> %31, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %33 = bitcast <8 x i16> %32 to <4 x i32> ; <<4 x i32>> [#uses=1] - %34 = shufflevector <4 x i32> %33, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %35 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %34) nounwind readnone ; <<4 x float>> [#uses=1] - %36 = fmul <4 x float> %35, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2113.i124.i.i = extractelement <4 x i32> %20, i32 2 ; <i32> [#uses=1] - %37 = shl i32 %tmp2113.i124.i.i, 2 ; <i32> [#uses=1] - %38 = getelementptr i8* %14, i32 %37 ; <i8*> [#uses=1] - %39 = bitcast i8* %38 to i32* ; <i32*> [#uses=1] - %40 = load i32* %39, align 4 ; <i32> [#uses=1] - %41 = or i32 %40, -16777216 ; <i32> [#uses=1] - %tmp1963.i125.i.i = insertelement <4 x i32> undef, i32 %41, i32 0 ; <<4 x i32>> [#uses=1] - %42 = bitcast <4 x i32> %tmp1963.i125.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %43 = shufflevector <16 x i8> %42, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %44 = bitcast <16 x i8> %43 to <8 x i16> ; <<8 x i16>> [#uses=1] - %45 = shufflevector <8 x i16> %44, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %46 = bitcast <8 x i16> %45 to <4 x i32> ; <<4 x i32>> [#uses=1] - %47 = shufflevector <4 x i32> %46, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %48 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %47) nounwind readnone ; <<4 x float>> [#uses=1] - %49 = fmul <4 x float> %48, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %tmp2112.i129.i.i = extractelement <4 x i32> %20, i32 3 ; <i32> [#uses=1] - %50 = shl i32 %tmp2112.i129.i.i, 2 ; <i32> [#uses=1] - %51 = getelementptr i8* %17, i32 %50 ; <i8*> [#uses=1] - %52 = bitcast i8* %51 to i32* ; <i32*> [#uses=1] - %53 = load i32* %52, align 4 ; <i32> [#uses=1] - %54 = or i32 %53, -16777216 ; <i32> [#uses=1] - %tmp1999.i130.i.i = insertelement <4 x i32> undef, i32 %54, i32 0 ; <<4 x i32>> [#uses=1] - %55 = bitcast <4 x i32> %tmp1999.i130.i.i to <16 x i8> ; <<16 x i8>> [#uses=1] - %56 = shufflevector <16 x i8> %55, <16 x i8> < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef >, <16 x i32> < i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23 > ; <<16 x i8>> [#uses=1] - %57 = bitcast <16 x i8> %56 to <8 x i16> ; <<8 x i16>> [#uses=1] - %58 = shufflevector <8 x i16> %57, <8 x i16> < i16 0, i16 0, i16 0, i16 0, i16 undef, i16 undef, i16 undef, i16 undef >, <8 x i32> < i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11 > ; <<8 x i16>> [#uses=1] - %59 = bitcast <8 x i16> %58 to <4 x i32> ; <<4 x i32>> [#uses=1] - %60 = shufflevector <4 x i32> %59, <4 x i32> undef, <4 x i32> < i32 2, i32 1, i32 0, i32 3 > ; <<4 x i32>> [#uses=1] - %61 = call <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32> %60) nounwind readnone ; <<4 x float>> [#uses=1] - %62 = fmul <4 x float> %61, < float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000, float 0x3F70101020000000 > ; <<4 x float>> [#uses=1] - %63 = fmul <4 x float> %23, zeroinitializer ; <<4 x float>> [#uses=1] - %64 = fadd <4 x float> zeroinitializer, %63 ; <<4 x float>> [#uses=1] - %65 = fmul <4 x float> %36, zeroinitializer ; <<4 x float>> [#uses=1] - %66 = fadd <4 x float> zeroinitializer, %65 ; <<4 x float>> [#uses=1] - %67 = fmul <4 x float> %49, zeroinitializer ; <<4 x float>> [#uses=1] - %68 = fadd <4 x float> zeroinitializer, %67 ; <<4 x float>> [#uses=1] - %69 = fmul <4 x float> %62, zeroinitializer ; <<4 x float>> [#uses=1] - %70 = fadd <4 x float> zeroinitializer, %69 ; <<4 x float>> [#uses=1] - %tmp7452.i.i.i = bitcast <4 x float> %64 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7454.i.i.i = and <4 x i32> %tmp7452.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7459.i.i.i = or <4 x i32> %tmp7454.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7460.i.i.i = bitcast <4 x i32> %tmp7459.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7468.i.i.i = bitcast <4 x float> %66 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7470.i.i.i = and <4 x i32> %tmp7468.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7475.i.i.i = or <4 x i32> %tmp7470.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7476.i.i.i = bitcast <4 x i32> %tmp7475.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7479.i.i.i = bitcast <4 x float> %.279.1.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7480.i.i.i = and <4 x i32> zeroinitializer, %tmp7479.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7484.i.i.i = bitcast <4 x float> %68 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7486.i.i.i = and <4 x i32> %tmp7484.i.i.i, %tmp7485.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7491.i.i.i = or <4 x i32> %tmp7486.i.i.i, %tmp7480.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7492.i.i.i = bitcast <4 x i32> %tmp7491.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %tmp7495.i.i.i = bitcast <4 x float> %.380.1.i to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7496.i.i.i = and <4 x i32> zeroinitializer, %tmp7495.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7500.i.i.i = bitcast <4 x float> %70 to <4 x i32> ; <<4 x i32>> [#uses=1] - %tmp7502.i.i.i = and <4 x i32> %tmp7500.i.i.i, zeroinitializer ; <<4 x i32>> [#uses=1] - %tmp7507.i.i.i = or <4 x i32> %tmp7502.i.i.i, %tmp7496.i.i.i ; <<4 x i32>> [#uses=1] - %tmp7508.i.i.i = bitcast <4 x i32> %tmp7507.i.i.i to <4 x float> ; <<4 x float>> [#uses=1] - %indvar.next.i.i.i = add i32 %aniso.0.i.i.i, 1 ; <i32> [#uses=1] - br label %bb7551.i.i.i - -bb7551.i.i.i: ; preds = %bb4426.i.i.i, %entry - %.077.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7460.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=0] - %.178.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7476.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=0] - %.279.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7492.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=1] - %.380.1.i = phi <4 x float> [ undef, %entry ], [ %tmp7508.i.i.i, %bb4426.i.i.i ] ; <<4 x float>> [#uses=1] - %aniso.0.i.i.i = phi i32 [ 0, %entry ], [ %indvar.next.i.i.i, %bb4426.i.i.i ] ; <i32> [#uses=1] - br i1 false, label %glvmInterpretFPTransformFour6.exit, label %bb4426.i.i.i - -glvmInterpretFPTransformFour6.exit: ; preds = %bb7551.i.i.i - unreachable -} - -declare <4 x float> @llvm.x86.sse2.cvtdq2ps(<4 x i32>) nounwind readnone diff --git a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll index 2e148ad..d64c966 100644 --- a/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll +++ b/test/CodeGen/X86/2009-02-12-InlineAsm-nieZ-constraints.ll @@ -1,18 +1,24 @@ -; RUN: llc < %s -march=x86 | grep {\$-81920} | count 3 -; RUN: llc < %s -march=x86 | grep {\$4294885376} | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s ; ModuleID = 'shant.c' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin9.6" define void @f() nounwind { -entry: +; CHECK: f: +; CHECK-NOT: ret +; CHECK: foo $-81920 +; CHECK-NOT: ret +; CHECK: foo $-81920 +; CHECK-NOT: ret +; CHECK: foo $-81920 +; CHECK-NOT: ret +; CHECK: foo $4294885376 +; CHECK: ret + call void asm sideeffect "foo $0", "n,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind call void asm sideeffect "foo $0", "i,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind call void asm sideeffect "foo $0", "e,~{dirflag},~{fpsr},~{flags}"(i32 -81920) nounwind call void asm sideeffect "foo $0", "Z,~{dirflag},~{fpsr},~{flags}"(i64 4294885376) nounwind - br label %return - -return: ; preds = %entry ret void } diff --git a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll b/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll deleted file mode 100644 index f739216..0000000 --- a/test/CodeGen/X86/2009-04-20-LinearScanOpt.ll +++ /dev/null @@ -1,121 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin10.0 -relocation-model=pic -disable-fp-elim -stats |& grep asm-printer | grep 77 -; rdar://6802189 - -; Test if linearscan is unfavoring registers for allocation to allow more reuse -; of reloads from stack slots. - - %struct.SHA_CTX = type { i32, i32, i32, i32, i32, i32, i32, [16 x i32], i32 } - -define fastcc void @sha1_block_data_order(%struct.SHA_CTX* nocapture %c, i8* %p, i64 %num) nounwind { -entry: - br label %bb - -bb: ; preds = %bb, %entry - %asmtmp511 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=3] - %asmtmp513 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=2] - %asmtmp516 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=1] - %asmtmp517 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2] - %0 = xor i32 0, %asmtmp513 ; <i32> [#uses=0] - %1 = add i32 0, %asmtmp517 ; <i32> [#uses=1] - %2 = add i32 %1, 0 ; <i32> [#uses=1] - %3 = add i32 %2, 0 ; <i32> [#uses=1] - %asmtmp519 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 0) nounwind ; <i32> [#uses=1] - %4 = xor i32 0, %asmtmp511 ; <i32> [#uses=1] - %asmtmp520 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %4) nounwind ; <i32> [#uses=2] - %5 = xor i32 0, %asmtmp516 ; <i32> [#uses=1] - %6 = xor i32 %5, %asmtmp519 ; <i32> [#uses=1] - %7 = add i32 %asmtmp513, -899497514 ; <i32> [#uses=1] - %8 = add i32 %7, %asmtmp520 ; <i32> [#uses=1] - %9 = add i32 %8, %6 ; <i32> [#uses=1] - %10 = add i32 %9, 0 ; <i32> [#uses=1] - %asmtmp523 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=1] - %asmtmp525 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %3) nounwind ; <i32> [#uses=2] - %11 = xor i32 0, %asmtmp525 ; <i32> [#uses=1] - %12 = add i32 0, %11 ; <i32> [#uses=1] - %13 = add i32 %12, 0 ; <i32> [#uses=2] - %asmtmp528 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %10) nounwind ; <i32> [#uses=1] - %14 = xor i32 0, %asmtmp520 ; <i32> [#uses=1] - %asmtmp529 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %14) nounwind ; <i32> [#uses=1] - %asmtmp530 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %13) nounwind ; <i32> [#uses=1] - %15 = add i32 0, %asmtmp530 ; <i32> [#uses=1] - %16 = xor i32 0, %asmtmp523 ; <i32> [#uses=1] - %asmtmp532 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %16) nounwind ; <i32> [#uses=2] - %asmtmp533 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %15) nounwind ; <i32> [#uses=1] - %17 = xor i32 %13, %asmtmp528 ; <i32> [#uses=1] - %18 = xor i32 %17, 0 ; <i32> [#uses=1] - %19 = add i32 %asmtmp525, -899497514 ; <i32> [#uses=1] - %20 = add i32 %19, %asmtmp532 ; <i32> [#uses=1] - %21 = add i32 %20, %18 ; <i32> [#uses=1] - %22 = add i32 %21, %asmtmp533 ; <i32> [#uses=1] - %23 = xor i32 0, %asmtmp511 ; <i32> [#uses=1] - %24 = xor i32 %23, 0 ; <i32> [#uses=1] - %asmtmp535 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %24) nounwind ; <i32> [#uses=3] - %25 = add i32 0, %asmtmp535 ; <i32> [#uses=1] - %26 = add i32 %25, 0 ; <i32> [#uses=1] - %27 = add i32 %26, 0 ; <i32> [#uses=1] - %28 = xor i32 0, %asmtmp529 ; <i32> [#uses=0] - %29 = xor i32 %22, 0 ; <i32> [#uses=1] - %30 = xor i32 %29, 0 ; <i32> [#uses=1] - %31 = add i32 0, %30 ; <i32> [#uses=1] - %32 = add i32 %31, 0 ; <i32> [#uses=3] - %asmtmp541 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2] - %asmtmp542 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %32) nounwind ; <i32> [#uses=1] - %33 = add i32 0, %asmtmp541 ; <i32> [#uses=1] - %34 = add i32 %33, 0 ; <i32> [#uses=1] - %35 = add i32 %34, %asmtmp542 ; <i32> [#uses=1] - %asmtmp543 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %27) nounwind ; <i32> [#uses=2] - %36 = xor i32 0, %asmtmp535 ; <i32> [#uses=0] - %37 = xor i32 %32, 0 ; <i32> [#uses=1] - %38 = xor i32 %37, %asmtmp543 ; <i32> [#uses=1] - %39 = add i32 0, %38 ; <i32> [#uses=1] - %40 = add i32 %39, 0 ; <i32> [#uses=2] - %asmtmp546 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %32) nounwind ; <i32> [#uses=1] - %asmtmp547 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 0) nounwind ; <i32> [#uses=2] - %41 = add i32 0, -899497514 ; <i32> [#uses=1] - %42 = add i32 %41, %asmtmp547 ; <i32> [#uses=1] - %43 = add i32 %42, 0 ; <i32> [#uses=1] - %44 = add i32 %43, 0 ; <i32> [#uses=3] - %asmtmp549 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %35) nounwind ; <i32> [#uses=2] - %45 = xor i32 0, %asmtmp541 ; <i32> [#uses=1] - %asmtmp550 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %45) nounwind ; <i32> [#uses=2] - %asmtmp551 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 5, i32 %44) nounwind ; <i32> [#uses=1] - %46 = xor i32 %40, %asmtmp546 ; <i32> [#uses=1] - %47 = xor i32 %46, %asmtmp549 ; <i32> [#uses=1] - %48 = add i32 %asmtmp543, -899497514 ; <i32> [#uses=1] - %49 = add i32 %48, %asmtmp550 ; <i32> [#uses=1] - %50 = add i32 %49, %47 ; <i32> [#uses=1] - %51 = add i32 %50, %asmtmp551 ; <i32> [#uses=1] - %asmtmp552 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %40) nounwind ; <i32> [#uses=2] - %52 = xor i32 %44, %asmtmp549 ; <i32> [#uses=1] - %53 = xor i32 %52, %asmtmp552 ; <i32> [#uses=1] - %54 = add i32 0, %53 ; <i32> [#uses=1] - %55 = add i32 %54, 0 ; <i32> [#uses=2] - %asmtmp555 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %44) nounwind ; <i32> [#uses=2] - %56 = xor i32 0, %asmtmp532 ; <i32> [#uses=1] - %57 = xor i32 %56, %asmtmp547 ; <i32> [#uses=1] - %asmtmp556 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %57) nounwind ; <i32> [#uses=1] - %58 = add i32 0, %asmtmp556 ; <i32> [#uses=1] - %59 = add i32 %58, 0 ; <i32> [#uses=1] - %60 = add i32 %59, 0 ; <i32> [#uses=1] - %asmtmp558 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %51) nounwind ; <i32> [#uses=1] - %61 = xor i32 %asmtmp517, %asmtmp511 ; <i32> [#uses=1] - %62 = xor i32 %61, %asmtmp535 ; <i32> [#uses=1] - %63 = xor i32 %62, %asmtmp550 ; <i32> [#uses=1] - %asmtmp559 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i32 %63) nounwind ; <i32> [#uses=1] - %64 = xor i32 %55, %asmtmp555 ; <i32> [#uses=1] - %65 = xor i32 %64, %asmtmp558 ; <i32> [#uses=1] - %asmtmp561 = tail call i32 asm "roll $1,$0", "=r,I,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 30, i32 %55) nounwind ; <i32> [#uses=1] - %66 = add i32 %asmtmp552, -899497514 ; <i32> [#uses=1] - %67 = add i32 %66, %65 ; <i32> [#uses=1] - %68 = add i32 %67, %asmtmp559 ; <i32> [#uses=1] - %69 = add i32 %68, 0 ; <i32> [#uses=1] - %70 = add i32 %69, 0 ; <i32> [#uses=1] - store i32 %70, i32* null, align 4 - %71 = add i32 0, %60 ; <i32> [#uses=1] - store i32 %71, i32* null, align 4 - %72 = add i32 0, %asmtmp561 ; <i32> [#uses=1] - store i32 %72, i32* null, align 4 - %73 = add i32 0, %asmtmp555 ; <i32> [#uses=1] - store i32 %73, i32* null, align 4 - br label %bb -} diff --git a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll index 1e7a418..0700323 100644 --- a/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll +++ b/test/CodeGen/X86/2009-12-01-EarlyClobberBug.ll @@ -22,8 +22,11 @@ return: ; preds = %entry define void @t2() nounwind ssp { entry: ; CHECK: t2: -; CHECK: movl %eax, %ecx -; CHECK: %ecx = foo (%ecx, %eax) +; CHECK: movl +; CHECK: [[D2:%e.x]] = foo +; CHECK: ([[D2]], +; CHECK-NOT: [[D2]] +; CHECK: ) %b = alloca i32 ; <i32*> [#uses=2] %a = alloca i32 ; <i32*> [#uses=1] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] diff --git a/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll b/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll index c5d3d16..739a27a 100644 --- a/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll +++ b/test/CodeGen/X86/2010-02-12-CoalescerBug-Impdef.ll @@ -22,6 +22,7 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\ %0 = type { %"union gimple_statement_d"* } %"BITMAP_WORD[]" = type [2 x i64] +%"uchar[]" = type [1 x i8] %"char[]" = type [4 x i8] %"enum dom_state[]" = type [2 x i32] %"int[]" = type [4 x i32] @@ -61,6 +62,7 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\ %"struct gimple_seq_d" = type { %"struct gimple_seq_node_d"*, %"struct gimple_seq_node_d"*, %"struct gimple_seq_d"* } %"struct gimple_seq_node_d" = type { %"union gimple_statement_d"*, %"struct gimple_seq_node_d"*, %"struct gimple_seq_node_d"* } %"struct gimple_statement_base" = type { i8, i8, i16, i32, i32, i32, %"struct basic_block_def"*, %"union tree_node"* } +%"struct phi_arg_d[]" = type [1 x %"struct phi_arg_d"] %"struct gimple_statement_phi" = type { %"struct gimple_statement_base", i32, i32, %"union tree_node"*, %"struct phi_arg_d[]" } %"struct htab" = type { i32 (i8*)*, i32 (i8*, i8*)*, void (i8*)*, i8**, i64, i64, i64, i32, i32, i8* (i64, i64)*, void (i8*)*, i8*, i8* (i8*, i64, i64)*, void (i8*, i8*)*, i32 } %"struct iv" = type { %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, %"union tree_node"*, i8, i8, i32 } @@ -78,7 +80,6 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\ %"struct object_block" = type { %"union section"*, i32, i64, %"struct VEC_rtx_gc"*, %"struct VEC_rtx_gc"* } %"struct obstack" = type { i64, %"struct _obstack_chunk"*, i8*, i8*, i8*, i64, i32, %"struct _obstack_chunk"* (i8*, i64)*, void (i8*, %"struct _obstack_chunk"*)*, i8*, i8 } %"struct phi_arg_d" = type { %"struct ssa_use_operand_d", %"union tree_node"*, i32 } -%"struct phi_arg_d[]" = type [1 x %"struct phi_arg_d"] %"struct pointer_map_t" = type opaque %"struct pt_solution" = type { i8, %"struct bitmap_head_def"* } %"struct rtx_def" = type { i16, i8, i8, %"union u" } @@ -98,7 +99,6 @@ module asm "\09.ident\09\22GCC: (GNU) 4.5.0 20100212 (experimental) LLVM: 95975\ %"struct unnamed_section" = type { %"struct section_common", void (i8*)*, i8*, %"union section"* } %"struct use_optype_d" = type { %"struct use_optype_d"*, %"struct ssa_use_operand_d" } %"struct version_info" = type { %"union tree_node"*, %"struct iv"*, i8, i32, i8 } -%"uchar[]" = type [1 x i8] %"union basic_block_il_dependent" = type { %"struct gimple_bb_info"* } %"union edge_def_insns" = type { %"struct gimple_seq_d"* } %"union gimple_statement_d" = type { %"struct gimple_statement_phi" } diff --git a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll index 1c7c28c..9a5958e 100644 --- a/test/CodeGen/X86/2010-04-08-CoalescerBug.ll +++ b/test/CodeGen/X86/2010-04-08-CoalescerBug.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s ; rdar://7842028 ; Do not delete partially dead copy instructions. diff --git a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll index bb1db59..05f581a 100644 --- a/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll +++ b/test/CodeGen/X86/2010-06-25-CoalescerSubRegDefDead.ll @@ -1,4 +1,4 @@ -; RUN: llc -O1 -mtriple=x86_64-unknown-linux-gnu -relocation-model=pic -disable-fp-elim < %s | FileCheck %s +; RUN: llc -O1 -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -relocation-model=pic -disable-fp-elim < %s | FileCheck %s ; <rdar://problem/8124405> %struct.type = type { %struct.subtype*, i32, i8, i32, i8, i32, i32, i32, i32, i32, i8, i32, i32, i32, i32, i32, [256 x i32], i32, [257 x i32], [257 x i32], i32*, i16*, i8*, i32, i32, i32, i32, i32, [256 x i8], [16 x i8], [256 x i8], [4096 x i8], [16 x i32], [18002 x i8], [18002 x i8], [6 x [258 x i8]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x [258 x i32]], [6 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32*, i32*, i32* } diff --git a/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll b/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll index be7d94c..e96da94 100644 --- a/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll +++ b/test/CodeGen/X86/2010-07-11-FPStackLoneUse.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mcpu=i486 +; RUN: llc < %s -mcpu=core2 ; PR7375 ; ; This function contains a block (while.cond) with a lonely RFP use that is diff --git a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll index eaede30..1b33977 100644 --- a/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll +++ b/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -combiner-alias-analysis -march=x86-64 | FileCheck %s +; RUN: llc < %s -combiner-alias-analysis -march=x86-64 -mcpu=core2 | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.4" diff --git a/test/CodeGen/X86/2010-11-09-MOVLPS.ll b/test/CodeGen/X86/2010-11-09-MOVLPS.ll index 2368f3f..710cb86 100644 --- a/test/CodeGen/X86/2010-11-09-MOVLPS.ll +++ b/test/CodeGen/X86/2010-11-09-MOVLPS.ll @@ -5,11 +5,11 @@ target triple = "x86_64-unknown-linux-gnu" module asm "\09.ident\09\22GCC: (GNU) 4.5.2 20100914 (prerelease) LLVM: 114628\22" +%"int[]" = type [4 x i32] %0 = type { %"int[]" } %float = type float %"float[]" = type [4 x float] %int = type i32 -%"int[]" = type [4 x i32] %"long unsigned int" = type i64 define void @swizzle(i8* %a, %0* %b, %0* %c) nounwind { diff --git a/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll index 07b1971..c6f4b49 100644 --- a/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll +++ b/test/CodeGen/X86/2011-04-13-SchedCmpJmp.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=yonah | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s ; Reduced from JavaScriptCore %"class.JSC::CodeLocationCall" = type { [8 x i8] } diff --git a/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll new file mode 100644 index 0000000..7632034 --- /dev/null +++ b/test/CodeGen/X86/2011-07-13-BadFrameIndexDisplacement.ll @@ -0,0 +1,20 @@ +; RUN: llc -march=x86-64 < %s -disable-fp-elim | FileCheck %s + +; This test is checking that we don't crash and we don't incorrectly fold +; a large displacement and a frame index into a single lea. +; <rdar://problem/9763308> + +declare void @bar([39 x i8]*) +define i32 @f(i64 %a, i64 %b) nounwind readnone { +entry: + %stack_main = alloca [39 x i8] + call void @bar([39 x i8]* %stack_main) + %tmp6 = add i64 %a, -2147483647 + %.sum = add i64 %tmp6, %b + %tmp8 = getelementptr inbounds [39 x i8]* %stack_main, i64 0, i64 %.sum + %tmp9 = load i8* %tmp8, align 1 + %tmp10 = sext i8 %tmp9 to i32 + ret i32 %tmp10 +} +; CHECK: f: +; CHECK: movsbl -2147483647 diff --git a/test/CodeGen/X86/allrem-moddi3.ll b/test/CodeGen/X86/allrem-moddi3.ll new file mode 100644 index 0000000..0c3d04f --- /dev/null +++ b/test/CodeGen/X86/allrem-moddi3.ll @@ -0,0 +1,19 @@ +; Test that, for a 64 bit signed rem, a libcall to allrem is made on Windows +; unless we have libgcc. + +; RUN: llc < %s -mtriple i386-pc-win32 | FileCheck %s +; RUN: llc < %s -mtriple i386-pc-cygwin | FileCheck %s -check-prefix USEMODDI +; RUN: llc < %s -mtriple i386-pc-mingw32 | FileCheck %s -check-prefix USEMODDI +; PR10305 +; END. + +define i32 @main(i32 %argc, i8** nocapture %argv) nounwind readonly { +entry: + %conv4 = sext i32 %argc to i64 + %div = srem i64 84, %conv4 + %conv7 = trunc i64 %div to i32 + ret i32 %conv7 +} + +; CHECK: allrem +; USEMODDI: moddi3 diff --git a/test/CodeGen/X86/asm-global-imm.ll b/test/CodeGen/X86/asm-global-imm.ll index 96da224..6c569d6 100644 --- a/test/CodeGen/X86/asm-global-imm.ll +++ b/test/CodeGen/X86/asm-global-imm.ll @@ -1,7 +1,4 @@ -; RUN: llc < %s -march=x86 -relocation-model=static | \ -; RUN: grep {test1 \$_GV} -; RUN: llc < %s -march=x86 -relocation-model=static | \ -; RUN: grep {test2 _GV} +; RUN: llc < %s -march=x86 -relocation-model=static | FileCheck %s ; PR882 target datalayout = "e-p:32:32" @@ -10,7 +7,13 @@ target triple = "i686-apple-darwin9.0.0d2" @str = external global [12 x i8] ; <[12 x i8]*> [#uses=1] define void @foo() { -entry: +; CHECK: foo: +; CHECK-NOT: ret +; CHECK: test1 $_GV +; CHECK-NOT: ret +; CHECK: test2 _GV +; CHECK: ret + tail call void asm sideeffect "test1 $0", "i,~{dirflag},~{fpsr},~{flags}"( i32* @GV ) tail call void asm sideeffect "test2 ${0:c}", "i,~{dirflag},~{fpsr},~{flags}"( i32* @GV ) ret void diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll index 9db6f6f..164252d 100644 --- a/test/CodeGen/X86/atomic-or.ll +++ b/test/CodeGen/X86/atomic-or.ll @@ -11,7 +11,7 @@ entry: ; CHECK: t1: ; CHECK: movl $2147483648, %eax ; CHECK: lock -; CHECK-NEXT: orq %rax, (%rdi) +; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}}) %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648) call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) ret void @@ -26,7 +26,7 @@ entry: ; CHECK: t2: ; CHECK-NOT: movl ; CHECK: lock -; CHECK-NEXT: orq $2147483644, (%rdi) +; CHECK-NEXT: orq $2147483644, (%r{{.*}}) %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483644) call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) ret void diff --git a/test/CodeGen/X86/avx-128.ll b/test/CodeGen/X86/avx-128.ll index c29cb5d..57a3826 100644 --- a/test/CodeGen/X86/avx-128.ll +++ b/test/CodeGen/X86/avx-128.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -march=x86 -mcpu=corei7 -mattr=avx | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s @z = common global <4 x float> zeroinitializer, align 16 @@ -20,3 +20,35 @@ entry: store double %conv, double* %d, align 8 ret void } + +; CHECK: vcvtsi2sdq (% +define double @funcA(i64* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i64* %e, align 8 + %conv = sitofp i64 %tmp1 to double + ret double %conv +} + +; CHECK: vcvtsi2sd (% +define double @funcB(i32* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i32* %e, align 4 + %conv = sitofp i32 %tmp1 to double + ret double %conv +} + +; CHECK: vcvtsi2ss (% +define float @funcC(i32* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i32* %e, align 4 + %conv = sitofp i32 %tmp1 to float + ret float %conv +} + +; CHECK: vcvtsi2ssq (% +define float @funcD(i64* nocapture %e) nounwind uwtable readonly ssp { +entry: + %tmp1 = load i64* %e, align 8 + %conv = sitofp i64 %tmp1 to float + ret float %conv +} diff --git a/test/CodeGen/X86/avx-256-arith.ll b/test/CodeGen/X86/avx-256-arith.ll new file mode 100644 index 0000000..5c512db --- /dev/null +++ b/test/CodeGen/X86/avx-256-arith.ll @@ -0,0 +1,116 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vaddpd +define <4 x double> @addpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <4 x double> %x, %y + ret <4 x double> %add.i +} + +; CHECK: vaddpd LCP{{.*}}(%rip) +define <4 x double> @addpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00> + ret <4 x double> %add.i +} + +; CHECK: vaddps +define <8 x float> @addps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <8 x float> %x, %y + ret <8 x float> %add.i +} + +; CHECK: vaddps LCP{{.*}}(%rip) +define <8 x float> @addps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %add.i = fadd <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000> + ret <8 x float> %add.i +} + +; CHECK: vsubpd +define <4 x double> @subpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %sub.i = fsub <4 x double> %x, %y + ret <4 x double> %sub.i +} + +; CHECK: vsubpd (% +define <4 x double> @subpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp { +entry: + %tmp2 = load <4 x double>* %x, align 32 + %sub.i = fsub <4 x double> %y, %tmp2 + ret <4 x double> %sub.i +} + +; CHECK: vsubps +define <8 x float> @subps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %sub.i = fsub <8 x float> %x, %y + ret <8 x float> %sub.i +} + +; CHECK: vsubps (% +define <8 x float> @subps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp { +entry: + %tmp2 = load <8 x float>* %x, align 32 + %sub.i = fsub <8 x float> %y, %tmp2 + ret <8 x float> %sub.i +} + +; CHECK: vmulpd +define <4 x double> @mulpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %mul.i = fmul <4 x double> %x, %y + ret <4 x double> %mul.i +} + +; CHECK: vmulpd LCP{{.*}}(%rip) +define <4 x double> @mulpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %mul.i = fmul <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00> + ret <4 x double> %mul.i +} + +; CHECK: vmulps +define <8 x float> @mulps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %mul.i = fmul <8 x float> %x, %y + ret <8 x float> %mul.i +} + +; CHECK: vmulps LCP{{.*}}(%rip) +define <8 x float> @mulps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %mul.i = fmul <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000> + ret <8 x float> %mul.i +} + +; CHECK: vdivpd +define <4 x double> @divpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %div.i = fdiv <4 x double> %x, %y + ret <4 x double> %div.i +} + +; CHECK: vdivpd LCP{{.*}}(%rip) +define <4 x double> @divpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %div.i = fdiv <4 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00> + ret <4 x double> %div.i +} + +; CHECK: vdivps +define <8 x float> @divps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %div.i = fdiv <8 x float> %x, %y + ret <8 x float> %div.i +} + +; CHECK: vdivps LCP{{.*}}(%rip) +define <8 x float> @divps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %div.i = fdiv <8 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000> + ret <8 x float> %div.i +} + diff --git a/test/CodeGen/X86/avx-256-arith.s b/test/CodeGen/X86/avx-256-arith.s new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/test/CodeGen/X86/avx-256-arith.s diff --git a/test/CodeGen/X86/avx-256-logic.ll b/test/CodeGen/X86/avx-256-logic.ll new file mode 100644 index 0000000..d9e5d08 --- /dev/null +++ b/test/CodeGen/X86/avx-256-logic.ll @@ -0,0 +1,161 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vandpd +define <4 x double> @andpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %x to <4 x i64> + %1 = bitcast <4 x double> %y to <4 x i64> + %and.i = and <4 x i64> %0, %1 + %2 = bitcast <4 x i64> %and.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vandpd LCP{{.*}}(%rip) +define <4 x double> @andpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %y to <4 x i64> + %and.i = and <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> + %1 = bitcast <4 x i64> %and.i to <4 x double> + ret <4 x double> %1 +} + +; CHECK: vandps +define <8 x float> @andps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %x to <8 x i32> + %1 = bitcast <8 x float> %y to <8 x i32> + %and.i = and <8 x i32> %0, %1 + %2 = bitcast <8 x i32> %and.i to <8 x float> + ret <8 x float> %2 +} + +; CHECK: vandps LCP{{.*}}(%rip) +define <8 x float> @andps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %y to <8 x i32> + %and.i = and <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938> + %1 = bitcast <8 x i32> %and.i to <8 x float> + ret <8 x float> %1 +} + +; CHECK: vxorpd +define <4 x double> @xorpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %x to <4 x i64> + %1 = bitcast <4 x double> %y to <4 x i64> + %xor.i = xor <4 x i64> %0, %1 + %2 = bitcast <4 x i64> %xor.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vxorpd LCP{{.*}}(%rip) +define <4 x double> @xorpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %y to <4 x i64> + %xor.i = xor <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> + %1 = bitcast <4 x i64> %xor.i to <4 x double> + ret <4 x double> %1 +} + +; CHECK: vxorps +define <8 x float> @xorps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %x to <8 x i32> + %1 = bitcast <8 x float> %y to <8 x i32> + %xor.i = xor <8 x i32> %0, %1 + %2 = bitcast <8 x i32> %xor.i to <8 x float> + ret <8 x float> %2 +} + +; CHECK: vxorps LCP{{.*}}(%rip) +define <8 x float> @xorps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %y to <8 x i32> + %xor.i = xor <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938> + %1 = bitcast <8 x i32> %xor.i to <8 x float> + ret <8 x float> %1 +} + +; CHECK: vorpd +define <4 x double> @orpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %x to <4 x i64> + %1 = bitcast <4 x double> %y to <4 x i64> + %or.i = or <4 x i64> %0, %1 + %2 = bitcast <4 x i64> %or.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vorpd LCP{{.*}}(%rip) +define <4 x double> @orpd256fold(<4 x double> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %y to <4 x i64> + %or.i = or <4 x i64> %0, <i64 4616752568008179712, i64 4614838538166547251, i64 4612361558371493478, i64 4608083138725491507> + %1 = bitcast <4 x i64> %or.i to <4 x double> + ret <4 x double> %1 +} + +; CHECK: vorps +define <8 x float> @orps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %x to <8 x i32> + %1 = bitcast <8 x float> %y to <8 x i32> + %or.i = or <8 x i32> %0, %1 + %2 = bitcast <8 x i32> %or.i to <8 x float> + ret <8 x float> %2 +} + +; CHECK: vorps LCP{{.*}}(%rip) +define <8 x float> @orps256fold(<8 x float> %y) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %y to <8 x i32> + %or.i = or <8 x i32> %0, <i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938, i32 1083179008, i32 1079613850, i32 1075000115, i32 1067030938> + %1 = bitcast <8 x i32> %or.i to <8 x float> + ret <8 x float> %1 +} + +; CHECK: vandnpd +define <4 x double> @andnotpd256(<4 x double> %y, <4 x double> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <4 x double> %x to <4 x i64> + %neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1> + %1 = bitcast <4 x double> %y to <4 x i64> + %and.i = and <4 x i64> %1, %neg.i + %2 = bitcast <4 x i64> %and.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vandnpd (% +define <4 x double> @andnotpd256fold(<4 x double> %y, <4 x double>* nocapture %x) nounwind uwtable readonly ssp { +entry: + %tmp2 = load <4 x double>* %x, align 32 + %0 = bitcast <4 x double> %y to <4 x i64> + %neg.i = xor <4 x i64> %0, <i64 -1, i64 -1, i64 -1, i64 -1> + %1 = bitcast <4 x double> %tmp2 to <4 x i64> + %and.i = and <4 x i64> %1, %neg.i + %2 = bitcast <4 x i64> %and.i to <4 x double> + ret <4 x double> %2 +} + +; CHECK: vandnps +define <8 x float> @andnotps256(<8 x float> %y, <8 x float> %x) nounwind uwtable readnone ssp { +entry: + %0 = bitcast <8 x float> %x to <8 x i32> + %neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> + %1 = bitcast <8 x float> %y to <8 x i32> + %and.i = and <8 x i32> %1, %neg.i + %2 = bitcast <8 x i32> %and.i to <8 x float> + ret <8 x float> %2 +} + +; CHECK: vandnps (% +define <8 x float> @andnotps256fold(<8 x float> %y, <8 x float>* nocapture %x) nounwind uwtable readonly ssp { +entry: + %tmp2 = load <8 x float>* %x, align 32 + %0 = bitcast <8 x float> %y to <8 x i32> + %neg.i = xor <8 x i32> %0, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1> + %1 = bitcast <8 x float> %tmp2 to <8 x i32> + %and.i = and <8 x i32> %1, %neg.i + %2 = bitcast <8 x i32> %and.i to <8 x float> + ret <8 x float> %2 +} diff --git a/test/CodeGen/X86/avx-load-store.ll b/test/CodeGen/X86/avx-load-store.ll new file mode 100644 index 0000000..5196089 --- /dev/null +++ b/test/CodeGen/X86/avx-load-store.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; CHECK: vmovaps +; CHECK: vmovaps +; CHECK: vmovapd +; CHECK: vmovapd +; CHECK: vmovaps +; CHECK: vmovaps +define void @test_256_load(double* nocapture %d, float* nocapture %f, <4 x i64>* nocapture %i) nounwind uwtable ssp { +entry: + %0 = bitcast double* %d to <4 x double>* + %tmp1.i = load <4 x double>* %0, align 32 + %1 = bitcast float* %f to <8 x float>* + %tmp1.i17 = load <8 x float>* %1, align 32 + %tmp1.i16 = load <4 x i64>* %i, align 32 + tail call void @dummy(<4 x double> %tmp1.i, <8 x float> %tmp1.i17, <4 x i64> %tmp1.i16) nounwind + store <4 x double> %tmp1.i, <4 x double>* %0, align 32 + store <8 x float> %tmp1.i17, <8 x float>* %1, align 32 + store <4 x i64> %tmp1.i16, <4 x i64>* %i, align 32 + ret void +} + +declare void @dummy(<4 x double>, <8 x float>, <4 x i64>) + diff --git a/test/CodeGen/X86/change-compare-stride-0.ll b/test/CodeGen/X86/change-compare-stride-0.ll index d520a6f..3a383ee 100644 --- a/test/CodeGen/X86/change-compare-stride-0.ll +++ b/test/CodeGen/X86/change-compare-stride-0.ll @@ -1,11 +1,14 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep {cmpl \$-478,} %t -; RUN: not grep inc %t -; RUN: not grep {leal 1(} %t -; RUN: not grep {leal -1(} %t -; RUN: grep dec %t | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind { +; CHECK: borf: +; CHECK-NOT: inc +; CHECK-NOT: leal 1( +; CHECK-NOT: leal -1( +; CHECK: decl +; CHECK-NEXT: cmpl $-478 +; CHECK: ret + bb4.thread: br label %bb2.outer diff --git a/test/CodeGen/X86/change-compare-stride-1.ll b/test/CodeGen/X86/change-compare-stride-1.ll index a9ddbdb..eee3b79 100644 --- a/test/CodeGen/X86/change-compare-stride-1.ll +++ b/test/CodeGen/X86/change-compare-stride-1.ll @@ -1,11 +1,14 @@ -; RUN: llc < %s -march=x86-64 > %t -; RUN: grep {cmpq \$-478,} %t -; RUN: not grep inc %t -; RUN: not grep {leal 1(} %t -; RUN: not grep {leal -1(} %t -; RUN: grep dec %t | count 1 +; RUN: llc < %s -march=x86-64 | FileCheck %s define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind { +; CHECK: borf: +; CHECK-NOT: inc +; CHECK-NOT: leal 1( +; CHECK-NOT: leal -1( +; CHECK: decq +; CHECK-NEXT: cmpq $-478 +; CHECK: ret + bb4.thread: br label %bb2.outer diff --git a/test/CodeGen/X86/change-compare-stride-trickiness-1.ll b/test/CodeGen/X86/change-compare-stride-trickiness-1.ll index cb63809..a3933e2 100644 --- a/test/CodeGen/X86/change-compare-stride-trickiness-1.ll +++ b/test/CodeGen/X86/change-compare-stride-trickiness-1.ll @@ -1,6 +1,4 @@ -; RUN: llc %s -o - --x86-asm-syntax=att | grep {cmp. \$10} -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-apple-darwin9" +; RUN: llc -march=x86 < %s | FileCheck %s ; The comparison happens after the relevant use, so the stride can easily ; be changed. The comparison can be done in a narrower mode than the @@ -9,6 +7,11 @@ target triple = "x86_64-apple-darwin9" ; could be made simpler. define void @foo() nounwind { +; CHECK: foo: +; CHECK-NOT: ret +; CHECK: cmpl $10 +; CHECK: ret + entry: br label %loop diff --git a/test/CodeGen/X86/crash.ll b/test/CodeGen/X86/crash.ll index 7c4e64c..b5b1ad4 100644 --- a/test/CodeGen/X86/crash.ll +++ b/test/CodeGen/X86/crash.ll @@ -215,3 +215,104 @@ bb2: } declare i64 @llvm.objectsize.i64(i8*, i1) nounwind readnone + +; PR10277 +; This test has dead code elimination caused by remat during spilling. +; DCE causes a live interval to break into connected components. +; One of the components is spilled. + +%t2 = type { i8 } +%t9 = type { %t10 } +%t10 = type { %t11 } +%t11 = type { %t12 } +%t12 = type { %t13*, %t13*, %t13* } +%t13 = type { %t14*, %t15, %t15 } +%t14 = type opaque +%t15 = type { i8, i32, i32 } +%t16 = type { %t17, i8* } +%t17 = type { %t18 } +%t18 = type { %t19 } +%t19 = type { %t20*, %t20*, %t20* } +%t20 = type { i32, i32 } +%t21 = type { %t13* } + +define void @_ZNK4llvm17MipsFrameLowering12emitPrologueERNS_15MachineFunctionE() ssp align 2 { +bb: + %tmp = load %t9** undef, align 4, !tbaa !0 + %tmp2 = getelementptr inbounds %t9* %tmp, i32 0, i32 0 + %tmp3 = getelementptr inbounds %t9* %tmp, i32 0, i32 0, i32 0, i32 0, i32 1 + br label %bb4 + +bb4: ; preds = %bb37, %bb + %tmp5 = phi i96 [ undef, %bb ], [ %tmp38, %bb37 ] + %tmp6 = phi i96 [ undef, %bb ], [ %tmp39, %bb37 ] + br i1 undef, label %bb34, label %bb7 + +bb7: ; preds = %bb4 + %tmp8 = load i32* undef, align 4 + %tmp9 = and i96 %tmp6, 4294967040 + %tmp10 = zext i32 %tmp8 to i96 + %tmp11 = shl nuw nsw i96 %tmp10, 32 + %tmp12 = or i96 %tmp9, %tmp11 + %tmp13 = or i96 %tmp12, 1 + %tmp14 = load i32* undef, align 4 + %tmp15 = and i96 %tmp5, 4294967040 + %tmp16 = zext i32 %tmp14 to i96 + %tmp17 = shl nuw nsw i96 %tmp16, 32 + %tmp18 = or i96 %tmp15, %tmp17 + %tmp19 = or i96 %tmp18, 1 + %tmp20 = load i8* undef, align 1 + %tmp21 = and i8 %tmp20, 1 + %tmp22 = icmp ne i8 %tmp21, 0 + %tmp23 = select i1 %tmp22, i96 %tmp19, i96 %tmp13 + %tmp24 = select i1 %tmp22, i96 %tmp13, i96 %tmp19 + store i96 %tmp24, i96* undef, align 4 + %tmp25 = load %t13** %tmp3, align 4 + %tmp26 = icmp eq %t13* %tmp25, undef + br i1 %tmp26, label %bb28, label %bb27 + +bb27: ; preds = %bb7 + br label %bb29 + +bb28: ; preds = %bb7 + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + br label %bb29 + +bb29: ; preds = %bb28, %bb27 + store i96 %tmp23, i96* undef, align 4 + %tmp30 = load %t13** %tmp3, align 4 + br i1 false, label %bb33, label %bb31 + +bb31: ; preds = %bb29 + %tmp32 = getelementptr inbounds %t13* %tmp30, i32 1 + store %t13* %tmp32, %t13** %tmp3, align 4 + br label %bb37 + +bb33: ; preds = %bb29 + unreachable + +bb34: ; preds = %bb4 + br i1 undef, label %bb36, label %bb35 + +bb35: ; preds = %bb34 + store %t13* null, %t13** %tmp3, align 4 + br label %bb37 + +bb36: ; preds = %bb34 + call void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10* %tmp2, %t21* byval align 4 undef, %t13* undef) + br label %bb37 + +bb37: ; preds = %bb36, %bb35, %bb31 + %tmp38 = phi i96 [ %tmp23, %bb31 ], [ %tmp5, %bb35 ], [ %tmp5, %bb36 ] + %tmp39 = phi i96 [ %tmp24, %bb31 ], [ %tmp6, %bb35 ], [ %tmp6, %bb36 ] + %tmp40 = add i32 undef, 1 + br label %bb4 +} + +declare %t14* @_ZN4llvm9MCContext16CreateTempSymbolEv(%t2*) + +declare void @_ZNSt6vectorIN4llvm11MachineMoveESaIS1_EE13_M_insert_auxEN9__gnu_cxx17__normal_iteratorIPS1_S3_EERKS1_(%t10*, %t21* byval align 4, %t13*) + +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind + +declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind diff --git a/test/CodeGen/X86/dag-rauw-cse.ll b/test/CodeGen/X86/dag-rauw-cse.ll index edcfeb7..eca8c86 100644 --- a/test/CodeGen/X86/dag-rauw-cse.ll +++ b/test/CodeGen/X86/dag-rauw-cse.ll @@ -1,7 +1,11 @@ -; RUN: llc < %s -march=x86 | grep {orl \$1} +; RUN: llc < %s -march=x86 | FileCheck %s ; PR3018 define i32 @test(i32 %A) nounwind { +; CHECK: test: +; CHECK-NOT: ret +; CHECK: orl $1 +; CHECK: ret %B = or i32 %A, 1 %C = or i32 %B, 1 %D = and i32 %C, 7057 diff --git a/test/CodeGen/X86/divide-by-constant.ll b/test/CodeGen/X86/divide-by-constant.ll index 08e3272..87c1be5 100644 --- a/test/CodeGen/X86/divide-by-constant.ll +++ b/test/CodeGen/X86/divide-by-constant.ll @@ -40,7 +40,7 @@ entry: %div = sdiv i16 %x, 33 ; <i32> [#uses=1] ret i16 %div ; CHECK: test4: -; CHECK: imull $1986, %eax, %eax +; CHECK: imull $1986, %eax, % } define i32 @test5(i32 %A) nounwind { diff --git a/test/CodeGen/X86/fma.ll b/test/CodeGen/X86/fma.ll new file mode 100644 index 0000000..5deedb9 --- /dev/null +++ b/test/CodeGen/X86/fma.ll @@ -0,0 +1,33 @@ +; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 | FileCheck %s + +; CHECK: test_f32 +; CHECK: _fmaf + +define float @test_f32(float %a, float %b, float %c) nounwind readnone ssp { +entry: + %call = tail call float @llvm.fma.f32(float %a, float %b, float %c) nounwind readnone + ret float %call +} + +; CHECK: test_f64 +; CHECK: _fma + +define double @test_f64(double %a, double %b, double %c) nounwind readnone ssp { +entry: + %call = tail call double @llvm.fma.f64(double %a, double %b, double %c) nounwind readnone + ret double %call +} + +; CHECK: test_f80 +; CHECK: _fmal + +define x86_fp80 @test_f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) nounwind readnone ssp { +entry: + %call = tail call x86_fp80 @llvm.fma.f80(x86_fp80 %a, x86_fp80 %b, x86_fp80 %c) nounwind readnone + ret x86_fp80 %call +} + +declare float @llvm.fma.f32(float, float, float) nounwind readnone +declare double @llvm.fma.f64(double, double, double) nounwind readnone +declare x86_fp80 @llvm.fma.f80(x86_fp80, x86_fp80, x86_fp80) nounwind readnone diff --git a/test/CodeGen/X86/fold-add.ll b/test/CodeGen/X86/fold-add.ll index 5e80ea5..63e7d36 100644 --- a/test/CodeGen/X86/fold-add.ll +++ b/test/CodeGen/X86/fold-add.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | grep {cmpb \$0, (%r.\*,%r.\*)} +; RUN: llc < %s -march=x86-64 | FileCheck %s target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" target triple = "x86_64-apple-darwin9.6" @@ -7,6 +7,11 @@ target triple = "x86_64-apple-darwin9.6" @llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32)* @longest_match to i8*)] ; <[1 x i8*]*> [#uses=0] define fastcc i32 @longest_match(i32 %cur_match) nounwind { +; CHECK: longest_match: +; CHECK-NOT: ret +; CHECK: cmpb $0, (%r{{.*}},%r{{.*}}) +; CHECK: ret + entry: %0 = load i32* @prev_length, align 4 ; <i32> [#uses=3] %1 = zext i32 %cur_match to i64 ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/fp-stack-2results.ll b/test/CodeGen/X86/fp-stack-2results.ll index e986e36..c8da9ea 100644 --- a/test/CodeGen/X86/fp-stack-2results.ll +++ b/test/CodeGen/X86/fp-stack-2results.ll @@ -5,7 +5,7 @@ ; This is basically this code on x86-64: ; _Complex long double test() { return 1.0; } -define {x86_fp80, x86_fp80} @test() { +define %0 @test() { %A = fpext double 1.0 to x86_fp80 %B = fpext double 0.0 to x86_fp80 %mrv = insertvalue %0 undef, x86_fp80 %A, 0 @@ -18,7 +18,7 @@ define {x86_fp80, x86_fp80} @test() { ; fld1 ; fld %st(0) ; ret -define {x86_fp80, x86_fp80} @test2() { +define %0 @test2() { %A = fpext double 1.0 to x86_fp80 %mrv = insertvalue %0 undef, x86_fp80 %A, 0 %mrv1 = insertvalue %0 %mrv, x86_fp80 %A, 1 @@ -27,39 +27,39 @@ define {x86_fp80, x86_fp80} @test2() { ; Uses both values. define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) { - %a = call {x86_fp80,x86_fp80} @test() - %b = extractvalue {x86_fp80,x86_fp80} %a, 0 + %a = call %0 @test() + %b = extractvalue %0 %a, 0 store x86_fp80 %b, x86_fp80* %P1 - %c = extractvalue {x86_fp80,x86_fp80} %a, 1 + %c = extractvalue %0 %a, 1 store x86_fp80 %c, x86_fp80* %P2 ret void } ; Uses both values, requires fxch define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) { - %a = call {x86_fp80,x86_fp80} @test() - %b = extractvalue {x86_fp80,x86_fp80} %a, 1 + %a = call %0 @test() + %b = extractvalue %0 %a, 1 store x86_fp80 %b, x86_fp80* %P1 - %c = extractvalue {x86_fp80,x86_fp80} %a, 0 + %c = extractvalue %0 %a, 0 store x86_fp80 %c, x86_fp80* %P2 ret void } ; Uses ST(0), ST(1) is dead but must be popped. define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) { - %a = call {x86_fp80,x86_fp80} @test() - %b = extractvalue {x86_fp80,x86_fp80} %a, 0 + %a = call %0 @test() + %b = extractvalue %0 %a, 0 store x86_fp80 %b, x86_fp80* %P1 ret void } ; Uses ST(1), ST(0) is dead and must be popped. define void @call4(x86_fp80 *%P1, x86_fp80 *%P2) { - %a = call {x86_fp80,x86_fp80} @test() + %a = call %0 @test() - %c = extractvalue {x86_fp80,x86_fp80} %a, 1 + %c = extractvalue %0 %a, 1 store x86_fp80 %c, x86_fp80* %P2 ret void } diff --git a/test/CodeGen/X86/h-registers-2.ll b/test/CodeGen/X86/h-registers-2.ll index 16e13f8..488444c 100644 --- a/test/CodeGen/X86/h-registers-2.ll +++ b/test/CodeGen/X86/h-registers-2.ll @@ -1,14 +1,19 @@ -; RUN: llc < %s -march=x86 > %t -; RUN: grep {movzbl %\[abcd\]h,} %t | count 1 -; RUN: grep {shll \$3,} %t | count 1 +; RUN: llc < %s -march=x86 | FileCheck %s ; Use an h register, but don't omit the explicit shift for ; non-address use(s). define i32 @foo(i8* %x, i32 %y) nounwind { +; CHECK: foo: +; CHECK-NOT: ret +; CHECK: movzbl %{{[abcd]h}}, +; CHECK-NOT: ret +; CHECK: shll $3, +; CHECK: ret + %t0 = lshr i32 %y, 8 ; <i32> [#uses=1] %t1 = and i32 %t0, 255 ; <i32> [#uses=2] - %t2 = shl i32 %t1, 3 + %t2 = shl i32 %t1, 3 %t3 = getelementptr i8* %x, i32 %t2 ; <i8*> [#uses=1] store i8 77, i8* %t3, align 4 ret i32 %t2 diff --git a/test/CodeGen/X86/inline-asm-error.ll b/test/CodeGen/X86/inline-asm-error.ll index 29c5ae5..134d6e9 100644 --- a/test/CodeGen/X86/inline-asm-error.ll +++ b/test/CodeGen/X86/inline-asm-error.ll @@ -5,10 +5,8 @@ ; RUN: FileCheck %s < %t2 ; RUN: FileCheck %s < %t3 -; The register allocator must fail on this function, and it should print the -; inline asm in the diagnostic. -; CHECK: LLVM ERROR: Ran out of registers during register allocation! -; CHECK: INLINEASM <es:hello world> +; The register allocator must fail on this function. +; CHECK: error: ran out of registers during register allocation define void @f(i32 %x0, i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32 %x5, i32 %x6, i32 %x7, i32 %x8, i32 %x9) nounwind ssp { entry: diff --git a/test/CodeGen/X86/inline-asm-q-regs.ll b/test/CodeGen/X86/inline-asm-q-regs.ll index 321fd30..1c8e2f9 100644 --- a/test/CodeGen/X86/inline-asm-q-regs.ll +++ b/test/CodeGen/X86/inline-asm-q-regs.ll @@ -3,8 +3,20 @@ %0 = type { i64, i64, i64, i64, i64 } ; type %0 -define void @t() nounwind { +define void @test1() nounwind { entry: %asmtmp = call %0 asm sideeffect "mov %cr0, $0 \0Amov %cr2, $1 \0Amov %cr3, $2 \0Amov %cr4, $3 \0Amov %cr8, $0 \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind ; <%0> [#uses=0] ret void } + +; PR9602 +define void @test2(float %tmp) nounwind { + call void asm sideeffect "$0", "q"(float %tmp) nounwind + call void asm sideeffect "$0", "Q"(float %tmp) nounwind + ret void +} + +define void @test3(double %tmp) nounwind { + call void asm sideeffect "$0", "q"(double %tmp) nounwind + ret void +} diff --git a/test/CodeGen/X86/inline-asm.ll b/test/CodeGen/X86/inline-asm.ll index c66d7a8..eef6c2f 100644 --- a/test/CodeGen/X86/inline-asm.ll +++ b/test/CodeGen/X86/inline-asm.ll @@ -23,3 +23,23 @@ define void @test4() nounwind { tail call void asm sideeffect "bork $0", "J"(i32 37) nounwind ret void } + +; rdar://9738585 +define i32 @test5() nounwind { +entry: + %0 = tail call i32 asm "test", "=l,~{dirflag},~{fpsr},~{flags}"() nounwind + ret i32 0 +} + +; rdar://9777108 PR10352 +define void @test6(i1 zeroext %desired) nounwind { +entry: + tail call void asm sideeffect "foo $0", "q,~{dirflag},~{fpsr},~{flags}"(i1 %desired) nounwind + ret void +} + +define void @test7(i1 zeroext %desired, i32* %p) nounwind { +entry: + %0 = tail call i8 asm sideeffect "xchg $0, $1", "=r,*m,0,~{memory},~{dirflag},~{fpsr},~{flags}"(i32* %p, i1 %desired) nounwind + ret void +} diff --git a/test/CodeGen/X86/isel-sink.ll b/test/CodeGen/X86/isel-sink.ll index 0f94b23..d275533 100644 --- a/test/CodeGen/X86/isel-sink.ll +++ b/test/CodeGen/X86/isel-sink.ll @@ -1,8 +1,14 @@ -; RUN: llc < %s -march=x86 | not grep lea -; RUN: llc < %s -march=x86 -mtriple=i686-apple-darwin8 | \ -; RUN: grep {movl \$4, (.*,.*,4)} +; RUN: llc < %s -march=x86 | FileCheck %s define i32 @test(i32* %X, i32 %B) { +; CHECK: test: +; CHECK-NOT: ret +; CHECK-NOT: lea +; CHECK: mov{{.}} $4, ({{.*}},{{.*}},4) +; CHECK: ret +; CHECK: mov{{.}} ({{.*}},{{.*}},4), +; CHECK: ret + ; This gep should be sunk out of this block into the load/store users. %P = getelementptr i32* %X, i32 %B %G = icmp ult i32 %B, 1234 @@ -14,5 +20,3 @@ F: %V = load i32* %P ret i32 %V } - - diff --git a/test/CodeGen/X86/loop-strength-reduce2.ll b/test/CodeGen/X86/loop-strength-reduce2.ll index 9b53adb..689ee1c 100644 --- a/test/CodeGen/X86/loop-strength-reduce2.ll +++ b/test/CodeGen/X86/loop-strength-reduce2.ll @@ -1,6 +1,7 @@ -; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic | grep {\$pb} | grep mov +; RUN: llc < %s -mtriple=i686-apple-darwin -relocation-model=pic | FileCheck %s ; ; Make sure the PIC label flags2-"L1$pb" is not moved up to the preheader. +; CHECK: mov{{.}} {{.*}}$pb @flags2 = internal global [8193 x i8] zeroinitializer, align 32 ; <[8193 x i8]*> [#uses=1] diff --git a/test/CodeGen/X86/lsr-nonaffine.ll b/test/CodeGen/X86/lsr-nonaffine.ll index 4771646..d0d2bbd 100644 --- a/test/CodeGen/X86/lsr-nonaffine.ll +++ b/test/CodeGen/X86/lsr-nonaffine.ll @@ -1,4 +1,4 @@ -; RUN: llc -asm-verbose=false -march=x86-64 -o - < %s | FileCheck %s +; RUN: llc -asm-verbose=false -march=x86-64 -mtriple=x86_64-apple-darwin -o - < %s | FileCheck %s ; LSR should leave non-affine expressions alone because it currently ; doesn't know how to do anything with them, and when it tries, it diff --git a/test/CodeGen/X86/lsr-redundant-addressing.ll b/test/CodeGen/X86/lsr-redundant-addressing.ll index aaa1426..cb0ac8b 100644 --- a/test/CodeGen/X86/lsr-redundant-addressing.ll +++ b/test/CodeGen/X86/lsr-redundant-addressing.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=x86-64 < %s | fgrep {addq $-16,} | count 1 +; RUN: llc -march=x86-64 < %s | FileCheck %s ; rdar://9081094 ; LSR shouldn't create lots of redundant address computations. @@ -10,6 +10,12 @@ @isa = external hidden unnamed_addr constant [13 x %1], align 32 define void @main_bb.i() nounwind { +; CHECK: main_bb.i: +; CHECK-NOT: ret +; CHECK: addq $-16, +; CHECK-NOT: ret +; CHECK: ret + bb: br label %bb38 diff --git a/test/CodeGen/X86/lsr-reuse-trunc.ll b/test/CodeGen/X86/lsr-reuse-trunc.ll index 4770519..1f87089 100644 --- a/test/CodeGen/X86/lsr-reuse-trunc.ll +++ b/test/CodeGen/X86/lsr-reuse-trunc.ll @@ -5,8 +5,9 @@ ; stick with indexing here. ; CHECK: movaps (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]] -; CHECK: movaps -; CHECK: [[X3]], (%{{rdi|rcx}},%rax,4) +; CHECK: cvtdq2ps +; CHECK: orps {{%xmm[0-9]+}}, [[X4:%xmm[0-9]+]] +; CHECK: movaps [[X4]], (%{{rdi|rcx}},%rax,4) ; CHECK: addq $4, %rax ; CHECK: cmpl %eax, (%{{rdx|r8}}) ; CHECK-NEXT: jg diff --git a/test/CodeGen/X86/membarrier.ll b/test/CodeGen/X86/membarrier.ll new file mode 100644 index 0000000..42f8ef5 --- /dev/null +++ b/test/CodeGen/X86/membarrier.ll @@ -0,0 +1,15 @@ +; RUN: llc < %s -march=x86-64 -mattr=-sse -O0 +; PR9675 + +define i32 @t() { +entry: + %i = alloca i32, align 4 + store i32 1, i32* %i, align 4 + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + %0 = call i32 @llvm.atomic.load.sub.i32.p0i32(i32* %i, i32 1) + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + ret i32 0 +} + +declare i32 @llvm.atomic.load.sub.i32.p0i32(i32* nocapture, i32) nounwind +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind diff --git a/test/CodeGen/X86/memcpy.ll b/test/CodeGen/X86/memcpy.ll index 72342cb..f43b0bf 100644 --- a/test/CodeGen/X86/memcpy.ll +++ b/test/CodeGen/X86/memcpy.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=LINUX -; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=DARWIN +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 | FileCheck %s -check-prefix=LINUX +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=DARWIN declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind diff --git a/test/CodeGen/X86/peep-test-3.ll b/test/CodeGen/X86/peep-test-3.ll index a34a978..528c4bc 100644 --- a/test/CodeGen/X86/peep-test-3.ll +++ b/test/CodeGen/X86/peep-test-3.ll @@ -9,7 +9,7 @@ entry: %0 = ptrtoint float* %A to i32 ; <i32> [#uses=1] %1 = and i32 %0, 3 ; <i32> [#uses=1] %2 = xor i32 %IA, 1 ; <i32> [#uses=1] -; CHECK: orl %ecx, %edx +; CHECK: orl %e ; CHECK-NEXT: je %3 = or i32 %2, %1 ; <i32> [#uses=1] %4 = icmp eq i32 %3, 0 ; <i1> [#uses=1] diff --git a/test/CodeGen/X86/pic_jumptable.ll b/test/CodeGen/X86/pic_jumptable.ll index b6761e3..8c16dc6 100644 --- a/test/CodeGen/X86/pic_jumptable.ll +++ b/test/CodeGen/X86/pic_jumptable.ll @@ -1,11 +1,14 @@ -; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false | grep -F .text._Z3fooILi1EEvi,"axG",@progbits,_Z3fooILi1EEvi,comdat -; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false | FileCheck %s +; RUN: llc < %s -relocation-model=pic -mtriple=i386-linux-gnu -asm-verbose=false \ +; RUN: | FileCheck %s --check-prefix=CHECK-LINUX +; RUN: llc < %s -relocation-model=pic -mtriple=i686-apple-darwin -asm-verbose=false \ +; RUN: | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin | not grep 'lJTI' ; rdar://6971437 ; rdar://7738756 declare void @_Z3bari(i32) +; CHECK-LINUX: .text._Z3fooILi1EEvi,"axG",@progbits,_Z3fooILi1EEvi,comdat define linkonce void @_Z3fooILi1EEvi(i32 %Y) nounwind { entry: ; CHECK: L0$pb diff --git a/test/CodeGen/X86/pr2182.ll b/test/CodeGen/X86/pr2182.ll index f97663c..2a8bb35 100644 --- a/test/CodeGen/X86/pr2182.ll +++ b/test/CodeGen/X86/pr2182.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep {addl \$3, (%eax)} | count 4 +; RUN: llc < %s | FileCheck %s ; PR2182 target datalayout = @@ -7,18 +7,25 @@ target triple = "i386-apple-darwin8" @x = weak global i32 0 ; <i32*> [#uses=8] define void @loop_2() nounwind { -entry: - %tmp = volatile load i32* @x, align 4 ; <i32> [#uses=1] - %tmp1 = add i32 %tmp, 3 ; <i32> [#uses=1] - volatile store i32 %tmp1, i32* @x, align 4 - %tmp.1 = volatile load i32* @x, align 4 ; <i32> [#uses=1] - %tmp1.1 = add i32 %tmp.1, 3 ; <i32> [#uses=1] - volatile store i32 %tmp1.1, i32* @x, align 4 - %tmp.2 = volatile load i32* @x, align 4 ; <i32> [#uses=1] - %tmp1.2 = add i32 %tmp.2, 3 ; <i32> [#uses=1] - volatile store i32 %tmp1.2, i32* @x, align 4 - %tmp.3 = volatile load i32* @x, align 4 ; <i32> [#uses=1] - %tmp1.3 = add i32 %tmp.3, 3 ; <i32> [#uses=1] - volatile store i32 %tmp1.3, i32* @x, align 4 - ret void +; CHECK: loop_2: +; CHECK-NOT: ret +; CHECK: addl $3, (%{{.*}}) +; CHECK-NEXT: addl $3, (%{{.*}}) +; CHECK-NEXT: addl $3, (%{{.*}}) +; CHECK-NEXT: addl $3, (%{{.*}}) +; CHECK-NEXT: ret + + %tmp = volatile load i32* @x, align 4 ; <i32> [#uses=1] + %tmp1 = add i32 %tmp, 3 ; <i32> [#uses=1] + volatile store i32 %tmp1, i32* @x, align 4 + %tmp.1 = volatile load i32* @x, align 4 ; <i32> [#uses=1] + %tmp1.1 = add i32 %tmp.1, 3 ; <i32> [#uses=1] + volatile store i32 %tmp1.1, i32* @x, align 4 + %tmp.2 = volatile load i32* @x, align 4 ; <i32> [#uses=1] + %tmp1.2 = add i32 %tmp.2, 3 ; <i32> [#uses=1] + volatile store i32 %tmp1.2, i32* @x, align 4 + %tmp.3 = volatile load i32* @x, align 4 ; <i32> [#uses=1] + %tmp1.3 = add i32 %tmp.3, 3 ; <i32> [#uses=1] + volatile store i32 %tmp1.3, i32* @x, align 4 + ret void } diff --git a/test/CodeGen/X86/pr2623.ll b/test/CodeGen/X86/pr2623.ll deleted file mode 100644 index 5d0eb5d..0000000 --- a/test/CodeGen/X86/pr2623.ll +++ /dev/null @@ -1,44 +0,0 @@ -; RUN: llc < %s -; PR2623 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" -target triple = "i386-unknown-freebsd7.0" - %.objc_id = type { %.objc_id }* - %.objc_selector = type { i8*, i8* }* -@.objc_sel_ptr = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr13 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr14 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr15 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr16 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr17 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr18 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr19 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr20 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] -@.objc_sel_ptr21 = external constant %.objc_selector ; <%.objc_selector*> [#uses=1] - -@.objc_untyped_selector_alias = alias internal %.objc_selector* @.objc_sel_ptr15 ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias1 = alias internal %.objc_selector* @.objc_sel_ptr ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias2 = alias internal %.objc_selector* @.objc_sel_ptr17 ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias3 = alias internal %.objc_selector* @.objc_sel_ptr16 ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias4 = alias internal %.objc_selector* @.objc_sel_ptr13 ; <%.objc_selector*> [#uses=0] -@.objc_untyped_selector_alias7 = alias internal %.objc_selector* @.objc_sel_ptr14 ; <%.objc_selector*> [#uses=0] -@getRange = alias internal %.objc_selector* @.objc_sel_ptr18 ; <%.objc_selector*> [#uses=0] -@"valueWithRange:" = alias internal %.objc_selector* @.objc_sel_ptr21 ; <%.objc_selector*> [#uses=0] -@rangeValue = alias internal %.objc_selector* @.objc_sel_ptr20 ; <%.objc_selector*> [#uses=0] -@"printRange:" = alias internal %.objc_selector* @.objc_sel_ptr19 ; <%.objc_selector*> [#uses=0] - -define void @"._objc_method_SmalltalkTool()-run"(i8* %self, %.objc_selector %_cmd) { -entry: - br i1 false, label %small_int_messagerangeValue, label %real_object_messagerangeValue - -small_int_messagerangeValue: ; preds = %entry - br label %Continue - -real_object_messagerangeValue: ; preds = %entry - br label %Continue - -Continue: ; preds = %real_object_messagerangeValue, %small_int_messagerangeValue - %rangeValue = phi { i32, i32 } [ undef, %small_int_messagerangeValue ], [ undef, %real_object_messagerangeValue ] ; <{ i32, i32 }> [#uses=1] - call void (%.objc_id, %.objc_selector, ...)* null( %.objc_id null, %.objc_selector null, { i32, i32 } %rangeValue ) - ret void -} diff --git a/test/CodeGen/X86/pr3216.ll b/test/CodeGen/X86/pr3216.ll index 38c9f32..63676d9 100644 --- a/test/CodeGen/X86/pr3216.ll +++ b/test/CodeGen/X86/pr3216.ll @@ -1,14 +1,18 @@ -; RUN: llc < %s -march=x86 | grep {sar. \$5} +; RUN: llc < %s -march=x86 | FileCheck %s @foo = global i8 127 define i32 @main() nounwind { -entry: - %tmp = load i8* @foo - %bf.lo = lshr i8 %tmp, 5 - %bf.lo.cleared = and i8 %bf.lo, 7 - %0 = shl i8 %bf.lo.cleared, 5 - %bf.val.sext = ashr i8 %0, 5 - %conv = sext i8 %bf.val.sext to i32 - ret i32 %conv +; CHECK: main: +; CHECK-NOT: ret +; CHECK: sar{{.}} $5 +; CHECK: ret + + %tmp = load i8* @foo + %bf.lo = lshr i8 %tmp, 5 + %bf.lo.cleared = and i8 %bf.lo, 7 + %1 = shl i8 %bf.lo.cleared, 5 + %bf.val.sext = ashr i8 %1, 5 + %conv = sext i8 %bf.val.sext to i32 + ret i32 %conv } diff --git a/test/CodeGen/X86/pr3317.ll b/test/CodeGen/X86/pr3317.ll index 9d6626b..d83daf0 100644 --- a/test/CodeGen/X86/pr3317.ll +++ b/test/CodeGen/X86/pr3317.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -march=x86 ; PR3317 +%VT = type [0 x i32 (...)*] %ArraySInt16 = type { %JavaObject, i8*, [0 x i16] } %ArraySInt8 = type { %JavaObject, i8*, [0 x i8] } %Attribut = type { %ArraySInt16*, i32, i32 } @@ -14,7 +15,6 @@ %JavaObject = type { %VT*, %JavaCommonClass*, i8* } %TaskClassMirror = type { i32, i8* } %UTF8 = type { %JavaObject, i8*, [0 x i16] } - %VT = type [0 x i32 (...)*] declare void @jnjvmNullPointerException() diff --git a/test/CodeGen/X86/reghinting.ll b/test/CodeGen/X86/reghinting.ll new file mode 100644 index 0000000..87f65ed --- /dev/null +++ b/test/CodeGen/X86/reghinting.ll @@ -0,0 +1,35 @@ +; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s +; PR10221 + +;; The registers %x and %y must both spill across the finit call. +;; Check that they are spilled early enough that not copies are needed for the +;; fadd and fpext. + +; CHECK: pr10221 +; CHECK-NOT: movaps +; CHECK: movss +; CHECK-NEXT: movss +; CHECK-NEXT: addss +; CHECK-NEXT: cvtss2sd +; CHECK-NEXT: finit + +define i32 @pr10221(float %x, float %y, i8** nocapture %_retval) nounwind uwtable ssp { +entry: + %add = fadd float %x, %y + %conv = fpext float %add to double + %call = tail call i32 @finit(double %conv) nounwind + %tobool = icmp eq i32 %call, 0 + br i1 %tobool, label %return, label %if.end + +if.end: ; preds = %entry + tail call void @foo(float %x, float %y) nounwind + br label %return + +return: ; preds = %entry, %if.end + %retval.0 = phi i32 [ 0, %if.end ], [ 5, %entry ] + ret i32 %retval.0 +} + +declare i32 @finit(double) + +declare void @foo(float, float) diff --git a/test/CodeGen/X86/sdiv-exact.ll b/test/CodeGen/X86/sdiv-exact.ll new file mode 100644 index 0000000..48bb883 --- /dev/null +++ b/test/CodeGen/X86/sdiv-exact.ll @@ -0,0 +1,18 @@ +; RUN: llc -march=x86 < %s | FileCheck %s + +define i32 @test1(i32 %x) { + %div = sdiv exact i32 %x, 25 + ret i32 %div +; CHECK: test1: +; CHECK: imull $-1030792151, 4(%esp) +; CHECK-NEXT: ret +} + +define i32 @test2(i32 %x) { + %div = sdiv exact i32 %x, 24 + ret i32 %div +; CHECK: test2: +; CHECK: sarl $3 +; CHECK-NEXT: imull $-1431655765 +; CHECK-NEXT: ret +} diff --git a/test/CodeGen/X86/shift-codegen.ll b/test/CodeGen/X86/shift-codegen.ll index 4cba183..7d961e8 100644 --- a/test/CodeGen/X86/shift-codegen.ll +++ b/test/CodeGen/X86/shift-codegen.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -relocation-model=static -march=x86 | \ -; RUN: grep {shll \$3} | count 2 +; RUN: llc < %s -relocation-model=static -march=x86 | FileCheck %s ; This should produce two shll instructions, not any lea's. @@ -9,19 +8,31 @@ target triple = "i686-apple-darwin8" define void @fn1() { -entry: - %tmp = load i32* @Y ; <i32> [#uses=1] - %tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1] - %tmp2 = load i32* @X ; <i32> [#uses=1] - %tmp3 = or i32 %tmp1, %tmp2 ; <i32> [#uses=1] - store i32 %tmp3, i32* @X - ret void +; CHECK: fn1: +; CHECK-NOT: ret +; CHECK-NOT: lea +; CHECK: shll $3 +; CHECK-NOT: lea +; CHECK: ret + + %tmp = load i32* @Y ; <i32> [#uses=1] + %tmp1 = shl i32 %tmp, 3 ; <i32> [#uses=1] + %tmp2 = load i32* @X ; <i32> [#uses=1] + %tmp3 = or i32 %tmp1, %tmp2 ; <i32> [#uses=1] + store i32 %tmp3, i32* @X + ret void } define i32 @fn2(i32 %X, i32 %Y) { -entry: - %tmp2 = shl i32 %Y, 3 ; <i32> [#uses=1] - %tmp4 = or i32 %tmp2, %X ; <i32> [#uses=1] - ret i32 %tmp4 +; CHECK: fn2: +; CHECK-NOT: ret +; CHECK-NOT: lea +; CHECK: shll $3 +; CHECK-NOT: lea +; CHECK: ret + + %tmp2 = shl i32 %Y, 3 ; <i32> [#uses=1] + %tmp4 = or i32 %tmp2, %X ; <i32> [#uses=1] + ret i32 %tmp4 } diff --git a/test/CodeGen/X86/sse1.ll b/test/CodeGen/X86/sse1.ll index 73f88ae..9b2e05b 100644 --- a/test/CodeGen/X86/sse1.ll +++ b/test/CodeGen/X86/sse1.ll @@ -1,6 +1,6 @@ ; Tests for SSE1 and below, without SSE2+. ; RUN: llc < %s -march=x86 -mcpu=pentium3 -O3 | FileCheck %s -; RUN: llc < %s -march=x86-64 -mcpu=pentium3 -O3 | FileCheck %s +; RUN: llc < %s -march=x86-64 -mattr=-sse2,+sse -O3 | FileCheck %s define <8 x i16> @test1(<8 x i32> %a) nounwind { ; CHECK: test1 diff --git a/test/CodeGen/X86/sse3.ll b/test/CodeGen/X86/sse3.ll index 8c2e58d..8b3a317 100644 --- a/test/CodeGen/X86/sse3.ll +++ b/test/CodeGen/X86/sse3.ll @@ -1,6 +1,6 @@ -; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+. +; These are tests for SSE3 codegen. -; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \ +; RUN: llc < %s -march=x86-64 -mcpu=nocona -mtriple=i686-apple-darwin9 -O3 \ ; RUN: | FileCheck %s --check-prefix=X64 ; Test for v8xi16 lowering where we extract the first element of the vector and @@ -169,10 +169,10 @@ define internal void @t10() nounwind { ; X64: t10: ; X64: pextrw $4, [[X0:%xmm[0-9]+]], %eax ; X64: unpcklpd [[X1:%xmm[0-9]+]] -; X64: pshuflw $8, [[X1]], [[X1]] -; X64: pinsrw $2, %eax, [[X1]] +; X64: pshuflw $8, [[X1]], [[X2:%xmm[0-9]+]] +; X64: pinsrw $2, %eax, [[X2]] ; X64: pextrw $6, [[X0]], %eax -; X64: pinsrw $3, %eax, [[X1]] +; X64: pinsrw $3, %eax, [[X2]] } diff --git a/test/CodeGen/X86/switch-bt.ll b/test/CodeGen/X86/switch-bt.ll index 9f491d4..8e39342 100644 --- a/test/CodeGen/X86/switch-bt.ll +++ b/test/CodeGen/X86/switch-bt.ll @@ -79,3 +79,23 @@ if.end: ; preds = %entry } declare void @bar() + +define void @test3(i32 %x) nounwind { +; CHECK: test3: +; CHECK: cmpl $5 +; CHECK: ja +; CHECK: cmpl $4 +; CHECK: jne + switch i32 %x, label %if.end [ + i32 0, label %if.then + i32 1, label %if.then + i32 2, label %if.then + i32 3, label %if.then + i32 5, label %if.then + ] +if.then: + tail call void @bar() nounwind + ret void +if.end: + ret void +} diff --git a/test/CodeGen/X86/testl-commute.ll b/test/CodeGen/X86/testl-commute.ll index 3d5f672..0e6f636 100644 --- a/test/CodeGen/X86/testl-commute.ll +++ b/test/CodeGen/X86/testl-commute.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s | grep {testl.*\(%r.i\), %} | count 3 +; RUN: llc < %s | FileCheck %s ; rdar://5671654 ; The loads should fold into the testl instructions, no matter how ; the inputs are commuted. @@ -7,6 +7,11 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3 target triple = "x86_64-apple-darwin7" define i32 @test(i32* %P, i32* %G) nounwind { +; CHECK: test: +; CHECK-NOT: ret +; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: ret + entry: %0 = load i32* %P, align 4 ; <i32> [#uses=3] %1 = load i32* %G, align 4 ; <i32> [#uses=1] @@ -23,6 +28,11 @@ bb1: ; preds = %entry } define i32 @test2(i32* %P, i32* %G) nounwind { +; CHECK: test2: +; CHECK-NOT: ret +; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: ret + entry: %0 = load i32* %P, align 4 ; <i32> [#uses=3] %1 = load i32* %G, align 4 ; <i32> [#uses=1] @@ -37,7 +47,13 @@ bb: ; preds = %entry bb1: ; preds = %entry ret i32 %0 } + define i32 @test3(i32* %P, i32* %G) nounwind { +; CHECK: test3: +; CHECK-NOT: ret +; CHECK: testl (%{{.*}}), %{{.*}} +; CHECK: ret + entry: %0 = load i32* %P, align 4 ; <i32> [#uses=3] %1 = load i32* %G, align 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/X86/tlv-1.ll b/test/CodeGen/X86/tlv-1.ll index 42940f1..5773260 100644 --- a/test/CodeGen/X86/tlv-1.ll +++ b/test/CodeGen/X86/tlv-1.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s +; RUN: llc < %s -mtriple x86_64-apple-darwin -mcpu=core2 | FileCheck %s %struct.A = type { [48 x i8], i32, i32, i32 } diff --git a/test/CodeGen/X86/twoaddr-remat.ll b/test/CodeGen/X86/twoaddr-remat.ll deleted file mode 100644 index 4940c78..0000000 --- a/test/CodeGen/X86/twoaddr-remat.ll +++ /dev/null @@ -1,67 +0,0 @@ -; RUN: llc < %s -march=x86 | grep 59796 | count 3 - - %Args = type %Value* - %Exec = type opaque* - %Identifier = type opaque* - %JSFunction = type %Value (%Exec, %Scope, %Value, %Args) - %PropertyNameArray = type opaque* - %Scope = type opaque* - %Value = type opaque* - -declare i1 @X1(%Exec) readonly - -declare %Value @X2(%Exec) - -declare i32 @X3(%Exec, %Value) - -declare %Value @X4(i32) readnone - -define internal %Value @fast3bitlookup(%Exec %exec, %Scope %scope, %Value %this, %Args %args) nounwind { -prologue: - %eh_check = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1] - br i1 %eh_check, label %exception, label %no_exception - -exception: ; preds = %no_exception, %prologue - %rethrow_result = tail call %Value @X2( %Exec %exec ) ; <%Value> [#uses=1] - ret %Value %rethrow_result - -no_exception: ; preds = %prologue - %args_intptr = bitcast %Args %args to i32* ; <i32*> [#uses=1] - %argc_val = load i32* %args_intptr ; <i32> [#uses=1] - %cmpParamArgc = icmp sgt i32 %argc_val, 0 ; <i1> [#uses=1] - %arg_ptr = getelementptr %Args %args, i32 1 ; <%Args> [#uses=1] - %arg_val = load %Args %arg_ptr ; <%Value> [#uses=1] - %ext_arg_val = select i1 %cmpParamArgc, %Value %arg_val, %Value inttoptr (i32 5 to %Value) ; <%Value> [#uses=1] - %toInt325 = tail call i32 @X3( %Exec %exec, %Value %ext_arg_val ) ; <i32> [#uses=3] - %eh_check6 = tail call i1 @X1( %Exec %exec ) readonly ; <i1> [#uses=1] - br i1 %eh_check6, label %exception, label %no_exception7 - -no_exception7: ; preds = %no_exception - %shl_tmp_result = shl i32 %toInt325, 1 ; <i32> [#uses=1] - %rhs_masked13 = and i32 %shl_tmp_result, 14 ; <i32> [#uses=1] - %ashr_tmp_result = lshr i32 59796, %rhs_masked13 ; <i32> [#uses=1] - %and_tmp_result15 = and i32 %ashr_tmp_result, 3 ; <i32> [#uses=1] - %ashr_tmp_result3283 = lshr i32 %toInt325, 2 ; <i32> [#uses=1] - %rhs_masked38 = and i32 %ashr_tmp_result3283, 14 ; <i32> [#uses=1] - %ashr_tmp_result39 = lshr i32 59796, %rhs_masked38 ; <i32> [#uses=1] - %and_tmp_result41 = and i32 %ashr_tmp_result39, 3 ; <i32> [#uses=1] - %addconv = add i32 %and_tmp_result15, %and_tmp_result41 ; <i32> [#uses=1] - %ashr_tmp_result6181 = lshr i32 %toInt325, 5 ; <i32> [#uses=1] - %rhs_masked67 = and i32 %ashr_tmp_result6181, 6 ; <i32> [#uses=1] - %ashr_tmp_result68 = lshr i32 59796, %rhs_masked67 ; <i32> [#uses=1] - %and_tmp_result70 = and i32 %ashr_tmp_result68, 3 ; <i32> [#uses=1] - %addconv82 = add i32 %addconv, %and_tmp_result70 ; <i32> [#uses=3] - %rangetmp = add i32 %addconv82, 536870912 ; <i32> [#uses=1] - %rangecmp = icmp ult i32 %rangetmp, 1073741824 ; <i1> [#uses=1] - br i1 %rangecmp, label %NumberLiteralIntFast, label %NumberLiteralIntSlow - -NumberLiteralIntFast: ; preds = %no_exception7 - %imm_shift = shl i32 %addconv82, 2 ; <i32> [#uses=1] - %imm_or = or i32 %imm_shift, 3 ; <i32> [#uses=1] - %imm_val = inttoptr i32 %imm_or to %Value ; <%Value> [#uses=1] - ret %Value %imm_val - -NumberLiteralIntSlow: ; preds = %no_exception7 - %toVal = call %Value @X4( i32 %addconv82 ) ; <%Value> [#uses=1] - ret %Value %toVal -} diff --git a/test/CodeGen/X86/vec_insert-2.ll b/test/CodeGen/X86/vec_insert-2.ll index b08044b..dee91fd 100644 --- a/test/CodeGen/X86/vec_insert-2.ll +++ b/test/CodeGen/X86/vec_insert-2.ll @@ -1,25 +1,42 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep {\$36,} | count 2 -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep shufps | count 2 -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep pinsrw | count 1 -; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | grep movhpd | count 1 -; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | grep unpcklpd | count 1 +; RUN: llc < %s -march=x86 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X32 %s +; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X64 %s define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind { - %tmp1 = insertelement <4 x float> %tmp, float %s, i32 3 - ret <4 x float> %tmp1 +; X32: t1: +; X32: shufps $36 +; X32: ret + + %tmp1 = insertelement <4 x float> %tmp, float %s, i32 3 + ret <4 x float> %tmp1 } define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind { - %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 3 - ret <4 x i32> %tmp1 +; X32: t2: +; X32: shufps $36 +; X32: ret + + %tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 3 + ret <4 x i32> %tmp1 } define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind { - %tmp1 = insertelement <2 x double> %tmp, double %s, i32 1 - ret <2 x double> %tmp1 +; X32: t3: +; X32: movhpd +; X32: ret + +; X64: t3: +; X64: unpcklpd +; X64: ret + + %tmp1 = insertelement <2 x double> %tmp, double %s, i32 1 + ret <2 x double> %tmp1 } define <8 x i16> @t4(i16 %s, <8 x i16> %tmp) nounwind { - %tmp1 = insertelement <8 x i16> %tmp, i16 %s, i32 5 - ret <8 x i16> %tmp1 +; X32: t4: +; X32: pinsrw +; X32: ret + + %tmp1 = insertelement <8 x i16> %tmp, i16 %s, i32 5 + ret <8 x i16> %tmp1 } diff --git a/test/CodeGen/X86/vec_set-A.ll b/test/CodeGen/X86/vec_set-A.ll index f05eecf..92dda4c 100644 --- a/test/CodeGen/X86/vec_set-A.ll +++ b/test/CodeGen/X86/vec_set-A.ll @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | grep {movl.*\$1, %} +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; CHECK: movl $1, %{{.*}} define <2 x i64> @test1() nounwind { entry: ret <2 x i64> < i64 1, i64 0 > diff --git a/test/CodeGen/X86/vector.ll b/test/CodeGen/X86/vector.ll index 3fff849..46b0e18 100644 --- a/test/CodeGen/X86/vector.ll +++ b/test/CodeGen/X86/vector.ll @@ -1,6 +1,6 @@ ; Test that vectors are scalarized/lowered correctly. ; RUN: llc < %s -march=x86 -mcpu=i386 > %t -; RUN: llc < %s -march=x86 -mcpu=yonah > %t +; RUN: llc < %s -march=x86 -mcpu=yonah >> %t %d8 = type <8 x double> %f1 = type <1 x float> |