diff options
Diffstat (limited to 'test/MC/Disassembler/ARM64/memory.txt')
| -rw-r--r-- | test/MC/Disassembler/ARM64/memory.txt | 558 |
1 files changed, 558 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM64/memory.txt b/test/MC/Disassembler/ARM64/memory.txt new file mode 100644 index 0000000..031bfa6 --- /dev/null +++ b/test/MC/Disassembler/ARM64/memory.txt @@ -0,0 +1,558 @@ +# RUN: llvm-mc --disassemble -triple arm64-apple-darwin < %s | FileCheck %s + +#----------------------------------------------------------------------------- +# Indexed loads +#----------------------------------------------------------------------------- + + 0x85 0x14 0x40 0xb9 + 0x64 0x00 0x40 0xf9 + 0xe2 0x13 0x40 0xf9 + 0xe5 0x07 0x40 0x3d + 0xe6 0x07 0x40 0x7d + 0xe7 0x07 0x40 0xbd + 0xe8 0x07 0x40 0xfd + 0xe9 0x07 0xc0 0x3d + 0x64 0x00 0x40 0x39 + 0x20 0x78 0xa0 0xb8 + 0x85 0x50 0x40 0x39 + +# CHECK: ldr w5, [x4, #20] +# CHECK: ldr x4, [x3] +# CHECK: ldr x2, [sp, #32] +# CHECK: ldr b5, [sp, #1] +# CHECK: ldr h6, [sp, #2] +# CHECK: ldr s7, [sp, #4] +# CHECK: ldr d8, [sp, #8] +# CHECK: ldr q9, [sp, #16] +# CHECK: ldrb w4, [x3] +# CHECK: ldrsw x0, [x1, x0, lsl #2] +# CHECK: ldrb w5, [x4, #20] +# CHECK: ldrsb w9, [x3] +# CHECK: ldrsb x2, [sp, #128] +# CHECK: ldrh w2, [sp, #32] +# CHECK: ldrsh w3, [sp, #32] +# CHECK: ldrsh x5, [x9, #24] +# CHECK: ldrsw x9, [sp, #512] +# CHECK: prfm pldl3strm, [sp, #32] + + 0x69 0x00 0xc0 0x39 + 0xe2 0x03 0x82 0x39 + 0xe2 0x43 0x40 0x79 + 0xe3 0x43 0xc0 0x79 + 0x25 0x31 0x80 0x79 + 0xe9 0x03 0x82 0xb9 + 0xe5 0x13 0x80 0xf9 + 0x40 0x00 0x80 0xf9 + 0x41 0x00 0x80 0xf9 + 0x42 0x00 0x80 0xf9 + 0x43 0x00 0x80 0xf9 + 0x44 0x00 0x80 0xf9 + 0x45 0x00 0x80 0xf9 + 0x50 0x00 0x80 0xf9 + 0x51 0x00 0x80 0xf9 + 0x52 0x00 0x80 0xf9 + 0x53 0x00 0x80 0xf9 + 0x54 0x00 0x80 0xf9 + 0x55 0x00 0x80 0xf9 + +# CHECK: prfm pldl1keep, [x2] +# CHECK: prfm pldl1strm, [x2] +# CHECK: prfm pldl2keep, [x2] +# CHECK: prfm pldl2strm, [x2] +# CHECK: prfm pldl3keep, [x2] +# CHECK: prfm pldl3strm, [x2] +# CHECK: prfm pstl1keep, [x2] +# CHECK: prfm pstl1strm, [x2] +# CHECK: prfm pstl2keep, [x2] +# CHECK: prfm pstl2strm, [x2] +# CHECK: prfm pstl3keep, [x2] +# CHECK: prfm pstl3strm, [x2] + +#----------------------------------------------------------------------------- +# Indexed stores +#----------------------------------------------------------------------------- + + 0x64 0x00 0x00 0xf9 + 0xe2 0x13 0x00 0xf9 + 0x85 0x14 0x00 0xb9 + 0xe5 0x07 0x00 0x3d + 0xe6 0x07 0x00 0x7d + 0xe7 0x07 0x00 0xbd + 0xe8 0x07 0x00 0xfd + 0xe9 0x07 0x80 0x3d + 0x64 0x00 0x00 0x39 + 0x85 0x50 0x00 0x39 + 0xe2 0x43 0x00 0x79 + +# CHECK: str x4, [x3] +# CHECK: str x2, [sp, #32] +# CHECK: str w5, [x4, #20] +# CHECK: str b5, [sp, #1] +# CHECK: str h6, [sp, #2] +# CHECK: str s7, [sp, #4] +# CHECK: str d8, [sp, #8] +# CHECK: str q9, [sp, #16] +# CHECK: strb w4, [x3] +# CHECK: strb w5, [x4, #20] +# CHECK: strh w2, [sp, #32] + +#----------------------------------------------------------------------------- +# Unscaled immediate loads and stores +#----------------------------------------------------------------------------- + + 0x62 0x00 0x40 0xb8 + 0xe2 0x83 0x41 0xb8 + 0x62 0x00 0x40 0xf8 + 0xe2 0x83 0x41 0xf8 + 0xe5 0x13 0x40 0x3c + 0xe6 0x23 0x40 0x7c + 0xe7 0x43 0x40 0xbc + 0xe8 0x83 0x40 0xfc + 0xe9 0x03 0xc1 0x3c + 0x69 0x00 0xc0 0x38 + 0xe2 0x03 0x88 0x38 + 0xe3 0x03 0xc2 0x78 + 0x25 0x81 0x81 0x78 + 0xe9 0x03 0x98 0xb8 + +# CHECK: ldur w2, [x3] +# CHECK: ldur w2, [sp, #24] +# CHECK: ldur x2, [x3] +# CHECK: ldur x2, [sp, #24] +# CHECK: ldur b5, [sp, #1] +# CHECK: ldur h6, [sp, #2] +# CHECK: ldur s7, [sp, #4] +# CHECK: ldur d8, [sp, #8] +# CHECK: ldur q9, [sp, #16] +# CHECK: ldursb w9, [x3] +# CHECK: ldursb x2, [sp, #128] +# CHECK: ldursh w3, [sp, #32] +# CHECK: ldursh x5, [x9, #24] +# CHECK: ldursw x9, [sp, #-128] + + 0x64 0x00 0x00 0xb8 + 0xe2 0x03 0x02 0xb8 + 0x64 0x00 0x00 0xf8 + 0xe2 0x03 0x02 0xf8 + 0x85 0x40 0x01 0xb8 + 0xe5 0x13 0x00 0x3c + 0xe6 0x23 0x00 0x7c + 0xe7 0x43 0x00 0xbc + 0xe8 0x83 0x00 0xfc + 0xe9 0x03 0x81 0x3c + 0x64 0x00 0x00 0x38 + 0x85 0x40 0x01 0x38 + 0xe2 0x03 0x02 0x78 + 0xe5 0x03 0x82 0xf8 + +# CHECK: stur w4, [x3] +# CHECK: stur w2, [sp, #32] +# CHECK: stur x4, [x3] +# CHECK: stur x2, [sp, #32] +# CHECK: stur w5, [x4, #20] +# CHECK: stur b5, [sp, #1] +# CHECK: stur h6, [sp, #2] +# CHECK: stur s7, [sp, #4] +# CHECK: stur d8, [sp, #8] +# CHECK: stur q9, [sp, #16] +# CHECK: sturb w4, [x3] +# CHECK: sturb w5, [x4, #20] +# CHECK: sturh w2, [sp, #32] +# CHECK: prfum pldl3strm, [sp, #32] + +#----------------------------------------------------------------------------- +# Unprivileged loads and stores +#----------------------------------------------------------------------------- + + 0x83 0x08 0x41 0xb8 + 0x83 0x08 0x41 0xf8 + 0x83 0x08 0x41 0x38 + 0x69 0x08 0xc0 0x38 + 0xe2 0x0b 0x88 0x38 + 0x83 0x08 0x41 0x78 + 0xe3 0x0b 0xc2 0x78 + 0x25 0x89 0x81 0x78 + 0xe9 0x0b 0x98 0xb8 + +# CHECK: ldtr w3, [x4, #16] +# CHECK: ldtr x3, [x4, #16] +# CHECK: ldtrb w3, [x4, #16] +# CHECK: ldtrsb w9, [x3] +# CHECK: ldtrsb x2, [sp, #128] +# CHECK: ldtrh w3, [x4, #16] +# CHECK: ldtrsh w3, [sp, #32] +# CHECK: ldtrsh x5, [x9, #24] +# CHECK: ldtrsw x9, [sp, #-128] + + 0x85 0x48 0x01 0xb8 + 0x64 0x08 0x00 0xf8 + 0xe2 0x0b 0x02 0xf8 + 0x64 0x08 0x00 0x38 + 0x85 0x48 0x01 0x38 + 0xe2 0x0b 0x02 0x78 + +# CHECK: sttr w5, [x4, #20] +# CHECK: sttr x4, [x3] +# CHECK: sttr x2, [sp, #32] +# CHECK: sttrb w4, [x3] +# CHECK: sttrb w5, [x4, #20] +# CHECK: sttrh w2, [sp, #32] + +#----------------------------------------------------------------------------- +# Pre-indexed loads and stores +#----------------------------------------------------------------------------- + + 0xfd 0x8c 0x40 0xf8 + 0xfe 0x8c 0x40 0xf8 + 0x05 0x1c 0x40 0x3c + 0x06 0x2c 0x40 0x7c + 0x07 0x4c 0x40 0xbc + 0x08 0x8c 0x40 0xfc + 0x09 0x0c 0xc1 0x3c + +# CHECK: ldr fp, [x7, #8]! +# CHECK: ldr lr, [x7, #8]! +# CHECK: ldr b5, [x0, #1]! +# CHECK: ldr h6, [x0, #2]! +# CHECK: ldr s7, [x0, #4]! +# CHECK: ldr d8, [x0, #8]! +# CHECK: ldr q9, [x0, #16]! + + 0xfe 0x8c 0x1f 0xf8 + 0xfd 0x8c 0x1f 0xf8 + 0x05 0xfc 0x1f 0x3c + 0x06 0xec 0x1f 0x7c + 0x07 0xcc 0x1f 0xbc + 0x08 0x8c 0x1f 0xfc + 0x09 0x0c 0x9f 0x3c + +# CHECK: str lr, [x7, #-8]! +# CHECK: str fp, [x7, #-8]! +# CHECK: str b5, [x0, #-1]! +# CHECK: str h6, [x0, #-2]! +# CHECK: str s7, [x0, #-4]! +# CHECK: str d8, [x0, #-8]! +# CHECK: str q9, [x0, #-16]! + +#----------------------------------------------------------------------------- +# post-indexed loads and stores +#----------------------------------------------------------------------------- + + 0xfe 0x84 0x1f 0xf8 + 0xfd 0x84 0x1f 0xf8 + 0x05 0xf4 0x1f 0x3c + 0x06 0xe4 0x1f 0x7c + 0x07 0xc4 0x1f 0xbc + 0x08 0x84 0x1f 0xfc + 0x09 0x04 0x9f 0x3c + +# CHECK: str lr, [x7], #-8 +# CHECK: str fp, [x7], #-8 +# CHECK: str b5, [x0], #-1 +# CHECK: str h6, [x0], #-2 +# CHECK: str s7, [x0], #-4 +# CHECK: str d8, [x0], #-8 +# CHECK: str q9, [x0], #-16 + + 0xfd 0x84 0x40 0xf8 + 0xfe 0x84 0x40 0xf8 + 0x05 0x14 0x40 0x3c + 0x06 0x24 0x40 0x7c + 0x07 0x44 0x40 0xbc + 0x08 0x84 0x40 0xfc + 0x09 0x04 0xc1 0x3c + +# CHECK: ldr fp, [x7], #8 +# CHECK: ldr lr, [x7], #8 +# CHECK: ldr b5, [x0], #1 +# CHECK: ldr h6, [x0], #2 +# CHECK: ldr s7, [x0], #4 +# CHECK: ldr d8, [x0], #8 +# CHECK: ldr q9, [x0], #16 + +#----------------------------------------------------------------------------- +# Load/Store pair (indexed offset) +#----------------------------------------------------------------------------- + + 0xe3 0x09 0x42 0x29 + 0xe4 0x27 0x7f 0xa9 + 0xc2 0x0d 0x42 0x69 + 0xe2 0x0f 0x7e 0x69 + 0x4a 0x04 0x48 0x2d + 0x4a 0x04 0x40 0x6d + +# CHECK: ldp w3, w2, [x15, #16] +# CHECK: ldp x4, x9, [sp, #-16] +# CHECK: ldpsw x2, x3, [x14, #16] +# CHECK: ldpsw x2, x3, [sp, #-16] +# CHECK: ldp s10, s1, [x2, #64] +# CHECK: ldp d10, d1, [x2] + + 0xe3 0x09 0x02 0x29 + 0xe4 0x27 0x3f 0xa9 + 0x4a 0x04 0x08 0x2d + 0x4a 0x04 0x00 0x6d + +# CHECK: stp w3, w2, [x15, #16] +# CHECK: stp x4, x9, [sp, #-16] +# CHECK: stp s10, s1, [x2, #64] +# CHECK: stp d10, d1, [x2] + +#----------------------------------------------------------------------------- +# Load/Store pair (pre-indexed) +#----------------------------------------------------------------------------- + + 0xe3 0x09 0xc2 0x29 + 0xe4 0x27 0xff 0xa9 + 0xc2 0x0d 0xc2 0x69 + 0xe2 0x0f 0xfe 0x69 + 0x4a 0x04 0xc8 0x2d + 0x4a 0x04 0xc1 0x6d + +# CHECK: ldp w3, w2, [x15, #16]! +# CHECK: ldp x4, x9, [sp, #-16]! +# CHECK: ldpsw x2, x3, [x14, #16]! +# CHECK: ldpsw x2, x3, [sp, #-16]! +# CHECK: ldp s10, s1, [x2, #64]! +# CHECK: ldp d10, d1, [x2, #16]! + + 0xe3 0x09 0x82 0x29 + 0xe4 0x27 0xbf 0xa9 + 0x4a 0x04 0x88 0x2d + 0x4a 0x04 0x81 0x6d + +# CHECK: stp w3, w2, [x15, #16]! +# CHECK: stp x4, x9, [sp, #-16]! +# CHECK: stp s10, s1, [x2, #64]! +# CHECK: stp d10, d1, [x2, #16]! + +#----------------------------------------------------------------------------- +# Load/Store pair (post-indexed) +#----------------------------------------------------------------------------- + + 0xe3 0x09 0xc2 0x28 + 0xe4 0x27 0xff 0xa8 + 0xc2 0x0d 0xc2 0x68 + 0xe2 0x0f 0xfe 0x68 + 0x4a 0x04 0xc8 0x2c + 0x4a 0x04 0xc1 0x6c + +# CHECK: ldp w3, w2, [x15], #16 +# CHECK: ldp x4, x9, [sp], #-16 +# CHECK: ldpsw x2, x3, [x14], #16 +# CHECK: ldpsw x2, x3, [sp], #-16 +# CHECK: ldp s10, s1, [x2], #64 +# CHECK: ldp d10, d1, [x2], #16 + + 0xe3 0x09 0x82 0x28 + 0xe4 0x27 0xbf 0xa8 + 0x4a 0x04 0x88 0x2c + 0x4a 0x04 0x81 0x6c + +# CHECK: stp w3, w2, [x15], #16 +# CHECK: stp x4, x9, [sp], #-16 +# CHECK: stp s10, s1, [x2], #64 +# CHECK: stp d10, d1, [x2], #16 + +#----------------------------------------------------------------------------- +# Load/Store pair (no-allocate) +#----------------------------------------------------------------------------- + + 0xe3 0x09 0x42 0x28 + 0xe4 0x27 0x7f 0xa8 + 0x4a 0x04 0x48 0x2c + 0x4a 0x04 0x40 0x6c + +# CHECK: ldnp w3, w2, [x15, #16] +# CHECK: ldnp x4, x9, [sp, #-16] +# CHECK: ldnp s10, s1, [x2, #64] +# CHECK: ldnp d10, d1, [x2] + + 0xe3 0x09 0x02 0x28 + 0xe4 0x27 0x3f 0xa8 + 0x4a 0x04 0x08 0x2c + 0x4a 0x04 0x00 0x6c + +# CHECK: stnp w3, w2, [x15, #16] +# CHECK: stnp x4, x9, [sp, #-16] +# CHECK: stnp s10, s1, [x2, #64] +# CHECK: stnp d10, d1, [x2] + +#----------------------------------------------------------------------------- +# Load/Store register offset +#----------------------------------------------------------------------------- + + 0x00 0x68 0x60 0xb8 + 0x00 0x78 0x60 0xb8 + 0x00 0x68 0x60 0xf8 + 0x00 0x78 0x60 0xf8 + 0x00 0xe8 0x60 0xf8 + +# CHECK: ldr w0, [x0, x0] +# CHECK: ldr w0, [x0, x0, lsl #2] +# CHECK: ldr x0, [x0, x0] +# CHECK: ldr x0, [x0, x0, lsl #3] +# CHECK: ldr x0, [x0, x0, sxtx] + + 0x21 0x68 0x62 0x3c + 0x21 0x78 0x62 0x3c + 0x21 0x68 0x62 0x7c + 0x21 0x78 0x62 0x7c + 0x21 0x68 0x62 0xbc + 0x21 0x78 0x62 0xbc + 0x21 0x68 0x62 0xfc + 0x21 0x78 0x62 0xfc + 0x21 0x68 0xe2 0x3c + 0x21 0x78 0xe2 0x3c + +# CHECK: ldr b1, [x1, x2] +# CHECK: ldr b1, [x1, x2, lsl #0] +# CHECK: ldr h1, [x1, x2] +# CHECK: ldr h1, [x1, x2, lsl #1] +# CHECK: ldr s1, [x1, x2] +# CHECK: ldr s1, [x1, x2, lsl #2] +# CHECK: ldr d1, [x1, x2] +# CHECK: ldr d1, [x1, x2, lsl #3] +# CHECK: ldr q1, [x1, x2] +# CHECK: ldr q1, [x1, x2, lsl #4] + + 0xe1 0x6b 0x23 0xfc + 0xe1 0x5b 0x23 0xfc + 0xe1 0x6b 0xa3 0x3c + 0xe1 0x5b 0xa3 0x3c + +# CHECK: str d1, [sp, x3] +# CHECK: str d1, [sp, x3, uxtw #3] +# CHECK: str q1, [sp, x3] +# CHECK: str q1, [sp, x3, uxtw #4] + +#----------------------------------------------------------------------------- +# Load/Store exclusive +#----------------------------------------------------------------------------- + + 0x26 0x7c 0x5f 0x08 + 0x26 0x7c 0x5f 0x48 + 0x27 0x0d 0x7f 0x88 + 0x27 0x0d 0x7f 0xc8 + +# CHECK: ldxrb w6, [x1] +# CHECK: ldxrh w6, [x1] +# CHECK: ldxp w7, w3, [x9] +# CHECK: ldxp x7, x3, [x9] + + 0x64 0x7c 0x01 0xc8 + 0x64 0x7c 0x01 0x88 + 0x64 0x7c 0x01 0x08 + 0x64 0x7c 0x01 0x48 + 0x22 0x18 0x21 0xc8 + 0x22 0x18 0x21 0x88 + +# CHECK: stxr w1, x4, [x3] +# CHECK: stxr w1, w4, [x3] +# CHECK: stxrb w1, w4, [x3] +# CHECK: stxrh w1, w4, [x3] +# CHECK: stxp w1, x2, x6, [x1] +# CHECK: stxp w1, w2, w6, [x1] + +#----------------------------------------------------------------------------- +# Load-acquire/Store-release non-exclusive +#----------------------------------------------------------------------------- + + 0xe4 0xff 0xdf 0x88 + 0xe4 0xff 0xdf 0xc8 + 0xe4 0xff 0xdf 0x08 + 0xe4 0xff 0xdf 0x48 + +# CHECK: ldar w4, [sp] +# CHECK: ldar x4, [sp] +# CHECK: ldarb w4, [sp] +# CHECK: ldarh w4, [sp] + + 0xc3 0xfc 0x9f 0x88 + 0xc3 0xfc 0x9f 0xc8 + 0xc3 0xfc 0x9f 0x08 + 0xc3 0xfc 0x9f 0x48 + +# CHECK: stlr w3, [x6] +# CHECK: stlr x3, [x6] +# CHECK: stlrb w3, [x6] +# CHECK: stlrh w3, [x6] + +#----------------------------------------------------------------------------- +# Load-acquire/Store-release exclusive +#----------------------------------------------------------------------------- + + 0x82 0xfc 0x5f 0x88 + 0x82 0xfc 0x5f 0xc8 + 0x82 0xfc 0x5f 0x08 + 0x82 0xfc 0x5f 0x48 + 0x22 0x98 0x7f 0x88 + 0x22 0x98 0x7f 0xc8 + +# CHECK: ldaxr w2, [x4] +# CHECK: ldaxr x2, [x4] +# CHECK: ldaxrb w2, [x4] +# CHECK: ldaxrh w2, [x4] +# CHECK: ldaxp w2, w6, [x1] +# CHECK: ldaxp x2, x6, [x1] + + 0x27 0xfc 0x08 0xc8 + 0x27 0xfc 0x08 0x88 + 0x27 0xfc 0x08 0x08 + 0x27 0xfc 0x08 0x48 + 0x22 0x98 0x21 0xc8 + 0x22 0x98 0x21 0x88 + +# CHECK: stlxr w8, x7, [x1] +# CHECK: stlxr w8, w7, [x1] +# CHECK: stlxrb w8, w7, [x1] +# CHECK: stlxrh w8, w7, [x1] +# CHECK: stlxp w1, x2, x6, [x1] +# CHECK: stlxp w1, w2, w6, [x1] + +#----------------------------------------------------------------------------- +# Load/Store with explicit LSL values +#----------------------------------------------------------------------------- + 0x20 0x78 0xa0 0xb8 + 0x20 0x78 0x60 0xf8 + 0x20 0x78 0x20 0xf8 + 0x20 0x78 0x60 0xb8 + 0x20 0x78 0x20 0xb8 + 0x20 0x78 0xe0 0x3c + 0x20 0x78 0xa0 0x3c + 0x20 0x78 0x60 0xfc + 0x20 0x78 0x20 0xfc + 0x20 0x78 0x60 0xbc + 0x20 0x78 0x20 0xbc + 0x20 0x78 0x60 0x7c + 0x20 0x78 0x60 0x3c + 0x20 0x78 0x60 0x38 + 0x20 0x78 0x20 0x38 + 0x20 0x78 0xe0 0x38 + 0x20 0x78 0x60 0x78 + 0x20 0x78 0x20 0x78 + 0x20 0x78 0xe0 0x78 + 0x20 0x78 0xa0 0x38 + 0x20 0x78 0xa0 0x78 + +# CHECK: ldrsw x0, [x1, x0, lsl #2] +# CHECK: ldr x0, [x1, x0, lsl #3] +# CHECK: str x0, [x1, x0, lsl #3] +# CHECK: ldr w0, [x1, x0, lsl #2] +# CHECK: str w0, [x1, x0, lsl #2] +# CHECK: ldr q0, [x1, x0, lsl #4] +# CHECK: str q0, [x1, x0, lsl #4] +# CHECK: ldr d0, [x1, x0, lsl #3] +# CHECK: str d0, [x1, x0, lsl #3] +# CHECK: ldr s0, [x1, x0, lsl #2] +# CHECK: str s0, [x1, x0, lsl #2] +# CHECK: ldr h0, [x1, x0, lsl #1] +# CHECK: ldr b0, [x1, x0, lsl #0] +# CHECK: ldrb w0, [x1, x0, lsl #0] +# CHECK: strb w0, [x1, x0, lsl #0] +# CHECK: ldrsb w0, [x1, x0, lsl #0] +# CHECK: ldrh w0, [x1, x0, lsl #1] +# CHECK: strh w0, [x1, x0, lsl #1] +# CHECK: ldrsh w0, [x1, x0, lsl #1] +# CHECK: ldrsb x0, [x1, x0, lsl #0] +# CHECK: ldrsh x0, [x1, x0, lsl #1] |