diff options
Diffstat (limited to 'test/MC/Disassembler/ARM')
| -rw-r--r-- | test/MC/Disassembler/ARM/armv8.1a.txt | 36 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-armv8.1a.txt | 83 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt | 72 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/neont2.txt | 6 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/thumb-v8.1a.txt | 98 |
5 files changed, 292 insertions, 3 deletions
diff --git a/test/MC/Disassembler/ARM/armv8.1a.txt b/test/MC/Disassembler/ARM/armv8.1a.txt new file mode 100644 index 0000000..de0c89e --- /dev/null +++ b/test/MC/Disassembler/ARM/armv8.1a.txt @@ -0,0 +1,36 @@ +# RUN: llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a +# RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8 + +[0x54,0x0b,0x12,0xf3] +[0x12,0x0b,0x21,0xf3] +[0x54,0x0c,0x12,0xf3] +[0x12,0x0c,0x21,0xf3] +# CHECK-V81a: vqrdmlah.s16 q0, q1, q2 +# CHECK-V81a: vqrdmlah.s32 d0, d1, d2 +# CHECK-V81a: vqrdmlsh.s16 q0, q1, q2 +# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x54,0x0b,0x12,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x12,0x0b,0x21,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x54,0x0c,0x12,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x12,0x0c,0x21,0xf3] + +[0x42,0x0e,0x92,0xf3] +[0x42,0x0e,0xa1,0xf2] +[0x42,0x0f,0x92,0xf3] +[0x42,0x0f,0xa1,0xf2] +# CHECK-V81a: vqrdmlah.s16 q0, q1, d2[0] +# CHECK-V81a: vqrdmlah.s32 d0, d1, d2[0] +# CHECK-V81a: vqrdmlsh.s16 q0, q1, d2[0] +# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x42,0x0e,0x92,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x42,0x0e,0xa1,0xf2] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x42,0x0f,0x92,0xf3] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x42,0x0f,0xa1,0xf2] diff --git a/test/MC/Disassembler/ARM/invalid-armv8.1a.txt b/test/MC/Disassembler/ARM/invalid-armv8.1a.txt new file mode 100644 index 0000000..1a9f275 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-armv8.1a.txt @@ -0,0 +1,83 @@ +# RUN: not llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s + +# Check, if sizes 00 and 11 are undefined for RDMA +[0x12,0x0b,0x01,0xf3] # vqrdmlah.s8 d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x12,0x0b,0x01,0xf3] # vqrdmlah.s8 d0, d1, d2 +# CHECK-NEXT: ^ + +[0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2 +# CHECK-NEXT: ^ + +[0x54,0x0b,0x02,0xf3] # vqrdmlah.s8 q0, q1, q2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x54,0x0b,0x02,0xf3] # vqrdmlah.s8 q0, q1, q2 +# CHECK-NEXT: ^ + +[0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0 +# CHECK-NEXT: ^ + +[0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8 d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8 d0, d1, d2 +# CHECK-NEXT: ^ + +[0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2 +# CHECK-NEXT: ^ + +[0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8 q0, q1, q2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8 q0, q1, q2 +# CHECK-NEXT: ^ + +[0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2 +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2 +# CHECK-NEXT: ^ + +[0x42,0x0e,0x81,0xf2] # vqrdmlah.s8 d0, d1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0e,0x81,0xf2] # vqrdmlah.s8 d0, d1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0e,0x82,0xf3] # vqrdmlah.s8 q0, q1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0e,0x82,0xf3] # vqrdmlah.s8 q0, q1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64 q0, q1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64 q0, q1, d2[0] +# CHECK-NEXT: ^ + + +[0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8 d0, d1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8 d0, d1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64 d0, d1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64 d0, d1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8 q0, q1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8 q0, q1, d2[0] +# CHECK-NEXT: ^ + +[0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64 q0, q1, d2[0] +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64 q0, q1, d2[0] +# CHECK-NEXT: ^ diff --git a/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt b/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt new file mode 100644 index 0000000..555b8c3 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt @@ -0,0 +1,72 @@ +# RUN: not llvm-mc -triple thumbv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s + +# Check, if sizes 00 and 11 are undefined for RDMA +[0x01,0xff,0x12,0x0b] # vqrdmlah.s8 d0, d1, d2 +[0x31,0xff,0x12,0x0b] # vqrdmlah.s64 d0, d1, d2 +[0x02,0xff,0x54,0x0b] # vqrdmlah.s8 q0, q1, q2 +[0x06,0xff,0x50,0x4b] # vqrdmlah.s64 q2, q3, q0 + +[0x01,0xff,0x12,0x0c] # vqrdmlsh.s8 d0, d1, d2 +[0x31,0xff,0x12,0x0c] # vqrdmlsh.s64 d0, d1, d2 +[0x02,0xff,0x54,0x0c] # vqrdmlsh.s8 q0, q1, q2 +[0x32,0xff,0x54,0x0c] # vqrdmlsh.s64 q0, q1, q2 + +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x01,0xff,0x12,0x0b] # vqrdmlah.s8 d0, d1, d2 +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x31,0xff,0x12,0x0b] # vqrdmlah.s64 d0, d1, d2 +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x02,0xff,0x54,0x0b] # vqrdmlah.s8 q0, q1, q2 +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x06,0xff,0x50,0x4b] # vqrdmlah.s64 q2, q3, q0 +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x01,0xff,0x12,0x0c] # vqrdmlsh.s8 d0, d1, d2 +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x31,0xff,0x12,0x0c] # vqrdmlsh.s64 d0, d1, d2 +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x02,0xff,0x54,0x0c] # vqrdmlsh.s8 q0, q1, q2 +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x32,0xff,0x54,0x0c] # vqrdmlsh.s64 q0, q1, q2 +# CHECK-NEXT: ^ + +[0x81,0xef,0x42,0x0e] # vqrdmlah.s8 d0, d1, d2[0] +[0xb1,0xef,0x42,0x0e] # vqrdmlah.s64 d0, d1, d2[0] +[0x82,0xff,0x42,0x0e] # vqrdmlah.s8 q0, q1, d2[0] +[0xb2,0xff,0x42,0x0e] # vqrdmlah.s64 q0, q1, d2[0] + +[0x81,0xef,0x42,0x0f] # vqrdmlsh.s8 d0, d1, d2[0] +[0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64 d0, d1, d2[0] +[0x82,0xff,0x42,0x0f] # vqrdmlsh.s8 q0, q1, d2[0] +[0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64 q0, q1, d2[0] + +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x81,0xef,0x42,0x0e] # vqrdmlah.s8 d0, d1, d2[0] +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0xb1,0xef,0x42,0x0e] # vqrdmlah.s64 d0, d1, d2[0] +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x82,0xff,0x42,0x0e] # vqrdmlah.s8 q0, q1, d2[0] +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0xb2,0xff,0x42,0x0e] # vqrdmlah.s64 q0, q1, d2[0] +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x81,0xef,0x42,0x0f] # vqrdmlsh.s8 d0, d1, d2[0] +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64 d0, d1, d2[0] +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0x82,0xff,0x42,0x0f] # vqrdmlsh.s8 q0, q1, d2[0] +# CHECK-NEXT: ^ +# CHECK: warning: invalid instruction encoding +# CHECK-NEXT: [0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64 q0, q1, d2[0] +# CHECK-NEXT: ^ diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt index e493fba..536095f 100644 --- a/test/MC/Disassembler/ARM/neont2.txt +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -1631,11 +1631,11 @@ # rdar://10798451 0xe7 0xf9 0x32 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7:16], r2 +# CHECK: vld2.8 {d17[], d19[]}, [r7:16], r2 0xe7 0xf9 0x3d 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7:16]! +# CHECK: vld2.8 {d17[], d19[]}, [r7:16]! 0xe7 0xf9 0x3f 0x1d -# CHECK vld2.8 {d17[], d19[]}, [r7:16] +# CHECK: vld2.8 {d17[], d19[]}, [r7:16] # rdar://11034702 0x04 0xf9 0x0d 0x87 diff --git a/test/MC/Disassembler/ARM/thumb-v8.1a.txt b/test/MC/Disassembler/ARM/thumb-v8.1a.txt new file mode 100644 index 0000000..10fea46 --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-v8.1a.txt @@ -0,0 +1,98 @@ +# RUN: llvm-mc -triple thumbv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a +# RUN: not llvm-mc -triple thumbv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8 + +[0x11,0xff,0x12,0x0b] +# CHECK-V81a: vqrdmlah.s16 d0, d1, d2 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x11,0xff,0x12,0x0b] +# CHECK-V8: ^ + +[0x21,0xff,0x12,0x0b] +# CHECK-V81a: vqrdmlah.s32 d0, d1, d2 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x21,0xff,0x12,0x0b] +# CHECK-V8: ^ + +[0x12,0xff,0x54,0x0b] +# CHECK-V81a: vqrdmlah.s16 q0, q1, q2 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x12,0xff,0x54,0x0b] +# CHECK-V8: ^ + +[0x26,0xff,0x50,0x4b] +# CHECK-V81a: vqrdmlah.s32 q2, q3, q0 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x26,0xff,0x50,0x4b] +# CHECK-V8: ^ + +[0x16,0xff,0x15,0x7c] +# CHECK-V81a: vqrdmlsh.s16 d7, d6, d5 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x16,0xff,0x15,0x7c] +# CHECK-V8: ^ + +[0x21,0xff,0x12,0x0c] +# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x21,0xff,0x12,0x0c] +# CHECK-V8: ^ + +[0x12,0xff,0x54,0x0c] +# CHECK-V81a: vqrdmlsh.s16 q0, q1, q2 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x12,0xff,0x54,0x0c] +# CHECK-V8: ^ + +[0x28,0xff,0x5a,0x6c] +# CHECK-V81a: vqrdmlsh.s32 q3, q4, q5 +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x28,0xff,0x5a,0x6c] +# CHECK-V8: ^ + +[0x91,0xef,0x42,0x0e] +# CHECK-V81a: vqrdmlah.s16 d0, d1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x91,0xef,0x42,0x0e] +# CHECK-V8: ^ + +[0xa1,0xef,0x42,0x0e] +# CHECK-V81a: vqrdmlah.s32 d0, d1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0xa1,0xef,0x42,0x0e] +# CHECK-V8: ^ + +[0x92,0xff,0x42,0x0e] +# CHECK-V81a: vqrdmlah.s16 q0, q1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x92,0xff,0x42,0x0e] +# CHECK-V8: ^ + +[0xa2,0xff,0x42,0x0e] +# CHECK-V81a: vqrdmlah.s32 q0, q1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0xa2,0xff,0x42,0x0e] +# CHECK-V8: ^ + +[0x91,0xef,0x42,0x0f] +# CHECK-V81a: vqrdmlsh.s16 d0, d1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x91,0xef,0x42,0x0f] +# CHECK-V8: ^ + +[0xa1,0xef,0x42,0x0f] +# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0xa1,0xef,0x42,0x0f] +# CHECK-V8: ^ + +[0x92,0xff,0x42,0x0f] +# CHECK-V81a: vqrdmlsh.s16 q0, q1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0x92,0xff,0x42,0x0f] +# CHECK-V8: ^ + +[0xa2,0xff,0x42,0x0f] +# CHECK-V81a: vqrdmlsh.s32 q0, q1, d2[0] +# CHECK-V8: warning: invalid instruction encoding +# CHECK-V8: [0xa2,0xff,0x42,0x0f] +# CHECK-V8: ^ |