diff options
Diffstat (limited to 'test/MC/Disassembler/ARM')
| -rw-r--r-- | test/MC/Disassembler/ARM/arm-tests.txt | 2 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/basic-arm-instructions.txt | 110 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/invalid-virtexts.arm.txt | 10 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/move-banked-regs-arm.txt | 66 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/virtexts-arm.txt | 41 | ||||
| -rw-r--r-- | test/MC/Disassembler/ARM/virtexts-thumb.txt | 61 |
6 files changed, 254 insertions, 36 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index e82f75a..008bb11 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,6 +1,6 @@ # RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s -# CHECK: addpl r4, pc, #318767104 +# CHECK: addpl r4, pc, #76, #10 0x4c 0x45 0x8f 0x52 # CHECK: b #0 diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index 8bcf4e6..335e69f 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -10,9 +10,12 @@ # CHECK: adc r1, r2, #983040 # CHECK: adc r1, r2, #15728640 # CHECK: adc r1, r2, #251658240 -# CHECK: adc r1, r2, #4026531840 -# CHECK: adc r1, r2, #4026531855 +# CHECK: adc r1, r2, #-268435456 +# CHECK: adc r1, r2, #-268435441 +# CHECK: adc r7, r8, #-2147483638 +# CHECK: adc r7, r8, #40, #2 # CHECK: adcs r1, r2, #3840 +# CHECK: adcs r7, r8, #40, #2 # CHECK: adcseq r1, r2, #3840 # CHECK: adceq r1, r2, #3840 @@ -25,8 +28,11 @@ 0x0f 0x14 0xa2 0xe2 0x0f 0x12 0xa2 0xe2 0xff 0x12 0xa2 0xe2 +0x2a 0x71 0xa8 0xe2 +0x28 0x71 0xa8 0xe2 0x0f 0x1c 0xb2 0xe2 +0x28 0x71 0xb8 0xe2 0x0f 0x1c 0xb2 0x02 0x0f 0x1c 0xa2 0x02 @@ -112,6 +118,8 @@ # ADD #------------------------------------------------------------------------------ # CHECK: add r4, r5, #61440 +# CHECK: add r7, r8, #-2147483638 +# CHECK: add r7, r8, #40, #2 # CHECK: add r4, r5, r6 # CHECK: add r4, r5, r6, lsl #5 # CHECK: add r4, r5, r6, lsr #5 @@ -138,6 +146,8 @@ # CHECK: add r4, r4, r5, rrx 0x0f 0x4a 0x85 0xe2 +0x2a 0x71 0x88 0xe2 +0x28 0x71 0x88 0xe2 0x06 0x40 0x85 0xe0 0x86 0x42 0x85 0xe0 0xa6 0x42 0x85 0xe0 @@ -165,6 +175,15 @@ 0x65 0x40 0x84 0xe0 #------------------------------------------------------------------------------ +# ADDS +#------------------------------------------------------------------------------ +# CHECK: adds r7, r8, #-2147483638 +# CHECK: adds r7, r8, #40, #2 + +0x2a 0x71 0x98 0xe2 +0x28 0x71 0x98 0xe2 + +#------------------------------------------------------------------------------ # ADR #------------------------------------------------------------------------------ # CHECK: add r2, pc, #3 @@ -183,6 +202,8 @@ # AND #------------------------------------------------------------------------------ # CHECK: and r10, r1, #15 +# CHECK: and r7, r8, #-2147483638 +# CHECK: and r7, r8, #40, #2 # CHECK: and r10, r1, r6 # CHECK: and r10, r1, r6, lsl #10 # CHECK: and r10, r1, r6, lsr #10 @@ -209,6 +230,8 @@ # CHECK: and r10, r10, r1, rrx 0x0f 0xa0 0x01 0xe2 +0x2a 0x71 0x08 0xe2 +0x28 0x71 0x08 0xe2 0x06 0xa0 0x01 0xe0 0x06 0xa5 0x01 0xe0 0x26 0xa5 0x01 0xe0 @@ -262,6 +285,8 @@ # BIC #------------------------------------------------------------------------------ # CHECK: bic r10, r1, #15 +# CHECK: bic r7, r8, #-2147483638 +# CHECK: bic r7, r8, #40, #2 # CHECK: bic r10, r1, r6 # CHECK: bic r10, r1, r6, lsl #10 # CHECK: bic r10, r1, r6, lsr #10 @@ -288,6 +313,8 @@ # CHECK: bic r10, r10, r1, rrx 0x0f 0xa0 0xc1 0xe3 +0x2a 0x71 0xc8 0xe3 +0x28 0x71 0xc8 0xe3 0x06 0xa0 0xc1 0xe1 0x06 0xa5 0xc1 0xe1 0x26 0xa5 0xc1 0xe1 @@ -393,6 +420,8 @@ # CMN #------------------------------------------------------------------------------ # CHECK: cmn r1, #15 +# CHECK: cmn r7, #40, #2 +# CHECK: cmn r7, #-2147483638 # CHECK: cmn r1, r6 # CHECK: cmn r1, r6, lsl #10 # CHECK: cmn r1, r6, lsr #10 @@ -406,6 +435,8 @@ # CHECK: cmn r1, r6, rrx 0x0f 0x00 0x71 0xe3 +0x28 0x01 0x77 0xe3 +0x2a 0x01 0x77 0xe3 0x06 0x00 0x71 0xe1 0x06 0x05 0x71 0xe1 0x26 0x05 0x71 0xe1 @@ -422,6 +453,8 @@ # CMP #------------------------------------------------------------------------------ # CHECK: cmp r1, #15 +# CHECK: cmp r7, #40, #2 +# CHECK: cmp r7, #-2147483638 # CHECK: cmp r1, r6 # CHECK: cmp r1, r6, lsl #10 # CHECK: cmp r1, r6, lsr #10 @@ -435,6 +468,8 @@ # CHECK: cmp r1, r6, rrx 0x0f 0x00 0x51 0xe3 +0x28 0x01 0x57 0xe3 +0x2a 0x01 0x57 0xe3 0x06 0x00 0x51 0xe1 0x06 0x05 0x51 0xe1 0x26 0x05 0x51 0xe1 @@ -556,6 +591,8 @@ # EOR #------------------------------------------------------------------------------ # CHECK: eor r4, r5, #61440 +# CHECK: eor r7, r8, #-2147483638 +# CHECK: eor r7, r8, #40, #2 # CHECK: eor r4, r5, r6 # CHECK: eor r4, r5, r6, lsl #5 # CHECK: eor r4, r5, r6, lsr #5 @@ -582,6 +619,8 @@ # CHECK: eor r4, r4, r5, rrx 0x0f 0x4a 0x25 0xe2 +0x2a 0x71 0x28 0xe2 +0x28 0x71 0x28 0xe2 0x06 0x40 0x25 0xe0 0x86 0x42 0x25 0xe0 0xa6 0x42 0x25 0xe0 @@ -714,10 +753,15 @@ # CHECK: mov r4, #4080 # CHECK: mov r5, #16711680 # CHECK: mov sp, #35 +# CHECK: mov r9, #240, #30 +# CHECK: mov r7, #-2147483638 +# CHECK: mov pc, #2147483658 # CHECK: movw r6, #65535 # CHECK: movw r9, #65535 # CHECK: movw sp, #1193 # CHECK: movs r3, #7 +# CHECK: movs r11, #99 +# CHECK: movs r11, #240, #30 # CHECK: moveq r4, #4080 # CHECK: movseq r5, #16711680 @@ -725,10 +769,15 @@ 0xff 0x4e 0xa0 0xe3 0xff 0x58 0xa0 0xe3 0x23 0xd0 0xa0 0xe3 +0xf0 0x9f 0xa0 0xe3 +0x2a 0x71 0xa0 0xe3 +0x2a 0xf1 0xa0 0xe3 0xff 0x6f 0x0f 0xe3 0xff 0x9f 0x0f 0xe3 0xa9 0xd4 0x00 0xe3 0x07 0x30 0xb0 0xe3 +0x63 0xb0 0xb0 0xe3 +0xf0 0xbf 0xb0 0xe3 0xff 0x4e 0xa0 0x03 0xff 0x58 0xb0 0x03 @@ -810,6 +859,8 @@ # CHECK: msr SPSR_fc, #5 # CHECK: msr SPSR_fsxc, #5 # CHECK: msr CPSR_fsxc, #5 +# CHECK: msr APSR_nzcvq, #2147483658 +# CHECK: msr SPSR_fsxc, #40, #2 0x05 0xf0 0x29 0xe3 0x05 0xf0 0x24 0xe3 @@ -825,6 +876,8 @@ 0x05 0xf0 0x69 0xe3 0x05 0xf0 0x6f 0xe3 0x05 0xf0 0x2f 0xe3 +0x2a 0xf1 0x28 0xe3 +0x28 0xf1 0x6f 0xe3 # CHECK: msr CPSR_fc, r0 # CHECK: msr APSR_g, r0 @@ -877,14 +930,22 @@ # CHECK: mvn r3, #7 # CHECK: mvn r4, #4080 # CHECK: mvn r5, #16711680 +# CHECK: mvn r7, #40, #2 +# CHECK: mvn r7, #-2147483638 # CHECK: mvns r3, #7 +# CHECK: mvns r11, #240, #30 +# CHECK: mvns r11, #-2147483638 # CHECK: mvneq r4, #4080 # CHECK: mvnseq r5, #16711680 0x07 0x30 0xe0 0xe3 0xff 0x4e 0xe0 0xe3 0xff 0x58 0xe0 0xe3 +0x28 0x71 0xe0 0xe3 +0x2a 0x71 0xe0 0xe3 0x07 0x30 0xf0 0xe3 +0xf0 0xbf 0xf0 0xe3 +0x2a 0xb1 0xf0 0xe3 0xff 0x4e 0xe0 0x03 0xff 0x58 0xf0 0x03 @@ -940,6 +1001,8 @@ # ORR #------------------------------------------------------------------------------ # CHECK: orr r4, r5, #61440 +# CHECK: orr r7, r8, #-2147483638 +# CHECK: orr r7, r8, #40, #2 # CHECK: orr r4, r5, r6 # CHECK: orr r4, r5, r6, lsl #5 # CHECK: orr r4, r5, r6, lsr #5 @@ -966,6 +1029,8 @@ # CHECK: orr r4, r4, r5, rrx 0x0f 0x4a 0x85 0xe3 +0x2a 0x71 0x88 0xe3 +0x28 0x71 0x88 0xe3 0x06 0x40 0x85 0xe1 0x86 0x42 0x85 0xe1 0xa6 0x42 0x85 0xe1 @@ -1204,6 +1269,8 @@ # RSB #------------------------------------------------------------------------------ # CHECK: rsb r4, r5, #61440 +# CHECK: rsb r7, r8, #-2147483638 +# CHECK: rsb r7, r8, #40, #2 # CHECK: rsb r4, r5, r6 # CHECK: rsb r4, r5, r6, lsl #5 # CHECK: rsblo r4, r5, r6, lsr #5 @@ -1230,6 +1297,8 @@ # CHECK: rsb r4, r4, r5, rrx 0x0f 0x4a 0x65 0xe2 +0x2a 0x71 0x68 0xe2 +0x28 0x71 0x68 0xe2 0x06 0x40 0x65 0xe0 0x86 0x42 0x65 0xe0 0xa6 0x42 0x65 0x30 @@ -1256,9 +1325,20 @@ 0x65 0x40 0x64 0xe0 #------------------------------------------------------------------------------ +# RSBS +#------------------------------------------------------------------------------ +# CHECK: rsbs r7, r8, #-2147483638 +# CHECK: rsbs r7, r8, #40, #2 + +0x2a 0x71 0x78 0xe2 +0x28 0x71 0x78 0xe2 + +#------------------------------------------------------------------------------ # RSC #------------------------------------------------------------------------------ # CHECK: rsc r4, r5, #61440 +# CHECK: rsc r7, r8, #-2147483638 +# CHECK: rsc r7, r8, #40, #2 # CHECK: rsc r4, r5, r6 # CHECK: rsc r4, r5, r6, lsl #5 # CHECK: rsclo r4, r5, r6, lsr #5 @@ -1283,6 +1363,8 @@ # CHECK: rsc r6, r6, r7, ror r9 0x0f 0x4a 0xe5 0xe2 +0x2a 0x71 0xe8 0xe2 +0x28 0x71 0xe8 0xe2 0x06 0x40 0xe5 0xe0 0x86 0x42 0xe5 0xe0 0xa6 0x42 0xe5 0x30 @@ -1357,6 +1439,8 @@ # SBC #------------------------------------------------------------------------------ # CHECK: sbc r4, r5, #61440 +# CHECK: sbc r7, r8, #-2147483638 +# CHECK: sbc r7, r8, #40, #2 # CHECK: sbc r4, r5, r6 # CHECK: sbc r4, r5, r6, lsl #5 # CHECK: sbc r4, r5, r6, lsr #5 @@ -1381,6 +1465,8 @@ # CHECK: sbc r6, r6, r7, ror r9 0x0f 0x4a 0xc5 0xe2 +0x2a 0x71 0xc8 0xe2 +0x28 0x71 0xc8 0xe2 0x06 0x40 0xc5 0xe0 0x86 0x42 0xc5 0xe0 0xa6 0x42 0xc5 0xe0 @@ -1868,6 +1954,8 @@ # SUB #------------------------------------------------------------------------------ # CHECK: sub r4, r5, #61440 +# CHECK: sub r7, r8, #-2147483638 +# CHECK: sub r7, r8, #40, #2 # CHECK: sub r4, r5, r6 # CHECK: sub r4, r5, r6, lsl #5 # CHECK: sub r4, r5, r6, lsr #5 @@ -1892,6 +1980,8 @@ # CHECK: sub r6, r6, r7, ror r9 0x0f 0x4a 0x45 0xe2 +0x2a 0x71 0x48 0xe2 +0x28 0x71 0x48 0xe2 0x06 0x40 0x45 0xe0 0x86 0x42 0x45 0xe0 0xa6 0x42 0x45 0xe0 @@ -1916,6 +2006,14 @@ 0x57 0x69 0x46 0xe0 0x77 0x69 0x46 0xe0 +#------------------------------------------------------------------------------ +# SUBS +#------------------------------------------------------------------------------ +# CHECK: subs r7, r8, #-2147483638 +# CHECK: subs r7, r8, #40, #2 + +0x2a 0x71 0x58 0xe2 +0x28 0x71 0x58 0xe2 #------------------------------------------------------------------------------ # SVC @@ -2044,6 +2142,8 @@ # TEQ #------------------------------------------------------------------------------ # CHECK: teq r5, #61440 +# CHECK: teq r7, #-2147483638 +# CHECK: teq r7, #40, #2 # CHECK: teq r4, r5 # CHECK: teq r4, r5, lsl #5 # CHECK: teq r4, r5, lsr #5 @@ -2056,6 +2156,8 @@ # CHECK: teq r6, r7, ror r9 0x0f 0x0a 0x35 0xe3 +0x2a 0x01 0x37 0xe3 +0x28 0x01 0x37 0xe3 0x05 0x00 0x34 0xe1 0x85 0x02 0x34 0xe1 0xa5 0x02 0x34 0xe1 @@ -2072,6 +2174,8 @@ # TST #------------------------------------------------------------------------------ # CHECK: tst r5, #61440 +# CHECK: tst r7, #-2147483638 +# CHECK: tst r7, #40, #2 # CHECK: tst r4, r5 # CHECK: tst r4, r5, lsl #5 # CHECK: tst r4, r5, lsr #5 @@ -2084,6 +2188,8 @@ # CHECK: tst r6, r7, ror r9 0x0f 0x0a 0x15 0xe3 +0x2a 0x01 0x17 0xe3 +0x28 0x01 0x17 0xe3 0x05 0x00 0x14 0xe1 0x85 0x02 0x14 0xe1 0xa5 0x02 0x14 0xe1 diff --git a/test/MC/Disassembler/ARM/invalid-virtexts.arm.txt b/test/MC/Disassembler/ARM/invalid-virtexts.arm.txt new file mode 100644 index 0000000..1daada9 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-virtexts.arm.txt @@ -0,0 +1,10 @@ +# RUN: not llvm-mc -disassemble -triple armv7a -mcpu=cortex-a15 %s 2>&1 | FileCheck --check-prefix=CHECK-ARM %s + +# HVC (ARM) +[0x7f,0xff,0x4f,0xf1] +# CHECK-ARM: warning: invalid instruction encoding + +[0x70,0xff,0x4f,0x01] +[0x7f,0xff,0x4f,0xd1] +# CHECK-ARM: warning: potentially undefined instruction encoding +# CHECK-ARM: warning: potentially undefined instruction encoding diff --git a/test/MC/Disassembler/ARM/move-banked-regs-arm.txt b/test/MC/Disassembler/ARM/move-banked-regs-arm.txt index dd1d463..b92c577 100644 --- a/test/MC/Disassembler/ARM/move-banked-regs-arm.txt +++ b/test/MC/Disassembler/ARM/move-banked-regs-arm.txt @@ -1,13 +1,13 @@ @ RUN: llvm-mc -disassemble -triple armv7 -mcpu=cyclone %s | FileCheck %s -[0x00,0x22,0x20,0xe1] -[0x00,0x32,0x21,0xe1] -[0x00,0x52,0x22,0xe1] -[0x00,0x72,0x23,0xe1] -[0x00,0xb2,0x24,0xe1] -[0x00,0x12,0x25,0xe1] -[0x00,0x22,0x26,0xe1] +[0x00,0x22,0x00,0xe1] +[0x00,0x32,0x01,0xe1] +[0x00,0x52,0x02,0xe1] +[0x00,0x72,0x03,0xe1] +[0x00,0xb2,0x04,0xe1] +[0x00,0x12,0x05,0xe1] +[0x00,0x22,0x06,0xe1] @ CHECK: mrs r2, r8_usr @ CHECK: mrs r3, r9_usr @ CHECK: mrs r5, r10_usr @@ -16,14 +16,14 @@ @ CHECK: mrs r1, sp_usr @ CHECK: mrs r2, lr_usr -[0x00,0x22,0x28,0xe1] -[0x00,0x32,0x29,0xe1] -[0x00,0x52,0x2a,0xe1] -[0x00,0x72,0x2b,0xe1] -[0x00,0xb2,0x2c,0xe1] -[0x00,0x12,0x2d,0xe1] -[0x00,0x22,0x2e,0xe1] -[0x00,0x32,0x6e,0xe1] +[0x00,0x22,0x08,0xe1] +[0x00,0x32,0x09,0xe1] +[0x00,0x52,0x0a,0xe1] +[0x00,0x72,0x0b,0xe1] +[0x00,0xb2,0x0c,0xe1] +[0x00,0x12,0x0d,0xe1] +[0x00,0x22,0x0e,0xe1] +[0x00,0x32,0x4e,0xe1] @ CHECK: mrs r2, r8_fiq @ CHECK: mrs r3, r9_fiq @ CHECK: mrs r5, r10_fiq @@ -33,44 +33,44 @@ @ CHECK: mrs r2, lr_fiq @ CHECK: mrs r3, SPSR_fiq -[0x00,0x43,0x20,0xe1] -[0x00,0x93,0x21,0xe1] -[0x00,0x13,0x60,0xe1] +[0x00,0x43,0x00,0xe1] +[0x00,0x93,0x01,0xe1] +[0x00,0x13,0x40,0xe1] @ CHECK: mrs r4, lr_irq @ CHECK: mrs r9, sp_irq @ CHECK: mrs r1, SPSR_irq -[0x00,0x13,0x22,0xe1] -[0x00,0x33,0x23,0xe1] -[0x00,0x53,0x62,0xe1] +[0x00,0x13,0x02,0xe1] +[0x00,0x33,0x03,0xe1] +[0x00,0x53,0x42,0xe1] @ CHECK: mrs r1, lr_svc @ CHECK: mrs r3, sp_svc @ CHECK: mrs r5, SPSR_svc -[0x00,0x53,0x24,0xe1] -[0x00,0x73,0x25,0xe1] -[0x00,0x93,0x64,0xe1] +[0x00,0x53,0x04,0xe1] +[0x00,0x73,0x05,0xe1] +[0x00,0x93,0x44,0xe1] @ CHECK: mrs r5, lr_abt @ CHECK: mrs r7, sp_abt @ CHECK: mrs r9, SPSR_abt -[0x00,0x93,0x26,0xe1] -[0x00,0xb3,0x27,0xe1] -[0x00,0xc3,0x66,0xe1] +[0x00,0x93,0x06,0xe1] +[0x00,0xb3,0x07,0xe1] +[0x00,0xc3,0x46,0xe1] @ CHECK: mrs r9, lr_und @ CHECK: mrs r11, sp_und @ CHECK: mrs r12, SPSR_und -[0x00,0x23,0x2c,0xe1] -[0x00,0x43,0x2d,0xe1] -[0x00,0x63,0x6c,0xe1] +[0x00,0x23,0x0c,0xe1] +[0x00,0x43,0x0d,0xe1] +[0x00,0x63,0x4c,0xe1] @ CHECK: mrs r2, lr_mon @ CHECK: mrs r4, sp_mon @ CHECK: mrs r6, SPSR_mon -[0x00,0x63,0x2e,0xe1] -[0x00,0x83,0x2f,0xe1] -[0x00,0xa3,0x6e,0xe1] +[0x00,0x63,0x0e,0xe1] +[0x00,0x83,0x0f,0xe1] +[0x00,0xa3,0x4e,0xe1] @ CHECK: mrs r6, elr_hyp @ CHECK: mrs r8, sp_hyp @ CHECK: mrs r10, SPSR_hyp diff --git a/test/MC/Disassembler/ARM/virtexts-arm.txt b/test/MC/Disassembler/ARM/virtexts-arm.txt new file mode 100644 index 0000000..a18466f --- /dev/null +++ b/test/MC/Disassembler/ARM/virtexts-arm.txt @@ -0,0 +1,41 @@ +# RUN: llvm-mc -disassemble -triple armv7a -mcpu=cortex-a15 %s | FileCheck %s + +[0x71,0x00,0x40,0xe1] +[0x77,0x00,0x40,0xe1] +[0x71,0x10,0x40,0xe1] +[0x7f,0xff,0x4f,0xe1] +# CHECK: hvc #1 +# CHECK: hvc #7 +# CHECK: hvc #257 +# CHECK: hvc #65535 + +[0x6e,0x00,0x60,0xe1] +[0x6e,0x00,0x60,0x01] +[0x6e,0x00,0x60,0x11] +[0x6e,0x00,0x60,0x21] +[0x6e,0x00,0x60,0x31] +[0x6e,0x00,0x60,0x41] +[0x6e,0x00,0x60,0x51] +[0x6e,0x00,0x60,0x61] +[0x6e,0x00,0x60,0x71] +[0x6e,0x00,0x60,0x81] +[0x6e,0x00,0x60,0x91] +[0x6e,0x00,0x60,0xa1] +[0x6e,0x00,0x60,0xb1] +[0x6e,0x00,0x60,0xc1] +[0x6e,0x00,0x60,0xd1] +# CHECK: eret +# CHECK: ereteq +# CHECK: eretne +# CHECK: ereths +# CHECK: eretlo +# CHECK: eretmi +# CHECK: eretpl +# CHECK: eretvs +# CHECK: eretvc +# CHECK: erethi +# CHECK: eretls +# CHECK: eretge +# CHECK: eretlt +# CHECK: eretgt +# CHECK: eretle diff --git a/test/MC/Disassembler/ARM/virtexts-thumb.txt b/test/MC/Disassembler/ARM/virtexts-thumb.txt new file mode 100644 index 0000000..da0f621 --- /dev/null +++ b/test/MC/Disassembler/ARM/virtexts-thumb.txt @@ -0,0 +1,61 @@ +# RUN: llvm-mc -disassemble -triple thumbv7 -mcpu=cortex-a15 %s | FileCheck %s --check-prefix=CHECK-THUMB +# RUN: not llvm-mc -disassemble -triple thumbv7 -mcpu=cortex-a9 %s 2>&1 | FileCheck %s --check-prefix=CHECK-NOVIRT + +[0xe0,0xf7,0x01,0x80] +[0xe0,0xf7,0x07,0x80] +[0xe0,0xf7,0x01,0x81] +[0xef,0xf7,0xff,0x8f] +# CHECK-THUMB: hvc.w #1 +# CHECK-THUMB: hvc.w #7 +# CHECK-THUMB: hvc.w #257 +# CHECK-THUMB: hvc.w #65535 +# CHECK-NOVIRT: warning: invalid instruction encoding +# CHECK-NOVIRT: warning: invalid instruction encoding +# CHECK-NOVIRT: warning: invalid instruction encoding +# CHECK-NOVIRT: warning: invalid instruction encoding + +[0xde,0xf3,0x00,0x8f] +[0x08,0xbf] [0xde,0xf3,0x00,0x8f] +[0x18,0xbf] [0xde,0xf3,0x00,0x8f] +[0x28,0xbf] [0xde,0xf3,0x00,0x8f] +[0x38,0xbf] [0xde,0xf3,0x00,0x8f] +[0x48,0xbf] [0xde,0xf3,0x00,0x8f] +[0x58,0xbf] [0xde,0xf3,0x00,0x8f] +[0x68,0xbf] [0xde,0xf3,0x00,0x8f] +[0x78,0xbf] [0xde,0xf3,0x00,0x8f] +[0x88,0xbf] [0xde,0xf3,0x00,0x8f] +[0x98,0xbf] [0xde,0xf3,0x00,0x8f] +[0xa8,0xbf] [0xde,0xf3,0x00,0x8f] +[0xb8,0xbf] [0xde,0xf3,0x00,0x8f] +[0xc8,0xbf] [0xde,0xf3,0x00,0x8f] +[0xd8,0xbf] [0xde,0xf3,0x00,0x8f] +# CHECK-THUMB: eret +# CHECK-THUMB: ereteq +# CHECK-THUMB: eretne +# CHECK-THUMB: ereths +# CHECK-THUMB: eretlo +# CHECK-THUMB: eretmi +# CHECK-THUMB: eretpl +# CHECK-THUMB: eretvs +# CHECK-THUMB: eretvc +# CHECK-THUMB: erethi +# CHECK-THUMB: eretls +# CHECK-THUMB: eretge +# CHECK-THUMB: eretlt +# CHECK-THUMB: eretgt +# CHECK-THUMB: eretle +# CHECK-NOVIRT: subs pc, lr, #0 +# CHECK-NOVIRT: subseq pc, lr, #0 +# CHECK-NOVIRT: subsne pc, lr, #0 +# CHECK-NOVIRT: subshs pc, lr, #0 +# CHECK-NOVIRT: subslo pc, lr, #0 +# CHECK-NOVIRT: subsmi pc, lr, #0 +# CHECK-NOVIRT: subspl pc, lr, #0 +# CHECK-NOVIRT: subsvs pc, lr, #0 +# CHECK-NOVIRT: subsvc pc, lr, #0 +# CHECK-NOVIRT: subshi pc, lr, #0 +# CHECK-NOVIRT: subsls pc, lr, #0 +# CHECK-NOVIRT: subsge pc, lr, #0 +# CHECK-NOVIRT: subslt pc, lr, #0 +# CHECK-NOVIRT: subsgt pc, lr, #0 +# CHECK-NOVIRT: subsle pc, lr, #0 |