diff options
Diffstat (limited to 'test/MC/Disassembler')
64 files changed, 10876 insertions, 82 deletions
diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 537ad55..69a094d 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mattr +mp | FileCheck %s # CHECK: addpl r4, pc, #318767104 0x4c 0x45 0x8f 0x52 @@ -45,8 +45,11 @@ # CHECK: isb 0x6f 0xf0 0x7f 0xf5 -# CHECK: ldclvc p5, cr15, [r8], #-0 -0x00 0xf5 0x78 0x7c +# FIXME: LDC encoding information is incorrect. Re-enable this along with more +# robust testing for other values when we get it fleshed out and working +# properly. +# CHECKx: ldclvc p5, cr15, [r8], #-0 +#0x00 0xf5 0x78 0x7c # CHECK: ldr r0, [r2], #15 0x0f 0x00 0x92 0xe4 @@ -57,11 +60,14 @@ # CHECK: ldrh r0, [r2], #0 0xb0 0x00 0xd2 0xe0 +# CHECK: ldrh r0, [r2] +0xb0 0x00 0xd2 0xe1 + # CHECK: ldrht r0, [r2], #15 0xbf 0x00 0xf2 0xe0 # CHECK: ldrsbtvs lr, [r2], -r9 -0xd9 0xe9 0x32 0x60 +0xd9 0xe0 0x32 0x60 # CHECK: lsls r0, r2, #31 0x82 0x0f 0xb0 0xe1 @@ -101,6 +107,12 @@ # CHECK: rfedb r0! 0x00 0x0a 0x30 0xf9 +# CHECK: srsdb sp!, #19 +0x13 0x05 0x6d 0xf9 + +# CHECK: srsia sp, #9 +0x09 0x05 0xcd 0xf8 + # CHECK-NOT: rsbeq r0, r2, r0, lsl #0 # CHECK: rsbeq r0, r2, r0 0x00 0x00 0x62 0x00 @@ -168,7 +180,7 @@ 0x15 0xff 0x2f 0x01 # CHECK: uqadd16mi r6, r11, r8 -0x18 0x60 0x6b 0x46 +0x18 0x6F 0x6b 0x46 # CHECK: str r0, [sp, #4] 0x04 0x00 0x8d 0xe5 @@ -221,7 +233,7 @@ # CHECK: umull r1, r2, r3, r4 0x93 0x14 0x82 0xe0 -# CHECK: pld [pc, #-0] +# CHECK: pldw [pc, #-0] 0x00 0xf0 0x1f 0xf5 # CHECK: pli [pc, #-0] @@ -230,12 +242,15 @@ # CHECK: pli [r3, r1, lsl #2] 0x01 0xf1 0xd3 0xf6 -# CHECK: stc p2, cr4, [r9], {157} +# CHECK: stc p2, c4, [r9], {157} 0x9d 0x42 0x89 0xec -# CHECK: stc2 p2, cr4, [r9], {157} +# CHECK: stc2 p2, c4, [r9], {157} 0x9d 0x42 0x89 0xfc +# CHECK: bne #-24 +0xfa 0xff 0xff 0x1a + # CHECK: blx #60 0x0f 0x00 0x00 0xfa @@ -287,3 +302,18 @@ # CHECK: nop 0x00 0xf0 0x20 0xe3 + +# CHECK: andeq r0, r0, r0, lsr #32 +0x20 0x00 0x00 0x00 + +# CHECK: strb r3, [r2], #1 +0x01 0x30 0xc2 0xe4 + +# CHECK: strheq r0, [r0, -r0] +0xb0 0x00 0x00 0x01 + +# CHECK: rfedb #4! +0x14 0x0 0x32 0xf9 + +# CHECK: stc2l p0, c0, [r2], #-96 +0x18 0x0 0x62 0xfc diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt new file mode 100644 index 0000000..fc7eda5 --- /dev/null +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -0,0 +1,2362 @@ +# RUN: llvm-mc -triple=armv7-apple-darwin -disassemble < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# ADC (immediate) +#------------------------------------------------------------------------------ +# CHECK: adc r1, r2, #15 +# CHECK: adc r1, r2, #240 +# CHECK: adc r1, r2, #3840 +# CHECK: adc r1, r2, #61440 +# CHECK: adc r1, r2, #983040 +# CHECK: adc r1, r2, #15728640 +# CHECK: adc r1, r2, #251658240 +# CHECK: adc r1, r2, #4026531840 +# CHECK: adc r1, r2, #4026531855 +# CHECK: adcs r1, r2, #3840 +# CHECK: adcseq r1, r2, #3840 +# CHECK: adceq r1, r2, #3840 + +0x0f 0x10 0xa2 0xe2 +0xf0 0x10 0xa2 0xe2 +0x0f 0x1c 0xa2 0xe2 +0x0f 0x1a 0xa2 0xe2 +0x0f 0x18 0xa2 0xe2 +0x0f 0x16 0xa2 0xe2 +0x0f 0x14 0xa2 0xe2 +0x0f 0x12 0xa2 0xe2 +0xff 0x12 0xa2 0xe2 + +0x0f 0x1c 0xb2 0xe2 +0x0f 0x1c 0xb2 0x02 +0x0f 0x1c 0xa2 0x02 + +#------------------------------------------------------------------------------ +# ADC (register) +# ADC (shifted register) +#------------------------------------------------------------------------------ +# CHECK: adc r4, r5, r6 + +# CHECK: adc r4, r5, r6, lsl #1 +# CHECK: adc r4, r5, r6, lsl #31 +# CHECK: adc r4, r5, r6, lsr #1 +# CHECK: adc r4, r5, r6, lsr #31 +# CHECK: adc r4, r5, r6, lsr #32 +# CHECK: adc r4, r5, r6, asr #1 +# CHECK: adc r4, r5, r6, asr #31 +# CHECK: adc r4, r5, r6, asr #32 +# CHECK: adc r4, r5, r6, ror #1 +# CHECK: adc r4, r5, r6, ror #31 + +# CHECK: adc r6, r7, r8, lsl r9 +# CHECK: adc r6, r7, r8, lsr r9 +# CHECK: adc r6, r7, r8, asr r9 +# CHECK: adc r6, r7, r8, ror r9 +# CHECK: adc r4, r5, r6, rrx + +# CHECK: adc r5, r5, r6 +# CHECK: adc r4, r4, r5, lsl #1 +# CHECK: adc r4, r4, r5, lsl #31 +# CHECK: adc r4, r4, r5, lsr #1 +# CHECK: adc r4, r4, r5, lsr #31 +# CHECK: adc r4, r4, r5, lsr #32 +# CHECK: adc r4, r4, r5, asr #1 +# CHECK: adc r4, r4, r5, asr #31 +# CHECK: adc r4, r4, r5, asr #32 +# CHECK: adc r4, r4, r5, ror #1 +# CHECK: adc r4, r4, r5, ror #31 +# CHECK: adc r4, r4, r5, rrx +# CHECK: adc r6, r6, r7, lsl r9 +# CHECK: adc r6, r6, r7, lsr r9 +# CHECK: adc r6, r6, r7, asr r9 +# CHECK: adc r6, r6, r7, ror r9 +# CHECK: adc r4, r4, r5, rrx + +0x06 0x40 0xa5 0xe0 + +0x86 0x40 0xa5 0xe0 +0x86 0x4f 0xa5 0xe0 +0xa6 0x40 0xa5 0xe0 +0xa6 0x4f 0xa5 0xe0 +0x26 0x40 0xa5 0xe0 +0xc6 0x40 0xa5 0xe0 +0xc6 0x4f 0xa5 0xe0 +0x46 0x40 0xa5 0xe0 +0xe6 0x40 0xa5 0xe0 +0xe6 0x4f 0xa5 0xe0 + +0x18 0x69 0xa7 0xe0 +0x38 0x69 0xa7 0xe0 +0x58 0x69 0xa7 0xe0 +0x78 0x69 0xa7 0xe0 +0x66 0x40 0xa5 0xe0 + +0x06 0x50 0xa5 0xe0 +0x85 0x40 0xa4 0xe0 +0x85 0x4f 0xa4 0xe0 +0xa5 0x40 0xa4 0xe0 +0xa5 0x4f 0xa4 0xe0 +0x25 0x40 0xa4 0xe0 +0xc5 0x40 0xa4 0xe0 +0xc5 0x4f 0xa4 0xe0 +0x45 0x40 0xa4 0xe0 +0xe5 0x40 0xa4 0xe0 +0xe5 0x4f 0xa4 0xe0 +0x65 0x40 0xa4 0xe0 +0x17 0x69 0xa6 0xe0 +0x37 0x69 0xa6 0xe0 +0x57 0x69 0xa6 0xe0 +0x77 0x69 0xa6 0xe0 +0x65 0x40 0xa4 0xe0 + +#------------------------------------------------------------------------------ +# ADD +#------------------------------------------------------------------------------ +# CHECK: add r4, r5, #61440 +# CHECK: add r4, r5, r6 +# CHECK: add r4, r5, r6, lsl #5 +# CHECK: add r4, r5, r6, lsr #5 +# CHECK: add r4, r5, r6, lsr #5 +# CHECK: add r4, r5, r6, asr #5 +# CHECK: add r4, r5, r6, ror #5 +# CHECK: add r6, r7, r8, lsl r9 +# CHECK: add r6, r7, r8, lsr r9 +# CHECK: add r6, r7, r8, asr r9 +# CHECK: add r6, r7, r8, ror r9 +# CHECK: add r4, r5, r6, rrx + +# CHECK: add r5, r5, #61440 +# CHECK: add r4, r4, r5 +# CHECK: add r4, r4, r5, lsl #5 +# CHECK: add r4, r4, r5, lsr #5 +# CHECK: add r4, r4, r5, lsr #5 +# CHECK: add r4, r4, r5, asr #5 +# CHECK: add r4, r4, r5, ror #5 +# CHECK: add r6, r6, r7, lsl r9 +# CHECK: add r6, r6, r7, lsr r9 +# CHECK: add r6, r6, r7, asr r9 +# CHECK: add r6, r6, r7, ror r9 +# CHECK: add r4, r4, r5, rrx + +0x0f 0x4a 0x85 0xe2 +0x06 0x40 0x85 0xe0 +0x86 0x42 0x85 0xe0 +0xa6 0x42 0x85 0xe0 +0xa6 0x42 0x85 0xe0 +0xc6 0x42 0x85 0xe0 +0xe6 0x42 0x85 0xe0 +0x18 0x69 0x87 0xe0 +0x38 0x69 0x87 0xe0 +0x58 0x69 0x87 0xe0 +0x78 0x69 0x87 0xe0 +0x66 0x40 0x85 0xe0 + + +0x0f 0x5a 0x85 0xe2 +0x05 0x40 0x84 0xe0 +0x85 0x42 0x84 0xe0 +0xa5 0x42 0x84 0xe0 +0xa5 0x42 0x84 0xe0 +0xc5 0x42 0x84 0xe0 +0xe5 0x42 0x84 0xe0 +0x17 0x69 0x86 0xe0 +0x37 0x69 0x86 0xe0 +0x57 0x69 0x86 0xe0 +0x77 0x69 0x86 0xe0 +0x65 0x40 0x84 0xe0 + +#------------------------------------------------------------------------------ +# ADR +#------------------------------------------------------------------------------ +# CHECK: add r2, pc, #3 +# CHECK: sub r2, pc, #3 + +0x03 0x20 0x8f 0xe2 +0x03 0x20 0x4f 0xe2 + +#------------------------------------------------------------------------------ +# AND +#------------------------------------------------------------------------------ +# CHECK: and r10, r1, #15 +# CHECK: and r10, r1, r6 +# CHECK: and r10, r1, r6, lsl #10 +# CHECK: and r10, r1, r6, lsr #10 +# CHECK: and r10, r1, r6, lsr #10 +# CHECK: and r10, r1, r6, asr #10 +# CHECK: and r10, r1, r6, ror #10 +# CHECK: and r6, r7, r8, lsl r2 +# CHECK: and r6, r7, r8, lsr r2 +# CHECK: and r6, r7, r8, asr r2 +# CHECK: and r6, r7, r8, ror r2 +# CHECK: and r10, r1, r6, rrx + +# CHECK: and r1, r1, #15 +# CHECK: and r10, r10, r1 +# CHECK: and r10, r10, r1, lsl #10 +# CHECK: and r10, r10, r1, lsr #10 +# CHECK: and r10, r10, r1, lsr #10 +# CHECK: and r10, r10, r1, asr #10 +# CHECK: and r10, r10, r1, ror #10 +# CHECK: and r6, r6, r7, lsl r2 +# CHECK: and r6, r6, r7, lsr r2 +# CHECK: and r6, r6, r7, asr r2 +# CHECK: and r6, r6, r7, ror r2 +# CHECK: and r10, r10, r1, rrx + +0x0f 0xa0 0x01 0xe2 +0x06 0xa0 0x01 0xe0 +0x06 0xa5 0x01 0xe0 +0x26 0xa5 0x01 0xe0 +0x26 0xa5 0x01 0xe0 +0x46 0xa5 0x01 0xe0 +0x66 0xa5 0x01 0xe0 +0x18 0x62 0x07 0xe0 +0x38 0x62 0x07 0xe0 +0x58 0x62 0x07 0xe0 +0x78 0x62 0x07 0xe0 +0x66 0xa0 0x01 0xe0 + +0x0f 0x10 0x01 0xe2 +0x01 0xa0 0x0a 0xe0 +0x01 0xa5 0x0a 0xe0 +0x21 0xa5 0x0a 0xe0 +0x21 0xa5 0x0a 0xe0 +0x41 0xa5 0x0a 0xe0 +0x61 0xa5 0x0a 0xe0 +0x17 0x62 0x06 0xe0 +0x37 0x62 0x06 0xe0 +0x57 0x62 0x06 0xe0 +0x77 0x62 0x06 0xe0 +0x61 0xa0 0x0a 0xe0 + +#------------------------------------------------------------------------------ +# FIXME: ASR +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# BFC +#------------------------------------------------------------------------------ +# CHECK: bfc r5, #3, #17 +# CHECK: bfclo r5, #3, #17 + +0x9f 0x51 0xd3 0xe7 +0x9f 0x51 0xd3 0x37 + + +#------------------------------------------------------------------------------ +# BFI +#------------------------------------------------------------------------------ +# CHECK: bfi r5, r2, #3, #17 +# CHECK: bfine r5, r2, #3, #17 + +0x92 0x51 0xd3 0xe7 +0x92 0x51 0xd3 0x17 + + +#------------------------------------------------------------------------------ +# BIC +#------------------------------------------------------------------------------ +# CHECK: bic r10, r1, #15 +# CHECK: bic r10, r1, r6 +# CHECK: bic r10, r1, r6, lsl #10 +# CHECK: bic r10, r1, r6, lsr #10 +# CHECK: bic r10, r1, r6, lsr #10 +# CHECK: bic r10, r1, r6, asr #10 +# CHECK: bic r10, r1, r6, ror #10 +# CHECK: bic r6, r7, r8, lsl r2 +# CHECK: bic r6, r7, r8, lsr r2 +# CHECK: bic r6, r7, r8, asr r2 +# CHECK: bic r6, r7, r8, ror r2 +# CHECK: bic r10, r1, r6, rrx + +# CHECK: bic r1, r1, #15 +# CHECK: bic r10, r10, r1 +# CHECK: bic r10, r10, r1, lsl #10 +# CHECK: bic r10, r10, r1, lsr #10 +# CHECK: bic r10, r10, r1, lsr #10 +# CHECK: bic r10, r10, r1, asr #10 +# CHECK: bic r10, r10, r1, ror #10 +# CHECK: bic r6, r6, r7, lsl r2 +# CHECK: bic r6, r6, r7, lsr r2 +# CHECK: bic r6, r6, r7, asr r2 +# CHECK: bic r6, r6, r7, ror r2 +# CHECK: bic r10, r10, r1, rrx + +0x0f 0xa0 0xc1 0xe3 +0x06 0xa0 0xc1 0xe1 +0x06 0xa5 0xc1 0xe1 +0x26 0xa5 0xc1 0xe1 +0x26 0xa5 0xc1 0xe1 +0x46 0xa5 0xc1 0xe1 +0x66 0xa5 0xc1 0xe1 +0x18 0x62 0xc7 0xe1 +0x38 0x62 0xc7 0xe1 +0x58 0x62 0xc7 0xe1 +0x78 0x62 0xc7 0xe1 +0x66 0xa0 0xc1 0xe1 + + +0x0f 0x10 0xc1 0xe3 +0x01 0xa0 0xca 0xe1 +0x01 0xa5 0xca 0xe1 +0x21 0xa5 0xca 0xe1 +0x21 0xa5 0xca 0xe1 +0x41 0xa5 0xca 0xe1 +0x61 0xa5 0xca 0xe1 +0x17 0x62 0xc6 0xe1 +0x37 0x62 0xc6 0xe1 +0x57 0x62 0xc6 0xe1 +0x77 0x62 0xc6 0xe1 +0x61 0xa0 0xca 0xe1 + +#------------------------------------------------------------------------------ +# BKPT +#------------------------------------------------------------------------------ +# CHECK: bkpt #10 +# CHECK: bkpt #65535 + +0x7a 0x00 0x20 0xe1 +0x7f 0xff 0x2f 0xe1 + +#------------------------------------------------------------------------------ +# BLX (register) +#------------------------------------------------------------------------------ +# CHECK: blx r2 +# CHECK: blxne r2 + +0x32 0xff 0x2f 0xe1 +0x32 0xff 0x2f 0x11 + +#------------------------------------------------------------------------------ +# BLX (immediate) +#------------------------------------------------------------------------------ +# CHECK: blx #32424576 +# CHECK: blx #16212288 + +0xa0 0xb0 0x7b 0xfa +0x50 0xd8 0x3d 0xfa + +#------------------------------------------------------------------------------ +# BX +#------------------------------------------------------------------------------ + +# CHECK: bx r2 +# CHECK: bxne r2 + +0x12 0xff 0x2f 0xe1 +0x12 0xff 0x2f 0x11 + +#------------------------------------------------------------------------------ +# BXJ +#------------------------------------------------------------------------------ + +# CHECK: bxj r2 +# CHECK: bxjne r2 + +0x22 0xff 0x2f 0xe1 +0x22 0xff 0x2f 0x11 + + +#------------------------------------------------------------------------------ +# CDP/CDP2 +#------------------------------------------------------------------------------ +# CHECK: cdp p7, #1, c1, c1, c1, #4 +# CHECK: cdp2 p7, #1, c1, c1, c1, #4 + +0x81 0x17 0x11 0xee +0x81 0x17 0x11 0xfe + + +#------------------------------------------------------------------------------ +# CLREX +#------------------------------------------------------------------------------ +# CHECK: clrex + +0x1f 0xf0 0x7f 0xf5 + + +#------------------------------------------------------------------------------ +# CLZ +#------------------------------------------------------------------------------ +# CHECK: clz r1, r2 +# CHECK: clzeq r1, r2 + +0x12 0x1f 0x6f 0xe1 +0x12 0x1f 0x6f 0x01 + +#------------------------------------------------------------------------------ +# CMN +#------------------------------------------------------------------------------ +# CHECK: cmn r1, #15 +# CHECK: cmn r1, r6 +# CHECK: cmn r1, r6, lsl #10 +# CHECK: cmn r1, r6, lsr #10 +# CHECK: cmn sp, r6, lsr #10 +# CHECK: cmn r1, r6, asr #10 +# CHECK: cmn r1, r6, ror #10 +# CHECK: cmn r7, r8, lsl r2 +# CHECK: cmn sp, r8, lsr r2 +# CHECK: cmn r7, r8, asr r2 +# CHECK: cmn r7, r8, ror r2 +# CHECK: cmn r1, r6, rrx + +0x0f 0x00 0x71 0xe3 +0x06 0x00 0x71 0xe1 +0x06 0x05 0x71 0xe1 +0x26 0x05 0x71 0xe1 +0x26 0x05 0x7d 0xe1 +0x46 0x05 0x71 0xe1 +0x66 0x05 0x71 0xe1 +0x18 0x02 0x77 0xe1 +0x38 0x02 0x7d 0xe1 +0x58 0x02 0x77 0xe1 +0x78 0x02 0x77 0xe1 +0x66 0x00 0x71 0xe1 + +#------------------------------------------------------------------------------ +# CMP +#------------------------------------------------------------------------------ +# CHECK: cmp r1, #15 +# CHECK: cmp r1, r6 +# CHECK: cmp r1, r6, lsl #10 +# CHECK: cmp r1, r6, lsr #10 +# CHECK: cmp sp, r6, lsr #10 +# CHECK: cmp r1, r6, asr #10 +# CHECK: cmp r1, r6, ror #10 +# CHECK: cmp r7, r8, lsl r2 +# CHECK: cmp sp, r8, lsr r2 +# CHECK: cmp r7, r8, asr r2 +# CHECK: cmp r7, r8, ror r2 +# CHECK: cmp r1, r6, rrx + +0x0f 0x00 0x51 0xe3 +0x06 0x00 0x51 0xe1 +0x06 0x05 0x51 0xe1 +0x26 0x05 0x51 0xe1 +0x26 0x05 0x5d 0xe1 +0x46 0x05 0x51 0xe1 +0x66 0x05 0x51 0xe1 +0x18 0x02 0x57 0xe1 +0x38 0x02 0x5d 0xe1 +0x58 0x02 0x57 0xe1 +0x78 0x02 0x57 0xe1 +0x66 0x00 0x51 0xe1 + + +#------------------------------------------------------------------------------ +# CPS +#------------------------------------------------------------------------------ +# CHECK: cpsie aif +# CHECK: cps #15 +# CHECK: cpsid if, #10 + +0xc0 0x01 0x08 0xf1 +0x0f 0x00 0x02 0xf1 +0xca 0x00 0x0e 0xf1 + + +#------------------------------------------------------------------------------ +# DBG +#------------------------------------------------------------------------------ +# CHECK: dbg #0 +# CHECK: dbg #5 +# CHECK: dbg #15 + +0xf0 0xf0 0x20 0xe3 +0xf5 0xf0 0x20 0xe3 +0xff 0xf0 0x20 0xe3 + + +#------------------------------------------------------------------------------ +# DMB +#------------------------------------------------------------------------------ +# CHECK: dmb sy +# CHECK: dmb st +# CHECK: dmb ish +# CHECK: dmb ishst +# CHECK: dmb nsh +# CHECK: dmb nshst +# CHECK: dmb osh +# CHECK: dmb oshst +# CHECK: dmb + +0x5f 0xf0 0x7f 0xf5 +0x5e 0xf0 0x7f 0xf5 +0x5b 0xf0 0x7f 0xf5 +0x5a 0xf0 0x7f 0xf5 +0x57 0xf0 0x7f 0xf5 +0x56 0xf0 0x7f 0xf5 +0x53 0xf0 0x7f 0xf5 +0x52 0xf0 0x7f 0xf5 +0x5f 0xf0 0x7f 0xf5 + +#------------------------------------------------------------------------------ +# DSB +#------------------------------------------------------------------------------ +# CHECK: dsb sy +# CHECK: dsb st +# CHECK: dsb ish +# CHECK: dsb ishst +# CHECK: dsb nsh +# CHECK: dsb nshst +# CHECK: dsb osh +# CHECK: dsb oshst +# CHECK: dsb + +0x4f 0xf0 0x7f 0xf5 +0x4e 0xf0 0x7f 0xf5 +0x4b 0xf0 0x7f 0xf5 +0x4a 0xf0 0x7f 0xf5 +0x47 0xf0 0x7f 0xf5 +0x46 0xf0 0x7f 0xf5 +0x43 0xf0 0x7f 0xf5 +0x42 0xf0 0x7f 0xf5 +0x4f 0xf0 0x7f 0xf5 + +#------------------------------------------------------------------------------ +# EOR +#------------------------------------------------------------------------------ +# CHECK: eor r4, r5, #61440 +# CHECK: eor r4, r5, r6 +# CHECK: eor r4, r5, r6, lsl #5 +# CHECK: eor r4, r5, r6, lsr #5 +# CHECK: eor r4, r5, r6, lsr #5 +# CHECK: eor r4, r5, r6, asr #5 +# CHECK: eor r4, r5, r6, ror #5 +# CHECK: eor r6, r7, r8, lsl r9 +# CHECK: eor r6, r7, r8, lsr r9 +# CHECK: eor r6, r7, r8, asr r9 +# CHECK: eor r6, r7, r8, ror r9 +# CHECK: eor r4, r5, r6, rrx + +# CHECK: eor r5, r5, #61440 +# CHECK: eor r4, r4, r5 +# CHECK: eor r4, r4, r5, lsl #5 +# CHECK: eor r4, r4, r5, lsr #5 +# CHECK: eor r4, r4, r5, lsr #5 +# CHECK: eor r4, r4, r5, asr #5 +# CHECK: eor r4, r4, r5, ror #5 +# CHECK: eor r6, r6, r7, lsl r9 +# CHECK: eor r6, r6, r7, lsr r9 +# CHECK: eor r6, r6, r7, asr r9 +# CHECK: eor r6, r6, r7, ror r9 +# CHECK: eor r4, r4, r5, rrx + +0x0f 0x4a 0x25 0xe2 +0x06 0x40 0x25 0xe0 +0x86 0x42 0x25 0xe0 +0xa6 0x42 0x25 0xe0 +0xa6 0x42 0x25 0xe0 +0xc6 0x42 0x25 0xe0 +0xe6 0x42 0x25 0xe0 +0x18 0x69 0x27 0xe0 +0x38 0x69 0x27 0xe0 +0x58 0x69 0x27 0xe0 +0x78 0x69 0x27 0xe0 +0x66 0x40 0x25 0xe0 + + +0x0f 0x5a 0x25 0xe2 +0x05 0x40 0x24 0xe0 +0x85 0x42 0x24 0xe0 +0xa5 0x42 0x24 0xe0 +0xa5 0x42 0x24 0xe0 +0xc5 0x42 0x24 0xe0 +0xe5 0x42 0x24 0xe0 +0x17 0x69 0x26 0xe0 +0x37 0x69 0x26 0xe0 +0x57 0x69 0x26 0xe0 +0x77 0x69 0x26 0xe0 +0x65 0x40 0x24 0xe0 + + +#------------------------------------------------------------------------------ +# ISB +#------------------------------------------------------------------------------ +# CHECK: isb sy + +0x6f 0xf0 0x7f 0xf5 + + + +#------------------------------------------------------------------------------ +# LDM* +#------------------------------------------------------------------------------ +# CHECK: ldm r2, {r1, r3, r4, r5, r6, sp} +# CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} +# CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} +# CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} + + +# CHECK: ldm r2!, {r1, r3, r4, r5, r6, sp} +# CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} +# CHECK: ldmda r2!, {r1, r3, r4, r5, r6, sp} +# CHECK: ldmdb r2!, {r1, r3, r4, r5, r6, sp} + +0x7a 0x20 0x92 0xe8 +0x7a 0x20 0x92 0xe9 +0x7a 0x20 0x12 0xe8 +0x7a 0x20 0x12 0xe9 + +0x7a 0x20 0xb2 0xe8 +0x7a 0x20 0xb2 0xe9 +0x7a 0x20 0x32 0xe8 +0x7a 0x20 0x32 0xe9 + + +#------------------------------------------------------------------------------ +# LDREX/LDREXB/LDREXH/LDREXD +#------------------------------------------------------------------------------ +# CHECK: ldrexb r3, [r4] +# CHECK: ldrexh r2, [r5] +# CHECK: ldrex r1, [r7] +# CHECK: ldrexd r6, r7, [r8] + +0x9f 0x3f 0xd4 0xe1 +0x9f 0x2f 0xf5 0xe1 +0x9f 0x1f 0x97 0xe1 +0x9f 0x6f 0xb8 0xe1 + + +#------------------------------------------------------------------------------ +# FIXME: LSL +#------------------------------------------------------------------------------ +#------------------------------------------------------------------------------ +# FIXME: LSR +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# MCR/MCR2 +#------------------------------------------------------------------------------ +# CHECK: mcr p7, #1, r5, c1, c1, #4 +# CHECK: mcr2 p7, #1, r5, c1, c1, #4 + +0x91 0x57 0x21 0xee +0x91 0x57 0x21 0xfe + +#------------------------------------------------------------------------------ +# MCRR/MCRR2 +#------------------------------------------------------------------------------ +# CHECK: mcrr p7, #15, r5, r4, c1 +# CHECK: mcrr2 p7, #15, r5, r4, c1 + +0xf1 0x57 0x44 0xec +0xf1 0x57 0x44 0xfc + + +#------------------------------------------------------------------------------ +# MLA +#------------------------------------------------------------------------------ +# CHECK: mla r1, r2, r3, r4 +# CHECK: mlas r1, r2, r3, r4 +# CHECK: mlane r1, r2, r3, r4 +# CHECK: mlasne r1, r2, r3, r4 + +0x92 0x43 0x21 0xe0 +0x92 0x43 0x31 0xe0 +0x92 0x43 0x21 0x10 +0x92 0x43 0x31 0x10 + +#------------------------------------------------------------------------------ +# MLS +#------------------------------------------------------------------------------ +# CHECK: mls r2, r5, r6, r3 +# CHECK: mlsne r2, r5, r6, r3 + +0x95 0x36 0x62 0xe0 +0x95 0x36 0x62 0x10 + +#------------------------------------------------------------------------------ +# MOV (immediate) +#------------------------------------------------------------------------------ +# CHECK: mov r3, #7 +# CHECK: mov r4, #4080 +# CHECK: mov r5, #16711680 +# CHECK: movw r6, #65535 +# CHECK: movw r9, #65535 +# CHECK: movs r3, #7 +# CHECK: moveq r4, #4080 +# CHECK: movseq r5, #16711680 + +0x07 0x30 0xa0 0xe3 +0xff 0x4e 0xa0 0xe3 +0xff 0x58 0xa0 0xe3 +0xff 0x6f 0x0f 0xe3 +0xff 0x9f 0x0f 0xe3 +0x07 0x30 0xb0 0xe3 +0xff 0x4e 0xa0 0x03 +0xff 0x58 0xb0 0x03 + +#------------------------------------------------------------------------------ +# MOV (register) +#------------------------------------------------------------------------------ +# CHECK: mov r2, r3 +# CHECK: movs r2, r3 +# CHECK: moveq r2, r3 +# CHECK: movseq r2, r3 + +0x03 0x20 0xa0 0xe1 +0x03 0x20 0xb0 0xe1 +0x03 0x20 0xa0 0x01 +0x03 0x20 0xb0 0x01 + +#------------------------------------------------------------------------------ +# MOVT +#------------------------------------------------------------------------------ +# CHECK: movt r3, #7 +# CHECK: movt r6, #65535 +# CHECK: movteq r4, #4080 + +0x07 0x30 0x40 0xe3 +0xff 0x6f 0x4f 0xe3 +0xf0 0x4f 0x40 0x03 + + +#------------------------------------------------------------------------------ +# MRC/MRC2 +#------------------------------------------------------------------------------ +# CHECK: mrc p14, #0, r1, c1, c2, #4 +# CHECK: mrc2 p14, #0, r1, c1, c2, #4 + +0x92 0x1e 0x11 0xee +0x92 0x1e 0x11 0xfe + +#------------------------------------------------------------------------------ +# MRRC/MRRC2 +#------------------------------------------------------------------------------ +# CHECK: mrrc p7, #1, r5, r4, c1 +# CHECK: mrrc2 p7, #1, r5, r4, c1 + +0x11 0x57 0x54 0xec +0x11 0x57 0x54 0xfc + + +#------------------------------------------------------------------------------ +# MRS +#------------------------------------------------------------------------------ +# CHECK: mrs r8, apsr +# CHECK: mrs r8, spsr +0x00 0x80 0x0f 0xe1 +0x00 0x80 0x4f 0xe1 + + + +#------------------------------------------------------------------------------ +# MSR +#------------------------------------------------------------------------------ + +# CHECK: msr CPSR_fc, #5 +# CHECK: msr APSR_g, #5 +# CHECK: msr APSR_nzcvq, #5 +# CHECK: msr APSR_nzcvq, #5 +# CHECK: msr APSR_nzcvqg, #5 +# CHECK: msr CPSR_fc, #5 +# CHECK: msr CPSR_c, #5 +# CHECK: msr CPSR_x, #5 +# CHECK: msr CPSR_fc, #5 +# CHECK: msr CPSR_fc, #5 +# CHECK: msr CPSR_fsx, #5 +# CHECK: msr SPSR_fc, #5 +# CHECK: msr SPSR_fsxc, #5 +# CHECK: msr CPSR_fsxc, #5 + +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x24 0xe3 +0x05 0xf0 0x28 0xe3 +0x05 0xf0 0x28 0xe3 +0x05 0xf0 0x2c 0xe3 +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x21 0xe3 +0x05 0xf0 0x22 0xe3 +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x29 0xe3 +0x05 0xf0 0x2e 0xe3 +0x05 0xf0 0x69 0xe3 +0x05 0xf0 0x6f 0xe3 +0x05 0xf0 0x2f 0xe3 + +# CHECK: msr CPSR_fc, r0 +# CHECK: msr APSR_g, r0 +# CHECK: msr APSR_nzcvq, r0 +# CHECK: msr APSR_nzcvq, r0 +# CHECK: msr APSR_nzcvqg, r0 +# CHECK: msr CPSR_fc, r0 +# CHECK: msr CPSR_c, r0 +# CHECK: msr CPSR_x, r0 +# CHECK: msr CPSR_fc, r0 +# CHECK: msr CPSR_fc, r0 +# CHECK: msr CPSR_fsx, r0 +# CHECK: msr SPSR_fc, r0 +# CHECK: msr SPSR_fsxc, r0 +# CHECK: msr CPSR_fsxc, r0 + +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x24 0xe1 +0x00 0xf0 0x28 0xe1 +0x00 0xf0 0x28 0xe1 +0x00 0xf0 0x2c 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x21 0xe1 +0x00 0xf0 0x22 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x29 0xe1 +0x00 0xf0 0x2e 0xe1 +0x00 0xf0 0x69 0xe1 +0x00 0xf0 0x6f 0xe1 +0x00 0xf0 0x2f 0xe1 + +#------------------------------------------------------------------------------ +# MUL +#------------------------------------------------------------------------------ + +# CHECK: mul r5, r6, r7 +# CHECK: muls r5, r6, r7 +# CHECK: mulgt r5, r6, r7 +# CHECK: mulsle r5, r6, r7 + +0x96 0x07 0x05 0xe0 +0x96 0x07 0x15 0xe0 +0x96 0x07 0x05 0xc0 +0x96 0x07 0x15 0xd0 + + +#------------------------------------------------------------------------------ +# MVN (immediate) +#------------------------------------------------------------------------------ +# CHECK: mvn r3, #7 +# CHECK: mvn r4, #4080 +# CHECK: mvn r5, #16711680 +# CHECK: mvns r3, #7 +# CHECK: mvneq r4, #4080 +# CHECK: mvnseq r5, #16711680 + +0x07 0x30 0xe0 0xe3 +0xff 0x4e 0xe0 0xe3 +0xff 0x58 0xe0 0xe3 +0x07 0x30 0xf0 0xe3 +0xff 0x4e 0xe0 0x03 +0xff 0x58 0xf0 0x03 + + +#------------------------------------------------------------------------------ +# MVN (register) +#------------------------------------------------------------------------------ +# CHECK: mvn r2, r3 +# CHECK: mvns r2, r3 +# CHECK: mvn r5, r6, lsl #19 +# CHECK: mvn r5, r6, lsr #9 +# CHECK: mvn r5, r6, asr #4 +# CHECK: mvn r5, r6, ror #6 +# CHECK: mvn r5, r6, rrx +# CHECK: mvneq r2, r3 +# CHECK: mvnseq r2, r3, lsl #10 + +0x03 0x20 0xe0 0xe1 +0x03 0x20 0xf0 0xe1 +0x86 0x59 0xe0 0xe1 +0xa6 0x54 0xe0 0xe1 +0x46 0x52 0xe0 0xe1 +0x66 0x53 0xe0 0xe1 +0x66 0x50 0xe0 0xe1 +0x03 0x20 0xe0 0x01 +0x03 0x25 0xf0 0x01 + + +#------------------------------------------------------------------------------ +# MVN (shifted register) +#------------------------------------------------------------------------------ +# CHECK: mvn r5, r6, lsl r7 +# CHECK: mvns r5, r6, lsr r7 +# CHECK: mvngt r5, r6, asr r7 +# CHECK: mvnslt r5, r6, ror r7 + +0x16 0x57 0xe0 0xe1 +0x36 0x57 0xf0 0xe1 +0x56 0x57 0xe0 0xc1 +0x76 0x57 0xf0 0xb1 + +#------------------------------------------------------------------------------ +# NOP +#------------------------------------------------------------------------------ +# CHECK: nop +# CHECK: nopgt + +0x00 0xf0 0x20 0xe3 +0x00 0xf0 0x20 0xc3 + + +#------------------------------------------------------------------------------ +# ORR +#------------------------------------------------------------------------------ +# CHECK: orr r4, r5, #61440 +# CHECK: orr r4, r5, r6 +# CHECK: orr r4, r5, r6, lsl #5 +# CHECK: orr r4, r5, r6, lsr #5 +# CHECK: orr r4, r5, r6, lsr #5 +# CHECK: orr r4, r5, r6, asr #5 +# CHECK: orr r4, r5, r6, ror #5 +# CHECK: orr r6, r7, r8, lsl r9 +# CHECK: orr r6, r7, r8, lsr r9 +# CHECK: orr r6, r7, r8, asr r9 +# CHECK: orr r6, r7, r8, ror r9 +# CHECK: orr r4, r5, r6, rrx + +# CHECK: orr r5, r5, #61440 +# CHECK: orr r4, r4, r5 +# CHECK: orr r4, r4, r5, lsl #5 +# CHECK: orr r4, r4, r5, lsr #5 +# CHECK: orr r4, r4, r5, lsr #5 +# CHECK: orr r4, r4, r5, asr #5 +# CHECK: orr r4, r4, r5, ror #5 +# CHECK: orr r6, r6, r7, lsl r9 +# CHECK: orr r6, r6, r7, lsr r9 +# CHECK: orr r6, r6, r7, asr r9 +# CHECK: orr r6, r6, r7, ror r9 +# CHECK: orr r4, r4, r5, rrx + +0x0f 0x4a 0x85 0xe3 +0x06 0x40 0x85 0xe1 +0x86 0x42 0x85 0xe1 +0xa6 0x42 0x85 0xe1 +0xa6 0x42 0x85 0xe1 +0xc6 0x42 0x85 0xe1 +0xe6 0x42 0x85 0xe1 +0x18 0x69 0x87 0xe1 +0x38 0x69 0x87 0xe1 +0x58 0x69 0x87 0xe1 +0x78 0x69 0x87 0xe1 +0x66 0x40 0x85 0xe1 + +0x0f 0x5a 0x85 0xe3 +0x05 0x40 0x84 0xe1 +0x85 0x42 0x84 0xe1 +0xa5 0x42 0x84 0xe1 +0xa5 0x42 0x84 0xe1 +0xc5 0x42 0x84 0xe1 +0xe5 0x42 0x84 0xe1 +0x17 0x69 0x86 0xe1 +0x37 0x69 0x86 0xe1 +0x57 0x69 0x86 0xe1 +0x77 0x69 0x86 0xe1 +0x65 0x40 0x84 0xe1 + +# CHECK: orrseq r4, r5, #61440 +# CHECK: orrne r4, r5, r6 +# CHECK: orrseq r4, r5, r6, lsl #5 +# CHECK: orrlo r6, r7, r8, ror r9 +# CHECK: orrshi r4, r5, r6, rrx +# CHECK: orrhs r5, r5, #61440 +# CHECK: orrseq r4, r4, r5 +# CHECK: orrne r6, r6, r7, asr r9 +# CHECK: orrslt r6, r6, r7, ror r9 +# CHECK: orrsgt r4, r4, r5, rrx + +0x0f 0x4a 0x95 0x03 +0x06 0x40 0x85 0x11 +0x86 0x42 0x95 0x01 +0x78 0x69 0x87 0x31 +0x66 0x40 0x95 0x81 +0x0f 0x5a 0x85 0x23 +0x05 0x40 0x94 0x01 +0x57 0x69 0x86 0x11 +0x77 0x69 0x96 0xb1 +0x65 0x40 0x94 0xc1 + +#------------------------------------------------------------------------------ +# PKH +#------------------------------------------------------------------------------ +# CHECK: pkhbt r2, r2, r3 +# CHECK: pkhbt r2, r2, r3, lsl #31 +# CHECK: pkhbt r2, r2, r3 +# CHECK: pkhbt r2, r2, r3, lsl #15 + +# CHECK: pkhbt r2, r2, r3 +# CHECK: pkhtb r2, r2, r3, asr #31 +# CHECK: pkhtb r2, r2, r3, asr #15 + +0x13 0x20 0x82 0xe6 +0x93 0x2f 0x82 0xe6 +0x13 0x20 0x82 0xe6 +0x93 0x27 0x82 0xe6 + +0x13 0x20 0x82 0xe6 +0xd3 0x2f 0x82 0xe6 +0xd3 0x27 0x82 0xe6 + +#------------------------------------------------------------------------------ +# FIXME: PLD +#------------------------------------------------------------------------------ +#------------------------------------------------------------------------------ +# FIXME: PLI +#------------------------------------------------------------------------------ + + +#------------------------------------------------------------------------------ +# POP +#------------------------------------------------------------------------------ +# CHECK: ldr r7, [sp], #4 +# CHECK: pop {r7, r8, r9, r10} + +0x04 0x70 0x9d 0xe4 +0x80 0x07 0xbd 0xe8 + + +#------------------------------------------------------------------------------ +# PUSH +#------------------------------------------------------------------------------ +# CHECK: str r7, [sp, #-4]! +# CHECK: push {r7, r8, r9, r10} + +0x04 0x70 0x2d 0xe5 +0x80 0x07 0x2d 0xe9 + + +#------------------------------------------------------------------------------ +# QADD/QADD16/QADD8 +#------------------------------------------------------------------------------ +# CHECK: qadd r1, r2, r3 +# CHECK: qaddne r1, r2, r3 +# CHECK: qadd16 r1, r2, r3 +# CHECK: qadd16gt r1, r2, r3 +# CHECK: qadd8 r1, r2, r3 +# CHECK: qadd8le r1, r2, r3 + +0x52 0x10 0x03 0xe1 +0x52 0x10 0x03 0x11 +0x13 0x1f 0x22 0xe6 +0x13 0x1f 0x22 0xc6 +0x93 0x1f 0x22 0xe6 +0x93 0x1f 0x22 0xd6 + + +#------------------------------------------------------------------------------ +# QDADD/QDSUB +#------------------------------------------------------------------------------ +# CHECK: qdadd r6, r7, r8 +# CHECK: qdaddhi r6, r7, r8 +# CHECK: qdsub r6, r7, r8 +# CHECK: qdsubhi r6, r7, r8 + +0x57 0x60 0x48 0xe1 +0x57 0x60 0x48 0x81 +0x57 0x60 0x68 0xe1 +0x57 0x60 0x68 0x81 + + +#------------------------------------------------------------------------------ +# QSAX +#------------------------------------------------------------------------------ +# CHECK: qsax r9, r12, r0 +# CHECK: qsaxeq r9, r12, r0 + +0x50 0x9f 0x2c 0xe6 +0x50 0x9f 0x2c 0x06 + + +#------------------------------------------------------------------------------ +# QSUB/QSUB16/QSUB8 +#------------------------------------------------------------------------------ +# CHECK: qsub r1, r2, r3 +# CHECK: qsubne r1, r2, r3 +# CHECK: qsub16 r1, r2, r3 +# CHECK: qsub16gt r1, r2, r3 +# CHECK: qsub8 r1, r2, r3 +# CHECK: qsub8le r1, r2, r3 + +0x52 0x10 0x23 0xe1 +0x52 0x10 0x23 0x11 +0x73 0x1f 0x22 0xe6 +0x73 0x1f 0x22 0xc6 +0xf3 0x1f 0x22 0xe6 +0xf3 0x1f 0x22 0xd6 + + +#------------------------------------------------------------------------------ +# RBIT +#------------------------------------------------------------------------------ +# CHECK: rbit r1, r2 +# CHECK: rbitne r1, r2 + +0x32 0x1f 0xff 0xe6 +0x32 0x1f 0xff 0x16 + + +#------------------------------------------------------------------------------ +# REV/REV16/REVSH +#------------------------------------------------------------------------------ +# CHECK: rev r1, r9 +# CHECK: revne r1, r5 +# CHECK: rev16 r8, r3 +# CHECK: rev16ne r12, r4 +# CHECK: revsh r4, r9 +# CHECK: revshne r9, r1 + +0x39 0x1f 0xbf 0xe6 +0x35 0x1f 0xbf 0x16 +0xb3 0x8f 0xbf 0xe6 +0xb4 0xcf 0xbf 0x16 +0xb9 0x4f 0xff 0xe6 +0xb1 0x9f 0xff 0x16 + + +#------------------------------------------------------------------------------ +# RFE +#------------------------------------------------------------------------------ +# CHECK: rfeda r2 +# CHECK: rfedb r3 +# CHECK: rfeia r5 +# CHECK: rfeib r6 + +# CHECK: rfeda r4! +# CHECK: rfedb r7! +# CHECK: rfeia r9! +# CHECK: rfeib r8! + +# CHECK: rfeda r2 +# CHECK: rfedb r3 +# CHECK: rfeia r5 +# CHECK: rfeib r6 + +# CHECK: rfeda r4! +# CHECK: rfedb r7! +# CHECK: rfeia r9! +# CHECK: rfeib r8! + +# CHECK: rfeia r1 +# CHECK: rfeia r1! + +0x00 0x0a 0x12 0xf8 +0x00 0x0a 0x13 0xf9 +0x00 0x0a 0x95 0xf8 +0x00 0x0a 0x96 0xf9 + +0x00 0x0a 0x34 0xf8 +0x00 0x0a 0x37 0xf9 +0x00 0x0a 0xb9 0xf8 +0x00 0x0a 0xb8 0xf9 + +0x00 0x0a 0x12 0xf8 +0x00 0x0a 0x13 0xf9 +0x00 0x0a 0x95 0xf8 +0x00 0x0a 0x96 0xf9 + +0x00 0x0a 0x34 0xf8 +0x00 0x0a 0x37 0xf9 +0x00 0x0a 0xb9 0xf8 +0x00 0x0a 0xb8 0xf9 + +0x00 0x0a 0x91 0xf8 +0x00 0x0a 0xb1 0xf8 + + +#------------------------------------------------------------------------------ +# RSB +#------------------------------------------------------------------------------ +# CHECK: rsb r4, r5, #61440 +# CHECK: rsb r4, r5, r6 +# CHECK: rsb r4, r5, r6, lsl #5 +# CHECK: rsblo r4, r5, r6, lsr #5 +# CHECK: rsb r4, r5, r6, lsr #5 +# CHECK: rsb r4, r5, r6, asr #5 +# CHECK: rsb r4, r5, r6, ror #5 +# CHECK: rsb r6, r7, r8, lsl r9 +# CHECK: rsb r6, r7, r8, lsr r9 +# CHECK: rsb r6, r7, r8, asr r9 +# CHECK: rsble r6, r7, r8, ror r9 +# CHECK: rsb r4, r5, r6, rrx + +# CHECK: rsb r5, r5, #61440 +# CHECK: rsb r4, r4, r5 +# CHECK: rsb r4, r4, r5, lsl #5 +# CHECK: rsb r4, r4, r5, lsr #5 +# CHECK: rsbne r4, r4, r5, lsr #5 +# CHECK: rsb r4, r4, r5, asr #5 +# CHECK: rsb r4, r4, r5, ror #5 +# CHECK: rsbgt r6, r6, r7, lsl r9 +# CHECK: rsb r6, r6, r7, lsr r9 +# CHECK: rsb r6, r6, r7, asr r9 +# CHECK: rsb r6, r6, r7, ror r9 +# CHECK: rsb r4, r4, r5, rrx + +0x0f 0x4a 0x65 0xe2 +0x06 0x40 0x65 0xe0 +0x86 0x42 0x65 0xe0 +0xa6 0x42 0x65 0x30 +0xa6 0x42 0x65 0xe0 +0xc6 0x42 0x65 0xe0 +0xe6 0x42 0x65 0xe0 +0x18 0x69 0x67 0xe0 +0x38 0x69 0x67 0xe0 +0x58 0x69 0x67 0xe0 +0x78 0x69 0x67 0xd0 +0x66 0x40 0x65 0xe0 + +0x0f 0x5a 0x65 0xe2 +0x05 0x40 0x64 0xe0 +0x85 0x42 0x64 0xe0 +0xa5 0x42 0x64 0xe0 +0xa5 0x42 0x64 0x10 +0xc5 0x42 0x64 0xe0 +0xe5 0x42 0x64 0xe0 +0x17 0x69 0x66 0xc0 +0x37 0x69 0x66 0xe0 +0x57 0x69 0x66 0xe0 +0x77 0x69 0x66 0xe0 +0x65 0x40 0x64 0xe0 + +#------------------------------------------------------------------------------ +# RSC +#------------------------------------------------------------------------------ +# CHECK: rsc r4, r5, #61440 +# CHECK: rsc r4, r5, r6 +# CHECK: rsc r4, r5, r6, lsl #5 +# CHECK: rsclo r4, r5, r6, lsr #5 +# CHECK: rsc r4, r5, r6, lsr #5 +# CHECK: rsc r4, r5, r6, asr #5 +# CHECK: rsc r4, r5, r6, ror #5 +# CHECK: rsc r6, r7, r8, lsl r9 +# CHECK: rsc r6, r7, r8, lsr r9 +# CHECK: rsc r6, r7, r8, asr r9 +# CHECK: rscle r6, r7, r8, ror r9 + +# CHECK: rsc r5, r5, #61440 +# CHECK: rsc r4, r4, r5 +# CHECK: rsc r4, r4, r5, lsl #5 +# CHECK: rsc r4, r4, r5, lsr #5 +# CHECK: rscne r4, r4, r5, lsr #5 +# CHECK: rsc r4, r4, r5, asr #5 +# CHECK: rsc r4, r4, r5, ror #5 +# CHECK: rscgt r6, r6, r7, lsl r9 +# CHECK: rsc r6, r6, r7, lsr r9 +# CHECK: rsc r6, r6, r7, asr r9 +# CHECK: rsc r6, r6, r7, ror r9 + +0x0f 0x4a 0xe5 0xe2 +0x06 0x40 0xe5 0xe0 +0x86 0x42 0xe5 0xe0 +0xa6 0x42 0xe5 0x30 +0xa6 0x42 0xe5 0xe0 +0xc6 0x42 0xe5 0xe0 +0xe6 0x42 0xe5 0xe0 +0x18 0x69 0xe7 0xe0 +0x38 0x69 0xe7 0xe0 +0x58 0x69 0xe7 0xe0 +0x78 0x69 0xe7 0xd0 + +0x0f 0x5a 0xe5 0xe2 +0x05 0x40 0xe4 0xe0 +0x85 0x42 0xe4 0xe0 +0xa5 0x42 0xe4 0xe0 +0xa5 0x42 0xe4 0x10 +0xc5 0x42 0xe4 0xe0 +0xe5 0x42 0xe4 0xe0 +0x17 0x69 0xe6 0xc0 +0x37 0x69 0xe6 0xe0 +0x57 0x69 0xe6 0xe0 +0x77 0x69 0xe6 0xe0 + +#------------------------------------------------------------------------------ +# SADD16/SADD8 +#------------------------------------------------------------------------------ +# CHECK: sadd16 r1, r2, r3 +# CHECK: sadd16gt r1, r2, r3 +# CHECK: sadd8 r1, r2, r3 +# CHECK: sadd8le r1, r2, r3 + +0x13 0x1f 0x12 0xe6 +0x13 0x1f 0x12 0xc6 +0x93 0x1f 0x12 0xe6 +0x93 0x1f 0x12 0xd6 + + +#------------------------------------------------------------------------------ +# SASX +#------------------------------------------------------------------------------ +# CHECK: sasx r9, r12, r0 +# CHECK: sasxeq r9, r12, r0 + +0x30 0x9f 0x1c 0xe6 +0x30 0x9f 0x1c 0x06 + + +#------------------------------------------------------------------------------ +# SBC +#------------------------------------------------------------------------------ +# CHECK: sbc r4, r5, #61440 +# CHECK: sbc r4, r5, r6 +# CHECK: sbc r4, r5, r6, lsl #5 +# CHECK: sbc r4, r5, r6, lsr #5 +# CHECK: sbc r4, r5, r6, lsr #5 +# CHECK: sbc r4, r5, r6, asr #5 +# CHECK: sbc r4, r5, r6, ror #5 +# CHECK: sbc r6, r7, r8, lsl r9 +# CHECK: sbc r6, r7, r8, lsr r9 +# CHECK: sbc r6, r7, r8, asr r9 +# CHECK: sbc r6, r7, r8, ror r9 + +# CHECK: sbc r5, r5, #61440 +# CHECK: sbc r4, r4, r5 +# CHECK: sbc r4, r4, r5, lsl #5 +# CHECK: sbc r4, r4, r5, lsr #5 +# CHECK: sbc r4, r4, r5, lsr #5 +# CHECK: sbc r4, r4, r5, asr #5 +# CHECK: sbc r4, r4, r5, ror #5 +# CHECK: sbc r6, r6, r7, lsl r9 +# CHECK: sbc r6, r6, r7, lsr r9 +# CHECK: sbc r6, r6, r7, asr r9 +# CHECK: sbc r6, r6, r7, ror r9 + +0x0f 0x4a 0xc5 0xe2 +0x06 0x40 0xc5 0xe0 +0x86 0x42 0xc5 0xe0 +0xa6 0x42 0xc5 0xe0 +0xa6 0x42 0xc5 0xe0 +0xc6 0x42 0xc5 0xe0 +0xe6 0x42 0xc5 0xe0 +0x18 0x69 0xc7 0xe0 +0x38 0x69 0xc7 0xe0 +0x58 0x69 0xc7 0xe0 +0x78 0x69 0xc7 0xe0 + +0x0f 0x5a 0xc5 0xe2 +0x05 0x40 0xc4 0xe0 +0x85 0x42 0xc4 0xe0 +0xa5 0x42 0xc4 0xe0 +0xa5 0x42 0xc4 0xe0 +0xc5 0x42 0xc4 0xe0 +0xe5 0x42 0xc4 0xe0 +0x17 0x69 0xc6 0xe0 +0x37 0x69 0xc6 0xe0 +0x57 0x69 0xc6 0xe0 +0x77 0x69 0xc6 0xe0 + + +#------------------------------------------------------------------------------ +# SBFX +#------------------------------------------------------------------------------ +# CHECK: sbfx r4, r5, #16, #1 +# CHECK: sbfxgt r4, r5, #16, #16 + +0x55 0x48 0xa0 0xe7 +0x55 0x48 0xaf 0xc7 + + +#------------------------------------------------------------------------------ +# SEL +#------------------------------------------------------------------------------ +# CHECK: sel r9, r2, r1 +# CHECK: selne r9, r2, r1 + +0xb1 0x9f 0x82 0xe6 +0xb1 0x9f 0x82 0x16 + + +#------------------------------------------------------------------------------ +# SETEND +#------------------------------------------------------------------------------ +# CHECK: setend be +# CHECK: setend le + +0x00 0x02 0x01 0xf1 +0x00 0x00 0x01 0xf1 + +#------------------------------------------------------------------------------ +# SEV +#------------------------------------------------------------------------------ +# CHECK: sev +# CHECK: seveq + +0x04 0xf0 0x20 0xe3 +0x04 0xf0 0x20 0x03 + +#------------------------------------------------------------------------------ +# SHADD16/SHADD8 +#------------------------------------------------------------------------------ +# CHECK: shadd16 r4, r8, r2 +# CHECK: shadd16gt r4, r8, r2 +# CHECK: shadd8 r4, r8, r2 +# CHECK: shadd8gt r4, r8, r2 + +0x12 0x4f 0x38 0xe6 +0x12 0x4f 0x38 0xc6 +0x92 0x4f 0x38 0xe6 +0x92 0x4f 0x38 0xc6 + + +#------------------------------------------------------------------------------ +# SHASX +#------------------------------------------------------------------------------ +# CHECK: shasx r4, r8, r2 +# CHECK: shasxgt r4, r8, r2 + +0x32 0x4f 0x38 0xe6 +0x32 0x4f 0x38 0xc6 + + +#------------------------------------------------------------------------------ +# SHSUB16/SHSUB8 +#------------------------------------------------------------------------------ +# CHECK: shsub16 r4, r8, r2 +# CHECK: shsub16gt r4, r8, r2 +# CHECK: shsub8 r4, r8, r2 +# CHECK: shsub8gt r4, r8, r2 + +0x72 0x4f 0x38 0xe6 +0x72 0x4f 0x38 0xc6 +0xf2 0x4f 0x38 0xe6 +0xf2 0x4f 0x38 0xc6 + +#------------------------------------------------------------------------------ +# SMC +#------------------------------------------------------------------------------ +# CHECK: smc #15 +# CHECK: smceq #0 + +0x7f 0x00 0x60 0xe1 +0x70 0x00 0x60 0x01 + +#------------------------------------------------------------------------------ +# SMLABB/SMLABT/SMLATB/SMLATT +#------------------------------------------------------------------------------ +# CHECK: smlabb r3, r1, r9, r0 +# CHECK: smlabt r5, r6, r4, r1 +# CHECK: smlatb r4, r2, r3, r2 +# CHECK: smlatt r8, r3, r8, r4 +# CHECK: smlabbge r3, r1, r9, r0 +# CHECK: smlabtle r5, r6, r4, r1 +# CHECK: smlatbne r4, r2, r3, r2 +# CHECK: smlatteq r8, r3, r8, r4 + +0x81 0x09 0x03 0xe1 +0xc6 0x14 0x05 0xe1 +0xa2 0x23 0x04 0xe1 +0xe3 0x48 0x08 0xe1 +0x81 0x09 0x03 0xa1 +0xc6 0x14 0x05 0xd1 +0xa2 0x23 0x04 0x11 +0xe3 0x48 0x08 0x01 + +#------------------------------------------------------------------------------ +# SMLAD/SMLADX +#------------------------------------------------------------------------------ +# CHECK: smlad r2, r3, r5, r8 +# CHECK: smladx r2, r3, r5, r8 +# CHECK: smladeq r2, r3, r5, r8 +# CHECK: smladxhi r2, r3, r5, r8 + +0x13 0x85 0x02 0xe7 +0x33 0x85 0x02 0xe7 +0x13 0x85 0x02 0x07 +0x33 0x85 0x02 0x87 + + +#------------------------------------------------------------------------------ +# SMLAL +#------------------------------------------------------------------------------ +# CHECK: smlal r2, r3, r5, r8 +# CHECK: smlals r2, r3, r5, r8 +# CHECK: smlaleq r2, r3, r5, r8 +# CHECK: smlalshi r2, r3, r5, r8 + +0x95 0x28 0xe3 0xe0 +0x95 0x28 0xf3 0xe0 +0x95 0x28 0xe3 0x00 +0x95 0x28 0xf3 0x80 + + +#------------------------------------------------------------------------------ +# SMLALBB/SMLALBT/SMLALTB/SMLALTT +#------------------------------------------------------------------------------ +# CHECK: smlalbb r3, r1, r9, r0 +# CHECK: smlalbt r5, r6, r4, r1 +# CHECK: smlaltb r4, r2, r3, r2 +# CHECK: smlaltt r8, r3, r8, r4 +# CHECK: smlalbbge r3, r1, r9, r0 +# CHECK: smlalbtle r5, r6, r4, r1 +# CHECK: smlaltbne r4, r2, r3, r2 +# CHECK: smlaltteq r8, r3, r8, r4 + +0x89 0x30 0x41 0xe1 +0xc4 0x51 0x46 0xe1 +0xa3 0x42 0x42 0xe1 +0xe8 0x84 0x43 0xe1 +0x89 0x30 0x41 0xa1 +0xc4 0x51 0x46 0xd1 +0xa3 0x42 0x42 0x11 +0xe8 0x84 0x43 0x01 + + +#------------------------------------------------------------------------------ +# SMLALD/SMLALDX +#------------------------------------------------------------------------------ +# CHECK: smlald r2, r3, r5, r8 +# CHECK: smlaldx r2, r3, r5, r8 +# CHECK: smlaldeq r2, r3, r5, r8 +# CHECK: smlaldxhi r2, r3, r5, r8 + +0x15 0x28 0x43 0xe7 +0x35 0x28 0x43 0xe7 +0x15 0x28 0x43 0x07 +0x35 0x28 0x43 0x87 + + +#------------------------------------------------------------------------------ +# SMLAWB/SMLAWT +#------------------------------------------------------------------------------ +# CHECK: smlawb r2, r3, r10, r8 +# CHECK: smlawt r8, r3, r5, r9 +# CHECK: smlawbeq r2, r7, r5, r8 +# CHECK: smlawthi r1, r3, r0, r8 + +0x83 0x8a 0x22 0xe1 +0xc3 0x95 0x28 0xe1 +0x87 0x85 0x22 0x01 +0xc3 0x80 0x21 0x81 + + +#------------------------------------------------------------------------------ +# SMLSD/SMLSDX +#------------------------------------------------------------------------------ +# CHECK: smlsd r2, r3, r5, r8 +# CHECK: smlsdx r2, r3, r5, r8 +# CHECK: smlsdeq r2, r3, r5, r8 +# CHECK: smlsdxhi r2, r3, r5, r8 + +0x53 0x85 0x02 0xe7 +0x73 0x85 0x02 0xe7 +0x53 0x85 0x02 0x07 +0x73 0x85 0x02 0x87 + + +#------------------------------------------------------------------------------ +# SMLSLD/SMLSLDX +#------------------------------------------------------------------------------ +# CHECK: smlsld r2, r9, r5, r1 +# CHECK: smlsldx r4, r11, r2, r8 +# CHECK: smlsldeq r8, r2, r5, r6 +# CHECK: smlsldxhi r1, r0, r3, r8 + +0x55 0x21 0x49 0xe7 +0x72 0x48 0x4b 0xe7 +0x55 0x86 0x42 0x07 +0x73 0x18 0x40 0x87 + + +#------------------------------------------------------------------------------ +# SMMLA/SMMLAR +#------------------------------------------------------------------------------ +# CHECK: smmla r1, r2, r3, r4 +# CHECK: smmlar r4, r3, r2, r1 +# CHECK: smmlalo r1, r2, r3, r4 +# CHECK: smmlarhs r4, r3, r2, r1 + +0x12 0x43 0x51 0xe7 +0x33 0x12 0x54 0xe7 +0x12 0x43 0x51 0x37 +0x33 0x12 0x54 0x27 + + +#------------------------------------------------------------------------------ +# SMMLS/SMMLSR +#------------------------------------------------------------------------------ +# CHECK: smmls r1, r2, r3, r4 +# CHECK: smmlsr r4, r3, r2, r1 +# CHECK: smmlslo r1, r2, r3, r4 +# CHECK: smmlsrhs r4, r3, r2, r1 + +0xd2 0x43 0x51 0xe7 +0xf3 0x12 0x54 0xe7 +0xd2 0x43 0x51 0x37 +0xf3 0x12 0x54 0x27 + + +#------------------------------------------------------------------------------ +# SMMUL/SMMULR +#------------------------------------------------------------------------------ +# CHECK: smmul r2, r3, r4 +# CHECK: smmulr r3, r2, r1 +# CHECK: smmullo r2, r3, r4 +# CHECK: smmulrhs r3, r2, r1 + +0x13 0xf4 0x52 0xe7 +0x32 0xf1 0x53 0xe7 +0x13 0xf4 0x52 0x37 +0x32 0xf1 0x53 0x27 + + +#------------------------------------------------------------------------------ +# SMUAD/SMUADX +#------------------------------------------------------------------------------ +# CHECK: smuad r2, r3, r4 +# CHECK: smuadx r3, r2, r1 +# CHECK: smuadlt r2, r3, r4 +# CHECK: smuadxge r3, r2, r1 + +0x13 0xf4 0x02 0xe7 +0x32 0xf1 0x03 0xe7 +0x13 0xf4 0x02 0xb7 +0x32 0xf1 0x03 0xa7 + + +#------------------------------------------------------------------------------ +# SMULBB/SMLALBT/SMLALTB/SMLALTT +#------------------------------------------------------------------------------ +# CHECK: smulbb r3, r9, r0 +# CHECK: smulbt r5, r4, r1 +# CHECK: smultb r4, r2, r2 +# CHECK: smultt r8, r3, r4 +# CHECK: smulbbge r1, r9, r0 +# CHECK: smulbtle r5, r6, r4 +# CHECK: smultbne r2, r3, r2 +# CHECK: smultteq r8, r3, r4 + +0x89 0x00 0x63 0xe1 +0xc4 0x01 0x65 0xe1 +0xa2 0x02 0x64 0xe1 +0xe3 0x04 0x68 0xe1 +0x89 0x00 0x61 0xa1 +0xc6 0x04 0x65 0xd1 +0xa3 0x02 0x62 0x11 +0xe3 0x04 0x68 0x01 + + +#------------------------------------------------------------------------------ +# SMULL +#------------------------------------------------------------------------------ +# CHECK: smull r3, r9, r0, r1 +# CHECK: smulls r3, r9, r0, r2 +# CHECK: smulleq r8, r3, r4, r5 +# CHECK: smullseq r8, r3, r4, r3 + +0x90 0x31 0xc9 0xe0 +0x90 0x32 0xd9 0xe0 +0x94 0x85 0xc3 0x00 +0x94 0x83 0xd3 0x00 + + +#------------------------------------------------------------------------------ +# SMULWB/SMULWT +#------------------------------------------------------------------------------ +# CHECK: smulwb r3, r9, r0 +# CHECK: smulwt r3, r9, r2 + +0xa9 0x00 0x23 0xe1 +0xe9 0x02 0x23 0xe1 + + +#------------------------------------------------------------------------------ +# SMUSD/SMUSDX +#------------------------------------------------------------------------------ +# CHECK: smusd r3, r0, r1 +# CHECK: smusdx r3, r9, r2 +# CHECK: smusdeq r8, r3, r2 +# CHECK: smusdxne r7, r4, r3 + +0x50 0xf1 0x03 0xe7 +0x79 0xf2 0x03 0xe7 +0x53 0xf2 0x08 0x07 +0x74 0xf3 0x07 0x17 + + +#------------------------------------------------------------------------------ +# SRS +#------------------------------------------------------------------------------ +# CHECK: srsda sp, #5 +# CHECK: srsdb sp, #1 +# CHECK: srsia sp, #0 +# CHECK: srsib sp, #15 + +# CHECK: srsda sp!, #31 +# CHECK: srsdb sp!, #19 +# CHECK: srsia sp!, #2 +# CHECK: srsib sp!, #14 + +# CHECK: srsda sp, #11 +# CHECK: srsdb sp, #10 +# CHECK: srsia sp, #9 +# CHECK: srsib sp, #5 + +# CHECK: srsda sp!, #5 +# CHECK: srsdb sp!, #5 +# CHECK: srsia sp!, #5 +# CHECK: srsib sp!, #5 + +# CHECK: srsia sp, #5 +# CHECK: srsia sp!, #5 + +0x05 0x05 0x4d 0xf8 +0x01 0x05 0x4d 0xf9 +0x00 0x05 0xcd 0xf8 +0x0f 0x05 0xcd 0xf9 + +0x1f 0x05 0x6d 0xf8 +0x13 0x05 0x6d 0xf9 +0x02 0x05 0xed 0xf8 +0x0e 0x05 0xed 0xf9 + +0x0b 0x05 0x4d 0xf8 +0x0a 0x05 0x4d 0xf9 +0x09 0x05 0xcd 0xf8 +0x05 0x05 0xcd 0xf9 + +0x05 0x05 0x6d 0xf8 +0x05 0x05 0x6d 0xf9 +0x05 0x05 0xed 0xf8 +0x05 0x05 0xed 0xf9 + +0x05 0x05 0xcd 0xf8 +0x05 0x05 0xed 0xf8 + + +#------------------------------------------------------------------------------ +# SSAT +#------------------------------------------------------------------------------ +# CHECK: ssat r8, #1, r10 +# CHECK: ssat r8, #1, r10, lsl #31 +# CHECK: ssat r8, #1, r10, asr #32 +# CHECK: ssat r8, #1, r10, asr #1 + +0x1a 0x80 0xa0 0xe6 +0x9a 0x8f 0xa0 0xe6 +0x5a 0x80 0xa0 0xe6 +0xda 0x80 0xa0 0xe6 + + +#------------------------------------------------------------------------------ +# SSAT16 +#------------------------------------------------------------------------------ +# CHECK: ssat16 r2, #1, r7 +# CHECK: ssat16 r3, #16, r5 + +0x37 0x2f 0xa0 0xe6 +0x35 0x3f 0xaf 0xe6 + + +#------------------------------------------------------------------------------ +# SSAX +#------------------------------------------------------------------------------ +# CHECK: ssax r2, r3, r4 +# CHECK: ssaxlt r2, r3, r4 + +0x54 0x2f 0x13 0xe6 +0x54 0x2f 0x13 0xb6 + +#------------------------------------------------------------------------------ +# SSUB16/SSUB8 +#------------------------------------------------------------------------------ +# CHECK: ssub16 r1, r0, r6 +# CHECK: ssub16ne r5, r3, r2 +# CHECK: ssub8 r9, r2, r4 +# CHECK: ssub8eq r5, r1, r2 + +0x76 0x1f 0x10 0xe6 +0x72 0x5f 0x13 0x16 +0xf4 0x9f 0x12 0xe6 +0xf2 0x5f 0x11 0x06 + + +#------------------------------------------------------------------------------ +# STM* +#------------------------------------------------------------------------------ +# CHECK: stm r2, {r1, r3, r4, r5, r6, sp} +# CHECK: stm r3, {r1, r3, r4, r5, r6, lr} +# CHECK: stmib r4, {r1, r3, r4, r5, r6, sp} +# CHECK: stmda r5, {r1, r3, r4, r5, r6, sp} +# CHECK: stmdb r6, {r1, r3, r4, r5, r6, r8} +# CHECK: stmdb sp, {r1, r3, r4, r5, r6, sp} + + +# CHECK: stm r8!, {r1, r3, r4, r5, r6, sp} +# CHECK: stmib r9!, {r1, r3, r4, r5, r6, sp} +# CHECK: stmda sp!, {r1, r3, r4, r5, r6} +# CHECK: stmdb r0!, {r1, r5, r7, sp} + +0x7a 0x20 0x82 0xe8 +0x7a 0x40 0x83 0xe8 +0x7a 0x20 0x84 0xe9 +0x7a 0x20 0x05 0xe8 +0x7a 0x01 0x06 0xe9 +0x7a 0x20 0x0d 0xe9 + +0x7a 0x20 0xa8 0xe8 +0x7a 0x20 0xa9 0xe9 +0x7a 0x00 0x2d 0xe8 +0xa2 0x20 0x20 0xe9 + + +#------------------------------------------------------------------------------ +# STREX/STREXB/STREXH/STREXD +#------------------------------------------------------------------------------ +# CHECK: strexb r1, r3, [r4 +# CHECK: strexh r4, r2, [r5 +# CHECK: strex r2, r1, [r7 +# CHECK: strexd r6, r2, r3, [r8 + +0x93 0x1f 0xc4 0xe1 +0x92 0x4f 0xe5 0xe1 +0x91 0x2f 0x87 0xe1 +0x92 0x6f 0xa8 0xe1 + + +#------------------------------------------------------------------------------ +# SUB +#------------------------------------------------------------------------------ +# CHECK: sub r4, r5, #61440 +# CHECK: sub r4, r5, r6 +# CHECK: sub r4, r5, r6, lsl #5 +# CHECK: sub r4, r5, r6, lsr #5 +# CHECK: sub r4, r5, r6, lsr #5 +# CHECK: sub r4, r5, r6, asr #5 +# CHECK: sub r4, r5, r6, ror #5 +# CHECK: sub r6, r7, r8, lsl r9 +# CHECK: sub r6, r7, r8, lsr r9 +# CHECK: sub r6, r7, r8, asr r9 +# CHECK: sub r6, r7, r8, ror r9 + +# CHECK: sub r5, r5, #61440 +# CHECK: sub r4, r4, r5 +# CHECK: sub r4, r4, r5, lsl #5 +# CHECK: sub r4, r4, r5, lsr #5 +# CHECK: sub r4, r4, r5, lsr #5 +# CHECK: sub r4, r4, r5, asr #5 +# CHECK: sub r4, r4, r5, ror #5 +# CHECK: sub r6, r6, r7, lsl r9 +# CHECK: sub r6, r6, r7, lsr r9 +# CHECK: sub r6, r6, r7, asr r9 +# CHECK: sub r6, r6, r7, ror r9 + +0x0f 0x4a 0x45 0xe2 +0x06 0x40 0x45 0xe0 +0x86 0x42 0x45 0xe0 +0xa6 0x42 0x45 0xe0 +0xa6 0x42 0x45 0xe0 +0xc6 0x42 0x45 0xe0 +0xe6 0x42 0x45 0xe0 +0x18 0x69 0x47 0xe0 +0x38 0x69 0x47 0xe0 +0x58 0x69 0x47 0xe0 +0x78 0x69 0x47 0xe0 + + +0x0f 0x5a 0x45 0xe2 +0x05 0x40 0x44 0xe0 +0x85 0x42 0x44 0xe0 +0xa5 0x42 0x44 0xe0 +0xa5 0x42 0x44 0xe0 +0xc5 0x42 0x44 0xe0 +0xe5 0x42 0x44 0xe0 +0x17 0x69 0x46 0xe0 +0x37 0x69 0x46 0xe0 +0x57 0x69 0x46 0xe0 +0x77 0x69 0x46 0xe0 + + +#------------------------------------------------------------------------------ +# SVC +#------------------------------------------------------------------------------ +# CHECK: svc #16 +# CHECK: svc #0 +# CHECK: svc #16777215 + +0x10 0x00 0x00 0xef +0x00 0x00 0x00 0xef +0xff 0xff 0xff 0xef + + +#------------------------------------------------------------------------------ +# SWP/SWPB +#------------------------------------------------------------------------------ +# CHECK: swp r1, r2, [r3 +# CHECK: swp r4, r4, [r6 +# CHECK: swpb r5, r1, [r9 + +0x92 0x10 0x03 0xe1 +0x94 0x40 0x06 0xe1 +0x91 0x50 0x49 0xe1 + + +#------------------------------------------------------------------------------ +# SXTAB +#------------------------------------------------------------------------------ +# CHECK: sxtab r2, r3, r4 +# CHECK: sxtab r4, r5, r6 +# CHECK: sxtablt r6, r2, r9, ror #8 +# CHECK: sxtab r5, r1, r4, ror #16 +# CHECK: sxtab r7, r8, r3, ror #24 + +0x74 0x20 0xa3 0xe6 +0x76 0x40 0xa5 0xe6 +0x79 0x64 0xa2 0xb6 +0x74 0x58 0xa1 0xe6 +0x73 0x7c 0xa8 0xe6 + + +#------------------------------------------------------------------------------ +# SXTAB16 +#------------------------------------------------------------------------------ +# CHECK: sxtab16ge r0, r1, r4 +# CHECK: sxtab16 r6, r2, r7 +# CHECK: sxtab16 r3, r5, r8, ror #8 +# CHECK: sxtab16 r3, r2, r1, ror #16 +# CHECK: sxtab16eq r1, r2, r3, ror #24 + +0x74 0x00 0x81 0xa6 +0x77 0x60 0x82 0xe6 +0x78 0x34 0x85 0xe6 +0x71 0x38 0x82 0xe6 +0x73 0x1c 0x82 0x06 + +#------------------------------------------------------------------------------ +# SXTAH +#------------------------------------------------------------------------------ +# CHECK: sxtah r1, r3, r9 +# CHECK: sxtahhi r6, r1, r6 +# CHECK: sxtah r3, r8, r3, ror #8 +# CHECK: sxtahlo r2, r2, r4, ror #16 +# CHECK: sxtah r9, r3, r3, ror #24 + +0x79 0x10 0xb3 0xe6 +0x76 0x60 0xb1 0x86 +0x73 0x34 0xb8 0xe6 +0x74 0x28 0xb2 0x36 +0x73 0x9c 0xb3 0xe6 + +#------------------------------------------------------------------------------ +# SXTB +#------------------------------------------------------------------------------ +# CHECK: sxtbge r2, r4 +# CHECK: sxtb r5, r6 +# CHECK: sxtb r6, r9, ror #8 +# CHECK: sxtblo r5, r1, ror #16 +# CHECK: sxtb r8, r3, ror #24 + +0x74 0x20 0xaf 0xa6 +0x76 0x50 0xaf 0xe6 +0x79 0x64 0xaf 0xe6 +0x71 0x58 0xaf 0x36 +0x73 0x8c 0xaf 0xe6 + + +#------------------------------------------------------------------------------ +# SXTB16 +#------------------------------------------------------------------------------ +# CHECK: sxtb16 r1, r4 +# CHECK: sxtb16 r6, r7 +# CHECK: sxtb16hs r3, r5, ror #8 +# CHECK: sxtb16 r3, r1, ror #16 +# CHECK: sxtb16ge r2, r3, ror #24 + +0x74 0x10 0x8f 0xe6 +0x77 0x60 0x8f 0xe6 +0x75 0x34 0x8f 0x26 +0x71 0x38 0x8f 0xe6 +0x73 0x2c 0x8f 0xa6 + + +#------------------------------------------------------------------------------ +# SXTH +#------------------------------------------------------------------------------ +# CHECK: sxthne r3, r9 +# CHECK: sxth r1, r6 +# CHECK: sxth r3, r8, ror #8 +# CHECK: sxthle r2, r2, ror #16 +# CHECK: sxth r9, r3, ror #24 + +0x79 0x30 0xbf 0x16 +0x76 0x10 0xbf 0xe6 +0x78 0x34 0xbf 0xe6 +0x72 0x28 0xbf 0xd6 +0x73 0x9c 0xbf 0xe6 + + +#------------------------------------------------------------------------------ +# FIXME: TBB/TBH +#------------------------------------------------------------------------------ + + +#------------------------------------------------------------------------------ +# TEQ +#------------------------------------------------------------------------------ +# CHECK: teq r5, #61440 +# CHECK: teq r4, r5 +# CHECK: teq r4, r5, lsl #5 +# CHECK: teq r4, r5, lsr #5 +# CHECK: teq r4, r5, lsr #5 +# CHECK: teq r4, r5, asr #5 +# CHECK: teq r4, r5, ror #5 +# CHECK: teq r6, r7, lsl r9 +# CHECK: teq r6, r7, lsr r9 +# CHECK: teq r6, r7, asr r9 +# CHECK: teq r6, r7, ror r9 + +0x0f 0x0a 0x35 0xe3 +0x05 0x00 0x34 0xe1 +0x85 0x02 0x34 0xe1 +0xa5 0x02 0x34 0xe1 +0xa5 0x02 0x34 0xe1 +0xc5 0x02 0x34 0xe1 +0xe5 0x02 0x34 0xe1 +0x17 0x09 0x36 0xe1 +0x37 0x09 0x36 0xe1 +0x57 0x09 0x36 0xe1 +0x77 0x09 0x36 0xe1 + + +#------------------------------------------------------------------------------ +# TST +#------------------------------------------------------------------------------ +# CHECK: tst r5, #61440 +# CHECK: tst r4, r5 +# CHECK: tst r4, r5, lsl #5 +# CHECK: tst r4, r5, lsr #5 +# CHECK: tst r4, r5, lsr #5 +# CHECK: tst r4, r5, asr #5 +# CHECK: tst r4, r5, ror #5 +# CHECK: tst r6, r7, lsl r9 +# CHECK: tst r6, r7, lsr r9 +# CHECK: tst r6, r7, asr r9 +# CHECK: tst r6, r7, ror r9 + +0x0f 0x0a 0x15 0xe3 +0x05 0x00 0x14 0xe1 +0x85 0x02 0x14 0xe1 +0xa5 0x02 0x14 0xe1 +0xa5 0x02 0x14 0xe1 +0xc5 0x02 0x14 0xe1 +0xe5 0x02 0x14 0xe1 +0x17 0x09 0x16 0xe1 +0x37 0x09 0x16 0xe1 +0x57 0x09 0x16 0xe1 +0x77 0x09 0x16 0xe1 + + +#------------------------------------------------------------------------------ +# UADD16/UADD8 +#------------------------------------------------------------------------------ +# CHECK: uadd16 r1, r2, r3 +# CHECK: uadd16gt r1, r2, r3 +# CHECK: uadd8 r1, r2, r3 +# CHECK: uadd8le r1, r2, r3 + +0x13 0x1f 0x52 0xe6 +0x13 0x1f 0x52 0xc6 +0x93 0x1f 0x52 0xe6 +0x93 0x1f 0x52 0xd6 + + +#------------------------------------------------------------------------------ +# UASX +#------------------------------------------------------------------------------ +# CHECK: uasx r9, r12, r0 +# CHECK: uasxeq r9, r12, r0 + +0x30 0x9f 0x5c 0xe6 +0x30 0x9f 0x5c 0x06 + + +#------------------------------------------------------------------------------ +# UBFX +#------------------------------------------------------------------------------ +# CHECK: ubfx r4, r5, #16, #1 +# CHECK: ubfxgt r4, r5, #16, #16 + +0x55 0x48 0xe0 0xe7 +0x55 0x48 0xef 0xc7 + + +#------------------------------------------------------------------------------ +# UHADD16/UHADD8 +#------------------------------------------------------------------------------ +# CHECK: uhadd16 r4, r8, r2 +# CHECK: uhadd16gt r4, r8, r2 +# CHECK: uhadd8 r4, r8, r2 +# CHECK: uhadd8gt r4, r8, r2 + +0x12 0x4f 0x78 0xe6 +0x12 0x4f 0x78 0xc6 +0x92 0x4f 0x78 0xe6 +0x92 0x4f 0x78 0xc6 + + +#------------------------------------------------------------------------------ +# UHASX +#------------------------------------------------------------------------------ +# CHECK: uhasx r4, r8, r2 +# CHECK: uhasxgt r4, r8, r2 + +0x32 0x4f 0x78 0xe6 +0x32 0x4f 0x78 0xc6 + + +#------------------------------------------------------------------------------ +# UHSUB16/UHSUB8 +#------------------------------------------------------------------------------ +# CHECK: uhsub16 r4, r8, r2 +# CHECK: uhsub16gt r4, r8, r2 +# CHECK: uhsub8 r4, r8, r2 +# CHECK: uhsub8gt r4, r8, r2 + +0x72 0x4f 0x78 0xe6 +0x72 0x4f 0x78 0xc6 +0xf2 0x4f 0x78 0xe6 +0xf2 0x4f 0x78 0xc6 + + +#------------------------------------------------------------------------------ +# UMAAL +#------------------------------------------------------------------------------ +# CHECK: umaal r3, r4, r5, r6 +# CHECK: umaallt r3, r4, r5, r6 + +0x95 0x36 0x44 0xe0 +0x95 0x36 0x44 0xb0 + + +#------------------------------------------------------------------------------ +# UMLAL +#------------------------------------------------------------------------------ +# CHECK: umlal r2, r4, r6, r8 +# CHECK: umlalgt r6, r1, r2, r6 +# CHECK: umlals r2, r9, r2, r3 +# CHECK: umlalseq r3, r5, r1, r2 + +0x96 0x28 0xa4 0xe0 +0x92 0x66 0xa1 0xc0 +0x92 0x23 0xb9 0xe0 +0x91 0x32 0xb5 0x00 + + +#------------------------------------------------------------------------------ +# UMULL +#------------------------------------------------------------------------------ +# CHECK: umull r2, r4, r6, r8 +# CHECK: umullgt r6, r1, r2, r6 +# CHECK: umulls r2, r9, r2, r3 +# CHECK: umullseq r3, r5, r1, r2 + +0x96 0x28 0x84 0xe0 +0x92 0x66 0x81 0xc0 +0x92 0x23 0x99 0xe0 +0x91 0x32 0x95 0x00 + + +#------------------------------------------------------------------------------ +# UQADD16/UQADD8 +#------------------------------------------------------------------------------ +# CHECK: uqadd16 r1, r2, r3 +# CHECK: uqadd16gt r4, r7, r9 +# CHECK: uqadd8 r3, r4, r8 +# CHECK: uqadd8le r8, r1, r2 + + +0x13 0x1f 0x62 0xe6 +0x19 0x4f 0x67 0xc6 +0x98 0x3f 0x64 0xe6 +0x92 0x8f 0x61 0xd6 + + +#------------------------------------------------------------------------------ +# UQASX +#------------------------------------------------------------------------------ +# CHECK: uqasx r2, r4, r1 +# CHECK: uqasxhi r5, r2, r9 + +0x31 0x2f 0x64 0xe6 +0x39 0x5f 0x62 0x86 + + +#------------------------------------------------------------------------------ +# UQSAX +#------------------------------------------------------------------------------ +# CHECK: uqsax r1, r3, r7 +# CHECK: uqsax r3, r6, r2 + +0x57 0x1f 0x63 0xe6 +0x52 0x3f 0x66 0xe6 + + +#------------------------------------------------------------------------------ +# UQSUB16/UQSUB8 +#------------------------------------------------------------------------------ +# CHECK: uqsub16 r1, r5, r3 +# CHECK: uqsub16gt r3, r2, r5 +# CHECK: uqsub8 r2, r1, r4 +# CHECK: uqsub8le r4, r6, r9 + +0x73 0x1f 0x65 0xe6 +0x75 0x3f 0x62 0xc6 +0xf4 0x2f 0x61 0xe6 +0xf9 0x4f 0x66 0xd6 + + +#------------------------------------------------------------------------------ +# USADA8/USAD8 +#------------------------------------------------------------------------------ +# CHECK: usad8 r2, r1, r4 +# CHECK: usad8le r4, r6, r9 +# CHECK: usada8 r1, r5, r3, r7 +# CHECK: usada8gt r3, r2, r5, r1 + +0x11 0xf4 0x82 0xe7 +0x16 0xf9 0x84 0xd7 +0x15 0x73 0x81 0xe7 +0x12 0x15 0x83 0xc7 + + +#------------------------------------------------------------------------------ +# USAT +#------------------------------------------------------------------------------ + +# CHECK: usat r8, #1, r10 +# CHECK: usat r8, #4, r10 +# CHECK: usat r8, #5, r10, lsl #31 +# CHECK: usat r8, #31, r10, asr #32 +# CHECK: usat r8, #16, r10, asr #1 + +0x1a 0x80 0xe1 0xe6 +0x1a 0x80 0xe4 0xe6 +0x9a 0x8f 0xe5 0xe6 +0x5a 0x80 0xff 0xe6 +0xda 0x80 0xf0 0xe6 + +#------------------------------------------------------------------------------ +# USAT16 +#------------------------------------------------------------------------------ +# CHECK: usat16 r2, #2, r7 +# CHECK: usat16 r3, #15, r5 + +0x37 0x2f 0xe2 0xe6 +0x35 0x3f 0xef 0xe6 + + +#------------------------------------------------------------------------------ +# USAX +#------------------------------------------------------------------------------ +# CHECK: usax r2, r3, r4 +# CHECK: usaxne r2, r3, r4 + +0x54 0x2f 0x53 0xe6 +0x54 0x2f 0x53 0x16 + +#------------------------------------------------------------------------------ +# USUB16/USUB8 +#------------------------------------------------------------------------------ +# CHECK: usub16 r4, r2, r7 +# CHECK: usub16hi r1, r1, r3 +# CHECK: usub8 r1, r8, r5 +# CHECK: usub8le r9, r2, r3 + +0x77 0x4f 0x52 0xe6 +0x73 0x1f 0x51 0x86 +0xf5 0x1f 0x58 0xe6 +0xf3 0x9f 0x52 0xd6 + + +#------------------------------------------------------------------------------ +# UXTAB +#------------------------------------------------------------------------------ +# CHECK: uxtab r2, r3, r4 +# CHECK: uxtab r4, r5, r6 +# CHECK: uxtablt r6, r2, r9, ror #8 +# CHECK: uxtab r5, r1, r4, ror #16 +# CHECK: uxtab r7, r8, r3, ror #24 + +0x74 0x20 0xe3 0xe6 +0x76 0x40 0xe5 0xe6 +0x79 0x64 0xe2 0xb6 +0x74 0x58 0xe1 0xe6 +0x73 0x7c 0xe8 0xe6 + + +#------------------------------------------------------------------------------ +# UXTAB16 +#------------------------------------------------------------------------------ +# CHECK: uxtab16ge r0, r1, r4 +# CHECK: uxtab16 r6, r2, r7 +# CHECK: uxtab16 r3, r5, r8, ror #8 +# CHECK: uxtab16 r3, r2, r1, ror #16 +# CHECK: uxtab16eq r1, r2, r3, ror #24 + +0x74 0x00 0xc1 0xa6 +0x77 0x60 0xc2 0xe6 +0x78 0x34 0xc5 0xe6 +0x71 0x38 0xc2 0xe6 +0x73 0x1c 0xc2 0x06 + +#------------------------------------------------------------------------------ +# UXTAH +#------------------------------------------------------------------------------ +# CHECK: uxtah r1, r3, r9 +# CHECK: uxtahhi r6, r1, r6 +# CHECK: uxtah r3, r8, r3, ror #8 +# CHECK: uxtahlo r2, r2, r4, ror #16 +# CHECK: uxtah r9, r3, r3, ror #24 + +0x79 0x10 0xf3 0xe6 +0x76 0x60 0xf1 0x86 +0x73 0x34 0xf8 0xe6 +0x74 0x28 0xf2 0x36 +0x73 0x9c 0xf3 0xe6 + +#------------------------------------------------------------------------------ +# UXTB +#------------------------------------------------------------------------------ +# CHECK: uxtbge r2, r4 +# CHECK: uxtb r5, r6 +# CHECK: uxtb r6, r9, ror #8 +# CHECK: uxtblo r5, r1, ror #16 +# CHECK: uxtb r8, r3, ror #24 + +0x74 0x20 0xef 0xa6 +0x76 0x50 0xef 0xe6 +0x79 0x64 0xef 0xe6 +0x71 0x58 0xef 0x36 +0x73 0x8c 0xef 0xe6 + + +#------------------------------------------------------------------------------ +# UXTB16 +#------------------------------------------------------------------------------ +# CHECK: uxtb16 r1, r4 +# CHECK: uxtb16 r6, r7 +# CHECK: uxtb16hs r3, r5, ror #8 +# CHECK: uxtb16 r3, r1, ror #16 +# CHECK: uxtb16ge r2, r3, ror #24 + +0x74 0x10 0xcf 0xe6 +0x77 0x60 0xcf 0xe6 +0x75 0x34 0xcf 0x26 +0x71 0x38 0xcf 0xe6 +0x73 0x2c 0xcf 0xa6 + + +#------------------------------------------------------------------------------ +# UXTH +#------------------------------------------------------------------------------ +# CHECK: uxthne r3, r9 +# CHECK: uxth r1, r6 +# CHECK: uxth r3, r8, ror #8 +# CHECK: uxthle r2, r2, ror #16 +# CHECK: uxth r9, r3, ror #24 + +0x79 0x30 0xff 0x16 +0x76 0x10 0xff 0xe6 +0x78 0x34 0xff 0xe6 +0x72 0x28 0xff 0xd6 +0x73 0x9c 0xff 0xe6 + +#------------------------------------------------------------------------------ +# WFE/WFI/YIELD +#------------------------------------------------------------------------------ +# CHECK: wfe +# CHECK: wfehi +# CHECK: wfi +# CHECK: wfilt +# CHECK: yield +# CHECK: yieldne + +0x02 0xf0 0x20 0xe3 +0x02 0xf0 0x20 0x83 +0x03 0xf0 0x20 0xe3 +0x03 0xf0 0x20 0xb3 +0x01 0xf0 0x20 0xe3 +0x01 0xf0 0x20 0x13 diff --git a/test/MC/Disassembler/ARM/fp-encoding.txt b/test/MC/Disassembler/ARM/fp-encoding.txt new file mode 100644 index 0000000..f3e0261 --- /dev/null +++ b/test/MC/Disassembler/ARM/fp-encoding.txt @@ -0,0 +1,213 @@ +# RUN: llvm-mc -triple armv7-apple-darwin -disassemble < %s | FileCheck %s + +0xa0 0x0b 0x71 0xee +# CHECK: vadd.f64 d16, d17, d16 + +0x80 0x0a 0x30 0xee +# CHECK: vadd.f32 s0, s1, s0 + +0xe0 0x0b 0x71 0xee +# CHECK: vsub.f64 d16, d17, d16 + +0xc0 0x0a 0x30 0xee +# CHECK: vsub.f32 s0, s1, s0 + +0xa0 0x0b 0xc1 0xee +# CHECK: vdiv.f64 d16, d17, d16 + +0x80 0x0a 0x80 0xee +# CHECK: vdiv.f32 s0, s1, s0 + +0xa0 0x0b 0x61 0xee +# CHECK: vmul.f64 d16, d17, d16 + +0x80 0x0a 0x20 0xee +# CHECK: vmul.f32 s0, s1, s0 + +0xe0 0x0b 0x61 0xee +# CHECK: vnmul.f64 d16, d17, d16 + +0xc0 0x0a 0x20 0xee +# CHECK: vnmul.f32 s0, s1, s0 + +0xe0 0x1b 0xf4 0xee +# CHECK: vcmpe.f64 d17, d16 + +0xc0 0x0a 0xf4 0xee +# CHECK: vcmpe.f32 s1, s0 + +0xe0 0x0b 0xf0 0xee +# CHECK: vabs.f64 d16, d16 + +0xc0 0x0a 0xb0 0xee +# CHECK: vabs.f32 s0, s0 + +0xe0 0x0b 0xb7 0xee +# CHECK: vcvt.f32.f64 s0, d16 + +0xc0 0x0a 0xf7 0xee +# CHECK: vcvt.f64.f32 d16, s0 + +0x60 0x0b 0xf1 0xee +# CHECK: vneg.f64 d16, d16 + +0x40 0x0a 0xb1 0xee +# CHECK: vneg.f32 s0, s0 + +0xe0 0x0b 0xf1 0xee +# CHECK: vsqrt.f64 d16, d16 + +0xc0 0x0a 0xb1 0xee +# CHECK: vsqrt.f32 s0, s0 + +0xc0 0x0b 0xf8 0xee +# CHECK: vcvt.f64.s32 d16, s0 + +0xc0 0x0a 0xb8 0xee +# CHECK: vcvt.f32.s32 s0, s0 + +0x40 0x0b 0xf8 0xee +# CHECK: vcvt.f64.u32 d16, s0 + +0x40 0x0a 0xb8 0xee +# CHECK: vcvt.f32.u32 s0, s0 + +0xe0 0x0b 0xbd 0xee +# CHECK: vcvt.s32.f64 s0, d16 + +0xc0 0x0a 0xbd 0xee +# CHECK: vcvt.s32.f32 s0, s0 + +0xe0 0x0b 0xbc 0xee +# CHECK: vcvt.u32.f64 s0, d16 + +0xc0 0x0a 0xbc 0xee +# CHECK: vcvt.u32.f32 s0, s0 + +0xa1 0x0b 0x42 0xee +# CHECK: vmla.f64 d16, d18, d17 + +0x00 0x0a 0x41 0xee +# CHECK: vmla.f32 s1, s2, s0 + +0xe1 0x0b 0x42 0xee +# CHECK: vmls.f64 d16, d18, d17 + +0x40 0x0a 0x41 0xee +# CHECK: vmls.f32 s1, s2, s0 + +0xe1 0x0b 0x52 0xee +# CHECK: vnmla.f64 d16, d18, d17 + +0x40 0x0a 0x51 0xee +# CHECK: vnmla.f32 s1, s2, s0 + +0xa1 0x0b 0x52 0xee +# CHECK: vnmls.f64 d16, d18, d17 + +0x00 0x0a 0x51 0xee +# CHECK: vnmls.f32 s1, s2, s0 + +0x60 0x0b 0xf1 0x1e +# CHECK: vnegne.f64 d16, d16 + +0x10 0x0a 0x00 0x1e +0x10 0x1a 0x00 0x0e +# CHECK: vmovne s0, r0 +# CHECK: vmoveq s0, r1 + +0x10 0x0a 0xf1 0xee +# CHECK: vmrs r0, fpscr +0x10 0x0a 0xf8 0xee +# CHECK: vmrs r0, fpexc +0x10 0x0a 0xf0 0xee +# CHECK: vmrs r0, fpsid + +0x10 0x0a 0xe1 0xee +# CHECK: vmsr fpscr, r0 +0x10 0x0a 0xe8 0xee +# CHECK: vmsr fpexc, r0 +0x10 0x0a 0xe0 0xee +# CHECK: vmsr fpsid, r0 + +0x10 0x0a 0x00 0xee +0x90 0x1a 0x00 0xee +0x10 0x2a 0x01 0xee +0x90 0x3a 0x01 0xee +# CHECK: vmov s0, r0 +# CHECK: vmov s1, r1 +# CHECK: vmov s2, r2 +# CHECK: vmov s3, r3 + +0x10 0x0a 0x10 0xee +0x90 0x1a 0x10 0xee +0x10 0x2a 0x11 0xee +0x90 0x3a 0x11 0xee +# CHECK: vmov r0, s0 +# CHECK: vmov r1, s1 +# CHECK: vmov r2, s2 +# CHECK: vmov r3, s3 + +0x30 0x0b 0x51 0xec +# CHECK: vmov r0, r1, d16 + +0x00 0x1b 0xd0 0xed +# CHECK: vldr.64 d17, [r0] + +0x08 0x1b 0x92 0xed +0x08 0x1b 0x12 0xed +# CHECK: vldr.64 d1, [r2, #32] +# CHECK: vldr.64 d1, [r2, #-32] + +0x00 0x2b 0x93 0xed +# CHECK: vldr.64 d2, [r3] + +0x00 0x3b 0x9f 0xed +# CHECK: vldr.64 d3, [pc] + +0x00 0x6a 0xd0 0xed +# CHECK: vldr.32 s13, [r0] + +0x08 0x0a 0xd2 0xed +0x08 0x0a 0x52 0xed +# CHECK: vldr.32 s1, [r2, #32] +# CHECK: vldr.32 s1, [r2, #-32] + +0x00 0x1a 0x93 0xed +# CHECK: vldr.32 s2, [r3] + +0x00 0x2a 0xdf 0xed +# CHECK: vldr.32 s5, [pc] + +0x00 0x4b 0x81 0xed +0x06 0x4b 0x81 0xed +0x06 0x4b 0x01 0xed +# CHECK: vstr.64 d4, [r1] +# CHECK: vstr.64 d4, [r1, #24] +# CHECK: vstr.64 d4, [r1, #-24] + +0x00 0x2a 0x81 0xed +0x06 0x2a 0x81 0xed +0x06 0x2a 0x01 0xed +# CHECK: vstr.32 s4, [r1] +# CHECK: vstr.32 s4, [r1, #24] +# CHECK: vstr.32 s4, [r1, #-24] + +0x0c 0x2b 0x91 0xec +0x06 0x1a 0x91 0xec +# CHECK: vldmia r1, {d2, d3, d4, d5, d6, d7} +# CHECK: vldmia r1, {s2, s3, s4, s5, s6, s7} + +0x0c 0x2b 0x81 0xec +0x06 0x1a 0x81 0xec +# CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} +# CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} + +0x40 0x0b 0xbd 0xee +0x60 0x0a 0xbd 0xee +0x40 0x0b 0xbc 0xee +0x60 0x0a 0xbc 0xee +# CHECK: vcvtr.s32.f64 s0, d0 +# CHECK: vcvtr.s32.f32 s0, s1 +# CHECK: vcvtr.u32.f64 s0, d0 +# CHECK: vcvtr.u32.f32 s0, s1 diff --git a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt index ca0c1ab..a0d5944 100644 --- a/test/MC/Disassembler/ARM/invalid-BFI-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-BFI-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=60 Name=BFI Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 1| 0: 1: 1: 0| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt index 66c43c2..d2d424c 100644 --- a/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-Bcc-thumb.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=2249 Name=tBcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- -# +# # if cond = '1110' then UNDEFINED 0x6f 0xde diff --git a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt index 5202217..6fdb55e 100644 --- a/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-CPS3p-arm.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} # invalid (imod, M, iflags) combination 0x93 0x1c 0x02 0xf1 diff --git a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt index 0a4be68..b441485 100644 --- a/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-DMB-thumb.txt @@ -1,11 +1,11 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=1908 Name=t2DMB Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 0: 0: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| # ------------------------------------------------------------------------------------------------- -# +# # Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. # Reject invalid encodings. # diff --git a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt index afa2baf..de042a97 100644 --- a/test/MC/Disassembler/ARM/invalid-DSB-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-DSB-arm.txt @@ -1,11 +1,11 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=102 Name=DSB Format=ARM_FORMAT_MISCFRM(26) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 0: 1: 0: 1| 0: 1: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 0: 0| # ------------------------------------------------------------------------------------------------- -# +# # Inst{3-0} encodes the option: SY, ST, ISH, ISHST, NSH, NSHST, OSH, OSHST. # Reject invalid encodings. # diff --git a/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt new file mode 100644 index 0000000..6174e92 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-IT-CBNZ-thumb.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding} + +# CBZ / CBNZ not allowed in IT block. + +0xdb 0xbf 0x42 0xbb diff --git a/test/MC/Disassembler/ARM/invalid-IT-thumb.txt b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt new file mode 100644 index 0000000..9b571b3 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-IT-thumb.txt @@ -0,0 +1,3 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-unknown-unknown |& grep {potentially undefined instruction encoding} + +0xff 0xbf 0x6b 0x80 0x00 0x75 diff --git a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt index b966a9d..0b0426b 100644 --- a/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDC-form-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 0: 1| 1: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 1: 0: 1: 1| 0: 1: 0: 0| 1: 0: 0: 1| 0: 0: 1: 0| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt new file mode 100644 index 0000000..a42b248 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding} + +# Writeback is not allowed is Rn is in the target register list. + +0xb4 0xe8 0x34 0x04 diff --git a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt index 7a35c2d..6b695b9 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRB_POST-arm.txt @@ -1,10 +1,10 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} # Opcode=140 Name=LDRB_POST Format=ARM_FORMAT_LDFRM(6) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 0| 1: 1: 0: 1| 0: 1: 1: 1| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 0: 1| # ------------------------------------------------------------------------------------------------- -# +# # if wback && (n == 15 || n == t) then UNPREDICTABLE 0x05 0x70 0xd7 0xe6 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt new file mode 100644 index 0000000..f8f23ed --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-LDRD-arm.txt @@ -0,0 +1,10 @@ +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} + +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# ------------------------------------------------------------------------------------------------- +# | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| X: X: X: 1| X: X: X: X| 1: 1: X: 1| X: X: X: X| +# ------------------------------------------------------------------------------------------------- +# +# A8.6.68 LDRD (register) +# if Rt{0} = 1 then UNDEFINED; +0xd0 0x10 0x00 0x00 diff --git a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt index da2e6be..7ea1b46 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRD_PRE-thumb.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=1930 Name=t2LDRD_PRE Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt index fb2ce20..067dcb3 100644 --- a/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDRT-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 0| 0: 0: 1: 1| 0: 1: 1: 1| 0: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt index ad79986..eef2c45 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_POST-arm.txt @@ -1,4 +1,5 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# XFAIL: * # LDR_PRE/POST has encoding Inst{4} = 0. 0xde 0x69 0x18 0x46 diff --git a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt index 36c1124..e42e0de 100644 --- a/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-LDR_PRE-arm.txt @@ -1,10 +1,10 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {potentially undefined instruction encoding} # Opcode=165 Name=LDR_PRE Format=ARM_FORMAT_LDFRM(6) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 1| 0: 1: 1: 1| 0: 1: 1: 0| 0: 0: 0: 0| 1: 0: 0: 0| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- -# +# # if m == 15 then UNPREDICTABLE 0x8f 0x60 0xb7 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt index 20293ad..6a1f11f 100644 --- a/test/MC/Disassembler/ARM/invalid-LSL-regform.txt +++ b/test/MC/Disassembler/ARM/invalid-LSL-regform.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 0: 0: 0: 1| 0: 0: 1: 0| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt index d39b9c1..8343d54 100644 --- a/test/MC/Disassembler/ARM/invalid-MCR-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MCR-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt index 0b8a077..235952f 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVTi16-arm.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=185 Name=MOVTi16 Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 0: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| # ------------------------------------------------------------------------------------------------- -# +# # if d == 15 then UNPREDICTABLE 0x00 0xf0 0x41 0xe3 diff --git a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt index f82d3cb..01c1466 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVr-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt index 3165ff7..757d167 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt index cfbba43..ba48877 100644 --- a/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MOVs-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt index e9d5deb..3765b1f 100644 --- a/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-MSRi-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt index 1fdfa82..cffd86d 100644 --- a/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt b/test/MC/Disassembler/ARM/invalid-RSC-arm.txt index e7992ae..096b909 100644 --- a/test/MC/Disassembler/ARM/invalid-RSC-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-RSC-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt index 1ecd87d..9e16536 100644 --- a/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SBFX-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=271 Name=SBFX Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 0: 1: 0| 0: 1: 1: 1| 0: 1: 0: 1| 0: 1: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt index c3dcf83..91f3d58 100644 --- a/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SMLAD-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=284 Name=SMLAD Format=ARM_FORMAT_MULFRM(1) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 0: 0: 1| 0: 1: 1: 1| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 1: 0| 1: 0: 0: 0| 0: 0: 0: 1| 1: 0: 1: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt index fdca9f9..fc5c711 100644 --- a/test/MC/Disassembler/ARM/invalid-SRS-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SRS-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=0 Name=PHI Format=(42) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt b/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt index 9cc8351..b236f8e 100644 --- a/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SSAT-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=322 Name=SSAT Format=ARM_FORMAT_SATFRM(13) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 1| 1: 0: 1: 0| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt index 0000c60..ca16724 100644 --- a/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-STMIA_UPD-thumb.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=2313 Name=tSTMIA_UPD Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 1: 1: 0: 0| 0: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| # ------------------------------------------------------------------------------------------------- -# +# # if BitCount(registers) < 1 then UNPREDICTABLE 0x00 0xc7 diff --git a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt b/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt index 5209323..d3998bd 100644 --- a/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-STRBrs-arm.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=355 Name=STRBrs Format=ARM_FORMAT_STFRM(7) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 1| 1: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| # ------------------------------------------------------------------------------------------------- -# +# # if t == 15 then UNPREDICTABLE 0x00 0xf0 0xcf 0xe7 diff --git a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt index 4ec681d..400d44c 100644 --- a/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-SXTB-arm.txt @@ -1,7 +1,7 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=390 Name=SXTBr_rot Format=ARM_FORMAT_EXTFRM(14) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 0| 1: 0: 1: 0| 1: 1: 1: 1| 1: 1: 1: 1| 0: 1: 0: 0| 0: 1: 1: 1| 0: 1: 0: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt index 7a3ef33..c7cbd84 100644 --- a/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt @@ -1,11 +1,11 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0| # ------------------------------------------------------------------------------------------------- # # A8.6.244 UMAAL # if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE; -0x98 0xbf 0x4f 0xf0 +0x98 0xbf 0x4f 0xf0 diff --git a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt b/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt index d3f508a..fb3e711 100644 --- a/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-UQADD8-arm.txt @@ -1,11 +1,11 @@ # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=426 Name=UQADD8 Format=ARM_FORMAT_DPFRM(4) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 1: 0| 0: 1: 0: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- -# +# # DPFrm with bad reg specifier(s) # # if d == 15 || n == 15 || m == 15 then UNPREDICTABLE; diff --git a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt index 56d9ad7..12da869 100644 --- a/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VLD1DUPq8_UPD-arm.txt @@ -1,4 +1,5 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# XFAIL: * # Opcode=737 Name=VLD1DUPq8_UPD Format=ARM_FORMAT_NLdSt(30) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt index 5fd0251..bab32ca 100644 --- a/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-VLD3DUPd32_UPD-thumb.txt @@ -1,11 +1,11 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=871 Name=VLD3DUPd32_UPD Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 0: 1: 0: 0| 1: 0: 1: 0| 0: 0: 1: 0| 0: 0: 1: 0| 1: 1: 1: 0| 1: 0: 0: 1| 0: 0: 1: 0| # ------------------------------------------------------------------------------------------------- -# +# # A8.6.315 VLD3 (single 3-element structure to all lanes) # The a bit must be encoded as 0. 0xa2 0xf9 0x92 0x2e diff --git a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt index eed012b..a53f940 100644 --- a/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt @@ -1,4 +1,5 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# XFAIL: * # Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt index 506250c..a12ca95 100644 --- a/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt +++ b/test/MC/Disassembler/ARM/invalid-VST2b32_UPD-arm.txt @@ -1,7 +1,8 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 |& grep {invalid instruction encoding} +# XFAIL: * # Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| # ------------------------------------------------------------------------------------------------- diff --git a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt index d0bc51e..df0a642 100644 --- a/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt @@ -1,11 +1,11 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0| # ------------------------------------------------------------------------------------------------- -# +# # A8.6.16 B # if cond<3:1> == '111' then SEE "Related Encodings" 0xaf 0xf7 0x44 0x8b diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt index 9befbd6..e1f841b8 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRBT-thumb.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=1922 Name=t2LDRBT Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 1: 0: 0: 0| 0: 0: 0: 1| 0: 0: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 0: 0: 0: 0| 0: 0: 1: 1| # ------------------------------------------------------------------------------------------------- -# +# # The unpriviledged Load/Store cannot have SP or PC as Rt. 0x10 0xf8 0x3 0xfe diff --git a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt index 598efd1..7c0efab 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDREXD-thumb.txt @@ -1,4 +1,5 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# XFAIL: * # Opcode=1934 Name=t2LDREXD Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt index a501eb9..a63d121 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi12-thumb.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=1953 Name=t2LDRSHi12 Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- -# +# # if Rt = '1111' then SEE "Unallocated memory hints" 0xb3 0xf9 0xdf 0xf8 diff --git a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt index f886a6f..f126ff0 100644 --- a/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2LDRSHi8-thumb.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=1954 Name=t2LDRSHi8 Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 1: 1| 0: 1: 0: 1| 1: 1: 1: 1| 1: 1: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| # ------------------------------------------------------------------------------------------------- -# +# # if Rt == '1111' and PUW == '100' then SEE "Unallocated memory hints" 0x35 0xf9 0x00 0xfc diff --git a/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt new file mode 100644 index 0000000..b3daa9a --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-t2PUSH-thumb.txt @@ -0,0 +1,5 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} + +# SP and PC are not allowed in the register list on STM instructions in Thumb2. + +0x2d 0xe9 0xf7 0xb6 diff --git a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt index c8f8ec2..2198efc 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STRD_PRE-thumb.txt @@ -1,4 +1,5 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# XFAIL: * # Opcode=2124 Name=t2STRD_PRE Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt index 35ea651..3f406d4 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STREXB-thumb.txt @@ -1,4 +1,5 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {invalid instruction encoding} +# XFAIL: * # Opcode=2127 Name=t2STREXB Format=ARM_FORMAT_THUMBFRM(25) # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 diff --git a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt index 9b0cf24..0f9a16e 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STREXD-thumb.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=2128 Name=t2STREXD Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 0| 1: 0: 0: 0| 1: 1: 0: 0| 0: 0: 1: 0| 0: 1: 1: 1| 1: 0: 0: 0| 0: 1: 1: 1| 1: 0: 0: 0| # ------------------------------------------------------------------------------------------------- -# +# # if d == n || d == t || d == t2 then UNPREDICTABLE mc-input.txt:1:1: warning: invalid instruction encoding diff --git a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt index 129a270..548ad05 100644 --- a/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt +++ b/test/MC/Disassembler/ARM/invalid-t2STR_POST-thumb.txt @@ -1,10 +1,10 @@ # RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding} # Opcode=2137 Name=t2STR_POST Format=ARM_FORMAT_THUMBFRM(25) -# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 +# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 # ------------------------------------------------------------------------------------------------- # | 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 1: 1: 0| 1: 0: 1: 1| 1: 1: 1: 1| 1: 1: 1: 1| # ------------------------------------------------------------------------------------------------- -# +# # if Rn == '1111' then UNDEFINED 0x4f 0xf8 0xff 0xeb diff --git a/test/MC/Disassembler/ARM/memory-arm-instructions.txt b/test/MC/Disassembler/ARM/memory-arm-instructions.txt new file mode 100644 index 0000000..4fa2897 --- /dev/null +++ b/test/MC/Disassembler/ARM/memory-arm-instructions.txt @@ -0,0 +1,470 @@ +# RUN: llvm-mc -triple=armv7-apple-darwin -disassemble < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# LDR (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldr r5, [r7] +# CHECK: ldr r6, [r3, #63] +# CHECK: ldr r2, [r4, #4095]! +# CHECK: ldr r1, [r2], #30 +# CHECK: ldr r3, [r1], #-30 + +0x00 0x50 0x97 0xe5 +0x3f 0x60 0x93 0xe5 +0xff 0x2f 0xb4 0xe5 +0x1e 0x10 0x92 0xe4 +0x1e 0x30 0x11 0xe4 + +#------------------------------------------------------------------------------ +# FIXME: LDR (literal) +#------------------------------------------------------------------------------ +# label operands currently assert the show-encoding asm comment helper due +# to the use of non-contiguous bit ranges for fixups in ARM. Once that's +# cleaned up, we can write useful assembly testcases for these sorts of +# instructions. + +#------------------------------------------------------------------------------ +# LDR (register) +#------------------------------------------------------------------------------ +# CHECK: ldr r3, [r8, r1] +# CHECK: ldr r2, [r5, -r3] +# CHECK: ldr r1, [r5, r9]! +# CHECK: ldr r6, [r7, -r8]! +# CHECK: ldr r1, [r0, r2, lsr #3]! +# CHECK: ldr r5, [r9], r2 +# CHECK: ldr r4, [r3], -r6 +# CHECK: ldr r3, [r8, -r2, lsl #15 +# CHECK: ldr r1, [r5], r3, asr #15 + +0x01 0x30 0x98 0xe7 +0x03 0x20 0x15 0xe7 +0x09 0x10 0xb5 0xe7 +0x08 0x60 0x37 0xe7 +0xa2 0x11 0xb0 0xe7 +0x02 0x50 0x99 0xe6 +0x06 0x40 0x13 0xe6 +0x82 0x37 0x18 0xe7 +0xc3 0x17 0x95 0xe6 + + +#------------------------------------------------------------------------------ +# LDRB (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrb r3, [r8] +# CHECK: ldrb r1, [sp, #63] +# CHECK: ldrb r9, [r3, #4095]! +# CHECK: ldrb r8, [r1], #22 +# CHECK: ldrb r2, [r7], #-19 + +0x00 0x30 0xd8 0xe5 +0x3f 0x10 0xdd 0xe5 +0xff 0x9f 0xf3 0xe5 +0x16 0x80 0xd1 0xe4 +0x13 0x20 0x57 0xe4 + + +#------------------------------------------------------------------------------ +# LDRB (register) +#------------------------------------------------------------------------------ +# CHECK: ldrb r9, [r8, r5] +# CHECK: ldrb r1, [r5, -r1] +# CHECK: ldrb r3, [r5, r2]! +# CHECK: ldrb r6, [r9, -r3]! +# CHECK: ldrb r2, [r1], r4 +# CHECK: ldrb r8, [r4], -r5 +# CHECK: ldrb r7, [r12, -r1, lsl #15 +# CHECK: ldrb r5, [r2], r9, asr #15 + +0x05 0x90 0xd8 0xe7 +0x01 0x10 0x55 0xe7 +0x02 0x30 0xf5 0xe7 +0x03 0x60 0x79 0xe7 +0x04 0x20 0xd1 0xe6 +0x05 0x80 0x54 0xe6 +0x81 0x77 0x5c 0xe7 +0xc9 0x57 0xd2 0xe6 + + +#------------------------------------------------------------------------------ +# LDRBT +#------------------------------------------------------------------------------ +# FIXME: Optional offset operand. +# CHECK: ldrbt r3, [r1], #4 +# CHECK: ldrbt r2, [r8], #-8 +# CHECK: ldrbt r8, [r7], r6 +# CHECK: ldrbt r1, [r2], -r6, lsl #12 + + +0x04 0x30 0xf1 0xe4 +0x08 0x20 0x78 0xe4 +0x06 0x80 0xf7 0xe6 +0x06 0x16 0x72 0xe6 + + +#------------------------------------------------------------------------------ +# LDRD (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrd r0, r1, [r5] +# CHECK: ldrd r8, r9, [r2, #15] +# CHECK: ldrd r2, r3, [r9, #32]! +# CHECK: ldrd r6, r7, [r1], #8 +# CHECK: ldrd r2, r3, [r8], #0 +# CHECK: ldrd r2, r3, [r8], #0 +# CHECK: ldrd r2, r3, [r8], #-0 + +0xd0 0x00 0xc5 0xe1 +0xdf 0x80 0xc2 0xe1 +0xd0 0x22 0xe9 0xe1 +0xd8 0x60 0xc1 0xe0 +0xd0 0x20 0xc8 0xe0 +0xd0 0x20 0xc8 0xe0 +0xd0 0x20 0x48 0xe0 + + +#------------------------------------------------------------------------------ +# FIXME: LDRD (label) +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# LDRD (register) +#------------------------------------------------------------------------------ +# CHECK: ldrd r4, r5, [r1, r3] +# CHECK: ldrd r4, r5, [r7, r2]! +# CHECK: ldrd r0, r1, [r8], r12 +# CHECK: ldrd r0, r1, [r8], -r12 + +0xd3 0x40 0x81 0xe1 +0xd2 0x40 0xa7 0xe1 +0xdc 0x00 0x88 0xe0 +0xdc 0x00 0x08 0xe0 + + +#------------------------------------------------------------------------------ +# LDRH (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrh r3, [r4 +# CHECK: ldrh r2, [r7, #4 +# CHECK: ldrh r1, [r8, #64]! +# CHECK: ldrh r12, [sp], #4 + +0xb0 0x30 0xd4 0xe1 +0xb4 0x20 0xd7 0xe1 +0xb0 0x14 0xf8 0xe1 +0xb4 0xc0 0xdd 0xe0 + + +#------------------------------------------------------------------------------ +# FIXME: LDRH (label) +#------------------------------------------------------------------------------ + + +#------------------------------------------------------------------------------ +# LDRH (register) +#------------------------------------------------------------------------------ +# CHECK: ldrh r6, [r5, r4 +# CHECK: ldrh r3, [r8, r11]! +# CHECK: ldrh r1, [r2, -r1]! +# CHECK: ldrh r9, [r7], r2 +# CHECK: ldrh r4, [r3], -r2 + +0xb4 0x60 0x95 0xe1 +0xbb 0x30 0xb8 0xe1 +0xb1 0x10 0x32 0xe1 +0xb2 0x90 0x97 0xe0 +0xb2 0x40 0x13 0xe0 + + +#------------------------------------------------------------------------------ +# LDRHT +#------------------------------------------------------------------------------ +# CHECK: ldrht r9, [r7], #128 +# CHECK: ldrht r4, [r3], #-75 +# CHECK: ldrht r9, [r7], r2 +# CHECK: ldrht r4, [r3], -r2 + +0xb0 0x98 0xf7 0xe0 +0xbb 0x44 0x73 0xe0 +0xb2 0x90 0xb7 0xe0 +0xb2 0x40 0x33 0xe0 + + +#------------------------------------------------------------------------------ +# LDRSB (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrsb r3, [r4 +# CHECK: ldrsb r2, [r7, #17 +# CHECK: ldrsb r1, [r8, #255]! +# CHECK: ldrsb r12, [sp], #9 + +0xd0 0x30 0xd4 0xe1 +0xd1 0x21 0xd7 0xe1 +0xdf 0x1f 0xf8 0xe1 +0xd9 0xc0 0xdd 0xe0 + + +#------------------------------------------------------------------------------ +# FIXME: LDRSB (label) +#------------------------------------------------------------------------------ + + +#------------------------------------------------------------------------------ +# LDRSB (register) +#------------------------------------------------------------------------------ +# CHECK: ldrsb r6, [r5, r4 +# CHECK: ldrsb r3, [r8, r11]! +# CHECK: ldrsb r1, [r2, -r1]! +# CHECK: ldrsb r9, [r7], r2 +# CHECK: ldrsb r4, [r3], -r2 + + +0xd4 0x60 0x95 0xe1 +0xdb 0x30 0xb8 0xe1 +0xd1 0x10 0x32 0xe1 +0xd2 0x90 0x97 0xe0 +0xd2 0x40 0x13 0xe0 + + +#------------------------------------------------------------------------------ +# LDRSBT +#------------------------------------------------------------------------------ +# CHECK: ldrsbt r5, [r6], #1 +# CHECK: ldrsbt r3, [r8], #-12 +# CHECK: ldrsbt r8, [r9], r5 +# CHECK: ldrsbt r2, [r1], -r4 + +0xd1 0x50 0xf6 0xe0 +0xdc 0x30 0x78 0xe0 +0xd5 0x80 0xb9 0xe0 +0xd4 0x20 0x31 0xe0 + + +#------------------------------------------------------------------------------ +# LDRSH (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrsh r5, [r9 +# CHECK: ldrsh r4, [r5, #7 +# CHECK: ldrsh r3, [r6, #55]! +# CHECK: ldrsh r2, [r7], #-9 + +0xf0 0x50 0xd9 0xe1 +0xf7 0x40 0xd5 0xe1 +0xf7 0x33 0xf6 0xe1 +0xf9 0x20 0x57 0xe0 + + +#------------------------------------------------------------------------------ +# FIXME: LDRSH (label) +#------------------------------------------------------------------------------ + + +#------------------------------------------------------------------------------ +# LDRSH (register) +#------------------------------------------------------------------------------ +# CHECK: ldrsh r3, [r1, r5 +# CHECK: ldrsh r4, [r6, r1]! +# CHECK: ldrsh r5, [r3, -r6]! +# CHECK: ldrsh r6, [r9], r8 +# CHECK: ldrsh r7, [r8], -r3 + +0xf5 0x30 0x91 0xe1 +0xf1 0x40 0xb6 0xe1 +0xf6 0x50 0x33 0xe1 +0xf8 0x60 0x99 0xe0 +0xf3 0x70 0x18 0xe0 + + +#------------------------------------------------------------------------------ +# LDRSHT +#------------------------------------------------------------------------------ +# CHECK: ldrsht r5, [r6], #1 +# CHECK: ldrsht r3, [r8], #-12 +# CHECK: ldrsht r8, [r9], r5 +# CHECK: ldrsht r2, [r1], -r4 + +0xf1 0x50 0xf6 0xe0 +0xfc 0x30 0x78 0xe0 +0xf5 0x80 0xb9 0xe0 +0xf4 0x20 0x31 0xe0 + + +#------------------------------------------------------------------------------ +# STR (immediate) +#------------------------------------------------------------------------------ +# CHECK: str r8, [r12 +# CHECK: str r7, [r1, #12 +# CHECK: str r3, [r5, #40]! +# CHECK: str r9, [sp], #4095 +# CHECK: str r1, [r7], #-128 + +0x00 0x80 0x8c 0xe5 +0x0c 0x70 0x81 0xe5 +0x28 0x30 0xa5 0xe5 +0xff 0x9f 0x8d 0xe4 +0x80 0x10 0x07 0xe4 + + +#------------------------------------------------------------------------------ +# FIXME: STR (literal) +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# STR (register) +#------------------------------------------------------------------------------ +# CHECK: str r9, [r6, r3 +# CHECK: str r8, [r0, -r2 +# CHECK: str r7, [r1, r6]! +# CHECK: str r6, [sp, -r1]! +# CHECK: str r5, [r3], r9 +# CHECK: str r4, [r2], -r5 +# CHECK: str r3, [r4, -r2, lsl #2 +# CHECK: str r2, [r7], r3, asr #24 + +0x03 0x90 0x86 0xe7 +0x02 0x80 0x00 0xe7 +0x06 0x70 0xa1 0xe7 +0x01 0x60 0x2d 0xe7 +0x09 0x50 0x83 0xe6 +0x05 0x40 0x02 0xe6 +0x02 0x31 0x04 0xe7 +0x43 0x2c 0x87 0xe6 + + +#------------------------------------------------------------------------------ +# STRB (immediate) +#------------------------------------------------------------------------------ +# CHECK: strb r9, [r2 +# CHECK: strb r7, [r1, #3 +# CHECK: strb r6, [r4, #405]! +# CHECK: strb r5, [r7], #72 +# CHECK: strb r1, [sp], #-1 + +0x00 0x90 0xc2 0xe5 +0x03 0x70 0xc1 0xe5 +0x95 0x61 0xe4 0xe5 +0x48 0x50 0xc7 0xe4 +0x01 0x10 0x4d 0xe4 + +#------------------------------------------------------------------------------ +# FIXME: STRB (literal) +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# STRB (register) +#------------------------------------------------------------------------------ +# CHECK: strb r1, [r2, r9 +# CHECK: strb r2, [r3, -r8 +# CHECK: strb r3, [r4, r7]! +# CHECK: strb r4, [r5, -r6]! +# CHECK: strb r5, [r6], r5 +# CHECK: strb r6, [r2], -r4 +# CHECK: strb r7, [r12, -r3, lsl #5 +# CHECK: strb sp, [r7], r2, asr #12 + +0x09 0x10 0xc2 0xe7 +0x08 0x20 0x43 0xe7 +0x07 0x30 0xe4 0xe7 +0x06 0x40 0x65 0xe7 +0x05 0x50 0xc6 0xe6 +0x04 0x60 0x42 0xe6 +0x83 0x72 0x4c 0xe7 +0x42 0xd6 0xc7 0xe6 + + +#------------------------------------------------------------------------------ +# STRBT +#------------------------------------------------------------------------------ +# FIXME: Optional offset operand. +# CHECK: strbt r6, [r2], #12 +# CHECK: strbt r5, [r6], #-13 +# CHECK: strbt r4, [r9], r5 +# CHECK: strbt r3, [r8], -r2, lsl #3 + +0x0c 0x60 0xe2 0xe4 +0x0d 0x50 0x66 0xe4 +0x05 0x40 0xe9 0xe6 +0x82 0x31 0x68 0xe6 + + +#------------------------------------------------------------------------------ +# STRD (immediate) +#------------------------------------------------------------------------------ +# CHECK: strd r0, r1, [r4] +# CHECK: strd r2, r3, [r6, #1] +# CHECK: strd r2, r3, [r7, #22]! +# CHECK: strd r4, r5, [r8], #7 +# CHECK: strd r4, r5, [sp], #0 +# CHECK: strd r6, r7, [lr], #0 +# CHECK: strd r6, r7, [r9], #-0 + +0xf0 0x00 0xc4 0xe1 +0xf1 0x20 0xc6 0xe1 +0xf6 0x21 0xe7 0xe1 +0xf7 0x40 0xc8 0xe0 +0xf0 0x40 0xcd 0xe0 +0xf0 0x60 0xce 0xe0 +0xf0 0x60 0x49 0xe0 + + +#------------------------------------------------------------------------------ +# FIXME: STRD (label) +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# STRD (register) +#------------------------------------------------------------------------------ +# CHECK: strd r8, r9, [r4, r1] +# CHECK: strd r6, r7, [r3, r9]! +# CHECK: strd r6, r7, [r5], r8 +# CHECK: strd r4, r5, [r12], -r10 + +0xf1 0x80 0x84 0xe1 +0xf9 0x60 0xa3 0xe1 +0xf8 0x60 0x85 0xe0 +0xfa 0x40 0x0c 0xe0 + +#------------------------------------------------------------------------------ +# STRH (immediate) +#------------------------------------------------------------------------------ +# CHECK: strh r3, [r4 +# CHECK: strh r2, [r7, #4 +# CHECK: strh r1, [r8, #64]! +# CHECK: strh r12, [sp], #4 + +0xb0 0x30 0xc4 0xe1 +0xb4 0x20 0xc7 0xe1 +0xb0 0x14 0xe8 0xe1 +0xb4 0xc0 0xcd 0xe0 + + +#------------------------------------------------------------------------------ +# FIXME: STRH (label) +#------------------------------------------------------------------------------ + + +#------------------------------------------------------------------------------ +# STRH (register) +#------------------------------------------------------------------------------ +# CHECK: strh r6, [r5, r4 +# CHECK: strh r3, [r8, r11]! +# CHECK: strh r1, [r2, -r1]! +# CHECK: strh r9, [r7], r2 +# CHECK: strh r4, [r3], -r2 + +0xb4 0x60 0x85 0xe1 +0xbb 0x30 0xa8 0xe1 +0xb1 0x10 0x22 0xe1 +0xb2 0x90 0x87 0xe0 +0xb2 0x40 0x03 0xe0 + +#------------------------------------------------------------------------------ +# STRHT +#------------------------------------------------------------------------------ +# CHECK: strht r2, [r5], #76 +# CHECK: strht r8, [r1], #-25 +# CHECK: strht r5, [r3], r4 +# CHECK: strht r6, [r8], -r0 + +0xbc 0x24 0xe5 0xe0 +0xb9 0x81 0x61 0xe0 +0xb4 0x50 0xa3 0xe0 +0xb0 0x60 0x28 0xe0 diff --git a/test/MC/Disassembler/ARM/neon-tests.txt b/test/MC/Disassembler/ARM/neon-tests.txt index 4fa5723..1e03deb 100644 --- a/test/MC/Disassembler/ARM/neon-tests.txt +++ b/test/MC/Disassembler/ARM/neon-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 | FileCheck %s # CHECK: vbif q15, q7, q0 0x50 0xe1 0x7e 0xf3 @@ -24,7 +24,7 @@ # CHECK: vld1.32 {d3[], d4[]}, [r0, :32]! 0xbd 0x3c 0xa0 0xf4 -# CHECK: vld4.16 {d3[], d4[], d5[], d6[]}, [r0, :64]! +# CHECK: vld4.16 {d3[], d5[], d7[], d9[]}, [r0, :64]! 0x7d 0x3f 0xa0 0xf4 # CHECK: vorr d0, d15, d15 @@ -87,5 +87,5 @@ # CHECK: usada8mi r8, r9, r5, r9 0x19 0x95 0x88 0x47 -# CHECK: vext.8 q4, q2, q1, #4 +# CHECK: vext.32 q4, q2, q1, #1 0x42 0x84 0xb4 0xf2 diff --git a/test/MC/Disassembler/ARM/neon.txt b/test/MC/Disassembler/ARM/neon.txt new file mode 100644 index 0000000..5d2df93 --- /dev/null +++ b/test/MC/Disassembler/ARM/neon.txt @@ -0,0 +1,1858 @@ +# RUN: llvm-mc -triple armv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s + +0x20 0x03 0xf1 0xf3 +# CHECK: vabs.s8 d16, d16 +0x20 0x03 0xf5 0xf3 +# CHECK: vabs.s16 d16, d16 +0x20 0x03 0xf9 0xf3 +# CHECK: vabs.s32 d16, d16 +0x20 0x07 0xf9 0xf3 +# CHECK: vabs.f32 d16, d16 +0x60 0x03 0xf1 0xf3 +# CHECK: vabs.s8 q8, q8 +0x60 0x03 0xf5 0xf3 +# CHECK: vabs.s16 q8, q8 +0x60 0x03 0xf9 0xf3 +# CHECK: vabs.s32 q8, q8 +0x60 0x07 0xf9 0xf3 +# CHECK: vabs.f32 q8, q8 + +0x20 0x07 0xf0 0xf3 +# CHECK: vqabs.s8 d16, d16 +0x20 0x07 0xf4 0xf3 +# CHECK: vqabs.s16 d16, d16 +0x20 0x07 0xf8 0xf3 +# CHECK: vqabs.s32 d16, d16 +0x60 0x07 0xf0 0xf3 +# CHECK: vqabs.s8 q8, q8 +0x60 0x07 0xf4 0xf3 +# CHECK: vqabs.s16 q8, q8 +0x60 0x07 0xf8 0xf3 +# CHECK: vqabs.s32 q8, q8 + +0xa1 0x07 0x40 0xf2 +# CHECK: vabd.s8 d16, d16, d17 +0xa1 0x07 0x50 0xf2 +# CHECK: vabd.s16 d16, d16, d17 +0xa1 0x07 0x60 0xf2 +# CHECK: vabd.s32 d16, d16, d17 +0xa1 0x07 0x40 0xf3 +# CHECK: vabd.u8 d16, d16, d17 +0xa1 0x07 0x50 0xf3 +# CHECK: vabd.u16 d16, d16, d17 + 0xa1 0x07 0x60 0xf3 +# CHECK: vabd.u32 d16, d16, d17 +0xa1 0x0d 0x60 0xf3 +# CHECK: vabd.f32 d16, d16, d17 +0xe2 0x07 0x40 0xf2 +# CHECK: vabd.s8 q8, q8, q9 +0xe2 0x07 0x50 0xf2 +# CHECK: vabd.s16 q8, q8, q9 +0xe2 0x07 0x60 0xf2 +# CHECK: vabd.s32 q8, q8, q9 +0xe2 0x07 0x40 0xf3 +# CHECK: vabd.u8 q8, q8, q9 +0xe2 0x07 0x50 0xf3 +# CHECK: vabd.u16 q8, q8, q9 +0xe2 0x07 0x60 0xf3 +# CHECK: vabd.u32 q8, q8, q9 +0xe2 0x0d 0x60 0xf3 +# CHECK: vabd.f32 q8, q8, q9 + +0xa1 0x07 0xc0 0xf2 +# CHECK: vabdl.s8 q8, d16, d17 +0xa1 0x07 0xd0 0xf2 +# CHECK: vabdl.s16 q8, d16, d17 +0xa1 0x07 0xe0 0xf2 +# CHECK: vabdl.s32 q8, d16, d17 +0xa1 0x07 0xc0 0xf3 +# CHECK: vabdl.u8 q8, d16, d17 +0xa1 0x07 0xd0 0xf3 +# CHECK: vabdl.u16 q8, d16, d17 +0xa1 0x07 0xe0 0xf3 +# CHECK: vabdl.u32 q8, d16, d17 + +0xb1 0x07 0x42 0xf2 +# CHECK: vaba.s8 d16, d18, d17 +0xb1 0x07 0x52 0xf2 +# CHECK: vaba.s16 d16, d18, d17 +0xb1 0x07 0x62 0xf2 +# CHECK: vaba.s32 d16, d18, d17 +0xb1 0x07 0x42 0xf3 +# CHECK: vaba.u8 d16, d18, d17 +0xb1 0x07 0x52 0xf3 +# CHECK: vaba.u16 d16, d18, d17 +0xb1 0x07 0x62 0xf3 +# CHECK: vaba.u32 d16, d18, d17 +0xf4 0x27 0x40 0xf2 +# CHECK: vaba.s8 q9, q8, q10 +0xf4 0x27 0x50 0xf2 +# CHECK: vaba.s16 q9, q8, q10 +0xf4 0x27 0x60 0xf2 +# CHECK: vaba.s32 q9, q8, q10 +0xf4 0x27 0x40 0xf3 +# CHECK: vaba.u8 q9, q8, q10 +0xf4 0x27 0x50 0xf3 +# CHECK: vaba.u16 q9, q8, q10 +0xf4 0x27 0x60 0xf3 +# CHECK: vaba.u32 q9, q8, q10 + +0xa2 0x05 0xc3 0xf2 +# CHECK: vabal.s8 q8, d19, d18 +0xa2 0x05 0xd3 0xf2 +# CHECK: vabal.s16 q8, d19, d18 +0xa2 0x05 0xe3 0xf2 +# CHECK: vabal.s32 q8, d19, d18 +0xa2 0x05 0xc3 0xf3 +# CHECK: vabal.u8 q8, d19, d18 +0xa2 0x05 0xd3 0xf3 +# CHECK: vabal.u16 q8, d19, d18 +0xa2 0x05 0xe3 0xf3 +# CHECK: vabal.u32 q8, d19, d18 + + + + +0xa0 0x08 0x41 0xf2 +# CHECK: vadd.i8 d16, d17, d16 +0xa0 0x08 0x51 0xf2 +# CHECK: vadd.i16 d16, d17, d16 +0xa0 0x08 0x71 0xf2 +# CHECK: vadd.i64 d16, d17, d16 +0xa0 0x08 0x61 0xf2 +# CHECK: vadd.i32 d16, d17, d16 +0xa1 0x0d 0x40 0xf2 +# CHECK: vadd.f32 d16, d16, d17 +0xe2 0x0d 0x40 0xf2 +# CHECK: vadd.f32 q8, q8, q9 + +0xa0 0x00 0xc1 0xf2 +# CHECK: vaddl.s8 q8, d17, d16 +0xa0 0x00 0xd1 0xf2 +# CHECK: vaddl.s16 q8, d17, d16 +0xa0 0x00 0xe1 0xf2 +# CHECK: vaddl.s32 q8, d17, d16 +0xa0 0x00 0xc1 0xf3 +# CHECK: vaddl.u8 q8, d17, d16 +0xa0 0x00 0xd1 0xf3 +# CHECK: vaddl.u16 q8, d17, d16 +0xa0 0x00 0xe1 0xf3 +# CHECK: vaddl.u32 q8, d17, d16 + +0xa2 0x01 0xc0 0xf2 +# CHECK: vaddw.s8 q8, q8, d18 +0xa2 0x01 0xd0 0xf2 +# CHECK: vaddw.s16 q8, q8, d18 +0xa2 0x01 0xe0 0xf2 +# CHECK: vaddw.s32 q8, q8, d18 +0xa2 0x01 0xc0 0xf3 +# CHECK: vaddw.u8 q8, q8, d18 +0xa2 0x01 0xd0 0xf3 +# CHECK: vaddw.u16 q8, q8, d18 +0xa2 0x01 0xe0 0xf3 +# CHECK: vaddw.u32 q8, q8, d18 + +0xa1 0x00 0x40 0xf2 +# CHECK: vhadd.s8 d16, d16, d17 +0xa1 0x00 0x50 0xf2 +# CHECK: vhadd.s16 d16, d16, d17 +0xa1 0x00 0x60 0xf2 +# CHECK: vhadd.s32 d16, d16, d17 +0xa1 0x00 0x40 0xf3 +# CHECK: vhadd.u8 d16, d16, d17 +0xa1 0x00 0x50 0xf3 +# CHECK: vhadd.u16 d16, d16, d17 +0xa1 0x00 0x60 0xf3 +# CHECK: vhadd.u32 d16, d16, d17 +0xe2 0x00 0x40 0xf2 +# CHECK: vhadd.s8 q8, q8, q9 +0xe2 0x00 0x50 0xf2 +# CHECK: vhadd.s16 q8, q8, q9 +0xe2 0x00 0x60 0xf2 +# CHECK: vhadd.s32 q8, q8, q9 + 0xe2 0x00 0x40 0xf3 +# CHECK: vhadd.u8 q8, q8, q9 +0xe2 0x00 0x50 0xf3 +# CHECK: vhadd.u16 q8, q8, q9 +0xe2 0x00 0x60 0xf3 +# CHECK: vhadd.u32 q8, q8, q9 + +0xa1 0x01 0x40 0xf2 +# CHECK: vrhadd.s8 d16, d16, d17 +0xa1 0x01 0x50 0xf2 +# CHECK: vrhadd.s16 d16, d16, d17 +0xa1 0x01 0x60 0xf2 +# CHECK: vrhadd.s32 d16, d16, d17 +0xa1 0x01 0x40 0xf3 +# CHECK: vrhadd.u8 d16, d16, d17 +0xa1 0x01 0x50 0xf3 +# CHECK: vrhadd.u16 d16, d16, d17 +0xa1 0x01 0x60 0xf3 +# CHECK: vrhadd.u32 d16, d16, d17 +0xe2 0x01 0x40 0xf2 +# CHECK: vrhadd.s8 q8, q8, q9 +0xe2 0x01 0x50 0xf2 +# CHECK: vrhadd.s16 q8, q8, q9 +0xe2 0x01 0x60 0xf2 +# CHECK: vrhadd.s32 q8, q8, q9 +0xe2 0x01 0x40 0xf3 +# CHECK: vrhadd.u8 q8, q8, q9 +0xe2 0x01 0x50 0xf3 +# CHECK: vrhadd.u16 q8, q8, q9 +0xe2 0x01 0x60 0xf3 +# CHECK: vrhadd.u32 q8, q8, q9 + +0xb1 0x00 0x40 0xf2 +# CHECK: vqadd.s8 d16, d16, d17 +0xb1 0x00 0x50 0xf2 +# CHECK: vqadd.s16 d16, d16, d17 +0xb1 0x00 0x60 0xf2 +# CHECK: vqadd.s32 d16, d16, d17 +0xb1 0x00 0x70 0xf2 +# CHECK: vqadd.s64 d16, d16, d17 +0xb1 0x00 0x40 0xf3 +# CHECK: vqadd.u8 d16, d16, d17 +0xb1 0x00 0x50 0xf3 +# CHECK: vqadd.u16 d16, d16, d17 +0xb1 0x00 0x60 0xf3 +# CHECK: vqadd.u32 d16, d16, d17 +0xb1 0x00 0x70 0xf3 +# CHECK: vqadd.u64 d16, d16, d17 +0xf2 0x00 0x40 0xf2 +# CHECK: vqadd.s8 q8, q8, q9 +0xf2 0x00 0x50 0xf2 +# CHECK: vqadd.s16 q8, q8, q9 +0xf2 0x00 0x60 0xf2 +# CHECK: vqadd.s32 q8, q8, q9 +0xf2 0x00 0x70 0xf2 +# CHECK: vqadd.s64 q8, q8, q9 +0xf2 0x00 0x40 0xf3 +# CHECK: vqadd.u8 q8, q8, q9 +0xf2 0x00 0x50 0xf3 +# CHECK: vqadd.u16 q8, q8, q9 +0xf2 0x00 0x60 0xf3 +# CHECK: vqadd.u32 q8, q8, q9 +0xf2 0x00 0x70 0xf3 +# CHECK: vqadd.u64 q8, q8, q9 + +0xa2 0x04 0xc0 0xf2 +# CHECK: vaddhn.i16 d16, q8, q9 +0xa2 0x04 0xd0 0xf2 +# CHECK: vaddhn.i32 d16, q8, q9 +0xa2 0x04 0xe0 0xf2 +# CHECK: vaddhn.i64 d16, q8, q9 +0xa2 0x04 0xc0 0xf3 +# CHECK: vraddhn.i16 d16, q8, q9 +0xa2 0x04 0xd0 0xf3 +# CHECK: vraddhn.i32 d16, q8, q9 +0xa2 0x04 0xe0 0xf3 +# CHECK: vraddhn.i64 d16, q8, q9 + + +0x20 0x05 0xf0 0xf3 +# CHECK: vcnt.8 d16, d16 +0x60 0x05 0xf0 0xf3 +# CHECK: vcnt.8 q8, q8 +0xa0 0x04 0xf0 0xf3 +# CHECK: vclz.i8 d16, d16 +0xa0 0x04 0xf4 0xf3 +# CHECK: vclz.i16 d16, d16 +0xa0 0x04 0xf8 0xf3 +# CHECK: vclz.i32 d16, d16 +0xe0 0x04 0xf0 0xf3 +# CHECK: vclz.i8 q8, q8 +0xe0 0x04 0xf4 0xf3 +# CHECK: vclz.i16 q8, q8 +0xe0 0x04 0xf8 0xf3 +# CHECK: vclz.i32 q8, q8 +0x20 0x04 0xf0 0xf3 +# CHECK: vcls.s8 d16, d16 +0x20 0x04 0xf4 0xf3 +# CHECK: vcls.s16 d16, d16 +0x20 0x04 0xf8 0xf3 +# CHECK: vcls.s32 d16, d16 +0x60 0x04 0xf0 0xf3 +# CHECK: vcls.s8 q8, q8 +0x60 0x04 0xf4 0xf3 +# CHECK: vcls.s16 q8, q8 +0x60 0x04 0xf8 0xf3 +# CHECK: vcls.s32 q8, q8 + + + + +0xb0 0x01 0x41 0xf2 +# CHECK: vand d16, d17, d16 +0xf2 0x01 0x40 0xf2 +# CHECK: vand q8, q8, q9 + +0xb0 0x01 0x41 0xf3 +# CHECK: veor d16, d17, d16 +0xf2 0x01 0x40 0xf3 +# CHECK: veor q8, q8, q9 + +0xb0 0x01 0x61 0xf2 +# CHECK: vorr d16, d17, d16 +0xf2 0x01 0x60 0xf2 +# CHECK: vorr q8, q8, q9 +0x11 0x07 0xc0 0xf2 +# CHECK: vorr.i32 d16, #0x1000000 +0x51 0x07 0xc0 0xf2 +# CHECK: vorr.i32 q8, #0x1000000 +0x50 0x01 0xc0 0xf2 +# CHECK: vorr.i32 q8, #0x0 + +0xb0 0x01 0x51 0xf2 +# CHECK: vbic d16, d17, d16 +0xf2 0x01 0x50 0xf2 +# CHECK: vbic q8, q8, q9 +0x3f 0x07 0xc7 0xf3 +# CHECK: vbic.i32 d16, #0xFF000000 +0x7f 0x07 0xc7 0xf3 +# CHECK: vbic.i32 q8, #0xFF000000 + +0xb0 0x01 0x71 0xf2 +# CHECK: vorn d16, d17, d16 +0xf2 0x01 0x70 0xf2 +# CHECK: vorn q8, q8, q9 + +0xa0 0x05 0xf0 0xf3 +# CHECK: vmvn d16, d16 +0xe0 0x05 0xf0 0xf3 +# CHECK: vmvn q8, q8 + +0xb0 0x21 0x51 0xf3 +# CHECK: vbsl d18, d17, d16 +0xf2 0x01 0x54 0xf3 +# CHECK: vbsl q8, q10, q9 + + +# CHECK: vceq.i8 d16, d16, d17 +# CHECK: vceq.i16 d16, d16, d17 +# CHECK: vceq.i32 d16, d16, d17 +# CHECK: vceq.f32 d16, d16, d17 +# CHECK: vceq.i8 q8, q8, q9 +# CHECK: vceq.i16 q8, q8, q9 +# CHECK: vceq.i32 q8, q8, q9 +# CHECK: vceq.f32 q8, q8, q9 + +0xb1 0x08 0x40 0xf3 +0xb1 0x08 0x50 0xf3 +0xb1 0x08 0x60 0xf3 +0xa1 0x0e 0x40 0xf2 +0xf2 0x08 0x40 0xf3 +0xf2 0x08 0x50 0xf3 +0xf2 0x08 0x60 0xf3 +0xe2 0x0e 0x40 0xf2 + +# CHECK: vcge.s8 d16, d16, d17 +# CHECK: vcge.s16 d16, d16, d17 +# CHECK: vcge.s32 d16, d16, d17 +# CHECK: vcge.u8 d16, d16, d17 +# CHECK: vcge.u16 d16, d16, d17 +# CHECK: vcge.u32 d16, d16, d17 +# CHECK: vcge.f32 d16, d16, d17 +# CHECK: vcge.s8 q8, q8, q9 +# CHECK: vcge.s16 q8, q8, q9 +# CHECK: vcge.s32 q8, q8, q9 +# CHECK: vcge.u8 q8, q8, q9 +# CHECK: vcge.u16 q8, q8, q9 +# CHECK: vcge.u32 q8, q8, q9 +# CHECK: vcge.f32 q8, q8, q9 +# CHECK: vacge.f32 d16, d16, d17 +# CHECK: vacge.f32 q8, q8, q9 + +0xb1 0x03 0x40 0xf2 +0xb1 0x03 0x50 0xf2 +0xb1 0x03 0x60 0xf2 +0xb1 0x03 0x40 0xf3 +0xb1 0x03 0x50 0xf3 +0xb1 0x03 0x60 0xf3 +0xa1 0x0e 0x40 0xf3 +0xf2 0x03 0x40 0xf2 +0xf2 0x03 0x50 0xf2 +0xf2 0x03 0x60 0xf2 +0xf2 0x03 0x40 0xf3 +0xf2 0x03 0x50 0xf3 +0xf2 0x03 0x60 0xf3 +0xe2 0x0e 0x40 0xf3 +0xb1 0x0e 0x40 0xf3 +0xf2 0x0e 0x40 0xf3 + +# CHECK: vcgt.s8 d16, d16, d17 +# CHECK: vcgt.s16 d16, d16, d17 +# CHECK: vcgt.s32 d16, d16, d17 +# CHECK: vcgt.u8 d16, d16, d17 +# CHECK: vcgt.u16 d16, d16, d17 +# CHECK: vcgt.u32 d16, d16, d17 +# CHECK: vcgt.f32 d16, d16, d17 +# CHECK: vcgt.s8 q8, q8, q9 +# CHECK: vcgt.s16 q8, q8, q9 +# CHECK: vcgt.s32 q8, q8, q9 +# CHECK: vcgt.u8 q8, q8, q9 +# CHECK: vcgt.u16 q8, q8, q9 +# CHECK: vcgt.u32 q8, q8, q9 +# CHECK: vcgt.f32 q8, q8, q9 +# CHECK: vacgt.f32 d16, d16, d17 +# CHECK: vacgt.f32 q8, q8, q9 + +0xa1 0x03 0x40 0xf2 +0xa1 0x03 0x50 0xf2 +0xa1 0x03 0x60 0xf2 +0xa1 0x03 0x40 0xf3 +0xa1 0x03 0x50 0xf3 +0xa1 0x03 0x60 0xf3 +0xa1 0x0e 0x60 0xf3 +0xe2 0x03 0x40 0xf2 +0xe2 0x03 0x50 0xf2 +0xe2 0x03 0x60 0xf2 +0xe2 0x03 0x40 0xf3 +0xe2 0x03 0x50 0xf3 +0xe2 0x03 0x60 0xf3 +0xe2 0x0e 0x60 0xf3 +0xb1 0x0e 0x60 0xf3 +0xf2 0x0e 0x60 0xf3 + +# CHECK: vtst.8 d16, d16, d17 +# CHECK: vtst.16 d16, d16, d17 +# CHECK: vtst.32 d16, d16, d17 +# CHECK: vtst.8 q8, q8, q9 +# CHECK: vtst.16 q8, q8, q9 +# CHECK: vtst.32 q8, q8, q9 + +0xb1 0x08 0x40 0xf2 +0xb1 0x08 0x50 0xf2 +0xb1 0x08 0x60 0xf2 +0xf2 0x08 0x40 0xf2 +0xf2 0x08 0x50 0xf2 +0xf2 0x08 0x60 0xf2 + +# CHECK: vceq.i8 d16, d16, #0 +# CHECK: vcge.s8 d16, d16, #0 +# CHECK: vcle.s8 d16, d16, #0 +# CHECK: vcgt.s8 d16, d16, #0 +# CHECK: vclt.s8 d16, d16, #0 + +0x20 0x01 0xf1 0xf3 +0xa0 0x00 0xf1 0xf3 +0xa0 0x01 0xf1 0xf3 +0x20 0x00 0xf1 0xf3 +0x20 0x02 0xf1 0xf3 + + +0x20 0x07 0xfb 0xf3 +# CHECK: vcvt.s32.f32 d16, d16 +0xa0 0x07 0xfb 0xf3 +# CHECK: vcvt.u32.f32 d16, d16 +0x20 0x06 0xfb 0xf3 +# CHECK: vcvt.f32.s32 d16, d16 +0xa0 0x06 0xfb 0xf3 +# CHECK: vcvt.f32.u32 d16, d16 +0x60 0x07 0xfb 0xf3 +# CHECK: vcvt.s32.f32 q8, q8 +0xe0 0x07 0xfb 0xf3 +# CHECK: vcvt.u32.f32 q8, q8 +0x60 0x06 0xfb 0xf3 +# CHECK: vcvt.f32.s32 q8, q8 +0xe0 0x06 0xfb 0xf3 +# CHECK: vcvt.f32.u32 q8, q8 +0x30 0x0f 0xff 0xf2 +# CHECK: vcvt.s32.f32 d16, d16, #1 +0x30 0x0f 0xff 0xf3 +# CHECK: vcvt.u32.f32 d16, d16, #1 +0x30 0x0e 0xff 0xf2 +# CHECK: vcvt.f32.s32 d16, d16, #1 +0x30 0x0e 0xff 0xf3 +# CHECK: vcvt.f32.u32 d16, d16, #1 +0x70 0x0f 0xff 0xf2 +# CHECK: vcvt.s32.f32 q8, q8, #1 +0x70 0x0f 0xff 0xf3 +# CHECK: vcvt.u32.f32 q8, q8, #1 +0x70 0x0e 0xff 0xf2 +# CHECK: vcvt.f32.s32 q8, q8, #1 +0x70 0x0e 0xff 0xf3 +# CHECK: vcvt.f32.u32 q8, q8, #1 +0x20 0x07 0xf6 0xf3 +# CHECK: vcvt.f32.f16 q8, d16 +0x20 0x06 0xf6 0xf3 +# CHECK: vcvt.f16.f32 d16, q8 + + + + +# CHECK: vdup.8 d16, r0 +# CHECK: vdup.16 d16, r0 +# CHECK: vdup.32 d16, r0 + +0x90 0x0b 0xc0 0xee +0xb0 0x0b 0x80 0xee +0x90 0x0b 0x80 0xee + +# CHECK: vdup.8 q8, r0 +# CHECK: vdup.16 q8, r0 +# CHECK: vdup.32 q8, r0 + +0x90 0x0b 0xe0 0xee +0xb0 0x0b 0xa0 0xee +0x90 0x0b 0xa0 0xee + +# CHECK: vdup.8 d16, d16[1 +# CHECK: vdup.16 d16, d16[1 +# CHECK: vdup.32 d16, d16[1 + +0x20 0x0c 0xf3 0xf3 +0x20 0x0c 0xf6 0xf3 +0x20 0x0c 0xfc 0xf3 + +# CHECK: vdup.8 q8, d16[1 +# CHECK: vdup.16 q8, d16[1 +# CHECK: vdup.32 q8, d16[1 + +0x60 0x0c 0xf3 0xf3 +0x60 0x0c 0xf6 0xf3 +0x60 0x0c 0xfc 0xf3 + + +0xb1 0x06 0x40 0xf2 +# CHECK: vmin.s8 d16, d16, d17 +0xb1 0x06 0x50 0xf2 +# CHECK: vmin.s16 d16, d16, d17 +0xb1 0x06 0x60 0xf2 +# CHECK: vmin.s32 d16, d16, d17 +0xb1 0x06 0x40 0xf3 +# CHECK: vmin.u8 d16, d16, d17 +0xb1 0x06 0x50 0xf3 +# CHECK: vmin.u16 d16, d16, d17 +0xb1 0x06 0x60 0xf3 +# CHECK: vmin.u32 d16, d16, d17 +0xa1 0x0f 0x60 0xf2 +# CHECK: vmin.f32 d16, d16, d17 +0xf2 0x06 0x40 0xf2 +# CHECK: vmin.s8 q8, q8, q9 +0xf2 0x06 0x50 0xf2 +# CHECK: vmin.s16 q8, q8, q9 +0xf2 0x06 0x60 0xf2 +# CHECK: vmin.s32 q8, q8, q9 +0xf2 0x06 0x40 0xf3 +# CHECK: vmin.u8 q8, q8, q9 +0xf2 0x06 0x50 0xf3 +# CHECK: vmin.u16 q8, q8, q9 +0xf2 0x06 0x60 0xf3 +# CHECK: vmin.u32 q8, q8, q9 +0xe2 0x0f 0x60 0xf2 +# CHECK: vmin.f32 q8, q8, q9 +0xa1 0x06 0x40 0xf2 +# CHECK: vmax.s8 d16, d16, d17 +0xa1 0x06 0x50 0xf2 +# CHECK: vmax.s16 d16, d16, d17 +0xa1 0x06 0x60 0xf2 +# CHECK: vmax.s32 d16, d16, d17 +0xa1 0x06 0x40 0xf3 +# CHECK: vmax.u8 d16, d16, d17 +0xa1 0x06 0x50 0xf3 +# CHECK: vmax.u16 d16, d16, d17 +0xa1 0x06 0x60 0xf3 +# CHECK: vmax.u32 d16, d16, d17 +0xa1 0x0f 0x40 0xf2 +# CHECK: vmax.f32 d16, d16, d17 +0xe2 0x06 0x40 0xf2 +# CHECK: vmax.s8 q8, q8, q9 +0xe2 0x06 0x50 0xf2 +# CHECK: vmax.s16 q8, q8, q9 +0xe2 0x06 0x60 0xf2 +# CHECK: vmax.s32 q8, q8, q9 +0xe2 0x06 0x40 0xf3 +# CHECK: vmax.u8 q8, q8, q9 +0xe2 0x06 0x50 0xf3 +# CHECK: vmax.u16 q8, q8, q9 +0xe2 0x06 0x60 0xf3 +# CHECK: vmax.u32 q8, q8, q9 +0xe2 0x0f 0x40 0xf2 +# CHECK: vmax.f32 q8, q8, q9 + + + +0x18 0x0e 0xc0 0xf2 +# CHECK: vmov.i8 d16, #0x8 +0x10 0x08 0xc1 0xf2 +# CHECK: vmov.i16 d16, #0x10 +0x10 0x0a 0xc1 0xf2 +# CHECK: vmov.i16 d16, #0x1000 +0x10 0x00 0xc2 0xf2 +# CHECK: vmov.i32 d16, #0x20 +0x10 0x02 0xc2 0xf2 +# CHECK: vmov.i32 d16, #0x2000 +0x10 0x04 0xc2 0xf2 +# CHECK: vmov.i32 d16, #0x200000 +0x10 0x06 0xc2 0xf2 +# CHECK: vmov.i32 d16, #0x20000000 +0x10 0x0c 0xc2 0xf2 +# CHECK: vmov.i32 d16, #0x20FF +0x10 0x0d 0xc2 0xf2 +# CHECK: vmov.i32 d16, #0x20FFFF +0x33 0x0e 0xc1 0xf3 +# CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF +0x58 0x0e 0xc0 0xf2 +# CHECK: vmov.i8 q8, #0x8 +0x50 0x08 0xc1 0xf2 +# CHECK: vmov.i16 q8, #0x10 +0x50 0x0a 0xc1 0xf2 +# CHECK: vmov.i16 q8, #0x1000 +0x50 0x00 0xc2 0xf2 +# CHECK: vmov.i32 q8, #0x20 +0x50 0x02 0xc2 0xf2 +# CHECK: vmov.i32 q8, #0x2000 +0x50 0x04 0xc2 0xf2 +# CHECK: vmov.i32 q8, #0x200000 +0x50 0x06 0xc2 0xf2 +# CHECK: vmov.i32 q8, #0x20000000 +0x50 0x0c 0xc2 0xf2 +# CHECK: vmov.i32 q8, #0x20FF +0x50 0x0d 0xc2 0xf2 +# CHECK: vmov.i32 q8, #0x20FFFF +0x73 0x0e 0xc1 0xf3 +# CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF +0x30 0x08 0xc1 0xf2 +# CHECK: vmvn.i16 d16, #0x10 +0x30 0x0a 0xc1 0xf2 +# CHECK: vmvn.i16 d16, #0x1000 +0x30 0x00 0xc2 0xf2 +# CHECK: vmvn.i32 d16, #0x20 +0x30 0x02 0xc2 0xf2 +# CHECK: vmvn.i32 d16, #0x2000 +0x30 0x04 0xc2 0xf2 +# CHECK: vmvn.i32 d16, #0x200000 +0x30 0x06 0xc2 0xf2 +# CHECK: vmvn.i32 d16, #0x20000000 +0x30 0x0c 0xc2 0xf2 +# CHECK: vmvn.i32 d16, #0x20FF +0x30 0x0d 0xc2 0xf2 +# CHECK: vmvn.i32 d16, #0x20FFFF +0x30 0x0a 0xc8 0xf2 +# CHECK: vmovl.s8 q8, d16 +0x30 0x0a 0xd0 0xf2 +# CHECK: vmovl.s16 q8, d16 +0x30 0x0a 0xe0 0xf2 +# CHECK: vmovl.s32 q8, d16 +0x30 0x0a 0xc8 0xf3 +# CHECK: vmovl.u8 q8, d16 +0x30 0x0a 0xd0 0xf3 +# CHECK: vmovl.u16 q8, d16 +0x30 0x0a 0xe0 0xf3 +# CHECK: vmovl.u32 q8, d16 +0x20 0x02 0xf2 0xf3 +# CHECK: vmovn.i16 d16, q8 +0x20 0x02 0xf6 0xf3 +# CHECK: vmovn.i32 d16, q8 +0x20 0x02 0xfa 0xf3 +# CHECK: vmovn.i64 d16, q8 +0xa0 0x02 0xf2 0xf3 +# CHECK: vqmovn.s16 d16, q8 +0xa0 0x02 0xf6 0xf3 +# CHECK: vqmovn.s32 d16, q8 +0xa0 0x02 0xfa 0xf3 +# CHECK: vqmovn.s64 d16, q8 +0xe0 0x02 0xf2 0xf3 +# CHECK: vqmovn.u16 d16, q8 +0xe0 0x02 0xf6 0xf3 +# CHECK: vqmovn.u32 d16, q8 +0xe0 0x02 0xfa 0xf3 +# CHECK: vqmovn.u64 d16, q8 +0x60 0x02 0xf2 0xf3 +# CHECK: vqmovun.s16 d16, q8 +0x60 0x02 0xf6 0xf3 +# CHECK: vqmovun.s32 d16, q8 +0x60 0x02 0xfa 0xf3 +# CHECK: vqmovun.s64 d16, q8 +0xb0 0x0b 0x50 0xee +# CHECK: vmov.s8 r0, d16[1 +0xf0 0x0b 0x10 0xee +# CHECK: vmov.s16 r0, d16[1 +0xb0 0x0b 0xd0 0xee +# CHECK: vmov.u8 r0, d16[1 +0xf0 0x0b 0x90 0xee +# CHECK: vmov.u16 r0, d16[1 +0x90 0x0b 0x30 0xee +# CHECK: vmov.32 r0, d16[1 +0xb0 0x1b 0x40 0xee +# CHECK: vmov.8 d16[1], r1 +0xf0 0x1b 0x00 0xee +# CHECK: vmov.16 d16[1], r1 +0x90 0x1b 0x20 0xee +# CHECK: vmov.32 d16[1], r1 +0xb0 0x1b 0x42 0xee +# CHECK: vmov.8 d18[1], r1 +0xf0 0x1b 0x02 0xee +# CHECK: vmov.16 d18[1], r1 +0x90 0x1b 0x22 0xee +# CHECK: vmov.32 d18[1], r1 + + + +0xa1 0x09 0x42 0xf2 +# CHECK: vmla.i8 d16, d18, d17 +0xa1 0x09 0x52 0xf2 +# CHECK: vmla.i16 d16, d18, d17 +0xa1 0x09 0x62 0xf2 +# CHECK: vmla.i32 d16, d18, d17 +0xb1 0x0d 0x42 0xf2 +# CHECK: vmla.f32 d16, d18, d17 +0xe4 0x29 0x40 0xf2 +# CHECK: vmla.i8 q9, q8, q10 +0xe4 0x29 0x50 0xf2 +# CHECK: vmla.i16 q9, q8, q10 +0xe4 0x29 0x60 0xf2 +# CHECK: vmla.i32 q9, q8, q10 +0xf4 0x2d 0x40 0xf2 +# CHECK: vmla.f32 q9, q8, q10 +0xa2 0x08 0xc3 0xf2 +# CHECK: vmlal.s8 q8, d19, d18 +0xa2 0x08 0xd3 0xf2 +# CHECK: vmlal.s16 q8, d19, d18 +0xa2 0x08 0xe3 0xf2 +# CHECK: vmlal.s32 q8, d19, d18 +0xa2 0x08 0xc3 0xf3 +# CHECK: vmlal.u8 q8, d19, d18 +0xa2 0x08 0xd3 0xf3 +# CHECK: vmlal.u16 q8, d19, d18 +0xa2 0x08 0xe3 0xf3 +# CHECK: vmlal.u32 q8, d19, d18 +0xa2 0x09 0xd3 0xf2 +# CHECK: vqdmlal.s16 q8, d19, d18 +0xa2 0x09 0xe3 0xf2 +# CHECK: vqdmlal.s32 q8, d19, d18 +0xa1 0x09 0x42 0xf3 +# CHECK: vmls.i8 d16, d18, d17 +0xa1 0x09 0x52 0xf3 +# CHECK: vmls.i16 d16, d18, d17 +0xa1 0x09 0x62 0xf3 +# CHECK: vmls.i32 d16, d18, d17 +0xb1 0x0d 0x62 0xf2 +# CHECK: vmls.f32 d16, d18, d17 +0xe4 0x29 0x40 0xf3 +# CHECK: vmls.i8 q9, q8, q10 +0xe4 0x29 0x50 0xf3 +# CHECK: vmls.i16 q9, q8, q10 +0xe4 0x29 0x60 0xf3 +# CHECK: vmls.i32 q9, q8, q10 +0xf4 0x2d 0x60 0xf2 +# CHECK: vmls.f32 q9, q8, q10 +0xa2 0x0a 0xc3 0xf2 +# CHECK: vmlsl.s8 q8, d19, d18 +0xa2 0x0a 0xd3 0xf2 +# CHECK: vmlsl.s16 q8, d19, d18 +0xa2 0x0a 0xe3 0xf2 +# CHECK: vmlsl.s32 q8, d19, d18 +0xa2 0x0a 0xc3 0xf3 +# CHECK: vmlsl.u8 q8, d19, d18 +0xa2 0x0a 0xd3 0xf3 +# CHECK: vmlsl.u16 q8, d19, d18 +0xa2 0x0a 0xe3 0xf3 +# CHECK: vmlsl.u32 q8, d19, d18 +0xa2 0x0b 0xd3 0xf2 +# CHECK: vqdmlsl.s16 q8, d19, d18 +0xa2 0x0b 0xe3 0xf2 +# CHECK: vqdmlsl.s32 q8, d19, d18 + + +0xb1 0x09 0x40 0xf2 +# CHECK: vmul.i8 d16, d16, d17 +0xb1 0x09 0x50 0xf2 +# CHECK: vmul.i16 d16, d16, d17 +0xb1 0x09 0x60 0xf2 +# CHECK: vmul.i32 d16, d16, d17 +0xb1 0x0d 0x40 0xf3 +# CHECK: vmul.f32 d16, d16, d17 +0xf2 0x09 0x40 0xf2 +# CHECK: vmul.i8 q8, q8, q9 +0xf2 0x09 0x50 0xf2 +# CHECK: vmul.i16 q8, q8, q9 +0xf2 0x09 0x60 0xf2 +# CHECK: vmul.i32 q8, q8, q9 +0xf2 0x0d 0x40 0xf3 +# CHECK: vmul.f32 q8, q8, q9 +0xb1 0x09 0x40 0xf3 +# CHECK: vmul.p8 d16, d16, d17 +0xf2 0x09 0x40 0xf3 +# CHECK: vmul.p8 q8, q8, q9 +0xa1 0x0b 0x50 0xf2 +# CHECK: vqdmulh.s16 d16, d16, d17 +0xa1 0x0b 0x60 0xf2 +# CHECK: vqdmulh.s32 d16, d16, d17 +0xe2 0x0b 0x50 0xf2 +# CHECK: vqdmulh.s16 q8, q8, q9 +0xe2 0x0b 0x60 0xf2 +# CHECK: vqdmulh.s32 q8, q8, q9 +0xa1 0x0b 0x50 0xf3 +# CHECK: vqrdmulh.s16 d16, d16, d17 +0xa1 0x0b 0x60 0xf3 +# CHECK: vqrdmulh.s32 d16, d16, d17 +0xe2 0x0b 0x50 0xf3 +# CHECK: vqrdmulh.s16 q8, q8, q9 +0xe2 0x0b 0x60 0xf3 +# CHECK: vqrdmulh.s32 q8, q8, q9 +0xa1 0x0c 0xc0 0xf2 +# CHECK: vmull.s8 q8, d16, d17 +0xa1 0x0c 0xd0 0xf2 +# CHECK: vmull.s16 q8, d16, d17 +0xa1 0x0c 0xe0 0xf2 +# CHECK: vmull.s32 q8, d16, d17 +0xa1 0x0c 0xc0 0xf3 +# CHECK: vmull.u8 q8, d16, d17 +0xa1 0x0c 0xd0 0xf3 +# CHECK: vmull.u16 q8, d16, d17 +0xa1 0x0c 0xe0 0xf3 +# CHECK: vmull.u32 q8, d16, d17 +0xa1 0x0e 0xc0 0xf2 +# CHECK: vmull.p8 q8, d16, d17 +0xa1 0x0d 0xd0 0xf2 +# CHECK: vqdmull.s16 q8, d16, d17 +0xa1 0x0d 0xe0 0xf2 +# CHECK: vqdmull.s32 q8, d16, d17 + + +0xa0 0x03 0xf1 0xf3 +# CHECK: vneg.s8 d16, d16 +0xa0 0x03 0xf5 0xf3 +# CHECK: vneg.s16 d16, d16 +0xa0 0x03 0xf9 0xf3 +# CHECK: vneg.s32 d16, d16 +0xa0 0x07 0xf9 0xf3 +# CHECK: vneg.f32 d16, d16 +0xe0 0x03 0xf1 0xf3 +# CHECK: vneg.s8 q8, q8 +0xe0 0x03 0xf5 0xf3 +# CHECK: vneg.s16 q8, q8 +0xe0 0x03 0xf9 0xf3 +# CHECK: vneg.s32 q8, q8 +0xe0 0x07 0xf9 0xf3 +# CHECK: vneg.f32 q8, q8 +0xa0 0x07 0xf0 0xf3 +# CHECK: vqneg.s8 d16, d16 +0xa0 0x07 0xf4 0xf3 +# CHECK: vqneg.s16 d16, d16 +0xa0 0x07 0xf8 0xf3 +# CHECK: vqneg.s32 d16, d16 +0xe0 0x07 0xf0 0xf3 +# CHECK: vqneg.s8 q8, q8 +0xe0 0x07 0xf4 0xf3 +# CHECK: vqneg.s16 q8, q8 +0xe0 0x07 0xf8 0xf3 +# CHECK: vqneg.s32 q8, q8 + + +0xb0 0x0b 0x41 0xf2 +# CHECK: vpadd.i8 d16, d17, d16 +0xb0 0x0b 0x51 0xf2 +# CHECK: vpadd.i16 d16, d17, d16 +0xb0 0x0b 0x61 0xf2 +# CHECK: vpadd.i32 d16, d17, d16 +0xa1 0x0d 0x40 0xf3 +# CHECK: vpadd.f32 d16, d16, d17 +0x20 0x02 0xf0 0xf3 +# CHECK: vpaddl.s8 d16, d16 +0x20 0x02 0xf4 0xf3 +# CHECK: vpaddl.s16 d16, d16 +0x20 0x02 0xf8 0xf3 +# CHECK: vpaddl.s32 d16, d16 +0xa0 0x02 0xf0 0xf3 +# CHECK: vpaddl.u8 d16, d16 +0xa0 0x02 0xf4 0xf3 +# CHECK: vpaddl.u16 d16, d16 +0xa0 0x02 0xf8 0xf3 +# CHECK: vpaddl.u32 d16, d16 +0x60 0x02 0xf0 0xf3 +# CHECK: vpaddl.s8 q8, q8 +0x60 0x02 0xf4 0xf3 +# CHECK: vpaddl.s16 q8, q8 +0x60 0x02 0xf8 0xf3 +# CHECK: vpaddl.s32 q8, q8 +0xe0 0x02 0xf0 0xf3 +# CHECK: vpaddl.u8 q8, q8 +0xe0 0x02 0xf4 0xf3 +# CHECK: vpaddl.u16 q8, q8 +0xe0 0x02 0xf8 0xf3 +# CHECK: vpaddl.u32 q8, q8 +0x21 0x06 0xf0 0xf3 +# CHECK: vpadal.s8 d16, d17 +0x21 0x06 0xf4 0xf3 +# CHECK: vpadal.s16 d16, d17 +0x21 0x06 0xf8 0xf3 +# CHECK: vpadal.s32 d16, d17 +0xa1 0x06 0xf0 0xf3 +# CHECK: vpadal.u8 d16, d17 +0xa1 0x06 0xf4 0xf3 +# CHECK: vpadal.u16 d16, d17 +0xa1 0x06 0xf8 0xf3 +# CHECK: vpadal.u32 d16, d17 +0x60 0x26 0xf0 0xf3 +# CHECK: vpadal.s8 q9, q8 +0x60 0x26 0xf4 0xf3 +# CHECK: vpadal.s16 q9, q8 +0x60 0x26 0xf8 0xf3 +# CHECK: vpadal.s32 q9, q8 +0xe0 0x26 0xf0 0xf3 +# CHECK: vpadal.u8 q9, q8 +0xe0 0x26 0xf4 0xf3 +# CHECK: vpadal.u16 q9, q8 +0xe0 0x26 0xf8 0xf3 +# CHECK: vpadal.u32 q9, q8 +0xb1 0x0a 0x40 0xf2 +# CHECK: vpmin.s8 d16, d16, d17 +0xb1 0x0a 0x50 0xf2 +# CHECK: vpmin.s16 d16, d16, d17 +0xb1 0x0a 0x60 0xf2 +# CHECK: vpmin.s32 d16, d16, d17 +0xb1 0x0a 0x40 0xf3 +# CHECK: vpmin.u8 d16, d16, d17 +0xb1 0x0a 0x50 0xf3 +# CHECK: vpmin.u16 d16, d16, d17 +0xb1 0x0a 0x60 0xf3 +# CHECK: vpmin.u32 d16, d16, d17 +0xa1 0x0f 0x60 0xf3 +# CHECK: vpmin.f32 d16, d16, d17 +0xa1 0x0a 0x40 0xf2 +# CHECK: vpmax.s8 d16, d16, d17 +0xa1 0x0a 0x50 0xf2 +# CHECK: vpmax.s16 d16, d16, d17 +0xa1 0x0a 0x60 0xf2 +# CHECK: vpmax.s32 d16, d16, d17 +0xa1 0x0a 0x40 0xf3 +# CHECK: vpmax.u8 d16, d16, d17 +0xa1 0x0a 0x50 0xf3 +# CHECK: vpmax.u16 d16, d16, d17 +0xa1 0x0a 0x60 0xf3 +# CHECK: vpmax.u32 d16, d16, d17 +0xa1 0x0f 0x40 0xf3 +# CHECK: vpmax.f32 d16, d16, d17 + + +0x20 0x04 0xfb 0xf3 +# CHECK: vrecpe.u32 d16, d16 +0x60 0x04 0xfb 0xf3 +# CHECK: vrecpe.u32 q8, q8 +0x20 0x05 0xfb 0xf3 +# CHECK: vrecpe.f32 d16, d16 +0x60 0x05 0xfb 0xf3 +# CHECK: vrecpe.f32 q8, q8 +0xb1 0x0f 0x40 0xf2 +# CHECK: vrecps.f32 d16, d16, d17 +0xf2 0x0f 0x40 0xf2 +# CHECK: vrecps.f32 q8, q8, q9 +0xa0 0x04 0xfb 0xf3 +# CHECK: vrsqrte.u32 d16, d16 +0xe0 0x04 0xfb 0xf3 +# CHECK: vrsqrte.u32 q8, q8 +0xa0 0x05 0xfb 0xf3 +# CHECK: vrsqrte.f32 d16, d16 +0xe0 0x05 0xfb 0xf3 +# CHECK: vrsqrte.f32 q8, q8 +0xb1 0x0f 0x60 0xf2 +# CHECK: vrsqrts.f32 d16, d16, d17 +0xf2 0x0f 0x60 0xf2 +# CHECK: vrsqrts.f32 q8, q8, q9 + + +0x20 0x00 0xf0 0xf3 +# CHECK: vrev64.8 d16, d16 +0x20 0x00 0xf4 0xf3 +# CHECK: vrev64.16 d16, d16 +0x20 0x00 0xf8 0xf3 +# CHECK: vrev64.32 d16, d16 +0x60 0x00 0xf0 0xf3 +# CHECK: vrev64.8 q8, q8 +0x60 0x00 0xf4 0xf3 +# CHECK: vrev64.16 q8, q8 +0x60 0x00 0xf8 0xf3 +# CHECK: vrev64.32 q8, q8 +0xa0 0x00 0xf0 0xf3 +# CHECK: vrev32.8 d16, d16 +0xa0 0x00 0xf4 0xf3 +# CHECK: vrev32.16 d16, d16 +0xe0 0x00 0xf0 0xf3 +# CHECK: vrev32.8 q8, q8 +0xe0 0x00 0xf4 0xf3 +# CHECK: vrev32.16 q8, q8 +0x20 0x01 0xf0 0xf3 +# CHECK: vrev16.8 d16, d16 +0x60 0x01 0xf0 0xf3 +# CHECK: vrev16.8 q8, q8 + + +0xb0 0x04 0x41 0xf2 +# CHECK: vqshl.s8 d16, d16, d17 +0xb0 0x04 0x51 0xf2 +# CHECK: vqshl.s16 d16, d16, d17 +0xb0 0x04 0x61 0xf2 +# CHECK: vqshl.s32 d16, d16, d17 +0xb0 0x04 0x71 0xf2 +# CHECK: vqshl.s64 d16, d16, d17 +0xb0 0x04 0x41 0xf3 +# CHECK: vqshl.u8 d16, d16, d17 +0xb0 0x04 0x51 0xf3 +# CHECK: vqshl.u16 d16, d16, d17 +0xb0 0x04 0x61 0xf3 +# CHECK: vqshl.u32 d16, d16, d17 +0xb0 0x04 0x71 0xf3 +# CHECK: vqshl.u64 d16, d16, d17 +0xf0 0x04 0x42 0xf2 +# CHECK: vqshl.s8 q8, q8, q9 +0xf0 0x04 0x52 0xf2 +# CHECK: vqshl.s16 q8, q8, q9 +0xf0 0x04 0x62 0xf2 +# CHECK: vqshl.s32 q8, q8, q9 +0xf0 0x04 0x72 0xf2 +# CHECK: vqshl.s64 q8, q8, q9 +0xf0 0x04 0x42 0xf3 +# CHECK: vqshl.u8 q8, q8, q9 +0xf0 0x04 0x52 0xf3 +# CHECK: vqshl.u16 q8, q8, q9 +0xf0 0x04 0x62 0xf3 +# CHECK: vqshl.u32 q8, q8, q9 +0xf0 0x04 0x72 0xf3 +# CHECK: vqshl.u64 q8, q8, q9 +0x30 0x07 0xcf 0xf2 +# CHECK: vqshl.s8 d16, d16, #7 +0x30 0x07 0xdf 0xf2 +# CHECK: vqshl.s16 d16, d16, #15 +0x30 0x07 0xff 0xf2 +# CHECK: vqshl.s32 d16, d16, #31 +0xb0 0x07 0xff 0xf2 +# CHECK: vqshl.s64 d16, d16, #63 +0x30 0x07 0xcf 0xf3 +# CHECK: vqshl.u8 d16, d16, #7 +0x30 0x07 0xdf 0xf3 +# CHECK: vqshl.u16 d16, d16, #15 +0x30 0x07 0xff 0xf3 +# CHECK: vqshl.u32 d16, d16, #31 +0xb0 0x07 0xff 0xf3 +# CHECK: vqshl.u64 d16, d16, #63 +0x30 0x06 0xcf 0xf3 +# CHECK: vqshlu.s8 d16, d16, #7 +0x30 0x06 0xdf 0xf3 +# CHECK: vqshlu.s16 d16, d16, #15 +0x30 0x06 0xff 0xf3 +# CHECK: vqshlu.s32 d16, d16, #31 +0xb0 0x06 0xff 0xf3 +# CHECK: vqshlu.s64 d16, d16, #63 +0x70 0x07 0xcf 0xf2 +# CHECK: vqshl.s8 q8, q8, #7 +0x70 0x07 0xdf 0xf2 +# CHECK: vqshl.s16 q8, q8, #15 +0x70 0x07 0xff 0xf2 +# CHECK: vqshl.s32 q8, q8, #31 +0xf0 0x07 0xff 0xf2 +# CHECK: vqshl.s64 q8, q8, #63 +0x70 0x07 0xcf 0xf3 +# CHECK: vqshl.u8 q8, q8, #7 +0x70 0x07 0xdf 0xf3 +# CHECK: vqshl.u16 q8, q8, #15 +0x70 0x07 0xff 0xf3 +# CHECK: vqshl.u32 q8, q8, #31 +0xf0 0x07 0xff 0xf3 +# CHECK: vqshl.u64 q8, q8, #63 +0x70 0x06 0xcf 0xf3 +# CHECK: vqshlu.s8 q8, q8, #7 +0x70 0x06 0xdf 0xf3 +# CHECK: vqshlu.s16 q8, q8, #15 +0x70 0x06 0xff 0xf3 +# CHECK: vqshlu.s32 q8, q8, #31 +0xf0 0x06 0xff 0xf3 +# CHECK: vqshlu.s64 q8, q8, #63 +0xb0 0x05 0x41 0xf2 +# CHECK: vqrshl.s8 d16, d16, d17 +0xb0 0x05 0x51 0xf2 +# CHECK: vqrshl.s16 d16, d16, d17 +0xb0 0x05 0x61 0xf2 +# CHECK: vqrshl.s32 d16, d16, d17 +0xb0 0x05 0x71 0xf2 +# CHECK: vqrshl.s64 d16, d16, d17 +0xb0 0x05 0x41 0xf3 +# CHECK: vqrshl.u8 d16, d16, d17 +0xb0 0x05 0x51 0xf3 +# CHECK: vqrshl.u16 d16, d16, d17 +0xb0 0x05 0x61 0xf3 +# CHECK: vqrshl.u32 d16, d16, d17 +0xb0 0x05 0x71 0xf3 +# CHECK: vqrshl.u64 d16, d16, d17 +0xf0 0x05 0x42 0xf2 +# CHECK: vqrshl.s8 q8, q8, q9 +0xf0 0x05 0x52 0xf2 +# CHECK: vqrshl.s16 q8, q8, q9 +0xf0 0x05 0x62 0xf2 +# CHECK: vqrshl.s32 q8, q8, q9 +0xf0 0x05 0x72 0xf2 +# CHECK: vqrshl.s64 q8, q8, q9 +0xf0 0x05 0x42 0xf3 +# CHECK: vqrshl.u8 q8, q8, q9 +0xf0 0x05 0x52 0xf3 +# CHECK: vqrshl.u16 q8, q8, q9 +0xf0 0x05 0x62 0xf3 +# CHECK: vqrshl.u32 q8, q8, q9 +0xf0 0x05 0x72 0xf3 +# CHECK: vqrshl.u64 q8, q8, q9 +0x30 0x09 0xc8 0xf2 +# CHECK: vqshrn.s16 d16, q8, #8 +0x30 0x09 0xd0 0xf2 +# CHECK: vqshrn.s32 d16, q8, #16 +0x30 0x09 0xe0 0xf2 +# CHECK: vqshrn.s64 d16, q8, #32 +0x30 0x09 0xc8 0xf3 +# CHECK: vqshrn.u16 d16, q8, #8 +0x30 0x09 0xd0 0xf3 +# CHECK: vqshrn.u32 d16, q8, #16 +0x30 0x09 0xe0 0xf3 +# CHECK: vqshrn.u64 d16, q8, #32 +0x30 0x08 0xc8 0xf3 +# CHECK: vqshrun.s16 d16, q8, #8 +0x30 0x08 0xd0 0xf3 +# CHECK: vqshrun.s32 d16, q8, #16 +0x30 0x08 0xe0 0xf3 +# CHECK: vqshrun.s64 d16, q8, #32 +0x70 0x09 0xc8 0xf2 +# CHECK: vqrshrn.s16 d16, q8, #8 +0x70 0x09 0xd0 0xf2 +# CHECK: vqrshrn.s32 d16, q8, #16 +0x70 0x09 0xe0 0xf2 +# CHECK: vqrshrn.s64 d16, q8, #32 +0x70 0x09 0xc8 0xf3 +# CHECK: vqrshrn.u16 d16, q8, #8 +0x70 0x09 0xd0 0xf3 +# CHECK: vqrshrn.u32 d16, q8, #16 +0x70 0x09 0xe0 0xf3 +# CHECK: vqrshrn.u64 d16, q8, #32 +0x70 0x08 0xc8 0xf3 +# CHECK: vqrshrun.s16 d16, q8, #8 +0x70 0x08 0xd0 0xf3 +# CHECK: vqrshrun.s32 d16, q8, #16 +0x70 0x08 0xe0 0xf3 +# CHECK: vqrshrun.s64 d16, q8, #32 + + +0xa1 0x04 0x40 0xf3 +# CHECK: vshl.u8 d16, d17, d16 +0xa1 0x04 0x50 0xf3 +# CHECK: vshl.u16 d16, d17, d16 +0xa1 0x04 0x60 0xf3 +# CHECK: vshl.u32 d16, d17, d16 +0xa1 0x04 0x70 0xf3 +# CHECK: vshl.u64 d16, d17, d16 +0x30 0x05 0xcf 0xf2 +# CHECK: vshl.i8 d16, d16, #7 +0x30 0x05 0xdf 0xf2 +# CHECK: vshl.i16 d16, d16, #15 +0x30 0x05 0xff 0xf2 +# CHECK: vshl.i32 d16, d16, #31 +0xb0 0x05 0xff 0xf2 +# CHECK: vshl.i64 d16, d16, #63 +0xe2 0x04 0x40 0xf3 +# CHECK: vshl.u8 q8, q9, q8 +0xe2 0x04 0x50 0xf3 +# CHECK: vshl.u16 q8, q9, q8 +0xe2 0x04 0x60 0xf3 +# CHECK: vshl.u32 q8, q9, q8 +0xe2 0x04 0x70 0xf3 +# CHECK: vshl.u64 q8, q9, q8 +0x70 0x05 0xcf 0xf2 +# CHECK: vshl.i8 q8, q8, #7 +0x70 0x05 0xdf 0xf2 +# CHECK: vshl.i16 q8, q8, #15 +0x70 0x05 0xff 0xf2 +# CHECK: vshl.i32 q8, q8, #31 +0xf0 0x05 0xff 0xf2 +# CHECK: vshl.i64 q8, q8, #63 +0x30 0x00 0xc9 0xf3 +# CHECK: vshr.u8 d16, d16, #7 +0x30 0x00 0xd1 0xf3 +# CHECK: vshr.u16 d16, d16, #15 +0x30 0x00 0xe1 0xf3 +# CHECK: vshr.u32 d16, d16, #31 +0xb0 0x00 0xc1 0xf3 +# CHECK: vshr.u64 d16, d16, #63 +0x70 0x00 0xc9 0xf3 +# CHECK: vshr.u8 q8, q8, #7 +0x70 0x00 0xd1 0xf3 +# CHECK: vshr.u16 q8, q8, #15 +0x70 0x00 0xe1 0xf3 +# CHECK: vshr.u32 q8, q8, #31 +0xf0 0x00 0xc1 0xf3 +# CHECK: vshr.u64 q8, q8, #63 +0x30 0x00 0xc9 0xf2 +# CHECK: vshr.s8 d16, d16, #7 +0x30 0x00 0xd1 0xf2 +# CHECK: vshr.s16 d16, d16, #15 +0x30 0x00 0xe1 0xf2 +# CHECK: vshr.s32 d16, d16, #31 +0xb0 0x00 0xc1 0xf2 +# CHECK: vshr.s64 d16, d16, #63 +0x70 0x00 0xc9 0xf2 +# CHECK: vshr.s8 q8, q8, #7 +0x70 0x00 0xd1 0xf2 +# CHECK: vshr.s16 q8, q8, #15 +0x70 0x00 0xe1 0xf2 +# CHECK: vshr.s32 q8, q8, #31 +0xf0 0x00 0xc1 0xf2 +# CHECK: vshr.s64 q8, q8, #63 +0x30 0x01 0xc9 0xf3 +# CHECK: vsra.u8 d16, d16, #7 +0x30 0x01 0xd1 0xf3 +# CHECK: vsra.u16 d16, d16, #15 +0x30 0x01 0xe1 0xf3 +# CHECK: vsra.u32 d16, d16, #31 +0xb0 0x01 0xc1 0xf3 +# CHECK: vsra.u64 d16, d16, #63 +0x70 0x01 0xc9 0xf3 +# CHECK: vsra.u8 q8, q8, #7 +0x70 0x01 0xd1 0xf3 +# CHECK: vsra.u16 q8, q8, #15 +0x70 0x01 0xe1 0xf3 +# CHECK: vsra.u32 q8, q8, #31 +0xf0 0x01 0xc1 0xf3 +# CHECK: vsra.u64 q8, q8, #63 +0x30 0x01 0xc9 0xf2 +# CHECK: vsra.s8 d16, d16, #7 +0x30 0x01 0xd1 0xf2 +# CHECK: vsra.s16 d16, d16, #15 +0x30 0x01 0xe1 0xf2 +# CHECK: vsra.s32 d16, d16, #31 +0xb0 0x01 0xc1 0xf2 +# CHECK: vsra.s64 d16, d16, #63 +0x70 0x01 0xc9 0xf2 +# CHECK: vsra.s8 q8, q8, #7 +0x70 0x01 0xd1 0xf2 +# CHECK: vsra.s16 q8, q8, #15 +0x70 0x01 0xe1 0xf2 +# CHECK: vsra.s32 q8, q8, #31 +0xf0 0x01 0xc1 0xf2 +# CHECK: vsra.s64 q8, q8, #63 +0x30 0x04 0xc9 0xf3 +# CHECK: vsri.8 d16, d16, #7 +0x30 0x04 0xd1 0xf3 +# CHECK: vsri.16 d16, d16, #15 +0x30 0x04 0xe1 0xf3 +# CHECK: vsri.32 d16, d16, #31 +0xb0 0x04 0xc1 0xf3 +# CHECK: vsri.64 d16, d16, #63 +0x70 0x04 0xc9 0xf3 +# CHECK: vsri.8 q8, q8, #7 +0x70 0x04 0xd1 0xf3 +# CHECK: vsri.16 q8, q8, #15 +0x70 0x04 0xe1 0xf3 +# CHECK: vsri.32 q8, q8, #31 +0xf0 0x04 0xc1 0xf3 +# CHECK: vsri.64 q8, q8, #63 +0x30 0x05 0xcf 0xf3 +# CHECK: vsli.8 d16, d16, #7 +0x30 0x05 0xdf 0xf3 +# CHECK: vsli.16 d16, d16, #15 +0x30 0x05 0xff 0xf3 +# CHECK: vsli.32 d16, d16, #31 +0xb0 0x05 0xff 0xf3 +# CHECK: vsli.64 d16, d16, #63 +0x70 0x05 0xcf 0xf3 +# CHECK: vsli.8 q8, q8, #7 +0x70 0x05 0xdf 0xf3 +# CHECK: vsli.16 q8, q8, #15 +0x70 0x05 0xff 0xf3 +# CHECK: vsli.32 q8, q8, #31 +0xf0 0x05 0xff 0xf3 +# CHECK: vsli.64 q8, q8, #63 +0x30 0x0a 0xcf 0xf2 +# CHECK: vshll.s8 q8, d16, #7 +0x30 0x0a 0xdf 0xf2 +# CHECK: vshll.s16 q8, d16, #15 +0x30 0x0a 0xff 0xf2 +# CHECK: vshll.s32 q8, d16, #31 +0x30 0x0a 0xcf 0xf3 +# CHECK: vshll.u8 q8, d16, #7 +0x30 0x0a 0xdf 0xf3 +# CHECK: vshll.u16 q8, d16, #15 +0x30 0x0a 0xff 0xf3 +# CHECK: vshll.u32 q8, d16, #31 +0x20 0x03 0xf2 0xf3 +# CHECK: vshll.i8 q8, d16, #8 +0x20 0x03 0xf6 0xf3 +# CHECK: vshll.i16 q8, d16, #16 +0x20 0x03 0xfa 0xf3 +# CHECK: vshll.i32 q8, d16, #32 +0x30 0x08 0xc8 0xf2 +# CHECK: vshrn.i16 d16, q8, #8 +0x30 0x08 0xd0 0xf2 +# CHECK: vshrn.i32 d16, q8, #16 +0x30 0x08 0xe0 0xf2 +# CHECK: vshrn.i64 d16, q8, #32 +0xa1 0x05 0x40 0xf2 +# CHECK: vrshl.s8 d16, d17, d16 +0xa1 0x05 0x50 0xf2 +# CHECK: vrshl.s16 d16, d17, d16 +0xa1 0x05 0x60 0xf2 +# CHECK: vrshl.s32 d16, d17, d16 +0xa1 0x05 0x70 0xf2 +# CHECK: vrshl.s64 d16, d17, d16 +0xa1 0x05 0x40 0xf3 +# CHECK: vrshl.u8 d16, d17, d16 +0xa1 0x05 0x50 0xf3 +# CHECK: vrshl.u16 d16, d17, d16 +0xa1 0x05 0x60 0xf3 +# CHECK: vrshl.u32 d16, d17, d16 +0xa1 0x05 0x70 0xf3 +# CHECK: vrshl.u64 d16, d17, d16 +0xe2 0x05 0x40 0xf2 +# CHECK: vrshl.s8 q8, q9, q8 +0xe2 0x05 0x50 0xf2 +# CHECK: vrshl.s16 q8, q9, q8 +0xe2 0x05 0x60 0xf2 +# CHECK: vrshl.s32 q8, q9, q8 +0xe2 0x05 0x70 0xf2 +# CHECK: vrshl.s64 q8, q9, q8 +0xe2 0x05 0x40 0xf3 +# CHECK: vrshl.u8 q8, q9, q8 +0xe2 0x05 0x50 0xf3 +# CHECK: vrshl.u16 q8, q9, q8 +0xe2 0x05 0x60 0xf3 +# CHECK: vrshl.u32 q8, q9, q8 +0xe2 0x05 0x70 0xf3 +# CHECK: vrshl.u64 q8, q9, q8 +0x30 0x02 0xc8 0xf2 +# CHECK: vrshr.s8 d16, d16, #8 +0x30 0x02 0xd0 0xf2 +# CHECK: vrshr.s16 d16, d16, #16 +0x30 0x02 0xe0 0xf2 +# CHECK: vrshr.s32 d16, d16, #32 +0xb0 0x02 0xc0 0xf2 +# CHECK: vrshr.s64 d16, d16, #64 +0x30 0x02 0xc8 0xf3 +# CHECK: vrshr.u8 d16, d16, #8 +0x30 0x02 0xd0 0xf3 +# CHECK: vrshr.u16 d16, d16, #16 +0x30 0x02 0xe0 0xf3 +# CHECK: vrshr.u32 d16, d16, #32 +0xb0 0x02 0xc0 0xf3 +# CHECK: vrshr.u64 d16, d16, #64 +0x70 0x02 0xc8 0xf2 +# CHECK: vrshr.s8 q8, q8, #8 +0x70 0x02 0xd0 0xf2 +# CHECK: vrshr.s16 q8, q8, #16 +0x70 0x02 0xe0 0xf2 +# CHECK: vrshr.s32 q8, q8, #32 +0xf0 0x02 0xc0 0xf2 +# CHECK: vrshr.s64 q8, q8, #64 +0x70 0x02 0xc8 0xf3 +# CHECK: vrshr.u8 q8, q8, #8 +0x70 0x02 0xd0 0xf3 +# CHECK: vrshr.u16 q8, q8, #16 +0x70 0x02 0xe0 0xf3 +# CHECK: vrshr.u32 q8, q8, #32 +0xf0 0x02 0xc0 0xf3 +# CHECK: vrshr.u64 q8, q8, #64 +0x70 0x08 0xc8 0xf2 +# CHECK: vrshrn.i16 d16, q8, #8 +0x70 0x08 0xd0 0xf2 +# CHECK: vrshrn.i32 d16, q8, #16 +0x70 0x08 0xe0 0xf2 +# CHECK: vrshrn.i64 d16, q8, #32 +0x70 0x09 0xcc 0xf2 +# CHECK: vqrshrn.s16 d16, q8, #4 +0x70 0x09 0xd3 0xf2 +# CHECK: vqrshrn.s32 d16, q8, #13 +0x70 0x09 0xf3 0xf2 +# CHECK: vqrshrn.s64 d16, q8, #13 +0x70 0x09 0xcc 0xf3 +# CHECK: vqrshrn.u16 d16, q8, #4 +0x70 0x09 0xd3 0xf3 +# CHECK: vqrshrn.u32 d16, q8, #13 +0x70 0x09 0xf3 0xf3 +# CHECK: vqrshrn.u64 d16, q8, #13 + + +0x30 0x11 0xc8 0xf2 +# CHECK: vsra.s8 d17, d16, #8 +0x30 0x11 0xd0 0xf2 +# CHECK: vsra.s16 d17, d16, #16 +0x30 0x11 0xe0 0xf2 +# CHECK: vsra.s32 d17, d16, #32 +0xb0 0x11 0xc0 0xf2 +# CHECK: vsra.s64 d17, d16, #64 +0x72 0x01 0xc8 0xf2 +# CHECK: vsra.s8 q8, q9, #8 +0x72 0x01 0xd0 0xf2 +# CHECK: vsra.s16 q8, q9, #16 +0x72 0x01 0xe0 0xf2 +# CHECK: vsra.s32 q8, q9, #32 +0xf2 0x01 0xc0 0xf2 +# CHECK: vsra.s64 q8, q9, #64 +0x30 0x11 0xc8 0xf3 +# CHECK: vsra.u8 d17, d16, #8 +0x30 0x11 0xd0 0xf3 +# CHECK: vsra.u16 d17, d16, #16 +0x30 0x11 0xe0 0xf3 +# CHECK: vsra.u32 d17, d16, #32 +0xb0 0x11 0xc0 0xf3 +# CHECK: vsra.u64 d17, d16, #64 +0x72 0x01 0xc8 0xf3 +# CHECK: vsra.u8 q8, q9, #8 +0x72 0x01 0xd0 0xf3 +# CHECK: vsra.u16 q8, q9, #16 +0x72 0x01 0xe0 0xf3 +# CHECK: vsra.u32 q8, q9, #32 +0xf2 0x01 0xc0 0xf3 +# CHECK: vsra.u64 q8, q9, #64 +0x30 0x13 0xc8 0xf2 +# CHECK: vrsra.s8 d17, d16, #8 +0x30 0x13 0xd0 0xf2 +# CHECK: vrsra.s16 d17, d16, #16 +0x30 0x13 0xe0 0xf2 +# CHECK: vrsra.s32 d17, d16, #32 +0xb0 0x13 0xc0 0xf2 +# CHECK: vrsra.s64 d17, d16, #64 +0x30 0x13 0xc8 0xf3 +# CHECK: vrsra.u8 d17, d16, #8 +0x30 0x13 0xd0 0xf3 +# CHECK: vrsra.u16 d17, d16, #16 +0x30 0x13 0xe0 0xf3 +# CHECK: vrsra.u32 d17, d16, #32 +0xb0 0x13 0xc0 0xf3 +# CHECK: vrsra.u64 d17, d16, #64 +0x72 0x03 0xc8 0xf2 +# CHECK: vrsra.s8 q8, q9, #8 +0x72 0x03 0xd0 0xf2 +# CHECK: vrsra.s16 q8, q9, #16 +0x72 0x03 0xe0 0xf2 +# CHECK: vrsra.s32 q8, q9, #32 +0xf2 0x03 0xc0 0xf2 +# CHECK: vrsra.s64 q8, q9, #64 +0x72 0x03 0xc8 0xf3 +# CHECK: vrsra.u8 q8, q9, #8 +0x72 0x03 0xd0 0xf3 +# CHECK: vrsra.u16 q8, q9, #16 +0x72 0x03 0xe0 0xf3 +# CHECK: vrsra.u32 q8, q9, #32 +0xf2 0x03 0xc0 0xf3 +# CHECK: vrsra.u64 q8, q9, #64 +0x30 0x15 0xcf 0xf3 +# CHECK: vsli.8 d17, d16, #7 +0x30 0x15 0xdf 0xf3 +# CHECK: vsli.16 d17, d16, #15 +0x30 0x15 0xff 0xf3 +# CHECK: vsli.32 d17, d16, #31 +0xb0 0x15 0xff 0xf3 +# CHECK: vsli.64 d17, d16, #63 +0x70 0x25 0xcf 0xf3 +# CHECK: vsli.8 q9, q8, #7 +0x70 0x25 0xdf 0xf3 +# CHECK: vsli.16 q9, q8, #15 +0x70 0x25 0xff 0xf3 +# CHECK: vsli.32 q9, q8, #31 +0xf0 0x25 0xff 0xf3 +# CHECK: vsli.64 q9, q8, #63 +0x30 0x14 0xc8 0xf3 +# CHECK: vsri.8 d17, d16, #8 +0x30 0x14 0xd0 0xf3 +# CHECK: vsri.16 d17, d16, #16 +0x30 0x14 0xe0 0xf3 +# CHECK: vsri.32 d17, d16, #32 +0xb0 0x14 0xc0 0xf3 +# CHECK: vsri.64 d17, d16, #64 +0x70 0x24 0xc8 0xf3 +# CHECK: vsri.8 q9, q8, #8 +0x70 0x24 0xd0 0xf3 +# CHECK: vsri.16 q9, q8, #16 +0x70 0x24 0xe0 0xf3 +# CHECK: vsri.32 q9, q8, #32 +0xf0 0x24 0xc0 0xf3 +# CHECK: vsri.64 q9, q8, #64 + + +0xa0 0x03 0xf1 0xf2 +# CHECK: vext.8 d16, d17, d16, #3 +0xa0 0x05 0xf1 0xf2 +# CHECK: vext.8 d16, d17, d16, #5 +0xe0 0x03 0xf2 0xf2 +# CHECK: vext.8 q8, q9, q8, #3 +0xe0 0x07 0xf2 0xf2 +# CHECK: vext.8 q8, q9, q8, #7 +0xa0 0x06 0xf1 0xf2 +# CHECK: vext.16 d16, d17, d16, #3 +0xe0 0x0c 0xf2 0xf2 +# CHECK: vext.32 q8, q9, q8, #3 +0xa0 0x10 0xf2 0xf3 +# CHECK: vtrn.8 d17, d16 +0xa0 0x10 0xf6 0xf3 +# CHECK: vtrn.16 d17, d16 +0xa0 0x10 0xfa 0xf3 +# CHECK: vtrn.32 d17, d16 +0xe0 0x20 0xf2 0xf3 +# CHECK: vtrn.8 q9, q8 +0xe0 0x20 0xf6 0xf3 +# CHECK: vtrn.16 q9, q8 +0xe0 0x20 0xfa 0xf3 +# CHECK: vtrn.32 q9, q8 +0x20 0x11 0xf2 0xf3 +# CHECK: vuzp.8 d17, d16 +0x20 0x11 0xf6 0xf3 +# CHECK: vuzp.16 d17, d16 +0x60 0x21 0xf2 0xf3 +# CHECK: vuzp.8 q9, q8 +0x60 0x21 0xf6 0xf3 +# CHECK: vuzp.16 q9, q8 +0x60 0x21 0xfa 0xf3 +# CHECK: vuzp.32 q9, q8 +0xa0 0x11 0xf2 0xf3 +# CHECK: vzip.8 d17, d16 +0xa0 0x11 0xf6 0xf3 +# CHECK: vzip.16 d17, d16 +0xe0 0x21 0xf2 0xf3 +# CHECK: vzip.8 q9, q8 +0xe0 0x21 0xf6 0xf3 +# CHECK: vzip.16 q9, q8 +0xe0 0x21 0xfa 0xf3 +# CHECK: vzip.32 q9, q8 + + +0xa0 0x08 0x41 0xf3 +# CHECK: vsub.i8 d16, d17, d16 +0xa0 0x08 0x51 0xf3 +# CHECK: vsub.i16 d16, d17, d16 +0xa0 0x08 0x61 0xf3 +# CHECK: vsub.i32 d16, d17, d16 +0xa0 0x08 0x71 0xf3 +# CHECK: vsub.i64 d16, d17, d16 +0xa1 0x0d 0x60 0xf2 +# CHECK: vsub.f32 d16, d16, d17 +0xe2 0x08 0x40 0xf3 +# CHECK: vsub.i8 q8, q8, q9 +0xe2 0x08 0x50 0xf3 +# CHECK: vsub.i16 q8, q8, q9 +0xe2 0x08 0x60 0xf3 +# CHECK: vsub.i32 q8, q8, q9 +0xe2 0x08 0x70 0xf3 +# CHECK: vsub.i64 q8, q8, q9 +0xe2 0x0d 0x60 0xf2 +# CHECK: vsub.f32 q8, q8, q9 +0xa0 0x02 0xc1 0xf2 +# CHECK: vsubl.s8 q8, d17, d16 +0xa0 0x02 0xd1 0xf2 +# CHECK: vsubl.s16 q8, d17, d16 +0xa0 0x02 0xe1 0xf2 +# CHECK: vsubl.s32 q8, d17, d16 +0xa0 0x02 0xc1 0xf3 +# CHECK: vsubl.u8 q8, d17, d16 +0xa0 0x02 0xd1 0xf3 +# CHECK: vsubl.u16 q8, d17, d16 +0xa0 0x02 0xe1 0xf3 +# CHECK: vsubl.u32 q8, d17, d16 +0xa2 0x03 0xc0 0xf2 +# CHECK: vsubw.s8 q8, q8, d18 +0xa2 0x03 0xd0 0xf2 +# CHECK: vsubw.s16 q8, q8, d18 +0xa2 0x03 0xe0 0xf2 +# CHECK: vsubw.s32 q8, q8, d18 +0xa2 0x03 0xc0 0xf3 +# CHECK: vsubw.u8 q8, q8, d18 +0xa2 0x03 0xd0 0xf3 +# CHECK: vsubw.u16 q8, q8, d18 +0xa2 0x03 0xe0 0xf3 +# CHECK: vsubw.u32 q8, q8, d18 +0xa1 0x02 0x40 0xf2 +# CHECK: vhsub.s8 d16, d16, d17 +0xa1 0x02 0x50 0xf2 +# CHECK: vhsub.s16 d16, d16, d17 +0xa1 0x02 0x60 0xf2 +# CHECK: vhsub.s32 d16, d16, d17 +0xa1 0x02 0x40 0xf3 +# CHECK: vhsub.u8 d16, d16, d17 +0xa1 0x02 0x50 0xf3 +# CHECK: vhsub.u16 d16, d16, d17 +0xa1 0x02 0x60 0xf3 +# CHECK: vhsub.u32 d16, d16, d17 +0xe2 0x02 0x40 0xf2 +# CHECK: vhsub.s8 q8, q8, q9 +0xe2 0x02 0x50 0xf2 +# CHECK: vhsub.s16 q8, q8, q9 +0xe2 0x02 0x60 0xf2 +# CHECK: vhsub.s32 q8, q8, q9 +0xb1 0x02 0x40 0xf2 +# CHECK: vqsub.s8 d16, d16, d17 +0xb1 0x02 0x50 0xf2 +# CHECK: vqsub.s16 d16, d16, d17 +0xb1 0x02 0x60 0xf2 +# CHECK: vqsub.s32 d16, d16, d17 +0xb1 0x02 0x70 0xf2 +# CHECK: vqsub.s64 d16, d16, d17 +0xb1 0x02 0x40 0xf3 +# CHECK: vqsub.u8 d16, d16, d17 +0xb1 0x02 0x50 0xf3 +# CHECK: vqsub.u16 d16, d16, d17 +0xb1 0x02 0x60 0xf3 +# CHECK: vqsub.u32 d16, d16, d17 +0xb1 0x02 0x70 0xf3 +# CHECK: vqsub.u64 d16, d16, d17 +0xf2 0x02 0x40 0xf2 +# CHECK: vqsub.s8 q8, q8, q9 +0xf2 0x02 0x50 0xf2 +# CHECK: vqsub.s16 q8, q8, q9 +0xf2 0x02 0x60 0xf2 +# CHECK: vqsub.s32 q8, q8, q9 +0xf2 0x02 0x70 0xf2 +# CHECK: vqsub.s64 q8, q8, q9 +0xf2 0x02 0x40 0xf3 +# CHECK: vqsub.u8 q8, q8, q9 +0xf2 0x02 0x50 0xf3 +# CHECK: vqsub.u16 q8, q8, q9 +0xf2 0x02 0x60 0xf3 +# CHECK: vqsub.u32 q8, q8, q9 +0xf2 0x02 0x70 0xf3 +# CHECK: vqsub.u64 q8, q8, q9 +0xa2 0x06 0xc0 0xf2 +# CHECK: vsubhn.i16 d16, q8, q9 +0xa2 0x06 0xd0 0xf2 +# CHECK: vsubhn.i32 d16, q8, q9 +0xa2 0x06 0xe0 0xf2 +# CHECK: vsubhn.i64 d16, q8, q9 +0xa2 0x06 0xc0 0xf3 +# CHECK: vrsubhn.i16 d16, q8, q9 +0xa2 0x06 0xd0 0xf3 +# CHECK: vrsubhn.i32 d16, q8, q9 +0xa2 0x06 0xe0 0xf3 +# CHECK: vrsubhn.i64 d16, q8, q9 + + + +0xa0 0x08 0xf1 0xf3 +# CHECK: vtbl.8 d16, {d17}, d16 +0xa2 0x09 0xf0 0xf3 +# CHECK: vtbl.8 d16, {d16, d17}, d18 +0xa4 0x0a 0xf0 0xf3 +# CHECK: vtbl.8 d16, {d16, d17, d18}, d20 +0xa4 0x0b 0xf0 0xf3 +# CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 +0xe1 0x28 0xf0 0xf3 +# CHECK: vtbx.8 d18, {d16}, d17 +0xe2 0x39 0xf0 0xf3 +# CHECK: vtbx.8 d19, {d16, d17}, d18 +0xe5 0x4a 0xf0 0xf3 +# CHECK: vtbx.8 d20, {d16, d17, d18}, d21 +0xe5 0x4b 0xf0 0xf3 +# CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 + + + +0x1f 0x07 0x60 0xf4 +# CHECK: vld1.8 {d16}, [r0, :64] +0x4f 0x07 0x60 0xf4 +# CHECK: vld1.16 {d16}, [r0] +0x8f 0x07 0x60 0xf4 +# CHECK: vld1.32 {d16}, [r0] +0xcf 0x07 0x60 0xf4 +# CHECK: vld1.64 {d16}, [r0] +0x1f 0x0a 0x60 0xf4 +# CHECK: vld1.8 {d16, d17}, [r0, :64] +0x6f 0x0a 0x60 0xf4 +# CHECK: vld1.16 {d16, d17}, [r0, :128] +0x8f 0x0a 0x60 0xf4 +# CHECK: vld1.32 {d16, d17}, [r0] +0xcf 0x0a 0x60 0xf4 +# CHECK: vld1.64 {d16, d17}, [r0] + +0x1f 0x08 0x60 0xf4 +# CHECK: vld2.8 {d16, d17}, [r0, :64] +0x6f 0x08 0x60 0xf4 +# CHECK: vld2.16 {d16, d17}, [r0, :128] +0x8f 0x08 0x60 0xf4 +# CHECK: vld2.32 {d16, d17}, [r0] +0x1f 0x03 0x60 0xf4 +# CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] +0x6f 0x03 0x60 0xf4 +# CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] +0xbf 0x03 0x60 0xf4 +# CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] + +0x1f 0x04 0x60 0xf4 +# CHECK: vld3.8 {d16, d17, d18}, [r0, :64] +0x4f 0x04 0x60 0xf4 +# CHECK: vld3.16 {d16, d17, d18}, [r0] +0x8f 0x04 0x60 0xf4 +# CHECK: vld3.32 {d16, d17, d18}, [r0] +0x1d 0x05 0x60 0xf4 +# CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! +0x1d 0x15 0x60 0xf4 +# CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! +0x4d 0x05 0x60 0xf4 +# CHECK: vld3.16 {d16, d18, d20}, [r0]! +0x4d 0x15 0x60 0xf4 +# CHECK: vld3.16 {d17, d19, d21}, [r0]! +0x8d 0x05 0x60 0xf4 +# CHECK: vld3.32 {d16, d18, d20}, [r0]! +0x8d 0x15 0x60 0xf4 +# CHECK: vld3.32 {d17, d19, d21}, [r0]! + +0x1f 0x00 0x60 0xf4 +# CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] +0x6f 0x00 0x60 0xf4 +# CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] +0xbf 0x00 0x60 0xf4 +# CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] +0x3d 0x01 0x60 0xf4 +# CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! +0x3d 0x11 0x60 0xf4 +# CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! +0x4d 0x01 0x60 0xf4 +# CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! +0x4d 0x11 0x60 0xf4 +# CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! +0x8d 0x01 0x60 0xf4 +# CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! +0x8d 0x11 0x60 0xf4 +# CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! + +0x6f 0x00 0xe0 0xf4 +# CHECK: vld1.8 {d16[3]}, [r0] +0x9f 0x04 0xe0 0xf4 +# CHECK: vld1.16 {d16[2]}, [r0, :16] +0xbf 0x08 0xe0 0xf4 +# CHECK: vld1.32 {d16[1]}, [r0, :32] + +0x3f 0x01 0xe0 0xf4 +# CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] +0x5f 0x05 0xe0 0xf4 +# CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] +0x8f 0x09 0xe0 0xf4 +# CHECK: vld2.32 {d16[1], d17[1]}, [r0] +0x6f 0x15 0xe0 0xf4 +# CHECK: vld2.16 {d17[1], d19[1]}, [r0] +0x5f 0x19 0xe0 0xf4 +# CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] + +0x2f 0x02 0xe0 0xf4 +# CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] +0x4f 0x06 0xe0 0xf4 +# CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] +0x8f 0x0a 0xe0 0xf4 +# CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0] +0x6f 0x06 0xe0 0xf4 +# CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] +0xcf 0x1a 0xe0 0xf4 +# CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] + +0x3f 0x03 0xe0 0xf4 +# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +0x4f 0x07 0xe0 0xf4 +# CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +0xaf 0x0b 0xe0 0xf4 +# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +0x7f 0x07 0xe0 0xf4 +# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +0x4f 0x1b 0xe0 0xf4 +# CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + + + +0x1f 0x07 0x40 0xf4 +# CHECK: vst1.8 {d16}, [r0, :64] +0x4f 0x07 0x40 0xf4 +# CHECK: vst1.16 {d16}, [r0] +0x8f 0x07 0x40 0xf4 +# CHECK: vst1.32 {d16}, [r0] +0xcf 0x07 0x40 0xf4 +# CHECK: vst1.64 {d16}, [r0] +0x1f 0x0a 0x40 0xf4 +# CHECK: vst1.8 {d16, d17}, [r0, :64] +0x6f 0x0a 0x40 0xf4 +# CHECK: vst1.16 {d16, d17}, [r0, :128] +0x8f 0x0a 0x40 0xf4 +# CHECK: vst1.32 {d16, d17}, [r0] +0xcf 0x0a 0x40 0xf4 +# CHECK: vst1.64 {d16, d17}, [r0] + +0x1f 0x08 0x40 0xf4 +# CHECK: vst2.8 {d16, d17}, [r0, :64] +0x6f 0x08 0x40 0xf4 +# CHECK: vst2.16 {d16, d17}, [r0, :128] +0x8f 0x08 0x40 0xf4 +# CHECK: vst2.32 {d16, d17}, [r0] +0x1f 0x03 0x40 0xf4 +# CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] +0x6f 0x03 0x40 0xf4 +# CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] +0xbf 0x03 0x40 0xf4 +# CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] + +0x1f 0x04 0x40 0xf4 +# CHECK: vst3.8 {d16, d17, d18}, [r0, :64] +0x4f 0x04 0x40 0xf4 +# CHECK: vst3.16 {d16, d17, d18}, [r0] +0x8f 0x04 0x40 0xf4 +# CHECK: vst3.32 {d16, d17, d18}, [r0] +0x1d 0x05 0x40 0xf4 +# CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! +0x1d 0x15 0x40 0xf4 +# CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! +0x4d 0x05 0x40 0xf4 +# CHECK: vst3.16 {d16, d18, d20}, [r0]! +0x4d 0x15 0x40 0xf4 +# CHECK: vst3.16 {d17, d19, d21}, [r0]! +0x8d 0x05 0x40 0xf4 +# CHECK: vst3.32 {d16, d18, d20}, [r0]! +0x8d 0x15 0x40 0xf4 +# CHECK: vst3.32 {d17, d19, d21}, [r0]! + +0x1f 0x00 0x40 0xf4 +# CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] +0x6f 0x00 0x40 0xf4 +# CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] +0x3d 0x01 0x40 0xf4 +# CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! +0x3d 0x11 0x40 0xf4 +# CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! +0x4d 0x01 0x40 0xf4 +# CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! +0x4d 0x11 0x40 0xf4 +# CHECK: vst4.16 {d17, d19, d21, d23}, [r0]! +0x8d 0x01 0x40 0xf4 +# CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! +0x8d 0x11 0x40 0xf4 +# CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! + +0x3f 0x01 0xc0 0xf4 +# CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] +0x5f 0x05 0xc0 0xf4 +# CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] +0x8f 0x09 0xc0 0xf4 +# CHECK: vst2.32 {d16[1], d17[1]}, [r0] +0x6f 0x15 0xc0 0xf4 +# CHECK: vst2.16 {d17[1], d19[1]}, [r0] +0x5f 0x19 0xc0 0xf4 +# CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] + +0x2f 0x02 0xc0 0xf4 +# CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] +0x4f 0x06 0xc0 0xf4 +# CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] +0x8f 0x0a 0xc0 0xf4 +# CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0] +0xaf 0x16 0xc0 0xf4 +# CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] +0x4f 0x0a 0xc0 0xf4 +# CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] + +0x3f 0x03 0xc0 0xf4 +# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +0x4f 0x07 0xc0 0xf4 +# CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +0xaf 0x0b 0xc0 0xf4 +# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +0xff 0x17 0xc0 0xf4 +# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +0x4f 0x1b 0xc0 0xf4 +# CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +0x0 0xc 0xa0 0xf4 +# CHECK: vld1.8 {d0[]}, [r0], r0 +0x0d 0x03 0x80 0xf4 +# CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]! + +0x3d 0x2a 0x5e 0x6c +# CHECK: vmovvs r2, lr, s29, s30 + +0xe9 0x1a 0xb2 0x4e +# CHECK: vcvttmi.f32.f16 s2, s19 diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt new file mode 100644 index 0000000..577703c --- /dev/null +++ b/test/MC/Disassembler/ARM/neont2.txt @@ -0,0 +1,1586 @@ +# RUN: llvm-mc -triple thumbv7-unknown-unknown -disassemble -mattr +fp16 < %s | FileCheck %s + +0xf1 0xff 0x20 0x03 +# CHECK: vabs.s8 d16, d16 +0xf5 0xff 0x20 0x03 +# CHECK: vabs.s16 d16, d16 +0xf9 0xff 0x20 0x03 +# CHECK: vabs.s32 d16, d16 +0xf9 0xff 0x20 0x07 +# CHECK: vabs.f32 d16, d16 +0xf1 0xff 0x60 0x03 +# CHECK: vabs.s8 q8, q8 +0xf5 0xff 0x60 0x03 +# CHECK: vabs.s16 q8, q8 +0xf9 0xff 0x60 0x03 +# CHECK: vabs.s32 q8, q8 +0xf9 0xff 0x60 0x07 +# CHECK: vabs.f32 q8, q8 + +0xf0 0xff 0x20 0x07 +# CHECK: vqabs.s8 d16, d16 +0xf4 0xff 0x20 0x07 +# CHECK: vqabs.s16 d16, d16 +0xf8 0xff 0x20 0x07 +# CHECK: vqabs.s32 d16, d16 +0xf0 0xff 0x60 0x07 +# CHECK: vqabs.s8 q8, q8 +0xf4 0xff 0x60 0x07 +# CHECK: vqabs.s16 q8, q8 +0xf8 0xff 0x60 0x07 +# CHECK: vqabs.s32 q8, q8 + +0x40 0xef 0xa1 0x07 +# CHECK: vabd.s8 d16, d16, d17 +0x50 0xef 0xa1 0x07 +# CHECK: vabd.s16 d16, d16, d17 +0x60 0xef 0xa1 0x07 +# CHECK: vabd.s32 d16, d16, d17 +0x40 0xff 0xa1 0x07 +# CHECK: vabd.u8 d16, d16, d17 +0x50 0xff 0xa1 0x07 +# CHECK: vabd.u16 d16, d16, d17 +0x60 0xff 0xa1 0x07 +# CHECK: vabd.u32 d16, d16, d17 +0x60 0xff 0xa1 0x0d +# CHECK: vabd.f32 d16, d16, d17 +0x40 0xef 0xe2 0x07 +# CHECK: vabd.s8 q8, q8, q9 +0x50 0xef 0xe2 0x07 +# CHECK: vabd.s16 q8, q8, q9 +0x60 0xef 0xe2 0x07 +# CHECK: vabd.s32 q8, q8, q9 +0x40 0xff 0xe2 0x07 +# CHECK: vabd.u8 q8, q8, q9 +0x50 0xff 0xe2 0x07 +# CHECK: vabd.u16 q8, q8, q9 +0x60 0xff 0xe2 0x07 +# CHECK: vabd.u32 q8, q8, q9 +0x60 0xff 0xe2 0x0d +# CHECK: vabd.f32 q8, q8, q9 + +0xc0 0xef 0xa1 0x07 +# CHECK: vabdl.s8 q8, d16, d17 +0xd0 0xef 0xa1 0x07 +# CHECK: vabdl.s16 q8, d16, d17 +0xe0 0xef 0xa1 0x07 +# CHECK: vabdl.s32 q8, d16, d17 +0xc0 0xff 0xa1 0x07 +# CHECK: vabdl.u8 q8, d16, d17 +0xd0 0xff 0xa1 0x07 +# CHECK: vabdl.u16 q8, d16, d17 +0xe0 0xff 0xa1 0x07 +# CHECK: vabdl.u32 q8, d16, d17 + +0x42 0xef 0xb1 0x07 +# CHECK: vaba.s8 d16, d18, d17 +0x52 0xef 0xb1 0x07 +# CHECK: vaba.s16 d16, d18, d17 +0x62 0xef 0xb1 0x07 +# CHECK: vaba.s32 d16, d18, d17 +0x42 0xff 0xb1 0x07 +# CHECK: vaba.u8 d16, d18, d17 +0x52 0xff 0xb1 0x07 +# CHECK: vaba.u16 d16, d18, d17 +0x62 0xff 0xb1 0x07 +# CHECK: vaba.u32 d16, d18, d17 +0x40 0xef 0xf4 0x27 +# CHECK: vaba.s8 q9, q8, q10 +0x50 0xef 0xf4 0x27 +# CHECK: vaba.s16 q9, q8, q10 +0x60 0xef 0xf4 0x27 +# CHECK: vaba.s32 q9, q8, q10 +0x40 0xff 0xf4 0x27 +# CHECK: vaba.u8 q9, q8, q10 +0x50 0xff 0xf4 0x27 +# CHECK: vaba.u16 q9, q8, q10 +0x60 0xff 0xf4 0x27 +# CHECK: vaba.u32 q9, q8, q10 + +0xc3 0xef 0xa2 0x05 +# CHECK: vabal.s8 q8, d19, d18 +0xd3 0xef 0xa2 0x05 +# CHECK: vabal.s16 q8, d19, d18 +0xe3 0xef 0xa2 0x05 +# CHECK: vabal.s32 q8, d19, d18 +0xc3 0xff 0xa2 0x05 +# CHECK: vabal.u8 q8, d19, d18 +0xd3 0xff 0xa2 0x05 +# CHECK: vabal.u16 q8, d19, d18 +0xe3 0xff 0xa2 0x05 +# CHECK: vabal.u32 q8, d19, d18 + +0x41 0xef 0xa0 0x08 +# CHECK: vadd.i8 d16, d17, d16 +0x51 0xef 0xa0 0x08 +# CHECK: vadd.i16 d16, d17, d16 +0x71 0xef 0xa0 0x08 +# CHECK: vadd.i64 d16, d17, d16 +0x61 0xef 0xa0 0x08 +# CHECK: vadd.i32 d16, d17, d16 +0x40 0xef 0xa1 0x0d +# CHECK: vadd.f32 d16, d16, d17 +0x40 0xef 0xe2 0x0d +# CHECK: vadd.f32 q8, q8, q9 + +0xc1 0xef 0xa0 0x00 +# CHECK: vaddl.s8 q8, d17, d16 +0xd1 0xef 0xa0 0x00 +# CHECK: vaddl.s16 q8, d17, d16 +0xe1 0xef 0xa0 0x00 +# CHECK: vaddl.s32 q8, d17, d16 +0xc1 0xff 0xa0 0x00 +# CHECK: vaddl.u8 q8, d17, d16 +0xd1 0xff 0xa0 0x00 +# CHECK: vaddl.u16 q8, d17, d16 +0xe1 0xff 0xa0 0x00 +# CHECK: vaddl.u32 q8, d17, d16 + +0xc0 0xef 0xa2 0x01 +# CHECK: vaddw.s8 q8, q8, d18 +0xd0 0xef 0xa2 0x01 +# CHECK: vaddw.s16 q8, q8, d18 +0xe0 0xef 0xa2 0x01 +# CHECK: vaddw.s32 q8, q8, d18 +0xc0 0xff 0xa2 0x01 +# CHECK: vaddw.u8 q8, q8, d18 +0xd0 0xff 0xa2 0x01 +# CHECK: vaddw.u16 q8, q8, d18 +0xe0 0xff 0xa2 0x01 +# CHECK: vaddw.u32 q8, q8, d18 + +0x40 0xef 0xa1 0x00 +# CHECK: vhadd.s8 d16, d16, d17 +0x50 0xef 0xa1 0x00 +# CHECK: vhadd.s16 d16, d16, d17 +0x60 0xef 0xa1 0x00 +# CHECK: vhadd.s32 d16, d16, d17 +0x40 0xff 0xa1 0x00 +# CHECK: vhadd.u8 d16, d16, d17 +0x50 0xff 0xa1 0x00 +# CHECK: vhadd.u16 d16, d16, d17 +0x60 0xff 0xa1 0x00 +# CHECK: vhadd.u32 d16, d16, d17 +0x40 0xef 0xe2 0x00 +# CHECK: vhadd.s8 q8, q8, q9 +0x50 0xef 0xe2 0x00 +# CHECK: vhadd.s16 q8, q8, q9 +0x60 0xef 0xe2 0x00 +# CHECK: vhadd.s32 q8, q8, q9 +0x40 0xff 0xe2 0x00 +# CHECK: vhadd.u8 q8, q8, q9 +0x50 0xff 0xe2 0x00 +# CHECK: vhadd.u16 q8, q8, q9 +0x60 0xff 0xe2 0x00 +# CHECK: vhadd.u32 q8, q8, q9 + +0x40 0xef 0xa1 0x01 +# CHECK: vrhadd.s8 d16, d16, d17 +0x50 0xef 0xa1 0x01 +# CHECK: vrhadd.s16 d16, d16, d17 +0x60 0xef 0xa1 0x01 +# CHECK: vrhadd.s32 d16, d16, d17 +0x40 0xff 0xa1 0x01 +# CHECK: vrhadd.u8 d16, d16, d17 +0x50 0xff 0xa1 0x01 +# CHECK: vrhadd.u16 d16, d16, d17 +0x60 0xff 0xa1 0x01 +# CHECK: vrhadd.u32 d16, d16, d17 +0x40 0xef 0xe2 0x01 +# CHECK: vrhadd.s8 q8, q8, q9 +0x50 0xef 0xe2 0x01 +# CHECK: vrhadd.s16 q8, q8, q9 +0x60 0xef 0xe2 0x01 +# CHECK: vrhadd.s32 q8, q8, q9 +0x40 0xff 0xe2 0x01 +# CHECK: vrhadd.u8 q8, q8, q9 +0x50 0xff 0xe2 0x01 +# CHECK: vrhadd.u16 q8, q8, q9 +0x60 0xff 0xe2 0x01 +# CHECK: vrhadd.u32 q8, q8, q9 + +0x40 0xef 0xb1 0x00 +# CHECK: vqadd.s8 d16, d16, d17 +0x50 0xef 0xb1 0x00 +# CHECK: vqadd.s16 d16, d16, d17 +0x60 0xef 0xb1 0x00 +# CHECK: vqadd.s32 d16, d16, d17 +0x70 0xef 0xb1 0x00 +# CHECK: vqadd.s64 d16, d16, d17 +0x40 0xff 0xb1 0x00 +# CHECK: vqadd.u8 d16, d16, d17 +0x50 0xff 0xb1 0x00 +# CHECK: vqadd.u16 d16, d16, d17 +0x60 0xff 0xb1 0x00 +# CHECK: vqadd.u32 d16, d16, d17 +0x70 0xff 0xb1 0x00 +# CHECK: vqadd.u64 d16, d16, d17 +0x40 0xef 0xf2 0x00 +# CHECK: vqadd.s8 q8, q8, q9 +0x50 0xef 0xf2 0x00 +# CHECK: vqadd.s16 q8, q8, q9 +0x60 0xef 0xf2 0x00 +# CHECK: vqadd.s32 q8, q8, q9 +0x70 0xef 0xf2 0x00 +# CHECK: vqadd.s64 q8, q8, q9 +0x40 0xff 0xf2 0x00 +# CHECK: vqadd.u8 q8, q8, q9 +0x50 0xff 0xf2 0x00 +# CHECK: vqadd.u16 q8, q8, q9 +0x60 0xff 0xf2 0x00 +# CHECK: vqadd.u32 q8, q8, q9 +0x70 0xff 0xf2 0x00 +# CHECK: vqadd.u64 q8, q8, q9 + +0xc0 0xef 0xa2 0x04 +# CHECK: vaddhn.i16 d16, q8, q9 +0xd0 0xef 0xa2 0x04 +# CHECK: vaddhn.i32 d16, q8, q9 +0xe0 0xef 0xa2 0x04 +# CHECK: vaddhn.i64 d16, q8, q9 +0xc0 0xff 0xa2 0x04 +# CHECK: vraddhn.i16 d16, q8, q9 +0xd0 0xff 0xa2 0x04 +# CHECK: vraddhn.i32 d16, q8, q9 +0xe0 0xff 0xa2 0x04 +# CHECK: vraddhn.i64 d16, q8, q9 + +0xf0 0xff 0x20 0x05 +# CHECK: vcnt.8 d16, d16 +0xf0 0xff 0x60 0x05 +# CHECK: vcnt.8 q8, q8 +0xf0 0xff 0xa0 0x04 +# CHECK: vclz.i8 d16, d16 +0xf4 0xff 0xa0 0x04 +# CHECK: vclz.i16 d16, d16 +0xf8 0xff 0xa0 0x04 +# CHECK: vclz.i32 d16, d16 +0xf0 0xff 0xe0 0x04 +# CHECK: vclz.i8 q8, q8 +0xf4 0xff 0xe0 0x04 +# CHECK: vclz.i16 q8, q8 +0xf8 0xff 0xe0 0x04 +# CHECK: vclz.i32 q8, q8 +0xf0 0xff 0x20 0x04 +# CHECK: vcls.s8 d16, d16 +0xf4 0xff 0x20 0x04 +# CHECK: vcls.s16 d16, d16 +0xf8 0xff 0x20 0x04 +# CHECK: vcls.s32 d16, d16 +0xf0 0xff 0x60 0x04 +# CHECK: vcls.s8 q8, q8 +0xf4 0xff 0x60 0x04 +# CHECK: vcls.s16 q8, q8 +0xf8 0xff 0x60 0x04 +# CHECK: vcls.s32 q8, q8 + + +0x41 0xef 0xb0 0x01 +# CHECK: vand d16, d17, d16 +0x40 0xef 0xf2 0x01 +# CHECK: vand q8, q8, q9 + +0x41 0xff 0xb0 0x01 +# CHECK: veor d16, d17, d16 +0x40 0xff 0xf2 0x01 +# CHECK: veor q8, q8, q9 + +0x61 0xef 0xb0 0x01 +# CHECK: vorr d16, d17, d16 +0x60 0xef 0xf2 0x01 +# CHECK: vorr q8, q8, q9 +0xc0 0xef 0x11 0x07 +# CHECK: vorr.i32 d16, #0x1000000 +0xc0 0xef 0x51 0x07 +# CHECK: vorr.i32 q8, #0x1000000 +0xc0 0xef 0x50 0x01 +# CHECK: vorr.i32 q8, #0x0 + +0x51 0xef 0xb0 0x01 +# CHECK: vbic d16, d17, d16 +0x50 0xef 0xf2 0x01 +# CHECK: vbic q8, q8, q9 +0xc7 0xff 0x3f 0x07 +# CHECK: vbic.i32 d16, #0xFF000000 +0xc7 0xff 0x7f 0x07 +# CHECK: vbic.i32 q8, #0xFF000000 + +0x71 0xef 0xb0 0x01 +# CHECK: vorn d16, d17, d16 +0x70 0xef 0xf2 0x01 +# CHECK: vorn q8, q8, q9 + +0xf0 0xff 0xa0 0x05 +# CHECK: vmvn d16, d16 +0xf0 0xff 0xe0 0x05 +# CHECK: vmvn q8, q8 + +0x51 0xff 0xb0 0x21 +# CHECK: vbsl d18, d17, d16 +0x54 0xff 0xf2 0x01 +# CHECK: vbsl q8, q10, q9 + +0xfb 0xff 0x20 0x07 +# CHECK: vcvt.s32.f32 d16, d16 +0xfb 0xff 0xa0 0x07 +# CHECK: vcvt.u32.f32 d16, d16 +0xfb 0xff 0x20 0x06 +# CHECK: vcvt.f32.s32 d16, d16 +0xfb 0xff 0xa0 0x06 +# CHECK: vcvt.f32.u32 d16, d16 +0xfb 0xff 0x60 0x07 +# CHECK: vcvt.s32.f32 q8, q8 +0xfb 0xff 0xe0 0x07 +# CHECK: vcvt.u32.f32 q8, q8 +0xfb 0xff 0x60 0x06 +# CHECK: vcvt.f32.s32 q8, q8 +0xfb 0xff 0xe0 0x06 +# CHECK: vcvt.f32.u32 q8, q8 +0xff 0xef 0x30 0x0f +# CHECK: vcvt.s32.f32 d16, d16, #1 +0xff 0xff 0x30 0x0f +# CHECK: vcvt.u32.f32 d16, d16, #1 +0xff 0xef 0x30 0x0e +# CHECK: vcvt.f32.s32 d16, d16, #1 +0xff 0xff 0x30 0x0e +# CHECK: vcvt.f32.u32 d16, d16, #1 +0xff 0xef 0x70 0x0f +# CHECK: vcvt.s32.f32 q8, q8, #1 +0xff 0xff 0x70 0x0f +# CHECK: vcvt.u32.f32 q8, q8, #1 +0xff 0xef 0x70 0x0e +# CHECK: vcvt.f32.s32 q8, q8, #1 +0xff 0xff 0x70 0x0e +# CHECK: vcvt.f32.u32 q8, q8, #1 +0xfb 0xff 0x20 0x07 +# CHECK: vcvt.s32.f32 d16, d16 +0xfb 0xff 0xa0 0x07 +# CHECK: vcvt.u32.f32 d16, d16 +0xfb 0xff 0x20 0x06 +# CHECK: vcvt.f32.s32 d16, d16 +0xfb 0xff 0xa0 0x06 +# CHECK: vcvt.f32.u32 d16, d16 +0xfb 0xff 0x60 0x07 +# CHECK: vcvt.s32.f32 q8, q8 +0xfb 0xff 0xe0 0x07 +# CHECK: vcvt.u32.f32 q8, q8 +0xfb 0xff 0x60 0x06 +# CHECK: vcvt.f32.s32 q8, q8 +0xfb 0xff 0xe0 0x06 +# CHECK: vcvt.f32.u32 q8, q8 +0xff 0xef 0x30 0x0f +# CHECK: vcvt.s32.f32 d16, d16, #1 +0xff 0xff 0x30 0x0f +# CHECK: vcvt.u32.f32 d16, d16, #1 +0xff 0xef 0x30 0x0e +# CHECK: vcvt.f32.s32 d16, d16, #1 +0xff 0xff 0x30 0x0e +# CHECK: vcvt.f32.u32 d16, d16, #1 +0xff 0xef 0x70 0x0f +# CHECK: vcvt.s32.f32 q8, q8, #1 +0xff 0xff 0x70 0x0f +# CHECK: vcvt.u32.f32 q8, q8, #1 +0xff 0xef 0x70 0x0e +# CHECK: vcvt.f32.s32 q8, q8, #1 +0xff 0xff 0x70 0x0e +# CHECK: vcvt.f32.u32 q8, q8, #1 +0xf6 0xff 0x20 0x07 +# CHECK: vcvt.f32.f16 q8, d16 +0xf6 0xff 0x20 0x06 +# CHECK: vcvt.f16.f32 d16, q8 + +0xc0 0xee 0x90 0x0b +# CHECK: vdup.8 d16, r0 +0x80 0xee 0xb0 0x0b +# CHECK: vdup.16 d16, r0 +0x80 0xee 0x90 0x0b +# CHECK: vdup.32 d16, r0 +0xe0 0xee 0x90 0x0b +# CHECK: vdup.8 q8, r0 +0xa0 0xee 0xb0 0x0b +# CHECK: vdup.16 q8, r0 +0xa0 0xee 0x90 0x0b +# CHECK: vdup.32 q8, r0 +0xf3 0xff 0x20 0x0c +# CHECK: vdup.8 d16, d16[1] +0xf6 0xff 0x20 0x0c +# CHECK: vdup.16 d16, d16[1] +0xfc 0xff 0x20 0x0c +# CHECK: vdup.32 d16, d16[1] +0xf3 0xff 0x60 0x0c +# CHECK: vdup.8 q8, d16[1] +0xf6 0xff 0x60 0x0c +# CHECK: vdup.16 q8, d16[1] +0xfc 0xff 0x60 0x0c +# CHECK: vdup.32 q8, d16[1] + +0x40 0xef 0xb1 0x06 +# CHECK: vmin.s8 d16, d16, d17 +0x50 0xef 0xb1 0x06 +# CHECK: vmin.s16 d16, d16, d17 +0x60 0xef 0xb1 0x06 +# CHECK: vmin.s32 d16, d16, d17 +0x40 0xff 0xb1 0x06 +# CHECK: vmin.u8 d16, d16, d17 +0x50 0xff 0xb1 0x06 +# CHECK: vmin.u16 d16, d16, d17 +0x60 0xff 0xb1 0x06 +# CHECK: vmin.u32 d16, d16, d17 +0x60 0xef 0xa1 0x0f +# CHECK: vmin.f32 d16, d16, d17 +0x40 0xef 0xf2 0x06 +# CHECK: vmin.s8 q8, q8, q9 +0x50 0xef 0xf2 0x06 +# CHECK: vmin.s16 q8, q8, q9 +0x60 0xef 0xf2 0x06 +# CHECK: vmin.s32 q8, q8, q9 +0x40 0xff 0xf2 0x06 +# CHECK: vmin.u8 q8, q8, q9 +0x50 0xff 0xf2 0x06 +# CHECK: vmin.u16 q8, q8, q9 +0x60 0xff 0xf2 0x06 +# CHECK: vmin.u32 q8, q8, q9 +0x60 0xef 0xe2 0x0f +# CHECK: vmin.f32 q8, q8, q9 +0x40 0xef 0xa1 0x06 +# CHECK: vmax.s8 d16, d16, d17 +0x50 0xef 0xa1 0x06 +# CHECK: vmax.s16 d16, d16, d17 +0x60 0xef 0xa1 0x06 +# CHECK: vmax.s32 d16, d16, d17 +0x40 0xff 0xa1 0x06 +# CHECK: vmax.u8 d16, d16, d17 +0x50 0xff 0xa1 0x06 +# CHECK: vmax.u16 d16, d16, d17 +0x60 0xff 0xa1 0x06 +# CHECK: vmax.u32 d16, d16, d17 +0x40 0xef 0xa1 0x0f +# CHECK: vmax.f32 d16, d16, d17 +0x40 0xef 0xe2 0x06 +# CHECK: vmax.s8 q8, q8, q9 +0x50 0xef 0xe2 0x06 +# CHECK: vmax.s16 q8, q8, q9 +0x60 0xef 0xe2 0x06 +# CHECK: vmax.s32 q8, q8, q9 +0x40 0xff 0xe2 0x06 +# CHECK: vmax.u8 q8, q8, q9 +0x50 0xff 0xe2 0x06 +# CHECK: vmax.u16 q8, q8, q9 +0x60 0xff 0xe2 0x06 +# CHECK: vmax.u32 q8, q8, q9 +0x40 0xef 0xe2 0x0f +# CHECK: vmax.f32 q8, q8, q9 + +0xc0 0xef 0x18 0x0e +# CHECK: vmov.i8 d16, #0x8 +0xc1 0xef 0x10 0x08 +# CHECK: vmov.i16 d16, #0x10 +0xc1 0xef 0x10 0x0a +# CHECK: vmov.i16 d16, #0x1000 +0xc2 0xef 0x10 0x00 +# CHECK: vmov.i32 d16, #0x20 +0xc2 0xef 0x10 0x02 +# CHECK: vmov.i32 d16, #0x2000 +0xc2 0xef 0x10 0x04 +# CHECK: vmov.i32 d16, #0x200000 +0xc2 0xef 0x10 0x06 +# CHECK: vmov.i32 d16, #0x20000000 +0xc2 0xef 0x10 0x0c +# CHECK: vmov.i32 d16, #0x20FF +0xc2 0xef 0x10 0x0d +# CHECK: vmov.i32 d16, #0x20FFFF +0xc1 0xff 0x33 0x0e +# CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF +0xc0 0xef 0x58 0x0e +# CHECK: vmov.i8 q8, #0x8 +0xc1 0xef 0x50 0x08 +# CHECK: vmov.i16 q8, #0x10 +0xc1 0xef 0x50 0x0a +# CHECK: vmov.i16 q8, #0x1000 +0xc2 0xef 0x50 0x00 +# CHECK: vmov.i32 q8, #0x20 +0xc2 0xef 0x50 0x02 +# CHECK: vmov.i32 q8, #0x2000 +0xc2 0xef 0x50 0x04 +# CHECK: vmov.i32 q8, #0x200000 +0xc2 0xef 0x50 0x06 +# CHECK: vmov.i32 q8, #0x20000000 +0xc2 0xef 0x50 0x0c +# CHECK: vmov.i32 q8, #0x20FF +0xc2 0xef 0x50 0x0d +# CHECK: vmov.i32 q8, #0x20FFFF +0xc1 0xff 0x73 0x0e +# CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF +0xc1 0xef 0x30 0x08 +# CHECK: vmvn.i16 d16, #0x10 +0xc1 0xef 0x30 0x0a +# CHECK: vmvn.i16 d16, #0x1000 +0xc2 0xef 0x30 0x00 +# CHECK: vmvn.i32 d16, #0x20 +0xc2 0xef 0x30 0x02 +# CHECK: vmvn.i32 d16, #0x2000 +0xc2 0xef 0x30 0x04 +# CHECK: vmvn.i32 d16, #0x200000 +0xc2 0xef 0x30 0x06 +# CHECK: vmvn.i32 d16, #0x20000000 +0xc2 0xef 0x30 0x0c +# CHECK: vmvn.i32 d16, #0x20FF +0xc2 0xef 0x30 0x0d +# CHECK: vmvn.i32 d16, #0x20FFFF +0xc8 0xef 0x30 0x0a +# CHECK: vmovl.s8 q8, d16 +0xd0 0xef 0x30 0x0a +# CHECK: vmovl.s16 q8, d16 +0xe0 0xef 0x30 0x0a +# CHECK: vmovl.s32 q8, d16 +0xc8 0xff 0x30 0x0a +# CHECK: vmovl.u8 q8, d16 +0xd0 0xff 0x30 0x0a +# CHECK: vmovl.u16 q8, d16 +0xe0 0xff 0x30 0x0a +# CHECK: vmovl.u32 q8, d16 +0xf2 0xff 0x20 0x02 +# CHECK: vmovn.i16 d16, q8 +0xf6 0xff 0x20 0x02 +# CHECK: vmovn.i32 d16, q8 +0xfa 0xff 0x20 0x02 +# CHECK: vmovn.i64 d16, q8 +0xf2 0xff 0xa0 0x02 +# CHECK: vqmovn.s16 d16, q8 +0xf6 0xff 0xa0 0x02 +# CHECK: vqmovn.s32 d16, q8 +0xfa 0xff 0xa0 0x02 +# CHECK: vqmovn.s64 d16, q8 +0xf2 0xff 0xe0 0x02 +# CHECK: vqmovn.u16 d16, q8 +0xf6 0xff 0xe0 0x02 +# CHECK: vqmovn.u32 d16, q8 +0xfa 0xff 0xe0 0x02 +# CHECK: vqmovn.u64 d16, q8 +0xf2 0xff 0x60 0x02 +# CHECK: vqmovun.s16 d16, q8 +0xf6 0xff 0x60 0x02 +# CHECK: vqmovun.s32 d16, q8 +0xfa 0xff 0x60 0x02 +# CHECK: vqmovun.s64 d16, q8 +0x50 0xee 0xb0 0x0b +# CHECK: vmov.s8 r0, d16[1] +0x10 0xee 0xf0 0x0b +# CHECK: vmov.s16 r0, d16[1] +0xd0 0xee 0xb0 0x0b +# CHECK: vmov.u8 r0, d16[1] +0x90 0xee 0xf0 0x0b +# CHECK: vmov.u16 r0, d16[1] +0x30 0xee 0x90 0x0b +# CHECK: vmov.32 r0, d16[1] +0x40 0xee 0xb0 0x1b +# CHECK: vmov.8 d16[1], r1 +0x00 0xee 0xf0 0x1b +# CHECK: vmov.16 d16[1], r1 +0x20 0xee 0x90 0x1b +# CHECK: vmov.32 d16[1], r1 +0x42 0xee 0xb0 0x1b +# CHECK: vmov.8 d18[1], r1 +0x02 0xee 0xf0 0x1b +# CHECK: vmov.16 d18[1], r1 +0x22 0xee 0x90 0x1b +# CHECK: vmov.32 d18[1], r1 + +0x42 0xef 0xa1 0x09 +# CHECK: vmla.i8 d16, d18, d17 +0x52 0xef 0xa1 0x09 +# CHECK: vmla.i16 d16, d18, d17 +0x62 0xef 0xa1 0x09 +# CHECK: vmla.i32 d16, d18, d17 +0x42 0xef 0xb1 0x0d +# CHECK: vmla.f32 d16, d18, d17 +0x40 0xef 0xe4 0x29 +# CHECK: vmla.i8 q9, q8, q10 +0x50 0xef 0xe4 0x29 +# CHECK: vmla.i16 q9, q8, q10 +0x60 0xef 0xe4 0x29 +# CHECK: vmla.i32 q9, q8, q10 +0x40 0xef 0xf4 0x2d +# CHECK: vmla.f32 q9, q8, q10 +0xc3 0xef 0xa2 0x08 +# CHECK: vmlal.s8 q8, d19, d18 +0xd3 0xef 0xa2 0x08 +# CHECK: vmlal.s16 q8, d19, d18 +0xe3 0xef 0xa2 0x08 +# CHECK: vmlal.s32 q8, d19, d18 +0xc3 0xff 0xa2 0x08 +# CHECK: vmlal.u8 q8, d19, d18 +0xd3 0xff 0xa2 0x08 +# CHECK: vmlal.u16 q8, d19, d18 +0xe3 0xff 0xa2 0x08 +# CHECK: vmlal.u32 q8, d19, d18 +0xd3 0xef 0xa2 0x09 +# CHECK: vqdmlal.s16 q8, d19, d18 +0xe3 0xef 0xa2 0x09 +# CHECK: vqdmlal.s32 q8, d19, d18 +0x42 0xff 0xa1 0x09 +# CHECK: vmls.i8 d16, d18, d17 +0x52 0xff 0xa1 0x09 +# CHECK: vmls.i16 d16, d18, d17 +0x62 0xff 0xa1 0x09 +# CHECK: vmls.i32 d16, d18, d17 +0x62 0xef 0xb1 0x0d +# CHECK: vmls.f32 d16, d18, d17 +0x40 0xff 0xe4 0x29 +# CHECK: vmls.i8 q9, q8, q10 +0x50 0xff 0xe4 0x29 +# CHECK: vmls.i16 q9, q8, q10 +0x60 0xff 0xe4 0x29 +# CHECK: vmls.i32 q9, q8, q10 +0x60 0xef 0xf4 0x2d +# CHECK: vmls.f32 q9, q8, q10 +0xc3 0xef 0xa2 0x0a +# CHECK: vmlsl.s8 q8, d19, d18 +0xd3 0xef 0xa2 0x0a +# CHECK: vmlsl.s16 q8, d19, d18 +0xe3 0xef 0xa2 0x0a +# CHECK: vmlsl.s32 q8, d19, d18 +0xc3 0xff 0xa2 0x0a +# CHECK: vmlsl.u8 q8, d19, d18 +0xd3 0xff 0xa2 0x0a +# CHECK: vmlsl.u16 q8, d19, d18 +0xe3 0xff 0xa2 0x0a +# CHECK: vmlsl.u32 q8, d19, d18 +0xd3 0xef 0xa2 0x0b +# CHECK: vqdmlsl.s16 q8, d19, d18 +0xe3 0xef 0xa2 0x0b +# CHECK: vqdmlsl.s32 q8, d19, d18 + +0x40 0xef 0xb1 0x09 +# CHECK: vmul.i8 d16, d16, d17 +0x50 0xef 0xb1 0x09 +# CHECK: vmul.i16 d16, d16, d17 +0x60 0xef 0xb1 0x09 +# CHECK: vmul.i32 d16, d16, d17 +0x40 0xff 0xb1 0x0d +# CHECK: vmul.f32 d16, d16, d17 +0x40 0xef 0xf2 0x09 +# CHECK: vmul.i8 q8, q8, q9 +0x50 0xef 0xf2 0x09 +# CHECK: vmul.i16 q8, q8, q9 +0x60 0xef 0xf2 0x09 +# CHECK: vmul.i32 q8, q8, q9 +0x40 0xff 0xf2 0x0d +# CHECK: vmul.f32 q8, q8, q9 +0x40 0xff 0xb1 0x09 +# CHECK: vmul.p8 d16, d16, d17 +0x40 0xff 0xf2 0x09 +# CHECK: vmul.p8 q8, q8, q9 +0x50 0xef 0xa1 0x0b +# CHECK: vqdmulh.s16 d16, d16, d17 +0x60 0xef 0xa1 0x0b +# CHECK: vqdmulh.s32 d16, d16, d17 +0x50 0xef 0xe2 0x0b +# CHECK: vqdmulh.s16 q8, q8, q9 +0x60 0xef 0xe2 0x0b +# CHECK: vqdmulh.s32 q8, q8, q9 +0x50 0xff 0xa1 0x0b +# CHECK: vqrdmulh.s16 d16, d16, d17 +0x60 0xff 0xa1 0x0b +# CHECK: vqrdmulh.s32 d16, d16, d17 +0x50 0xff 0xe2 0x0b +# CHECK: vqrdmulh.s16 q8, q8, q9 +0x60 0xff 0xe2 0x0b +# CHECK: vqrdmulh.s32 q8, q8, q9 +0xc0 0xef 0xa1 0x0c +# CHECK: vmull.s8 q8, d16, d17 +0xd0 0xef 0xa1 0x0c +# CHECK: vmull.s16 q8, d16, d17 +0xe0 0xef 0xa1 0x0c +# CHECK: vmull.s32 q8, d16, d17 +0xc0 0xff 0xa1 0x0c +# CHECK: vmull.u8 q8, d16, d17 +0xd0 0xff 0xa1 0x0c +# CHECK: vmull.u16 q8, d16, d17 +0xe0 0xff 0xa1 0x0c +# CHECK: vmull.u32 q8, d16, d17 +0xc0 0xef 0xa1 0x0e +# CHECK: vmull.p8 q8, d16, d17 +0xd0 0xef 0xa1 0x0d +# CHECK: vqdmull.s16 q8, d16, d17 +0xe0 0xef 0xa1 0x0d +# CHECK: vqdmull.s32 q8, d16, d17 +0xf1 0xff 0xa0 0x03 +# CHECK: vneg.s8 d16, d16 +0xf5 0xff 0xa0 0x03 +# CHECK: vneg.s16 d16, d16 +0xf9 0xff 0xa0 0x03 +# CHECK: vneg.s32 d16, d16 +0xf9 0xff 0xa0 0x07 +# CHECK: vneg.f32 d16, d16 +0xf1 0xff 0xe0 0x03 +# CHECK: vneg.s8 q8, q8 +0xf5 0xff 0xe0 0x03 +# CHECK: vneg.s16 q8, q8 +0xf9 0xff 0xe0 0x03 +# CHECK: vneg.s32 q8, q8 +0xf9 0xff 0xe0 0x07 +# CHECK: vneg.f32 q8, q8 +0xf0 0xff 0xa0 0x07 +# CHECK: vqneg.s8 d16, d16 +0xf4 0xff 0xa0 0x07 +# CHECK: vqneg.s16 d16, d16 +0xf8 0xff 0xa0 0x07 +# CHECK: vqneg.s32 d16, d16 +0xf0 0xff 0xe0 0x07 +# CHECK: vqneg.s8 q8, q8 +0xf4 0xff 0xe0 0x07 +# CHECK: vqneg.s16 q8, q8 +0xf8 0xff 0xe0 0x07 +# CHECK: vqneg.s32 q8, q8 + +0x41 0xef 0xb0 0x0b +# CHECK: vpadd.i8 d16, d17, d16 +0x51 0xef 0xb0 0x0b +# CHECK: vpadd.i16 d16, d17, d16 +0x61 0xef 0xb0 0x0b +# CHECK: vpadd.i32 d16, d17, d16 +0x40 0xff 0xa1 0x0d +# CHECK: vpadd.f32 d16, d16, d17 +0xf0 0xff 0x20 0x02 +# CHECK: vpaddl.s8 d16, d16 +0xf4 0xff 0x20 0x02 +# CHECK: vpaddl.s16 d16, d16 +0xf8 0xff 0x20 0x02 +# CHECK: vpaddl.s32 d16, d16 +0xf0 0xff 0xa0 0x02 +# CHECK: vpaddl.u8 d16, d16 +0xf4 0xff 0xa0 0x02 +# CHECK: vpaddl.u16 d16, d16 +0xf8 0xff 0xa0 0x02 +# CHECK: vpaddl.u32 d16, d16 +0xf0 0xff 0x60 0x02 +# CHECK: vpaddl.s8 q8, q8 +0xf4 0xff 0x60 0x02 +# CHECK: vpaddl.s16 q8, q8 +0xf8 0xff 0x60 0x02 +# CHECK: vpaddl.s32 q8, q8 +0xf0 0xff 0xe0 0x02 +# CHECK: vpaddl.u8 q8, q8 +0xf4 0xff 0xe0 0x02 +# CHECK: vpaddl.u16 q8, q8 +0xf8 0xff 0xe0 0x02 +# CHECK: vpaddl.u32 q8, q8 +0xf0 0xff 0x21 0x06 +# CHECK: vpadal.s8 d16, d17 +0xf4 0xff 0x21 0x06 +# CHECK: vpadal.s16 d16, d17 +0xf8 0xff 0x21 0x06 +# CHECK: vpadal.s32 d16, d17 +0xf0 0xff 0xa1 0x06 +# CHECK: vpadal.u8 d16, d17 +0xf4 0xff 0xa1 0x06 +# CHECK: vpadal.u16 d16, d17 +0xf8 0xff 0xa1 0x06 +# CHECK: vpadal.u32 d16, d17 +0xf0 0xff 0x60 0x26 +# CHECK: vpadal.s8 q9, q8 +0xf4 0xff 0x60 0x26 +# CHECK: vpadal.s16 q9, q8 +0xf8 0xff 0x60 0x26 +# CHECK: vpadal.s32 q9, q8 +0xf0 0xff 0xe0 0x26 +# CHECK: vpadal.u8 q9, q8 +0xf4 0xff 0xe0 0x26 +# CHECK: vpadal.u16 q9, q8 +0xf8 0xff 0xe0 0x26 +# CHECK: vpadal.u32 q9, q8 +0x40 0xef 0xb1 0x0a +# CHECK: vpmin.s8 d16, d16, d17 +0x50 0xef 0xb1 0x0a +# CHECK: vpmin.s16 d16, d16, d17 +0x60 0xef 0xb1 0x0a +# CHECK: vpmin.s32 d16, d16, d17 +0x40 0xff 0xb1 0x0a +# CHECK: vpmin.u8 d16, d16, d17 +0x50 0xff 0xb1 0x0a +# CHECK: vpmin.u16 d16, d16, d17 +0x60 0xff 0xb1 0x0a +# CHECK: vpmin.u32 d16, d16, d17 +0x60 0xff 0xa1 0x0f +# CHECK: vpmin.f32 d16, d16, d17 +0x40 0xef 0xa1 0x0a +# CHECK: vpmax.s8 d16, d16, d17 +0x50 0xef 0xa1 0x0a +# CHECK: vpmax.s16 d16, d16, d17 +0x60 0xef 0xa1 0x0a +# CHECK: vpmax.s32 d16, d16, d17 +0x40 0xff 0xa1 0x0a +# CHECK: vpmax.u8 d16, d16, d17 +0x50 0xff 0xa1 0x0a +# CHECK: vpmax.u16 d16, d16, d17 +0x60 0xff 0xa1 0x0a +# CHECK: vpmax.u32 d16, d16, d17 +0x40 0xff 0xa1 0x0f +# CHECK: vpmax.f32 d16, d16, d17 +0xfb 0xff 0x20 0x04 +# CHECK: vrecpe.u32 d16, d16 +0xfb 0xff 0x60 0x04 +# CHECK: vrecpe.u32 q8, q8 +0xfb 0xff 0x20 0x05 +# CHECK: vrecpe.f32 d16, d16 +0xfb 0xff 0x60 0x05 +# CHECK: vrecpe.f32 q8, q8 +0x40 0xef 0xb1 0x0f +# CHECK: vrecps.f32 d16, d16, d17 +0x40 0xef 0xf2 0x0f +# CHECK: vrecps.f32 q8, q8, q9 +0xfb 0xff 0xa0 0x04 +# CHECK: vrsqrte.u32 d16, d16 +0xfb 0xff 0xe0 0x04 +# CHECK: vrsqrte.u32 q8, q8 +0xfb 0xff 0xa0 0x05 +# CHECK: vrsqrte.f32 d16, d16 +0xfb 0xff 0xe0 0x05 +# CHECK: vrsqrte.f32 q8, q8 +0x60 0xef 0xb1 0x0f +# CHECK: vrsqrts.f32 d16, d16, d17 +0x60 0xef 0xf2 0x0f +# CHECK: vrsqrts.f32 q8, q8, q9 + + +0xf0 0xff 0x20 0x00 +# CHECK: vrev64.8 d16, d16 +0xf4 0xff 0x20 0x00 +# CHECK: vrev64.16 d16, d16 +0xf8 0xff 0x20 0x00 +# CHECK: vrev64.32 d16, d16 +0xf0 0xff 0x60 0x00 +# CHECK: vrev64.8 q8, q8 +0xf4 0xff 0x60 0x00 +# CHECK: vrev64.16 q8, q8 +0xf8 0xff 0x60 0x00 +# CHECK: vrev64.32 q8, q8 +0xf0 0xff 0xa0 0x00 +# CHECK: vrev32.8 d16, d16 +0xf4 0xff 0xa0 0x00 +# CHECK: vrev32.16 d16, d16 +0xf0 0xff 0xe0 0x00 +# CHECK: vrev32.8 q8, q8 +0xf4 0xff 0xe0 0x00 +# CHECK: vrev32.16 q8, q8 +0xf0 0xff 0x20 0x01 +# CHECK: vrev16.8 d16, d16 +0xf0 0xff 0x60 0x01 +# CHECK: vrev16.8 q8, q8 +0x41 0xef 0xb0 0x04 +# CHECK: vqshl.s8 d16, d16, d17 +0x51 0xef 0xb0 0x04 +# CHECK: vqshl.s16 d16, d16, d17 +0x61 0xef 0xb0 0x04 +# CHECK: vqshl.s32 d16, d16, d17 +0x71 0xef 0xb0 0x04 +# CHECK: vqshl.s64 d16, d16, d17 +0x41 0xff 0xb0 0x04 +# CHECK: vqshl.u8 d16, d16, d17 +0x51 0xff 0xb0 0x04 +# CHECK: vqshl.u16 d16, d16, d17 +0x61 0xff 0xb0 0x04 +# CHECK: vqshl.u32 d16, d16, d17 +0x71 0xff 0xb0 0x04 +# CHECK: vqshl.u64 d16, d16, d17 +0x42 0xef 0xf0 0x04 +# CHECK: vqshl.s8 q8, q8, q9 +0x52 0xef 0xf0 0x04 +# CHECK: vqshl.s16 q8, q8, q9 +0x62 0xef 0xf0 0x04 +# CHECK: vqshl.s32 q8, q8, q9 +0x72 0xef 0xf0 0x04 +# CHECK: vqshl.s64 q8, q8, q9 +0x42 0xff 0xf0 0x04 +# CHECK: vqshl.u8 q8, q8, q9 +0x52 0xff 0xf0 0x04 +# CHECK: vqshl.u16 q8, q8, q9 +0x62 0xff 0xf0 0x04 +# CHECK: vqshl.u32 q8, q8, q9 +0x72 0xff 0xf0 0x04 +# CHECK: vqshl.u64 q8, q8, q9 +0xcf 0xef 0x30 0x07 +# CHECK: vqshl.s8 d16, d16, #7 +0xdf 0xef 0x30 0x07 +# CHECK: vqshl.s16 d16, d16, #15 +0xff 0xef 0x30 0x07 +# CHECK: vqshl.s32 d16, d16, #31 +0xff 0xef 0xb0 0x07 +# CHECK: vqshl.s64 d16, d16, #63 +0xcf 0xff 0x30 0x07 +# CHECK: vqshl.u8 d16, d16, #7 +0xdf 0xff 0x30 0x07 +# CHECK: vqshl.u16 d16, d16, #15 +0xff 0xff 0x30 0x07 +# CHECK: vqshl.u32 d16, d16, #31 +0xff 0xff 0xb0 0x07 +# CHECK: vqshl.u64 d16, d16, #63 +0xcf 0xff 0x30 0x06 +# CHECK: vqshlu.s8 d16, d16, #7 +0xdf 0xff 0x30 0x06 +# CHECK: vqshlu.s16 d16, d16, #15 +0xff 0xff 0x30 0x06 +# CHECK: vqshlu.s32 d16, d16, #31 +0xff 0xff 0xb0 0x06 +# CHECK: vqshlu.s64 d16, d16, #63 +0xcf 0xef 0x70 0x07 +# CHECK: vqshl.s8 q8, q8, #7 +0xdf 0xef 0x70 0x07 +# CHECK: vqshl.s16 q8, q8, #15 +0xff 0xef 0x70 0x07 +# CHECK: vqshl.s32 q8, q8, #31 +0xff 0xef 0xf0 0x07 +# CHECK: vqshl.s64 q8, q8, #63 +0xcf 0xff 0x70 0x07 +# CHECK: vqshl.u8 q8, q8, #7 +0xdf 0xff 0x70 0x07 +# CHECK: vqshl.u16 q8, q8, #15 +0xff 0xff 0x70 0x07 +# CHECK: vqshl.u32 q8, q8, #31 +0xff 0xff 0xf0 0x07 +# CHECK: vqshl.u64 q8, q8, #63 +0xcf 0xff 0x70 0x06 +# CHECK: vqshlu.s8 q8, q8, #7 +0xdf 0xff 0x70 0x06 +# CHECK: vqshlu.s16 q8, q8, #15 +0xff 0xff 0x70 0x06 +# CHECK: vqshlu.s32 q8, q8, #31 +0xff 0xff 0xf0 0x06 +# CHECK: vqshlu.s64 q8, q8, #63 +0x41 0xef 0xb0 0x05 +# CHECK: vqrshl.s8 d16, d16, d17 +0x51 0xef 0xb0 0x05 +# CHECK: vqrshl.s16 d16, d16, d17 +0x61 0xef 0xb0 0x05 +# CHECK: vqrshl.s32 d16, d16, d17 +0x71 0xef 0xb0 0x05 +# CHECK: vqrshl.s64 d16, d16, d17 +0x41 0xff 0xb0 0x05 +# CHECK: vqrshl.u8 d16, d16, d17 +0x51 0xff 0xb0 0x05 +# CHECK: vqrshl.u16 d16, d16, d17 +0x61 0xff 0xb0 0x05 +# CHECK: vqrshl.u32 d16, d16, d17 +0x71 0xff 0xb0 0x05 +# CHECK: vqrshl.u64 d16, d16, d17 +0x42 0xef 0xf0 0x05 +# CHECK: vqrshl.s8 q8, q8, q9 +0x52 0xef 0xf0 0x05 +# CHECK: vqrshl.s16 q8, q8, q9 +0x62 0xef 0xf0 0x05 +# CHECK: vqrshl.s32 q8, q8, q9 +0x72 0xef 0xf0 0x05 +# CHECK: vqrshl.s64 q8, q8, q9 +0x42 0xff 0xf0 0x05 +# CHECK: vqrshl.u8 q8, q8, q9 +0x52 0xff 0xf0 0x05 +# CHECK: vqrshl.u16 q8, q8, q9 +0x62 0xff 0xf0 0x05 +# CHECK: vqrshl.u32 q8, q8, q9 +0x72 0xff 0xf0 0x05 +# CHECK: vqrshl.u64 q8, q8, q9 +0xc8 0xef 0x30 0x09 +# CHECK: vqshrn.s16 d16, q8, #8 +0xd0 0xef 0x30 0x09 +# CHECK: vqshrn.s32 d16, q8, #16 +0xe0 0xef 0x30 0x09 +# CHECK: vqshrn.s64 d16, q8, #32 +0xc8 0xff 0x30 0x09 +# CHECK: vqshrn.u16 d16, q8, #8 +0xd0 0xff 0x30 0x09 +# CHECK: vqshrn.u32 d16, q8, #16 +0xe0 0xff 0x30 0x09 +# CHECK: vqshrn.u64 d16, q8, #32 +0xc8 0xff 0x30 0x08 +# CHECK: vqshrun.s16 d16, q8, #8 +0xd0 0xff 0x30 0x08 +# CHECK: vqshrun.s32 d16, q8, #16 +0xe0 0xff 0x30 0x08 +# CHECK: vqshrun.s64 d16, q8, #32 +0xc8 0xef 0x70 0x09 +# CHECK: vqrshrn.s16 d16, q8, #8 +0xd0 0xef 0x70 0x09 +# CHECK: vqrshrn.s32 d16, q8, #16 +0xe0 0xef 0x70 0x09 +# CHECK: vqrshrn.s64 d16, q8, #32 +0xc8 0xff 0x70 0x09 +# CHECK: vqrshrn.u16 d16, q8, #8 +0xd0 0xff 0x70 0x09 +# CHECK: vqrshrn.u32 d16, q8, #16 +0xe0 0xff 0x70 0x09 +# CHECK: vqrshrn.u64 d16, q8, #32 +0xc8 0xff 0x70 0x08 +# CHECK: vqrshrun.s16 d16, q8, #8 +0xd0 0xff 0x70 0x08 +# CHECK: vqrshrun.s32 d16, q8, #16 +0xe0 0xff 0x70 0x08 +# CHECK: vqrshrun.s64 d16, q8, #32 +0x40 0xff 0xa1 0x04 +# CHECK: vshl.u8 d16, d17, d16 +0x50 0xff 0xa1 0x04 +# CHECK: vshl.u16 d16, d17, d16 +0x60 0xff 0xa1 0x04 +# CHECK: vshl.u32 d16, d17, d16 +0x70 0xff 0xa1 0x04 +# CHECK: vshl.u64 d16, d17, d16 +0xcf 0xef 0x30 0x05 +# CHECK: vshl.i8 d16, d16, #7 +0xdf 0xef 0x30 0x05 +# CHECK: vshl.i16 d16, d16, #15 +0xff 0xef 0x30 0x05 +# CHECK: vshl.i32 d16, d16, #31 +0xff 0xef 0xb0 0x05 +# CHECK: vshl.i64 d16, d16, #63 +0x40 0xff 0xe2 0x04 +# CHECK: vshl.u8 q8, q9, q8 +0x50 0xff 0xe2 0x04 +# CHECK: vshl.u16 q8, q9, q8 +0x60 0xff 0xe2 0x04 +# CHECK: vshl.u32 q8, q9, q8 +0x70 0xff 0xe2 0x04 +# CHECK: vshl.u64 q8, q9, q8 +0xcf 0xef 0x70 0x05 +# CHECK: vshl.i8 q8, q8, #7 +0xdf 0xef 0x70 0x05 +# CHECK: vshl.i16 q8, q8, #15 +0xff 0xef 0x70 0x05 +# CHECK: vshl.i32 q8, q8, #31 +0xff 0xef 0xf0 0x05 +# CHECK: vshl.i64 q8, q8, #63 +0xc8 0xff 0x30 0x00 +# CHECK: vshr.u8 d16, d16, #8 +0xd0 0xff 0x30 0x00 +# CHECK: vshr.u16 d16, d16, #16 +0xe0 0xff 0x30 0x00 +# CHECK: vshr.u32 d16, d16, #32 +0xc0 0xff 0xb0 0x00 +# CHECK: vshr.u64 d16, d16, #64 +0xc8 0xff 0x70 0x00 +# CHECK: vshr.u8 q8, q8, #8 +0xd0 0xff 0x70 0x00 +# CHECK: vshr.u16 q8, q8, #16 +0xe0 0xff 0x70 0x00 +# CHECK: vshr.u32 q8, q8, #32 +0xc0 0xff 0xf0 0x00 +# CHECK: vshr.u64 q8, q8, #64 +0xc8 0xef 0x30 0x00 +# CHECK: vshr.s8 d16, d16, #8 +0xd0 0xef 0x30 0x00 +# CHECK: vshr.s16 d16, d16, #16 +0xe0 0xef 0x30 0x00 +# CHECK: vshr.s32 d16, d16, #32 +0xc0 0xef 0xb0 0x00 +# CHECK: vshr.s64 d16, d16, #64 +0xc8 0xef 0x70 0x00 +# CHECK: vshr.s8 q8, q8, #8 +0xd0 0xef 0x70 0x00 +# CHECK: vshr.s16 q8, q8, #16 +0xe0 0xef 0x70 0x00 +# CHECK: vshr.s32 q8, q8, #32 +0xc0 0xef 0xf0 0x00 +# CHECK: vshr.s64 q8, q8, #64 +0xcf 0xef 0x30 0x0a +# CHECK: vshll.s8 q8, d16, #7 +0xdf 0xef 0x30 0x0a +# CHECK: vshll.s16 q8, d16, #15 +0xff 0xef 0x30 0x0a +# CHECK: vshll.s32 q8, d16, #31 +0xcf 0xff 0x30 0x0a +# CHECK: vshll.u8 q8, d16, #7 +0xdf 0xff 0x30 0x0a +# CHECK: vshll.u16 q8, d16, #15 +0xff 0xff 0x30 0x0a +# CHECK: vshll.u32 q8, d16, #31 +0xf2 0xff 0x20 0x03 +# CHECK: vshll.i8 q8, d16, #8 +0xf6 0xff 0x20 0x03 +# CHECK: vshll.i16 q8, d16, #16 +0xfa 0xff 0x20 0x03 +# CHECK: vshll.i32 q8, d16, #32 +0xc8 0xef 0x30 0x08 +# CHECK: vshrn.i16 d16, q8, #8 +0xd0 0xef 0x30 0x08 +# CHECK: vshrn.i32 d16, q8, #16 +0xe0 0xef 0x30 0x08 +# CHECK: vshrn.i64 d16, q8, #32 +0x40 0xef 0xa1 0x05 +# CHECK: vrshl.s8 d16, d17, d16 +0x50 0xef 0xa1 0x05 +# CHECK: vrshl.s16 d16, d17, d16 +0x60 0xef 0xa1 0x05 +# CHECK: vrshl.s32 d16, d17, d16 +0x70 0xef 0xa1 0x05 +# CHECK: vrshl.s64 d16, d17, d16 +0x40 0xff 0xa1 0x05 +# CHECK: vrshl.u8 d16, d17, d16 +0x50 0xff 0xa1 0x05 +# CHECK: vrshl.u16 d16, d17, d16 +0x60 0xff 0xa1 0x05 +# CHECK: vrshl.u32 d16, d17, d16 +0x70 0xff 0xa1 0x05 +# CHECK: vrshl.u64 d16, d17, d16 +0x40 0xef 0xe2 0x05 +# CHECK: vrshl.s8 q8, q9, q8 +0x50 0xef 0xe2 0x05 +# CHECK: vrshl.s16 q8, q9, q8 +0x60 0xef 0xe2 0x05 +# CHECK: vrshl.s32 q8, q9, q8 +0x70 0xef 0xe2 0x05 +# CHECK: vrshl.s64 q8, q9, q8 +0x40 0xff 0xe2 0x05 +# CHECK: vrshl.u8 q8, q9, q8 +0x50 0xff 0xe2 0x05 +# CHECK: vrshl.u16 q8, q9, q8 +0x60 0xff 0xe2 0x05 +# CHECK: vrshl.u32 q8, q9, q8 +0x70 0xff 0xe2 0x05 +# CHECK: vrshl.u64 q8, q9, q8 +0xc8 0xef 0x30 0x02 +# CHECK: vrshr.s8 d16, d16, #8 +0xd0 0xef 0x30 0x02 +# CHECK: vrshr.s16 d16, d16, #16 +0xe0 0xef 0x30 0x02 +# CHECK: vrshr.s32 d16, d16, #32 +0xc0 0xef 0xb0 0x02 +# CHECK: vrshr.s64 d16, d16, #64 +0xc8 0xff 0x30 0x02 +# CHECK: vrshr.u8 d16, d16, #8 +0xd0 0xff 0x30 0x02 +# CHECK: vrshr.u16 d16, d16, #16 +0xe0 0xff 0x30 0x02 +# CHECK: vrshr.u32 d16, d16, #32 +0xc0 0xff 0xb0 0x02 +# CHECK: vrshr.u64 d16, d16, #64 +0xc8 0xef 0x70 0x02 +# CHECK: vrshr.s8 q8, q8, #8 +0xd0 0xef 0x70 0x02 +# CHECK: vrshr.s16 q8, q8, #16 +0xe0 0xef 0x70 0x02 +# CHECK: vrshr.s32 q8, q8, #32 +0xc0 0xef 0xf0 0x02 +# CHECK: vrshr.s64 q8, q8, #64 +0xc8 0xff 0x70 0x02 +# CHECK: vrshr.u8 q8, q8, #8 +0xd0 0xff 0x70 0x02 +# CHECK: vrshr.u16 q8, q8, #16 +0xe0 0xff 0x70 0x02 +# CHECK: vrshr.u32 q8, q8, #32 +0xc0 0xff 0xf0 0x02 +# CHECK: vrshr.u64 q8, q8, #64 +0xc8 0xef 0x70 0x08 +# CHECK: vrshrn.i16 d16, q8, #8 +0xd0 0xef 0x70 0x08 +# CHECK: vrshrn.i32 d16, q8, #16 +0xe0 0xef 0x70 0x08 +# CHECK: vrshrn.i64 d16, q8, #32 +0xc8 0xef 0x30 0x11 +# CHECK: vsra.s8 d17, d16, #8 +0xd0 0xef 0x30 0x11 +# CHECK: vsra.s16 d17, d16, #16 +0xe0 0xef 0x30 0x11 +# CHECK: vsra.s32 d17, d16, #32 +0xc0 0xef 0xb0 0x11 +# CHECK: vsra.s64 d17, d16, #64 +0xc8 0xef 0x72 0x01 +# CHECK: vsra.s8 q8, q9, #8 +0xd0 0xef 0x72 0x01 +# CHECK: vsra.s16 q8, q9, #16 +0xe0 0xef 0x72 0x01 +# CHECK: vsra.s32 q8, q9, #32 +0xc0 0xef 0xf2 0x01 +# CHECK: vsra.s64 q8, q9, #64 +0xc8 0xff 0x30 0x11 +# CHECK: vsra.u8 d17, d16, #8 +0xd0 0xff 0x30 0x11 +# CHECK: vsra.u16 d17, d16, #16 +0xe0 0xff 0x30 0x11 +# CHECK: vsra.u32 d17, d16, #32 +0xc0 0xff 0xb0 0x11 +# CHECK: vsra.u64 d17, d16, #64 +0xc8 0xff 0x72 0x01 +# CHECK: vsra.u8 q8, q9, #8 +0xd0 0xff 0x72 0x01 +# CHECK: vsra.u16 q8, q9, #16 +0xe0 0xff 0x72 0x01 +# CHECK: vsra.u32 q8, q9, #32 +0xc0 0xff 0xf2 0x01 +# CHECK: vsra.u64 q8, q9, #64 +0xc8 0xef 0x30 0x13 +# CHECK: vrsra.s8 d17, d16, #8 +0xd0 0xef 0x30 0x13 +# CHECK: vrsra.s16 d17, d16, #16 +0xe0 0xef 0x30 0x13 +# CHECK: vrsra.s32 d17, d16, #32 +0xc0 0xef 0xb0 0x13 +# CHECK: vrsra.s64 d17, d16, #64 +0xc8 0xff 0x30 0x13 +# CHECK: vrsra.u8 d17, d16, #8 +0xd0 0xff 0x30 0x13 +# CHECK: vrsra.u16 d17, d16, #16 +0xe0 0xff 0x30 0x13 +# CHECK: vrsra.u32 d17, d16, #32 +0xc0 0xff 0xb0 0x13 +# CHECK: vrsra.u64 d17, d16, #64 +0xc8 0xef 0x72 0x03 +# CHECK: vrsra.s8 q8, q9, #8 +0xd0 0xef 0x72 0x03 +# CHECK: vrsra.s16 q8, q9, #16 +0xe0 0xef 0x72 0x03 +# CHECK: vrsra.s32 q8, q9, #32 +0xc0 0xef 0xf2 0x03 +# CHECK: vrsra.s64 q8, q9, #64 +0xc8 0xff 0x72 0x03 +# CHECK: vrsra.u8 q8, q9, #8 +0xd0 0xff 0x72 0x03 +# CHECK: vrsra.u16 q8, q9, #16 +0xe0 0xff 0x72 0x03 +# CHECK: vrsra.u32 q8, q9, #32 +0xc0 0xff 0xf2 0x03 +# CHECK: vrsra.u64 q8, q9, #64 +0xcf 0xff 0x30 0x15 +# CHECK: vsli.8 d17, d16, #7 +0xdf 0xff 0x30 0x15 +# CHECK: vsli.16 d17, d16, #15 +0xff 0xff 0x30 0x15 +# CHECK: vsli.32 d17, d16, #31 +0xff 0xff 0xb0 0x15 +# CHECK: vsli.64 d17, d16, #63 +0xcf 0xff 0x70 0x25 +# CHECK: vsli.8 q9, q8, #7 +0xdf 0xff 0x70 0x25 +# CHECK: vsli.16 q9, q8, #15 +0xff 0xff 0x70 0x25 +# CHECK: vsli.32 q9, q8, #31 +0xff 0xff 0xf0 0x25 +# CHECK: vsli.64 q9, q8, #63 +0xc8 0xff 0x30 0x14 +# CHECK: vsri.8 d17, d16, #8 +0xd0 0xff 0x30 0x14 +# CHECK: vsri.16 d17, d16, #16 +0xe0 0xff 0x30 0x14 +# CHECK: vsri.32 d17, d16, #32 +0xc0 0xff 0xb0 0x14 +# CHECK: vsri.64 d17, d16, #64 +0xc8 0xff 0x70 0x24 +# CHECK: vsri.8 q9, q8, #8 +0xd0 0xff 0x70 0x24 +# CHECK: vsri.16 q9, q8, #16 +0xe0 0xff 0x70 0x24 +# CHECK: vsri.32 q9, q8, #32 +0xc0 0xff 0xf0 0x24 +# CHECK: vsri.64 q9, q8, #64 +0xf1 0xef 0xa0 0x03 +# CHECK: vext.8 d16, d17, d16, #3 +0xf1 0xef 0xa0 0x05 +# CHECK: vext.8 d16, d17, d16, #5 +0xf2 0xef 0xe0 0x03 +# CHECK: vext.8 q8, q9, q8, #3 +0xf2 0xef 0xe0 0x07 +# CHECK: vext.8 q8, q9, q8, #7 +0xf1 0xef 0xa0 0x06 +# CHECK: vext.16 d16, d17, d16, #3 +0xf2 0xef 0xe0 0x0c +# CHECK: vext.32 q8, q9, q8, #3 +0xf2 0xff 0xa0 0x10 +# CHECK: vtrn.8 d17, d16 +0xf6 0xff 0xa0 0x10 +# CHECK: vtrn.16 d17, d16 +0xfa 0xff 0xa0 0x10 +# CHECK: vtrn.32 d17, d16 +0xf2 0xff 0xe0 0x20 +# CHECK: vtrn.8 q9, q8 +0xf6 0xff 0xe0 0x20 +# CHECK: vtrn.16 q9, q8 +0xfa 0xff 0xe0 0x20 +# CHECK: vtrn.32 q9, q8 +0xf2 0xff 0x20 0x11 +# CHECK: vuzp.8 d17, d16 +0xf6 0xff 0x20 0x11 +# CHECK: vuzp.16 d17, d16 +0xf2 0xff 0x60 0x21 +# CHECK: vuzp.8 q9, q8 +0xf6 0xff 0x60 0x21 +# CHECK: vuzp.16 q9, q8 +0xfa 0xff 0x60 0x21 +# CHECK: vuzp.32 q9, q8 +0xf2 0xff 0xa0 0x11 +# CHECK: vzip.8 d17, d16 +0xf6 0xff 0xa0 0x11 +# CHECK: vzip.16 d17, d16 +0xf2 0xff 0xe0 0x21 +# CHECK: vzip.8 q9, q8 +0xf6 0xff 0xe0 0x21 +# CHECK: vzip.16 q9, q8 +0xfa 0xff 0xe0 0x21 +# CHECK: vzip.32 q9, q8 + + +0xf1 0xef 0xa0 0x03 +# CHECK: vext.8 d16, d17, d16, #3 +0xf1 0xef 0xa0 0x05 +# CHECK: vext.8 d16, d17, d16, #5 +0xf2 0xef 0xe0 0x03 +# CHECK: vext.8 q8, q9, q8, #3 +0xf2 0xef 0xe0 0x07 +# CHECK: vext.8 q8, q9, q8, #7 +0xf1 0xef 0xa0 0x06 +# CHECK: vext.16 d16, d17, d16, #3 +0xf2 0xef 0xe0 0x0c +# CHECK: vext.32 q8, q9, q8, #3 +0xf2 0xff 0xa0 0x10 +# CHECK: vtrn.8 d17, d16 +0xf6 0xff 0xa0 0x10 +# CHECK: vtrn.16 d17, d16 +0xfa 0xff 0xa0 0x10 +# CHECK: vtrn.32 d17, d16 +0xf2 0xff 0xe0 0x20 +# CHECK: vtrn.8 q9, q8 +0xf6 0xff 0xe0 0x20 +# CHECK: vtrn.16 q9, q8 +0xfa 0xff 0xe0 0x20 +# CHECK: vtrn.32 q9, q8 +0xf2 0xff 0x20 0x11 +# CHECK: vuzp.8 d17, d16 +0xf6 0xff 0x20 0x11 +# CHECK: vuzp.16 d17, d16 +0xf2 0xff 0x60 0x21 +# CHECK: vuzp.8 q9, q8 +0xf6 0xff 0x60 0x21 +# CHECK: vuzp.16 q9, q8 +0xfa 0xff 0x60 0x21 +# CHECK: vuzp.32 q9, q8 +0xf2 0xff 0xa0 0x11 +# CHECK: vzip.8 d17, d16 +0xf6 0xff 0xa0 0x11 +# CHECK: vzip.16 d17, d16 +0xf2 0xff 0xe0 0x21 +# CHECK: vzip.8 q9, q8 +0xf6 0xff 0xe0 0x21 +# CHECK: vzip.16 q9, q8 +0xfa 0xff 0xe0 0x21 +# CHECK: vzip.32 q9, q8 + +0xf1 0xff 0xa0 0x08 +# CHECK: vtbl.8 d16, {d17}, d16 +0xf0 0xff 0xa2 0x09 +# CHECK: vtbl.8 d16, {d16, d17}, d18 +0xf0 0xff 0xa4 0x0a +# CHECK: vtbl.8 d16, {d16, d17, d18}, d20 +0xf0 0xff 0xa4 0x0b +# CHECK: vtbl.8 d16, {d16, d17, d18, d19}, d20 +0xf0 0xff 0xe1 0x28 +# CHECK: vtbx.8 d18, {d16}, d17 +0xf0 0xff 0xe2 0x39 +# CHECK: vtbx.8 d19, {d16, d17}, d18 +0xf0 0xff 0xe5 0x4a +# CHECK: vtbx.8 d20, {d16, d17, d18}, d21 +0xf0 0xff 0xe5 0x4b +# CHECK: vtbx.8 d20, {d16, d17, d18, d19}, d21 + +0x60 0xf9 0x1f 0x07 +# CHECK: vld1.8 {d16}, [r0, :64] +0x60 0xf9 0x4f 0x07 +# CHECK: vld1.16 {d16}, [r0] +0x60 0xf9 0x8f 0x07 +# CHECK: vld1.32 {d16}, [r0] +0x60 0xf9 0xcf 0x07 +# CHECK: vld1.64 {d16}, [r0] +0x60 0xf9 0x1f 0x0a +# CHECK: vld1.8 {d16, d17}, [r0, :64] +0x60 0xf9 0x6f 0x0a +# CHECK: vld1.16 {d16, d17}, [r0, :128] +0x60 0xf9 0x8f 0x0a +# CHECK: vld1.32 {d16, d17}, [r0] +0x60 0xf9 0xcf 0x0a +# CHECK: vld1.64 {d16, d17}, [r0] + +0x60 0xf9 0x1f 0x08 +# CHECK: vld2.8 {d16, d17}, [r0, :64] +0x60 0xf9 0x6f 0x08 +# CHECK: vld2.16 {d16, d17}, [r0, :128] +0x60 0xf9 0x8f 0x08 +# CHECK: vld2.32 {d16, d17}, [r0] +0x60 0xf9 0x1f 0x03 +# CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] +0x60 0xf9 0x6f 0x03 +# CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] +0x60 0xf9 0xbf 0x03 +# CHECK: vld2.32 {d16, d17, d18, d19}, [r0, :256] + +0x60 0xf9 0x1f 0x04 +# CHECK: vld3.8 {d16, d17, d18}, [r0, :64] +0x60 0xf9 0x4f 0x04 +# CHECK: vld3.16 {d16, d17, d18}, [r0] +0x60 0xf9 0x8f 0x04 +# CHECK: vld3.32 {d16, d17, d18}, [r0] +0x60 0xf9 0x1d 0x05 +# CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! +0x60 0xf9 0x1d 0x15 +# CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! +0x60 0xf9 0x4d 0x05 +# CHECK: vld3.16 {d16, d18, d20}, [r0]! +0x60 0xf9 0x4d 0x15 +# CHECK: vld3.16 {d17, d19, d21}, [r0]! +0x60 0xf9 0x8d 0x05 +# CHECK: vld3.32 {d16, d18, d20}, [r0]! +0x60 0xf9 0x8d 0x15 +# CHECK: vld3.32 {d17, d19, d21}, [r0]! + +0x60 0xf9 0x1f 0x00 +# CHECK: vld4.8 {d16, d17, d18, d19}, [r0, :64] +0x60 0xf9 0x6f 0x00 +# CHECK: vld4.16 {d16, d17, d18, d19}, [r0, :128] +0x60 0xf9 0xbf 0x00 +# CHECK: vld4.32 {d16, d17, d18, d19}, [r0, :256] +0x60 0xf9 0x3d 0x01 +# CHECK: vld4.8 {d16, d18, d20, d22}, [r0, :256]! +0x60 0xf9 0x3d 0x11 +# CHECK: vld4.8 {d17, d19, d21, d23}, [r0, :256]! +0x60 0xf9 0x4d 0x01 +# CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! +0x60 0xf9 0x4d 0x11 +# CHECK: vld4.16 {d17, d19, d21, d23}, [r0]! +0x60 0xf9 0x8d 0x01 +# CHECK: vld4.32 {d16, d18, d20, d22}, [r0]! +0x60 0xf9 0x8d 0x11 +# CHECK: vld4.32 {d17, d19, d21, d23}, [r0]! + +0xe0 0xf9 0x6f 0x00 +# CHECK: vld1.8 {d16[3]}, [r0] +0xe0 0xf9 0x9f 0x04 +# CHECK: vld1.16 {d16[2]}, [r0, :16] +0xe0 0xf9 0xbf 0x08 +# CHECK: vld1.32 {d16[1]}, [r0, :32] + +0xe0 0xf9 0x3f 0x01 +# CHECK: vld2.8 {d16[1], d17[1]}, [r0, :16] +0xe0 0xf9 0x5f 0x05 +# CHECK: vld2.16 {d16[1], d17[1]}, [r0, :32] +0xe0 0xf9 0x8f 0x09 +# CHECK: vld2.32 {d16[1], d17[1]}, [r0] +0xe0 0xf9 0x6f 0x15 +# CHECK: vld2.16 {d17[1], d19[1]}, [r0] +0xe0 0xf9 0x5f 0x19 +# CHECK: vld2.32 {d17[0], d19[0]}, [r0, :64] + +0xe0 0xf9 0x2f 0x02 +# CHECK: vld3.8 {d16[1], d17[1], d18[1]}, [r0] +0xe0 0xf9 0x4f 0x06 +# CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [r0] +0xe0 0xf9 0x8f 0x0a +# CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r0] +0xe0 0xf9 0x6f 0x06 +# CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [r0] +0xe0 0xf9 0xcf 0x1a +# CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0] + +0xe0 0xf9 0x3f 0x03 +# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +0xe0 0xf9 0x4f 0x07 +# CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +0xe0 0xf9 0xaf 0x0b +# CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +0xe0 0xf9 0x7f 0x07 +# CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0, :64] +0xe0 0xf9 0x4f 0x1b +# CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] + +0x40 0xf9 0x1f 0x07 +# CHECK: vst1.8 {d16}, [r0, :64] +0x40 0xf9 0x4f 0x07 +# CHECK: vst1.16 {d16}, [r0] +0x40 0xf9 0x8f 0x07 +# CHECK: vst1.32 {d16}, [r0] +0x40 0xf9 0xcf 0x07 +# CHECK: vst1.64 {d16}, [r0] +0x40 0xf9 0x1f 0x0a +# CHECK: vst1.8 {d16, d17}, [r0, :64] +0x40 0xf9 0x6f 0x0a +# CHECK: vst1.16 {d16, d17}, [r0, :128] +0x40 0xf9 0x8f 0x0a +# CHECK: vst1.32 {d16, d17}, [r0] +0x40 0xf9 0xcf 0x0a +# CHECK: vst1.64 {d16, d17}, [r0] + +0x40 0xf9 0x1f 0x08 +# CHECK: vst2.8 {d16, d17}, [r0, :64] +0x40 0xf9 0x6f 0x08 +# CHECK: vst2.16 {d16, d17}, [r0, :128] +0x40 0xf9 0x8f 0x08 +# CHECK: vst2.32 {d16, d17}, [r0] +0x40 0xf9 0x1f 0x03 +# CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] +0x40 0xf9 0x6f 0x03 +# CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] +0x40 0xf9 0xbf 0x03 +# CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] + +0x40 0xf9 0x1f 0x04 +# CHECK: vst3.8 {d16, d17, d18}, [r0, :64] +0x40 0xf9 0x4f 0x04 +# CHECK: vst3.16 {d16, d17, d18}, [r0] +0x40 0xf9 0x8f 0x04 +# CHECK: vst3.32 {d16, d17, d18}, [r0] +0x40 0xf9 0x1d 0x05 +# CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! +0x40 0xf9 0x1d 0x15 +# CHECK: vst3.8 {d17, d19, d21}, [r0, :64]! +0x40 0xf9 0x4d 0x05 +# CHECK: vst3.16 {d16, d18, d20}, [r0]! +0x40 0xf9 0x4d 0x15 +# CHECK: vst3.16 {d17, d19, d21}, [r0]! +0x40 0xf9 0x8d 0x05 +# CHECK: vst3.32 {d16, d18, d20}, [r0]! +0x40 0xf9 0x8d 0x15 +# CHECK: vst3.32 {d17, d19, d21}, [r0]! + +0x40 0xf9 0x1f 0x00 +# CHECK: vst4.8 {d16, d17, d18, d19}, [r0, :64] +0x40 0xf9 0x6f 0x00 +# CHECK: vst4.16 {d16, d17, d18, d19}, [r0, :128] +0x40 0xf9 0x3d 0x01 +# CHECK: vst4.8 {d16, d18, d20, d22}, [r0, :256]! +0x40 0xf9 0x3d 0x11 +# CHECK: vst4.8 {d17, d19, d21, d23}, [r0, :256]! +0x40 0xf9 0x4d 0x01 +# CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! +0x40 0xf9 0x4d 0x11 +# CHECK: vst4.16 {d17, d19, d21, d23}, [r0]! +0x40 0xf9 0x8d 0x01 +# CHECK: vst4.32 {d16, d18, d20, d22}, [r0]! +0x40 0xf9 0x8d 0x11 +# CHECK: vst4.32 {d17, d19, d21, d23}, [r0]! + +0xc0 0xf9 0x3f 0x01 +# CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] +0xc0 0xf9 0x5f 0x05 +# CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] +0xc0 0xf9 0x8f 0x09 +# CHECK: vst2.32 {d16[1], d17[1]}, [r0] +0xc0 0xf9 0x6f 0x15 +# CHECK: vst2.16 {d17[1], d19[1]}, [r0] +0xc0 0xf9 0x5f 0x19 +# CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] + +0xc0 0xf9 0x2f 0x02 +# CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r0] +0xc0 0xf9 0x4f 0x06 +# CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] +0xc0 0xf9 0x8f 0x0a +# CHECK: vst3.32 {d16[1], d17[1], d18[1]}, [r0] +0xc0 0xf9 0xaf 0x16 +# CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] +0xc0 0xf9 0x4f 0x0a +# CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r0] + +0xc0 0xf9 0x3f 0x03 +# CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] +0xc0 0xf9 0x4f 0x07 +# CHECK: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] +0xc0 0xf9 0xaf 0x0b +# CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] +0xc0 0xf9 0xff 0x17 +# CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] +0xc0 0xf9 0x4f 0x1b +# CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] diff --git a/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt b/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt new file mode 100644 index 0000000..497cb9a --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-MSR-MClass.txt @@ -0,0 +1,7 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mcpu cortex-m3 | FileCheck %s + +# CHECK: msr primask, r0 +0x80 0xf3 0x10 0x80 + +# CHECK: mrs r0, primask +0xef 0xf3 0x10 0x80 diff --git a/test/MC/Disassembler/ARM/thumb-printf.txt b/test/MC/Disassembler/ARM/thumb-printf.txt index 6c2c500..8158a73 100644 --- a/test/MC/Disassembler/ARM/thumb-printf.txt +++ b/test/MC/Disassembler/ARM/thumb-printf.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 | FileCheck %s # CHECK: push {r0, r1, r2, r3} # CHECK-NEXT: push {r4, r5, r7, lr} diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 0d55bb7..18b8f47 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 | FileCheck %s +# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 -mattr +t2xtpk,+mp | FileCheck %s # CHECK: add r5, sp, #68 0x11 0xad @@ -27,7 +27,7 @@ # CHECK: cmn.w r0, #31 0x10 0xf1 0x1f 0x0f -# CHECK: ldmia r0!, {r1} +# CHECK: ldm r0!, {r1} 0x02 0xc8 # CHECK: ldr r5, #432 @@ -42,7 +42,7 @@ # CHECK: str r2, [r5, r3] 0xea 0x50 -# CHECK: ldrb.w r8, #-24 +# CHECK: ldrb.w r8, [pc, #-24] 0x1f 0xf8 0x18 0x80 # CHECK: ldrd r0, r1, [r7, #64]! @@ -112,7 +112,7 @@ # CHECK: lsleq r1, r0, #28 0x01 0x07 -# CHECK: stmiane r0!, {r1, r2, r3} +# CHECK: stmne r0!, {r1, r2, r3} 0x0e 0xc0 # IT block end @@ -143,16 +143,16 @@ # CHECK: vcmpe.f64 d8, #0 0xb5 0xee 0xc0 0x8b -# CHECK: stmdb.w sp, {r0, r2, r3, r8, r11, lr} +# CHECK: stmdb sp, {r0, r2, r3, r8, r11, lr} 0x0d 0xe9 0x0d 0x49 -# CHECK: stmia r5!, {r0, r1, r2, r3, r4} +# CHECK: stm r5!, {r0, r1, r2, r3, r4} 0x1f 0xc5 -# CHECK: ldmia r5, {r0, r1, r2, r3, r4, r5} +# CHECK: ldm r5, {r0, r1, r2, r3, r4, r5} 0x3f 0xcd -# CHECK: ldmia r5!, {r0, r1, r2, r3, r4} +# CHECK: ldm r5!, {r0, r1, r2, r3, r4} 0x1f 0xcd # CHECK: addw r0, pc, #1050 @@ -218,7 +218,7 @@ # CHECK: pld [r5, #30] 0x95 0xf8 0x1e 0xf0 -# CHECK: stc2 p12, cr15, [r9], {137} +# CHECK: stc2 p12, c15, [r9], {137} 0x89 0xfc 0x89 0xfc # CHECK: vmov r1, r0, d11 @@ -265,3 +265,39 @@ # CHECK: bne #24 0x0c 0xd1 + +# CHECK: vadd.f32 q0, q1, q2 +0x02 0xef 0x44 0x0d + +# CHECK: ldrsb r1, [r0, r0] +0x01 0x56 + +# CHECK: ldrsh r1, [r0, r0] +0x01 0x5E + +# CHECK: and.w r5, r1, r10, ror #7 +0x1 0xea 0xfa 0x95 + +# CHECK: ldrsh r6, [sp], #81 +0x3d 0xf9 0x51 0x6b + +# CHECK: usat16 r4, #10, r1 +0xa1 0xf3 0x0a 0x04 + +# CHECK: smlad r5, r12, r8, r11 +0x2c 0xfb 0x8 0xb5 + +# CHECK: teq.w r0, r11 +0x90 0xea 0xb 0x8f + +# CHECK: uxtb16 r9, r12, ror #16 +0x3f 0xfa 0xec 0xf9 + +# CHECK: pldw [r11, r12, lsl #2] +0x3b 0xf8 0x2c 0xf0 + +# CHECK: msr CPSR_fc, r0 +0x80 0xf3 0x00 0x89 + +# CHECK: mrs r0, apsr +0xef 0xf3 0x00 0x80 diff --git a/test/MC/Disassembler/ARM/thumb1.txt b/test/MC/Disassembler/ARM/thumb1.txt new file mode 100644 index 0000000..17c4bad --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb1.txt @@ -0,0 +1,530 @@ +# RUN: llvm-mc -triple=thumbv6-apple-darwin -disassemble < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# ADC (register) +#------------------------------------------------------------------------------ +# CHECK: adcs r4, r6 + +0x74 0x41 + + +#------------------------------------------------------------------------------ +# ADD (immediate) +#------------------------------------------------------------------------------ +# CHECK: adds r1, r2, #3 +# CHECK: adds r2, r2, #3 +# CHECK: adds r2, #8 + +0xd1 0x1c +0xd2 0x1c +0x08 0x32 + +#------------------------------------------------------------------------------ +# ADD (register) +#------------------------------------------------------------------------------ +# CHECK: adds r1, r2, r3 +# CHECK: add r2, r8 + +0xd1 0x18 +0x42 0x44 + +#------------------------------------------------------------------------------ +# ADD (SP plus immediate) +#------------------------------------------------------------------------------ +# CHECK: add sp, #508 +# CHECK: add sp, #4 +# CHECK: add r2, sp, #8 +# CHECK: add r2, sp, #1020 + +0x7f 0xb0 +0x01 0xb0 +0x02 0xaa +0xff 0xaa + + +#------------------------------------------------------------------------------ +# ADD (SP plus register) +#------------------------------------------------------------------------------ +# CHECK: add sp, r3 +# CHECK: add r2, sp, r2 + +0x9d 0x44 +0x6a 0x44 + +#------------------------------------------------------------------------------ +# ADR +#------------------------------------------------------------------------------ +# CHECK: adr r2, #3 +0x03 0xa2 + +#------------------------------------------------------------------------------ +# ASR (immediate) +#------------------------------------------------------------------------------ +# CHECK: asrs r2, r3, #32 +# CHECK: asrs r2, r3, #5 +# CHECK: asrs r2, r3, #1 + +0x1a 0x10 +0x5a 0x11 +0x5a 0x10 + +#------------------------------------------------------------------------------ +# ASR (register) +#------------------------------------------------------------------------------ +# CHECK: asrs r5, r2 + +0x15 0x41 + +#------------------------------------------------------------------------------ +# BICS +#------------------------------------------------------------------------------ +# CHECK: bics r1, r6 + +0xb1 0x43 + +#------------------------------------------------------------------------------ +# BKPT +#------------------------------------------------------------------------------ +# CHECK: bkpt #0 +# CHECK: bkpt #255 + +0x00 0xbe +0xff 0xbe + +#------------------------------------------------------------------------------ +# BLX (register) +#------------------------------------------------------------------------------ +# CHECK: blx r4 + +0xa0 0x47 + +#------------------------------------------------------------------------------ +# BX +#------------------------------------------------------------------------------ +# CHECK: bx r2 + +0x10 0x47 + +#------------------------------------------------------------------------------ +# CMN +#------------------------------------------------------------------------------ +# CHECK: cmn r5, r1 + +0xcd 0x42 + +#------------------------------------------------------------------------------ +# CMP +#------------------------------------------------------------------------------ +# CHECK: cmp r6, #32 +# CHECK: cmp r3, r4 +# CHECK: cmp r8, r1 + +0x20 0x2e +0xa3 0x42 +0x88 0x45 + +#------------------------------------------------------------------------------ +# EOR +#------------------------------------------------------------------------------ +# CHECK: eors r4, r5 + +0x6c 0x40 + +#------------------------------------------------------------------------------ +# LDM +#------------------------------------------------------------------------------ +# CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} +# CHECK: ldm r2!, {r1, r3, r4, r5, r7} +# CHECK: ldm r1, {r1} + +0xff 0xcb +0xba 0xca +0x02 0xc9 + + +#------------------------------------------------------------------------------ +# LDR (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldr r1, [r5] +# CHECK: ldr r2, [r6, #32] +# CHECK: ldr r3, [r7, #124] +# CHECK: ldr r1, [sp] +# CHECK: ldr r2, [sp, #24] +# CHECK: ldr r3, [sp, #1020] + + +0x29 0x68 +0x32 0x6a +0xfb 0x6f +0x00 0x99 +0x06 0x9a +0xff 0x9b + +#------------------------------------------------------------------------------ +# LDR (register) +#------------------------------------------------------------------------------ +# CHECK: ldr r1, [r2, r3] + +0xd1 0x58 + + +#------------------------------------------------------------------------------ +# LDRB (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrb r4, [r3] +# CHECK: ldrb r5, [r6] +# CHECK: ldrb r6, [r7, #31] + +0x1c 0x78 +0x35 0x78 +0xfe 0x7f + + +#------------------------------------------------------------------------------ +# LDRB (register) +#------------------------------------------------------------------------------ +# CHECK: ldrb r6, [r4, r5] + +0x66 0x5d + + +#------------------------------------------------------------------------------ +# LDRH (immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrh r3, [r3] +# CHECK: ldrh r4, [r6, #2] +# CHECK: ldrh r5, [r7, #62] + +0x1b 0x88 +0x74 0x88 +0xfd 0x8f + +#------------------------------------------------------------------------------ +# LDRH (register) +#------------------------------------------------------------------------------ +# CHECK: ldrh r6, [r2, r6] + +0x96 0x5b + + +#------------------------------------------------------------------------------ +# LDRSB/LDRSH +#------------------------------------------------------------------------------ +# CHECK: ldrsb r6, [r2, r6] +# CHECK: ldrsh r3, [r7, r1] + +0x96 0x57 +0x7b 0x5e + +#------------------------------------------------------------------------------ +# LSL (immediate) +#------------------------------------------------------------------------------ +# CHECK: movs r4, r5 +# CHECK: lsls r4, r5, #4 + +0x2c 0x00 +0x2c 0x01 + + +#------------------------------------------------------------------------------ +# LSL (register) +#------------------------------------------------------------------------------ +# CHECK: lsls r2, r6 + +0xb2 0x40 + + +#------------------------------------------------------------------------------ +# LSR (immediate) +#------------------------------------------------------------------------------ +# CHECK: lsrs r1, r3, #1 +# CHECK: lsrs r1, r3, #32 + +0x59 0x08 +0x19 0x08 + + +#------------------------------------------------------------------------------ +# LSR (register) +#------------------------------------------------------------------------------ +# CHECK: lsrs r2, r6 + +0xf2 0x40 + +#------------------------------------------------------------------------------ +# MOV (immediate) +#------------------------------------------------------------------------------ +# CHECK: movs r2, #0 +# CHECK: movs r2, #255 +# CHECK: movs r2, #23 + +0x00 0x22 +0xff 0x22 +0x17 0x22 + + +#------------------------------------------------------------------------------ +# MOV (register) +#------------------------------------------------------------------------------ +# CHECK: mov r3, r4 +# CHECK: movs r1, r3 + +0x23 0x46 +0x19 0x00 + + +#------------------------------------------------------------------------------ +# MUL +#------------------------------------------------------------------------------ +# CHECK: muls r1, r2, r1 +# CHECK: muls r3, r4 + +0x51 0x43 +0x63 0x43 + + +#------------------------------------------------------------------------------ +# MVN +#------------------------------------------------------------------------------ +# CHECK: mvns r6, r3 + +0xde 0x43 + +#------------------------------------------------------------------------------ +# NEG +#------------------------------------------------------------------------------ +# CHECK: rsbs r3, r4, #0 + +0x63 0x42 + + +#------------------------------------------------------------------------------ +# NOP +#------------------------------------------------------------------------------ +# CHECK: nop + +0xc0 0x46 + + +#------------------------------------------------------------------------------ +# ORR +#------------------------------------------------------------------------------ +# CHECK: orrs r3, r4 + +0x23 0x43 + +#------------------------------------------------------------------------------ +# POP +#------------------------------------------------------------------------------ +# CHECK: pop {r2, r3, r6} + +0x4c 0xbc + + +#------------------------------------------------------------------------------ +# PUSH +#------------------------------------------------------------------------------ +# CHECK: push {r1, r2, r7} + +0x86 0xb4 + + +#------------------------------------------------------------------------------ +# REV/REV16/REVSH +#------------------------------------------------------------------------------ +# CHECK: rev r6, r3 +# CHECK: rev16 r7, r2 +# CHECK: revsh r5, r1 + +0x1e 0xba +0x57 0xba +0xcd 0xba + + +#------------------------------------------------------------------------------ +# ROR +#------------------------------------------------------------------------------ +# CHECK: rors r2, r7 + +0xfa 0x41 + +#------------------------------------------------------------------------------ +# RSB +#------------------------------------------------------------------------------ +# CHECK: rsbs r1, r3, #0 + +0x59 0x42 + + +#------------------------------------------------------------------------------ +# SBC +#------------------------------------------------------------------------------ +# CHECK: sbcs r4, r3 + +0x9c 0x41 + + +#------------------------------------------------------------------------------ +# SETEND +#------------------------------------------------------------------------------ +# CHECK: setend be +# CHECK: setend le + +0x58 0xb6 +0x50 0xb6 + +#------------------------------------------------------------------------------ +# STM +#------------------------------------------------------------------------------ +# CHECK: stm r1!, {r2, r6} +# CHECK: stm r1!, {r1, r2, r3, r7} + +0x44 0xc1 +0x8e 0xc1 + + +#------------------------------------------------------------------------------ +# STR (immediate) +#------------------------------------------------------------------------------ +# CHECK: str r2, [r7] +# CHECK: str r2, [r7] +# CHECK: str r5, [r1, #4] +# CHECK: str r3, [r7, #124] +# CHECK: str r2, [sp] +# CHECK: str r3, [sp] +# CHECK: str r4, [sp, #20] +# CHECK: str r5, [sp, #1020] + +0x3a 0x60 +0x3a 0x60 +0x4d 0x60 +0xfb 0x67 +0x00 0x92 +0x00 0x93 +0x05 0x94 +0xff 0x95 + + +#------------------------------------------------------------------------------ +# STR (register) +#------------------------------------------------------------------------------ +# CHECK: str r2, [r7, r3] + +0xfa 0x50 + + +#------------------------------------------------------------------------------ +# STRB (immediate) +#------------------------------------------------------------------------------ +# CHECK: strb r4, [r3] +# CHECK: strb r5, [r6] +# CHECK: strb r6, [r7, #31] + +0x1c 0x70 +0x35 0x70 +0xfe 0x77 + + +#------------------------------------------------------------------------------ +# STRB (register) +#------------------------------------------------------------------------------ +# CHECK: strb r6, [r4, r5] + +0x66 0x55 + + +#------------------------------------------------------------------------------ +# STRH (immediate) +#------------------------------------------------------------------------------ +# CHECK: strh r3, [r3] +# CHECK: strh r4, [r6, #2] +# CHECK: strh r5, [r7, #62] + +0x1b 0x80 +0x74 0x80 +0xfd 0x87 + + +#------------------------------------------------------------------------------ +# STRH (register) +#------------------------------------------------------------------------------ +# CHECK: strh r6, [r2, r6] + +0x96 0x53 + + +#------------------------------------------------------------------------------ +# SUB (immediate) +#------------------------------------------------------------------------------ +# CHECK: subs r1, r2, #3 +# CHECK: subs r2, #3 +# CHECK: subs r2, #8 + +0xd1 0x1e +0x03 0x3a +0x08 0x3a + +#------------------------------------------------------------------------------ +# SUB (register) +#------------------------------------------------------------------------------ +# CHECK: subs r1, r2, r3 + +0xd1 0x1a + +#------------------------------------------------------------------------------ +# SUB (SP minus immediate) +#------------------------------------------------------------------------------ +# CHECK: sub sp, #12 +# CHECK: sub sp, #508 + +0x83 0xb0 +0xff 0xb0 + +#------------------------------------------------------------------------------ +# SVC +#------------------------------------------------------------------------------ +# CHECK: svc #0 +# CHECK: svc #255 + +0x00 0xdf +0xff 0xdf + + +#------------------------------------------------------------------------------ +# SXTB/SXTH +#------------------------------------------------------------------------------ +# CHECK: sxtb r3, r5 +# CHECK: sxth r3, r5 + +0x6b 0xb2 +0x2b 0xb2 + + +#------------------------------------------------------------------------------ +# TST +#------------------------------------------------------------------------------ +# CHECK: tst r6, r1 + +0x0e 0x42 + + +#------------------------------------------------------------------------------ +# UXTB/UXTH +#------------------------------------------------------------------------------ +# CHECK: uxtb r7, r2 +# CHECK: uxth r1, r4 + +0xd7 0xb2 +0xa1 0xb2 + + +#------------------------------------------------------------------------------ +# WFE/WFI/YIELD +#------------------------------------------------------------------------------ +# CHECK: wfe +# CHECK: wfi +# CHECK: yield + +0x20 0xbf +0x30 0xbf +0x10 0xbf diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt new file mode 100644 index 0000000..ed8d988 --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -0,0 +1,2558 @@ +# RUN: llvm-mc -triple=thumbv7-apple-darwin -disassemble < %s | FileCheck %s + +#------------------------------------------------------------------------------ +# ADC (immediate) +#------------------------------------------------------------------------------ +# CHECK: adc r0, r1, #4 +# CHECK: adcs r0, r1, #0 +# CHECK: adc r1, r2, #255 +# CHECK: adc r3, r7, #5570645 +# CHECK: adc r8, r12, #2852170240 +# CHECK: adc r9, r7, #2779096485 +# CHECK: adc r5, r3, #2264924160 +# CHECK: adc r4, r2, #2139095040 +# CHECK: adc r4, r2, #1664 + +0x41 0xf1 0x04 0x00 +0x51 0xf1 0x00 0x00 +0x42 0xf1 0xff 0x01 +0x47 0xf1 0x55 0x13 +0x4c 0xf1 0xaa 0x28 +0x47 0xf1 0xa5 0x39 +0x43 0xf1 0x07 0x45 +0x42 0xf1 0xff 0x44 +0x42 0xf5 0xd0 0x64 + +#------------------------------------------------------------------------------ +# ADC (register) +#------------------------------------------------------------------------------ +# CHECK: adc.w r4, r5, r6 +# CHECK: adcs.w r4, r5, r6 +# CHECK: adc.w r9, r1, r3 +# CHECK: adcs.w r9, r1, r3 +# CHECK: adc.w r0, r1, r3, ror #4 +# CHECK: adcs.w r0, r1, r3, lsl #7 +# CHECK: adc.w r0, r1, r3, lsr #31 +# CHECK: adcs.w r0, r1, r3, asr #32 + +0x45 0xeb 0x06 0x04 +0x55 0xeb 0x06 0x04 +0x41 0xeb 0x03 0x09 +0x51 0xeb 0x03 0x09 +0x41 0xeb 0x33 0x10 +0x51 0xeb 0xc3 0x10 +0x41 0xeb 0xd3 0x70 +0x51 0xeb 0x23 0x00 + + +#------------------------------------------------------------------------------ +# ADD (immediate) +#------------------------------------------------------------------------------ +# CHECK: itet eq +# CHECK: addeq r1, r2, #4 +# CHECK: addwne r5, r3, #1023 +# CHECK: addweq r4, r5, #293 +# CHECK: add.w r2, sp, #1024 +# CHECK: add.w r2, r8, #65280 +# CHECK: addw r2, r3, #257 +# CHECK: add.w r12, r6, #256 +# CHECK: addw r12, r6, #256 +# CHECK: adds.w r1, r2, #496 + +0x0a 0xbf +0x11 0x1d +0x03 0xf2 0xff 0x35 +0x05 0xf2 0x25 0x14 +0x0d 0xf5 0x80 0x62 +0x08 0xf5 0x7f 0x42 +0x03 0xf2 0x01 0x12 +0x06 0xf5 0x80 0x7c +0x06 0xf2 0x00 0x1c +0x12 0xf5 0xf8 0x71 + + +#------------------------------------------------------------------------------ +# ADD (register) +#------------------------------------------------------------------------------ +# CHECK: add.w r1, r2, r8 +# CHECK: add.w r5, r9, r2, asr #32 +# CHECK: adds.w r7, r3, r1, lsl #31 +# CHECK: adds.w r0, r3, r6, lsr #25 +# CHECK: add.w r4, r8, r1, ror #12 + +0x02 0xeb 0x08 0x01 +0x09 0xeb 0x22 0x05 +0x13 0xeb 0xc1 0x77 +0x13 0xeb 0x56 0x60 +0x08 0xeb 0x31 0x34 + + +#------------------------------------------------------------------------------ +# ADR +#------------------------------------------------------------------------------ +# CHECK: subw r11, pc, #3270 +# CHECK: subw r11, pc, #826 + +0xaf 0xf6 0xc6 0x4b +0xaf 0xf2 0x3a 0x3b + +#------------------------------------------------------------------------------ +# AND (immediate) +#------------------------------------------------------------------------------ +# CHECK: and r2, r5, #1044480 +# CHECK: ands r3, r12, #15 +# CHECK: and r1, r1, #255 + +0x05 0xf4 0x7f 0x22 +0x1c 0xf0 0x0f 0x03 +0x01 0xf0 0xff 0x01 + + +#------------------------------------------------------------------------------ +# AND (register) +#------------------------------------------------------------------------------ +# CHECK: and.w r4, r9, r8 +# CHECK: and.w r1, r4, r8, asr #3 +# CHECK: ands.w r2, r1, r7, lsl #1 +# CHECK: ands.w r4, r5, r2, lsr #20 +# CHECK: and.w r9, r12, r1, ror #17 + +0x09 0xea 0x08 0x04 +0x04 0xea 0xe8 0x01 +0x11 0xea 0x47 0x02 +0x15 0xea 0x12 0x54 +0x0c 0xea 0x71 0x49 + +#------------------------------------------------------------------------------ +# ASR (immediate) +#------------------------------------------------------------------------------ +# CHECK: asr.w r2, r3, #12 +# CHECK: asrs.w r8, r3, #32 +# CHECK: asrs.w r2, r3, #1 +# CHECK: asr.w r2, r3, #4 +# CHECK: asrs.w r2, r12, #15 + +# CHECK: asr.w r3, r3, #19 +# CHECK: asrs.w r8, r8, #2 +# CHECK: asrs.w r7, r7, #5 +# CHECK: asr.w r12, r12, #21 + +0x4f 0xea 0x23 0x32 +0x5f 0xea 0x23 0x08 +0x5f 0xea 0x63 0x02 +0x4f 0xea 0x23 0x12 +0x5f 0xea 0xec 0x32 + +0x4f 0xea 0xe3 0x43 +0x5f 0xea 0xa8 0x08 +0x5f 0xea 0x67 0x17 +0x4f 0xea 0x6c 0x5c + + +#------------------------------------------------------------------------------ +# ASR (register) +#------------------------------------------------------------------------------ +# CHECK: asr.w r3, r4, r2 +# CHECK: asr.w r1, r1, r2 +# CHECK: asrs.w r3, r4, r8 + +0x44 0xfa 0x02 0xf3 +0x41 0xfa 0x02 0xf1 +0x54 0xfa 0x08 0xf3 + +#------------------------------------------------------------------------------ +# B +#------------------------------------------------------------------------------ +# CHECK: bmi.w #-183396 + +0x13 0xf5 0xce 0xa9 + + +#------------------------------------------------------------------------------ +# BFC +#------------------------------------------------------------------------------ +# CHECK: bfc r5, #3, #17 +# CHECK: it lo +# CHECK: bfclo r5, #3, #17 + +0x6f 0xf3 0xd3 0x05 +0x38 0xbf +0x6f 0xf3 0xd3 0x05 + + +#------------------------------------------------------------------------------ +# BFI +#------------------------------------------------------------------------------ +# CHECK: bfi r5, r2, #3, #17 +# CHECK: it ne +# CHECK: bfine r5, r2, #3, #17 +# CHECK: bfi r6, r0, #0, #32 +# CHECK: bfi r6, r0, #31, #1 + +0x62 0xf3 0xd3 0x05 +0x18 0xbf +0x62 0xf3 0xd3 0x05 +0x60 0xf3 0x1f 0x06 +0x60 0xf3 0xdf 0x76 + + +#------------------------------------------------------------------------------ +# BIC +#------------------------------------------------------------------------------ +# CHECK: bic r10, r1, #15 +# CHECK: bic.w r12, r3, r6 +# CHECK: bic.w r11, r2, r6, lsl #12 +# CHECK: bic.w r8, r4, r1, lsr #11 +# CHECK: bic.w r7, r5, r7, lsr #15 +# CHECK: bic.w r6, r7, r9, asr #32 +# CHECK: bic.w r5, r6, r8, ror #1 + +# CHECK: bic r1, r1, #15 +# CHECK: bic.w r1, r1, r1 +# CHECK: bic.w r4, r4, r2, lsl #31 +# CHECK: bic.w r6, r6, r3, lsr #12 +# CHECK: bic.w r7, r7, r4, lsr #7 +# CHECK: bic.w r8, r8, r5, asr #15 +# CHECK: bic.w r12, r12, r6, ror #29 + +0x21 0xf0 0x0f 0x0a +0x23 0xea 0x06 0x0c +0x22 0xea 0x06 0x3b +0x24 0xea 0xd1 0x28 +0x25 0xea 0xd7 0x37 +0x27 0xea 0x29 0x06 +0x26 0xea 0x78 0x05 + +0x21 0xf0 0x0f 0x01 +0x21 0xea 0x01 0x01 +0x24 0xea 0xc2 0x74 +0x26 0xea 0x13 0x36 +0x27 0xea 0xd4 0x17 +0x28 0xea 0xe5 0x38 +0x2c 0xea 0x76 0x7c + + +#------------------------------------------------------------------------------ +# BXJ +#------------------------------------------------------------------------------ +# CHECK: bxj r5 +# CHECK: it ne +# CHECK: bxjne r7 + +0xc5 0xf3 0x00 0x8f +0x18 0xbf +0xc7 0xf3 0x00 0x8f + + +#------------------------------------------------------------------------------ +# CBZ/CBNZ +#------------------------------------------------------------------------------ +# CHECK: cbnz r7, #6 +# CHECK: cbnz r7, #12 + +0x1f 0xb9 +0x37 0xb9 + +#------------------------------------------------------------------------------ +# CDP/CDP2 +#------------------------------------------------------------------------------ +# CHECK: cdp p7, #1, c1, c1, c1, #4 +# CHECK: cdp2 p7, #1, c1, c1, c1, #4 + +0x11 0xee 0x81 0x17 +0x11 0xfe 0x81 0x17 + + +#------------------------------------------------------------------------------ +# CLREX +#------------------------------------------------------------------------------ +#CHECK: clrex +#CHECK: it ne +#CHECK: clrexne + +0xbf 0xf3 0x2f 0x8f +0x18 0xbf +0xbf 0xf3 0x2f 0x8f + + +#------------------------------------------------------------------------------ +# CLZ +#------------------------------------------------------------------------------ +#CHECK: clz r1, r2 +#CHECK: it eq +#CHECK: clzeq r1, r2 + +0xb2 0xfa 0x82 0xf1 +0x08 0xbf +0xb2 0xfa 0x82 0xf1 + + +#------------------------------------------------------------------------------ +# CMN +#------------------------------------------------------------------------------ +#CHECK: cmn.w r1, #15 +#CHECK: cmn.w r8, r6 +#CHECK: cmn.w r1, r6, lsl #10 +#CHECK: cmn.w r1, r6, lsr #10 +#CHECK: cmn.w sp, r6, lsr #10 +#CHECK: cmn.w r1, r6, asr #10 +#CHECK: cmn.w r1, r6, ror #10 + +0x11 0xf1 0x0f 0x0f +0x18 0xeb 0x06 0x0f +0x11 0xeb 0x86 0x2f +0x11 0xeb 0x96 0x2f +0x1d 0xeb 0x96 0x2f +0x11 0xeb 0xa6 0x2f +0x11 0xeb 0xb6 0x2f + + +#------------------------------------------------------------------------------ +# CMP +#------------------------------------------------------------------------------ +#CHECK: cmp.w r5, #65280 +#CHECK: cmp.w r4, r12 +#CHECK: cmp.w r9, r6, lsl #12 +#CHECK: cmp.w r3, r7, lsr #31 +#CHECK: cmp.w sp, r6, lsr #1 +#CHECK: cmp.w r2, r5, asr #24 +#CHECK: cmp.w r1, r4, ror #15 + +0xb5 0xf5 0x7f 0x4f +0xb4 0xeb 0x0c 0x0f +0xb9 0xeb 0x06 0x3f +0xb3 0xeb 0xd7 0x7f +0xbd 0xeb 0x56 0x0f +0xb2 0xeb 0x25 0x6f +0xb1 0xeb 0xf4 0x3f + + +#------------------------------------------------------------------------------ +# DBG +#------------------------------------------------------------------------------ +#CHECK: dbg #5 +#CHECK: dbg #0 +#CHECK: dbg #15 + +0xaf 0xf3 0xf5 0x80 +0xaf 0xf3 0xf0 0x80 +0xaf 0xf3 0xff 0x80 + + +#------------------------------------------------------------------------------ +# DMB +#------------------------------------------------------------------------------ +#CHECK: dmb sy +#CHECK: dmb st +#CHECK: dmb ish +#CHECK: dmb ishst +#CHECK: dmb nsh +#CHECK: dmb nshst +#CHECK: dmb osh +#CHECK: dmb oshst +#CHECK: dmb + +0xbf 0xf3 0x5f 0x8f +0xbf 0xf3 0x5e 0x8f +0xbf 0xf3 0x5b 0x8f +0xbf 0xf3 0x5a 0x8f +0xbf 0xf3 0x57 0x8f +0xbf 0xf3 0x56 0x8f +0xbf 0xf3 0x53 0x8f +0xbf 0xf3 0x52 0x8f +0xbf 0xf3 0x5f 0x8f + + +#------------------------------------------------------------------------------ +# DSB +#------------------------------------------------------------------------------ +#CHECK: dsb sy +#CHECK: dsb st +#CHECK: dsb ish +#CHECK: dsb ishst +#CHECK: dsb nsh +#CHECK: dsb nshst +#CHECK: dsb osh +#CHECK: dsb oshst + +0xbf 0xf3 0x4f 0x8f +0xbf 0xf3 0x4e 0x8f +0xbf 0xf3 0x4b 0x8f +0xbf 0xf3 0x4a 0x8f +0xbf 0xf3 0x47 0x8f +0xbf 0xf3 0x46 0x8f +0xbf 0xf3 0x43 0x8f +0xbf 0xf3 0x42 0x8f + + +#------------------------------------------------------------------------------ +# EOR +#------------------------------------------------------------------------------ +#CHECK: eor r4, r5, #61440 +#CHECK: eor.w r4, r5, r6 +#CHECK: eor.w r4, r5, r6, lsl #5 +#CHECK: eor.w r4, r5, r6, lsr #5 +#CHECK: eor.w r4, r5, r6, lsr #5 +#CHECK: eor.w r4, r5, r6, asr #5 +#CHECK: eor.w r4, r5, r6, ror #5 + +0x85 0xf4 0x70 0x44 +0x85 0xea 0x06 0x04 +0x85 0xea 0x46 0x14 +0x85 0xea 0x56 0x14 +0x85 0xea 0x56 0x14 +0x85 0xea 0x66 0x14 +0x85 0xea 0x76 0x14 + + +#------------------------------------------------------------------------------ +# ISB +#------------------------------------------------------------------------------ +#CHECK: isb sy + +0xbf 0xf3 0x6f 0x8f + +#------------------------------------------------------------------------------ +# IT +#------------------------------------------------------------------------------ +# Test encodings of a few full IT blocks, not just the IT instruction + +# CHECK: iteet eq +# CHECK: addeq r0, r1, r2 +# CHECK: nopne +# CHECK: subne r5, r6, r7 +# CHECK: addeq r1, r2, #4 + +0x0d 0xbf +0x88 0x18 +0x00 0xbf +0xf5 0x1b +0x11 0x1d + +# CHECK: ittee ls +# CHECK: addls r0, r1, r2 +# CHECK: nopls +# CHECK: subhi r5, r6, r7 +# CHECK: addhi r1, r2, #4 + +0x99 0xbf +0x88 0x18 +0x00 0xbf +0xf5 0x1b +0x11 0x1d + + +#------------------------------------------------------------------------------ +# LDMIA +#------------------------------------------------------------------------------ +# CHECK: ldm.w r4, {r4, r5, r8, r9} +# CHECK: ldm.w r4, {r5, r6} +# CHECK: ldm.w r5!, {r3, r8} +# CHECK: ldm.w r4, {r4, r5, r8, r9} +# CHECK: ldm.w r4, {r5, r6} +# CHECK: ldm.w r5!, {r3, r8} +# CHECK: ldm.w r5!, {r1, r2} +# CHECK: ldm.w r2, {r1, r2} + +# CHECK: ldm.w r4, {r4, r5, r8, r9} +# CHECK: ldm.w r4, {r5, r6} +# CHECK: ldm.w r5!, {r3, r8} +# CHECK: ldm.w r4, {r4, r5, r8, r9} +# CHECK: ldm.w r4, {r5, r6} +# CHECK: ldm.w r5!, {r3, r8} +# CHECK: ldm.w r5!, {r3, r8} + +0x94 0xe8 0x30 0x03 +0x94 0xe8 0x60 0x00 +0xb5 0xe8 0x08 0x01 +0x94 0xe8 0x30 0x03 +0x94 0xe8 0x60 0x00 +0xb5 0xe8 0x08 0x01 +0xb5 0xe8 0x06 0x00 +0x92 0xe8 0x06 0x00 + +0x94 0xe8 0x30 0x03 +0x94 0xe8 0x60 0x00 +0xb5 0xe8 0x08 0x01 +0x94 0xe8 0x30 0x03 +0x94 0xe8 0x60 0x00 +0xb5 0xe8 0x08 0x01 +0xb5 0xe8 0x08 0x01 + + +#------------------------------------------------------------------------------ +# LDMDB +#------------------------------------------------------------------------------ +# CHECK: ldmdb r4, {r4, r5, r8, r9} +# CHECK: ldmdb r4, {r5, r6} +# CHECK: ldmdb r5!, {r3, r8} +# CHECK: ldmdb r5!, {r3, r8} + +0x14 0xe9 0x30 0x03 +0x14 0xe9 0x60 0x00 +0x35 0xe9 0x08 0x01 +0x35 0xe9 0x08 0x01 + + +#------------------------------------------------------------------------------ +# LDR(immediate) +#------------------------------------------------------------------------------ +# CHECK: ldr r5, [r5, #-4] +# CHECK: ldr r5, [r6, #32] +# CHECK: ldr.w r5, [r6, #33] +# CHECK: ldr.w r5, [r6, #257] +# CHECK: ldr.w pc, [r7, #257] + +0x55 0xf8 0x04 0x5c +0x35 0x6a +0xd6 0xf8 0x21 0x50 +0xd6 0xf8 0x01 0x51 +0xd7 0xf8 0x01 0xf1 + + +#------------------------------------------------------------------------------ +# LDR(register) +#------------------------------------------------------------------------------ +# CHECK: ldr.w r1, [r8, r1] +# CHECK: ldr.w r4, [r5, r2] +# CHECK: ldr.w r6, [r0, r2, lsl #3] +# CHECK: ldr.w r8, [r8, r2, lsl #2] +# CHECK: ldr.w r7, [sp, r2, lsl #1] +# CHECK: ldr.w r7, [sp, r2] +# CHECK: ldr r2, [r4, #255]! +# CHECK: ldr r8, [sp, #4]! +# CHECK: ldr lr, [sp, #-4]! +# CHECK: ldr r2, [r4], #255 +# CHECK: ldr r8, [sp], #4 +# CHECK: ldr lr, [sp], #-4 + +0x58 0xf8 0x01 0x10 +0x55 0xf8 0x02 0x40 +0x50 0xf8 0x32 0x60 +0x58 0xf8 0x22 0x80 +0x5d 0xf8 0x12 0x70 +0x5d 0xf8 0x02 0x70 +0x54 0xf8 0xff 0x2f +0x5d 0xf8 0x04 0x8f +0x5d 0xf8 0x04 0xed +0x54 0xf8 0xff 0x2b +0x5d 0xf8 0x04 0x8b +0x5d 0xf8 0x04 0xe9 + + +#------------------------------------------------------------------------------ +# LDRB(immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrb r5, [r5, #-4] +# CHECK: ldrb.w r5, [r6, #32] +# CHECK: ldrb.w r5, [r6, #33] +# CHECK: ldrb.w r5, [r6, #257] +# CHECK: ldrb.w lr, [r7, #257] + +0x15 0xf8 0x04 0x5c +0x96 0xf8 0x20 0x50 +0x96 0xf8 0x21 0x50 +0x96 0xf8 0x01 0x51 +0x97 0xf8 0x01 0xe1 + + +#------------------------------------------------------------------------------ +# LDRB(register) +#------------------------------------------------------------------------------ +# CHECK: ldrb.w r1, [r8, r1] +# CHECK: ldrb.w r4, [r5, r2] +# CHECK: ldrb.w r6, [r0, r2, lsl #3] +# CHECK: ldrb.w r8, [r8, r2, lsl #2] +# CHECK: ldrb.w r7, [sp, r2, lsl #1] +# CHECK: ldrb.w r7, [sp, r2] +# CHECK: ldrb r5, [r8, #255]! +# CHECK: ldrb r2, [r5, #4]! +# CHECK: ldrb r1, [r4, #-4]! +# CHECK: ldrb lr, [r3], #255 +# CHECK: ldrb r9, [r2], #4 +# CHECK: ldrb r3, [sp], #-4 + +0x18 0xf8 0x01 0x10 +0x15 0xf8 0x02 0x40 +0x10 0xf8 0x32 0x60 +0x18 0xf8 0x22 0x80 +0x1d 0xf8 0x12 0x70 +0x1d 0xf8 0x02 0x70 +0x18 0xf8 0xff 0x5f +0x15 0xf8 0x04 0x2f +0x14 0xf8 0x04 0x1d +0x13 0xf8 0xff 0xeb +0x12 0xf8 0x04 0x9b +0x1d 0xf8 0x04 0x39 + + +#------------------------------------------------------------------------------ +# LDRBT +#------------------------------------------------------------------------------ +# CHECK: ldrbt r1, [r2] +# CHECK: ldrbt r1, [r8] +# CHECK: ldrbt r1, [r8, #3] +# CHECK: ldrbt r1, [r8, #255] + +0x12 0xf8 0x00 0x1e +0x18 0xf8 0x00 0x1e +0x18 0xf8 0x03 0x1e +0x18 0xf8 0xff 0x1e + + +#------------------------------------------------------------------------------ +# LDRD(immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrd r3, r5, [r6, #24] +# CHECK: ldrd r3, r5, [r6, #24]! +# CHECK: ldrd r3, r5, [r6], #4 +# CHECK: ldrd r3, r5, [r6], #-8 +# CHECK: ldrd r3, r5, [r6] +# CHECK: ldrd r8, r1, [r3] + +0xd6 0xe9 0x06 0x35 +0xf6 0xe9 0x06 0x35 +0xf6 0xe8 0x01 0x35 +0x76 0xe8 0x02 0x35 +0xd6 0xe9 0x00 0x35 +0xd3 0xe9 0x00 0x81 + + +#------------------------------------------------------------------------------ +# FIXME: LDRD(literal) +#------------------------------------------------------------------------------ + + +#------------------------------------------------------------------------------ +# LDREX/LDREXB/LDREXH/LDREXD +#------------------------------------------------------------------------------ +# CHECK: ldrex r1, [r4] +# CHECK: ldrex r8, [r4] +# CHECK: ldrex r2, [sp, #128] +# CHECK: ldrexb r5, [r7] +# CHECK: ldrexh r9, [r12] +# CHECK: ldrexd r9, r3, [r4] + +0x54 0xe8 0x00 0x1f +0x54 0xe8 0x00 0x8f +0x5d 0xe8 0x20 0x2f +0xd7 0xe8 0x4f 0x5f +0xdc 0xe8 0x5f 0x9f +0xd4 0xe8 0x7f 0x93 + + +#------------------------------------------------------------------------------ +# LDRH(immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrh r5, [r5, #-4] +# CHECK: ldrh r5, [r6, #32] +# CHECK: ldrh.w r5, [r6, #33] +# CHECK: ldrh.w r5, [r6, #257] +# CHECK: ldrh.w lr, [r7, #257] +# CHECK: ldrh.w r0, [pc, #-21] + +0x35 0xf8 0x04 0x5c +0x35 0x8c +0xb6 0xf8 0x21 0x50 +0xb6 0xf8 0x01 0x51 +0xb7 0xf8 0x01 0xe1 +0x3f 0xf8 0x15 0x00 + + +#------------------------------------------------------------------------------ +# LDRH(register) +#------------------------------------------------------------------------------ +# CHECK: ldrh.w r1, [r8, r1] +# CHECK: ldrh.w r4, [r5, r2] +# CHECK: ldrh.w r6, [r0, r2, lsl #3] +# CHECK: ldrh.w r8, [r8, r2, lsl #2] +# CHECK: ldrh.w r7, [sp, r2, lsl #1] +# CHECK: ldrh.w r7, [sp, r2] +# CHECK: ldrh r5, [r8, #255]! +# CHECK: ldrh r2, [r5, #4]! +# CHECK: ldrh r1, [r4, #-4]! +# CHECK: ldrh lr, [r3], #255 +# CHECK: ldrh r9, [r2], #4 +# CHECK: ldrh r3, [sp], #-4 + +0x38 0xf8 0x01 0x10 +0x35 0xf8 0x02 0x40 +0x30 0xf8 0x32 0x60 +0x38 0xf8 0x22 0x80 +0x3d 0xf8 0x12 0x70 +0x3d 0xf8 0x02 0x70 +0x38 0xf8 0xff 0x5f +0x35 0xf8 0x04 0x2f +0x34 0xf8 0x04 0x1d +0x33 0xf8 0xff 0xeb +0x32 0xf8 0x04 0x9b +0x3d 0xf8 0x04 0x39 + + +#------------------------------------------------------------------------------ +# LDRSB(immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrsb r5, [r5, #-4] +# CHECK: ldrsb.w r5, [r6, #32] +# CHECK: ldrsb.w r5, [r6, #33] +# CHECK: ldrsb.w r5, [r6, #257] +# CHECK: ldrsb.w lr, [r7, #257] + +0x15 0xf9 0x04 0x5c +0x96 0xf9 0x20 0x50 +0x96 0xf9 0x21 0x50 +0x96 0xf9 0x01 0x51 +0x97 0xf9 0x01 0xe1 + + +#------------------------------------------------------------------------------ +# LDRSB(register) +#------------------------------------------------------------------------------ +# CHECK: ldrsb.w r1, [r8, r1] +# CHECK: ldrsb.w r4, [r5, r2] +# CHECK: ldrsb.w r6, [r0, r2, lsl #3] +# CHECK: ldrsb.w r8, [r8, r2, lsl #2] +# CHECK: ldrsb.w r7, [sp, r2, lsl #1] +# CHECK: ldrsb.w r7, [sp, r2] +# CHECK: ldrsb r5, [r8, #255]! +# CHECK: ldrsb r2, [r5, #4]! +# CHECK: ldrsb r1, [r4, #-4]! +# CHECK: ldrsb lr, [r3], #255 +# CHECK: ldrsb r9, [r2], #4 +# CHECK: ldrsb r3, [sp], #-4 + +0x18 0xf9 0x01 0x10 +0x15 0xf9 0x02 0x40 +0x10 0xf9 0x32 0x60 +0x18 0xf9 0x22 0x80 +0x1d 0xf9 0x12 0x70 +0x1d 0xf9 0x02 0x70 +0x18 0xf9 0xff 0x5f +0x15 0xf9 0x04 0x2f +0x14 0xf9 0x04 0x1d +0x13 0xf9 0xff 0xeb +0x12 0xf9 0x04 0x9b +0x1d 0xf9 0x04 0x39 + + +#------------------------------------------------------------------------------ +# LDRSBT +#------------------------------------------------------------------------------ +# CHECK: ldrsbt r1, [r2] +# CHECK: ldrsbt r1, [r8] +# CHECK: ldrsbt r1, [r8, #3] +# CHECK: ldrsbt r1, [r8, #255] + +0x12 0xf9 0x00 0x1e +0x18 0xf9 0x00 0x1e +0x18 0xf9 0x03 0x1e +0x18 0xf9 0xff 0x1e + + +#------------------------------------------------------------------------------ +# LDRSH(immediate) +#------------------------------------------------------------------------------ +# CHECK: ldrsh r5, [r5, #-4] +# CHECK: ldrsh.w r5, [r6, #32] +# CHECK: ldrsh.w r5, [r6, #33] +# CHECK: ldrsh.w r5, [r6, #257] +# CHECK: ldrsh.w lr, [r7, #257] +# CHECK: ldrsh r10, [r5, #-0] + +0x35 0xf9 0x04 0x5c +0xb6 0xf9 0x20 0x50 +0xb6 0xf9 0x21 0x50 +0xb6 0xf9 0x01 0x51 +0xb7 0xf9 0x01 0xe1 +0x35 0xf9 0x00 0xac + +#------------------------------------------------------------------------------ +# LDRSH(register) +#------------------------------------------------------------------------------ +# CHECK: ldrsh.w r1, [r8, r1] +# CHECK: ldrsh.w r4, [r5, r2] +# CHECK: ldrsh.w r6, [r0, r2, lsl #3] +# CHECK: ldrsh.w r8, [r8, r2, lsl #2] +# CHECK: ldrsh.w r7, [sp, r2, lsl #1] +# CHECK: ldrsh.w r7, [sp, r2] +# CHECK: ldrsh r5, [r8, #255]! +# CHECK: ldrsh r2, [r5, #4]! +# CHECK: ldrsh r1, [r4, #-4]! +# CHECK: ldrsh lr, [r3], #255 +# CHECK: ldrsh r9, [r2], #4 +# CHECK: ldrsh r3, [sp], #-4 + +0x38 0xf9 0x01 0x10 +0x35 0xf9 0x02 0x40 +0x30 0xf9 0x32 0x60 +0x38 0xf9 0x22 0x80 +0x3d 0xf9 0x12 0x70 +0x3d 0xf9 0x02 0x70 +0x38 0xf9 0xff 0x5f +0x35 0xf9 0x04 0x2f +0x34 0xf9 0x04 0x1d +0x33 0xf9 0xff 0xeb +0x32 0xf9 0x04 0x9b +0x3d 0xf9 0x04 0x39 + + +#------------------------------------------------------------------------------ +# LDRSHT +#------------------------------------------------------------------------------ +# CHECK: ldrsht r1, [r2] +# CHECK: ldrsht r1, [r8] +# CHECK: ldrsht r1, [r8, #3] +# CHECK: ldrsht r1, [r8, #255] + +0x32 0xf9 0x00 0x1e +0x38 0xf9 0x00 0x1e +0x38 0xf9 0x03 0x1e +0x38 0xf9 0xff 0x1e + + +#------------------------------------------------------------------------------ +# LDRT +#------------------------------------------------------------------------------ +# CHECK: ldrt r1, [r2] +# CHECK: ldrt r2, [r6] +# CHECK: ldrt r3, [r7, #3] +# CHECK: ldrt r4, [r9, #255] + +0x52 0xf8 0x00 0x1e +0x56 0xf8 0x00 0x2e +0x57 0xf8 0x03 0x3e +0x59 0xf8 0xff 0x4e + + +#------------------------------------------------------------------------------ +# LSL (immediate) +#------------------------------------------------------------------------------ +# CHECK: lsl.w r2, r3, #12 +# CHECK: lsls.w r8, r3, #31 +# CHECK: lsls.w r2, r3, #1 +# CHECK: lsl.w r2, r3, #4 +# CHECK: lsls.w r2, r12, #15 + +# CHECK: lsl.w r3, r3, #19 +# CHECK: lsls.w r8, r8, #2 +# CHECK: lsls.w r7, r7, #5 +# CHECK: lsl.w r12, r12, #21 + +0x4f 0xea 0x03 0x32 +0x5f 0xea 0xc3 0x78 +0x5f 0xea 0x43 0x02 +0x4f 0xea 0x03 0x12 +0x5f 0xea 0xcc 0x32 + +0x4f 0xea 0xc3 0x43 +0x5f 0xea 0x88 0x08 +0x5f 0xea 0x47 0x17 +0x4f 0xea 0x4c 0x5c + + +#------------------------------------------------------------------------------ +# LSL (register) +#------------------------------------------------------------------------------ +# CHECK: lsl.w r3, r4, r2 +# CHECK: lsl.w r1, r1, r2 +# CHECK: lsls.w r3, r4, r8 + +0x04 0xfa 0x02 0xf3 +0x01 0xfa 0x02 0xf1 +0x14 0xfa 0x08 0xf3 + + +#------------------------------------------------------------------------------ +# LSR (immediate) +#------------------------------------------------------------------------------ +# CHECK: lsr.w r2, r3, #12 +# CHECK: lsrs.w r8, r3, #32 +# CHECK: lsrs.w r2, r3, #1 +# CHECK: lsr.w r2, r3, #4 +# CHECK: lsrs.w r2, r12, #15 + +# CHECK: lsr.w r3, r3, #19 +# CHECK: lsrs.w r8, r8, #2 +# CHECK: lsrs.w r7, r7, #5 +# CHECK: lsr.w r12, r12, #21 + +0x4f 0xea 0x13 0x32 +0x5f 0xea 0x13 0x08 +0x5f 0xea 0x53 0x02 +0x4f 0xea 0x13 0x12 +0x5f 0xea 0xdc 0x32 + +0x4f 0xea 0xd3 0x43 +0x5f 0xea 0x98 0x08 +0x5f 0xea 0x57 0x17 +0x4f 0xea 0x5c 0x5c + + +#------------------------------------------------------------------------------ +# LSR (register) +#------------------------------------------------------------------------------ +# CHECK: lsr.w r3, r4, r2 +# CHECK: lsr.w r1, r1, r2 +# CHECK: lsrs.w r3, r4, r8 + +0x24 0xfa 0x02 0xf3 +0x21 0xfa 0x02 0xf1 +0x34 0xfa 0x08 0xf3 + +#------------------------------------------------------------------------------ +# MCR/MCR2 +#------------------------------------------------------------------------------ +# CHECK: mcr p7, #1, r5, c1, c1, #4 +# CHECK: mcr2 p7, #1, r5, c1, c1, #4 + +0x21 0xee 0x91 0x57 +0x21 0xfe 0x91 0x57 + + +#------------------------------------------------------------------------------ +# MCRR/MCRR2 +#------------------------------------------------------------------------------ +# CHECK: mcrr p7, #15, r5, r4, c1 +# CHECK: mcrr2 p7, #15, r5, r4, c1 + +0x44 0xec 0xf1 0x57 +0x44 0xfc 0xf1 0x57 + + +#------------------------------------------------------------------------------ +# MLA/MLS +#------------------------------------------------------------------------------ +# CHECK: mla r1, r2, r3, r4 +# CHECK: mls r1, r2, r3, r4 + +0x02 0xfb 0x03 0x41 +0x02 0xfb 0x13 0x41 + + +#------------------------------------------------------------------------------ +# MOV(immediate) +#------------------------------------------------------------------------------ +# CHECK: movs r1, #21 +# CHECK: movs.w r1, #21 +# CHECK: movs.w r8, #21 +# CHECK: movw r0, #65535 +# CHECK: movw r1, #43777 +# CHECK: movw r1, #43792 +# CHECK: mov.w r0, #66846720 +# CHECK: mov.w r0, #66846720 +# CHECK: movs.w r0, #66846720 + +0x15 0x21 +0x5f 0xf0 0x15 0x01 +0x5f 0xf0 0x15 0x08 +0x4f 0xf6 0xff 0x70 +0x4a 0xf6 0x01 0x31 +0x4a 0xf6 0x10 0x31 +0x4f 0xf0 0x7f 0x70 +0x4f 0xf0 0x7f 0x70 +0x5f 0xf0 0x7f 0x70 + +#------------------------------------------------------------------------------ +# MOVT +#------------------------------------------------------------------------------ +# CHECK: movt r3, #7 +# CHECK: movt r6, #65535 +# CHECK: it eq +# CHECK: movteq r4, #4080 + +0xc0 0xf2 0x07 0x03 +0xcf 0xf6 0xff 0x76 +0x08 0xbf +0xc0 0xf6 0xf0 0x74 + +#------------------------------------------------------------------------------ +# MRC/MRC2 +#------------------------------------------------------------------------------ +# CHECK: mrc p14, #0, r1, c1, c2, #4 +# CHECK: mrc2 p14, #0, r1, c1, c2, #4 + +0x11 0xee 0x92 0x1e +0x11 0xfe 0x92 0x1e + + +#------------------------------------------------------------------------------ +# MRRC/MRRC2 +#------------------------------------------------------------------------------ +# CHECK: mrrc p7, #1, r5, r4, c1 +# CHECK: mrrc2 p7, #1, r5, r4, c1 + +0x54 0xec 0x11 0x57 +0x54 0xfc 0x11 0x57 + + +#------------------------------------------------------------------------------ +# MRS +#------------------------------------------------------------------------------ +# CHECK: mrs r8, apsr +# CHECK: mrs r8, spsr + +0xef 0xf3 0x00 0x88 +0xff 0xf3 0x00 0x88 + + +#------------------------------------------------------------------------------ +# MSR +#------------------------------------------------------------------------------ +# CHECK: msr APSR_nzcvq, r1 +# CHECK: msr APSR_g, r2 +# CHECK: msr APSR_nzcvq, r3 +# CHECK: msr APSR_nzcvq, r4 +# CHECK: msr APSR_nzcvqg, r5 +# CHECK: msr CPSR_fc, r6 +# CHECK: msr CPSR_c, r7 +# CHECK: msr CPSR_x, r8 +# CHECK: msr CPSR_fc, r9 +# CHECK: msr CPSR_fc, r11 +# CHECK: msr CPSR_fsx, r12 +# CHECK: msr SPSR_fc, r0 +# CHECK: msr SPSR_fsxc, r5 +# CHECK: msr CPSR_fsxc, r8 + +0x81 0xf3 0x00 0x88 +0x82 0xf3 0x00 0x84 +0x83 0xf3 0x00 0x88 +0x84 0xf3 0x00 0x88 +0x85 0xf3 0x00 0x8c +0x86 0xf3 0x00 0x89 +0x87 0xf3 0x00 0x81 +0x88 0xf3 0x00 0x82 +0x89 0xf3 0x00 0x89 +0x8b 0xf3 0x00 0x89 +0x8c 0xf3 0x00 0x8e +0x90 0xf3 0x00 0x89 +0x95 0xf3 0x00 0x8f +0x88 0xf3 0x00 0x8f + + +#------------------------------------------------------------------------------ +# MUL +#------------------------------------------------------------------------------ +# CHECK: muls r3, r4, r3 +# CHECK: mul r3, r4, r3 +# CHECK: mul r3, r4, r6 +# CHECK: it eq +# CHECK: muleq r3, r4, r5 + +0x63 0x43 +0x04 0xfb 0x03 0xf3 +0x04 0xfb 0x06 0xf3 +0x08 0xbf +0x04 0xfb 0x05 0xf3 + + +#------------------------------------------------------------------------------ +# MVN(immediate) +#------------------------------------------------------------------------------ +# CHECK: mvns r8, #21 +# CHECK: mvn r0, #66846720 +# CHECK: mvns r0, #66846720 +# CHECK: itte eq +# CHECK: mvnseq r1, #12 +# CHECK: mvneq r1, #12 +# CHECK: mvnne r1, #12 + +0x7f 0xf0 0x15 0x08 +0x6f 0xf0 0x7f 0x70 +0x7f 0xf0 0x7f 0x70 +0x06 0xbf +0x7f 0xf0 0x0c 0x01 +0x6f 0xf0 0x0c 0x01 +0x6f 0xf0 0x0c 0x01 + + +#------------------------------------------------------------------------------ +# MVN(register) +#------------------------------------------------------------------------------ +# CHECK: mvn.w r2, r3 +# CHECK: mvns r2, r3 +# CHECK: mvn.w r5, r6, lsl #19 +# CHECK: mvn.w r5, r6, lsr #9 +# CHECK: mvn.w r5, r6, asr #4 +# CHECK: mvn.w r5, r6, ror #6 +# CHECK: mvn.w r5, r6, rrx +# CHECK: it eq +# CHECK: mvneq r2, r3 + +0x6f 0xea 0x03 0x02 +0xda 0x43 +0x6f 0xea 0xc6 0x45 +0x6f 0xea 0x56 0x25 +0x6f 0xea 0x26 0x15 +0x6f 0xea 0xb6 0x15 +0x6f 0xea 0x36 0x05 +0x08 0xbf +0xda 0x43 + +#------------------------------------------------------------------------------ +# NOP +#------------------------------------------------------------------------------ +# CHECK: nop.w + +0xaf 0xf3 0x00 0x80 + + +#------------------------------------------------------------------------------ +# ORN +#------------------------------------------------------------------------------ +# CHECK: orn r4, r5, #61440 +# CHECK: orn r4, r5, r6 +# CHECK: orns r4, r5, r6 +# CHECK: orn r4, r5, r6, lsl #5 +# CHECK: orns r4, r5, r6, lsr #5 +# CHECK: orn r4, r5, r6, lsr #5 +# CHECK: orns r4, r5, r6, asr #5 +# CHECK: orn r4, r5, r6, ror #5 + +0x65 0xf4 0x70 0x44 +0x65 0xea 0x06 0x04 +0x75 0xea 0x06 0x04 +0x65 0xea 0x46 0x14 +0x75 0xea 0x56 0x14 +0x65 0xea 0x56 0x14 +0x75 0xea 0x66 0x14 +0x65 0xea 0x76 0x14 + + +#------------------------------------------------------------------------------ +# ORR +#------------------------------------------------------------------------------ +# CHECK: orr r4, r5, #61440 +# CHECK: orr.w r4, r5, r6 +# CHECK: orr.w r4, r5, r6, lsl #5 +# CHECK: orrs.w r4, r5, r6, lsr #5 +# CHECK: orr.w r4, r5, r6, lsr #5 +# CHECK: orrs.w r4, r5, r6, asr #5 +# CHECK: orr.w r4, r5, r6, ror #5 + +0x45 0xf4 0x70 0x44 +0x45 0xea 0x06 0x04 +0x45 0xea 0x46 0x14 +0x55 0xea 0x56 0x14 +0x45 0xea 0x56 0x14 +0x55 0xea 0x66 0x14 +0x45 0xea 0x76 0x14 + + +#------------------------------------------------------------------------------ +# PKH +#------------------------------------------------------------------------------ +# CHECK: pkhbt r2, r2, r3 +# CHECK: pkhbt r2, r2, r3, lsl #31 +# CHECK: pkhbt r2, r2, r3, lsl #15 + +# CHECK: pkhtb r2, r2, r3, asr #31 +# CHECK: pkhtb r2, r2, r3, asr #15 + +0xc2 0xea 0x03 0x02 +0xc2 0xea 0xc3 0x72 +0xc2 0xea 0xc3 0x32 + +0xc2 0xea 0xe3 0x72 +0xc2 0xea 0xe3 0x32 + + +#------------------------------------------------------------------------------ +# PLD(immediate) +#------------------------------------------------------------------------------ +# CHECK: pld [r5, #-4] +# CHECK: pld [r6, #32] +# CHECK: pld [r6, #33] +# CHECK: pld [r6, #257] +# CHECK: pld [r7, #257] + +0x15 0xf8 0x04 0xfc +0x96 0xf8 0x20 0xf0 +0x96 0xf8 0x21 0xf0 +0x96 0xf8 0x01 0xf1 +0x97 0xf8 0x01 0xf1 + +#------------------------------------------------------------------------------ +# PLD(register) +#------------------------------------------------------------------------------ +# CHECK: pld [r8, r1] +# CHECK: pld [r5, r2] +# CHECK: pld [r0, r2, lsl #3] +# CHECK: pld [r8, r2, lsl #2] +# CHECK: pld [sp, r2, lsl #1] +# CHECK: pld [sp, r2] + +0x18 0xf8 0x01 0xf0 +0x15 0xf8 0x02 0xf0 +0x10 0xf8 0x32 0xf0 +0x18 0xf8 0x22 0xf0 +0x1d 0xf8 0x12 0xf0 +0x1d 0xf8 0x02 0xf0 + +#------------------------------------------------------------------------------ +# PLI(immediate) +#------------------------------------------------------------------------------ +# CHECK: pli [r5, #-4] +# CHECK: pli [r6, #32] +# CHECK: pli [r6, #33] +# CHECK: pli [r6, #257] +# CHECK: pli [r7, #257] + +0x15 0xf9 0x04 0xfc +0x96 0xf9 0x20 0xf0 +0x96 0xf9 0x21 0xf0 +0x96 0xf9 0x01 0xf1 +0x97 0xf9 0x01 0xf1 + +#------------------------------------------------------------------------------ +# PLI(register) +#------------------------------------------------------------------------------ +# CHECK: pli [r8, r1] +# CHECK: pli [r5, r2] +# CHECK: pli [r0, r2, lsl #3] +# CHECK: pli [r8, r2, lsl #2] +# CHECK: pli [sp, r2, lsl #1] +# CHECK: pli [sp, r2] + +0x18 0xf9 0x01 0xf0 +0x15 0xf9 0x02 0xf0 +0x10 0xf9 0x32 0xf0 +0x18 0xf9 0x22 0xf0 +0x1d 0xf9 0x12 0xf0 +0x1d 0xf9 0x02 0xf0 + + +#------------------------------------------------------------------------------ +# QADD/QADD16/QADD8 +#------------------------------------------------------------------------------ +# CHECK: qadd r1, r2, r3 +# CHECK: qadd16 r1, r2, r3 +# CHECK: qadd8 r1, r2, r3 +# CHECK: itte gt +# CHECK: qaddgt r1, r2, r3 +# CHECK: qadd16gt r1, r2, r3 +# CHECK: qadd8le r1, r2, r3 + +0x83 0xfa 0x82 0xf1 +0x92 0xfa 0x13 0xf1 +0x82 0xfa 0x13 0xf1 +0xc6 0xbf +0x83 0xfa 0x82 0xf1 +0x92 0xfa 0x13 0xf1 +0x82 0xfa 0x13 0xf1 + + +#------------------------------------------------------------------------------ +# QDADD/QDSUB +#------------------------------------------------------------------------------ +# CHECK: qdadd r6, r7, r8 +# CHECK: qdsub r6, r7, r8 +# CHECK: itt hi +# CHECK: qdaddhi r6, r7, r8 +# CHECK: qdsubhi r6, r7, r8 + +0x88 0xfa 0x97 0xf6 +0x88 0xfa 0xb7 0xf6 +0x84 0xbf +0x88 0xfa 0x97 0xf6 +0x88 0xfa 0xb7 0xf6 + + +#------------------------------------------------------------------------------ +# QSAX +#------------------------------------------------------------------------------ +# CHECK: qsax r9, r12, r0 +# CHECK: it eq +# CHECK: qsaxeq r9, r12, r0 + +0xec 0xfa 0x10 0xf9 +0x08 0xbf +0xec 0xfa 0x10 0xf9 + + +#------------------------------------------------------------------------------ +# QSUB/QSUB16/QSUB8 +#------------------------------------------------------------------------------ +# CHECK: qsub r1, r2, r3 +# CHECK: qsub16 r1, r2, r3 +# CHECK: qsub8 r1, r2, r3 +# CHECK: itet le +# CHECK: qsuble r1, r2, r3 +# CHECK: qsub16gt r1, r2, r3 +# CHECK: qsub8le r1, r2, r3 + +0x83 0xfa 0xa2 0xf1 +0xd2 0xfa 0x13 0xf1 +0xc2 0xfa 0x13 0xf1 +0xd6 0xbf +0x83 0xfa 0xa2 0xf1 +0xd2 0xfa 0x13 0xf1 +0xc2 0xfa 0x13 0xf1 + + +#------------------------------------------------------------------------------ +# RBIT +#------------------------------------------------------------------------------ +# CHECK: rbit r1, r2 +# CHECK: it ne +# CHECK: rbitne r1, r2 + +0x92 0xfa 0xa2 0xf1 +0x18 0xbf +0x92 0xfa 0xa2 0xf1 + + +#------------------------------------------------------------------------------ +# REV +#------------------------------------------------------------------------------ +# CHECK: rev.w r1, r2 +# CHECK: rev.w r2, r8 +# CHECK: itt ne +# CHECK: revne r1, r2 +# CHECK: revne.w r1, r8 + +0x92 0xfa 0x82 0xf1 +0x98 0xfa 0x88 0xf2 +0x1c 0xbf +0x11 0xba +0x98 0xfa 0x88 0xf1 + + +#------------------------------------------------------------------------------ +# REV16 +#------------------------------------------------------------------------------ +# CHECK: rev16.w r1, r2 +# CHECK: rev16.w r2, r8 +# CHECK: itt ne +# CHECK: rev16ne r1, r2 +# CHECK: rev16ne.w r1, r8 + +0x92 0xfa 0x92 0xf1 +0x98 0xfa 0x98 0xf2 +0x1c 0xbf +0x51 0xba +0x98 0xfa 0x98 0xf1 + + +#------------------------------------------------------------------------------ +# REVSH +#------------------------------------------------------------------------------ +# CHECK: revsh.w r1, r2 +# CHECK: revsh.w r2, r8 +# CHECK: itt ne +# CHECK: revshne r1, r2 +# CHECK: revshne.w r1, r8 + +0x92 0xfa 0xb2 0xf1 +0x98 0xfa 0xb8 0xf2 +0x1c 0xbf +0xd1 0xba +0x98 0xfa 0xb8 0xf1 + + +#------------------------------------------------------------------------------ +# ROR (immediate) +#------------------------------------------------------------------------------ +# CHECK: ror.w r2, r3, #12 +# CHECK: rors.w r8, r3, #31 +# CHECK: rors.w r2, r3, #1 +# CHECK: ror.w r2, r3, #4 +# CHECK: rors.w r2, r12, #15 + +# CHECK: ror.w r3, r3, #19 +# CHECK: rors.w r8, r8, #2 +# CHECK: rors.w r7, r7, #5 +# CHECK: ror.w r12, r12, #21 + +0x4f 0xea 0x33 0x32 +0x5f 0xea 0xf3 0x78 +0x5f 0xea 0x73 0x02 +0x4f 0xea 0x33 0x12 +0x5f 0xea 0xfc 0x32 + +0x4f 0xea 0xf3 0x43 +0x5f 0xea 0xb8 0x08 +0x5f 0xea 0x77 0x17 +0x4f 0xea 0x7c 0x5c + + +#------------------------------------------------------------------------------ +# ROR (register) +#------------------------------------------------------------------------------ +# CHECK: ror.w r3, r4, r2 +# CHECK: ror.w r1, r1, r2 +# CHECK: rors.w r3, r4, r8 + +0x64 0xfa 0x02 0xf3 +0x61 0xfa 0x02 0xf1 +0x74 0xfa 0x08 0xf3 + + +#------------------------------------------------------------------------------ +# RRX +#------------------------------------------------------------------------------ +# CHECK: rrx r1, r2 +# CHECK: rrxs r1, r2 +# CHECK: ite lt +# CHECK: rrxlt r9, r12 +# CHECK: rrxsge r8, r3 + +0x4f 0xea 0x32 0x01 +0x5f 0xea 0x32 0x01 +0xb4 0xbf +0x4f 0xea 0x3c 0x09 +0x5f 0xea 0x33 0x08 + +#------------------------------------------------------------------------------ +# RSB (immediate) +#------------------------------------------------------------------------------ +# CHECK: rsb.w r2, r5, #1044480 +# CHECK: rsbs.w r3, r12, #15 +# CHECK: rsb.w r1, r1, #255 + +0xc5 0xf5 0x7f 0x22 +0xdc 0xf1 0x0f 0x03 +0xc1 0xf1 0xff 0x01 + + +#------------------------------------------------------------------------------ +# RSB (register) +#------------------------------------------------------------------------------ +# CHECK: rsb r4, r4, r8 +# CHECK: rsb r4, r9, r8 +# CHECK: rsb r1, r4, r8, asr #3 +# CHECK: rsbs r2, r1, r7, lsl #1 + +0xc4 0xeb 0x08 0x04 +0xc9 0xeb 0x08 0x04 +0xc4 0xeb 0xe8 0x01 +0xd1 0xeb 0x47 0x02 + + +#------------------------------------------------------------------------------ +# SADD16 +#------------------------------------------------------------------------------ +# CHECK: sadd16 r3, r4, r8 +# CHECK: it ne +# CHECK: sadd16ne r3, r4, r8 + +0x94 0xfa 0x08 0xf3 +0x18 0xbf +0x94 0xfa 0x08 0xf3 + + +#------------------------------------------------------------------------------ +# SADD8 +#------------------------------------------------------------------------------ +# CHECK: sadd8 r3, r4, r8 +# CHECK: it ne +# CHECK: sadd8ne r3, r4, r8 + +0x84 0xfa 0x08 0xf3 +0x18 0xbf +0x84 0xfa 0x08 0xf3 + + +#------------------------------------------------------------------------------ +# SASX +#------------------------------------------------------------------------------ +# CHECK: sasx r9, r2, r7 +# CHECK: it ne +# CHECK: sasxne r2, r5, r6 + +0xa2 0xfa 0x07 0xf9 +0x18 0xbf +0xa5 0xfa 0x06 0xf2 + + +#------------------------------------------------------------------------------ +# SBC (immediate) +#------------------------------------------------------------------------------ +# CHECK: sbc r0, r1, #4 +# CHECK: sbcs r0, r1, #0 +# CHECK: sbc r1, r2, #255 +# CHECK: sbc r3, r7, #5570645 +# CHECK: sbc r8, r12, #2852170240 +# CHECK: sbc r9, r7, #2779096485 +# CHECK: sbc r5, r3, #2264924160 +# CHECK: sbc r4, r2, #2139095040 +# CHECK: sbc r4, r2, #1664 + +0x61 0xf1 0x04 0x00 +0x71 0xf1 0x00 0x00 +0x62 0xf1 0xff 0x01 +0x67 0xf1 0x55 0x13 +0x6c 0xf1 0xaa 0x28 +0x67 0xf1 0xa5 0x39 +0x63 0xf1 0x07 0x45 +0x62 0xf1 0xff 0x44 +0x62 0xf5 0xd0 0x64 + + +#------------------------------------------------------------------------------ +# SBC (register) +#------------------------------------------------------------------------------ +# CHECK: sbc.w r4, r5, r6 +# CHECK: sbcs.w r4, r5, r6 +# CHECK: sbc.w r9, r1, r3 +# CHECK: sbcs.w r9, r1, r3 +# CHECK: sbc.w r0, r1, r3, ror #4 +# CHECK: sbcs.w r0, r1, r3, lsl #7 +# CHECK: sbc.w r0, r1, r3, lsr #31 +# CHECK: sbcs.w r0, r1, r3, asr #32 + +0x65 0xeb 0x06 0x04 +0x75 0xeb 0x06 0x04 +0x61 0xeb 0x03 0x09 +0x71 0xeb 0x03 0x09 +0x61 0xeb 0x33 0x10 +0x71 0xeb 0xc3 0x10 +0x61 0xeb 0xd3 0x70 +0x71 0xeb 0x23 0x00 + + +#------------------------------------------------------------------------------ +# SBFX +#------------------------------------------------------------------------------ +# CHECK: sbfx r4, r5, #16, #1 +# CHECK: it gt +# CHECK: sbfxgt r4, r5, #16, #16 + +0x45 0xf3 0x00 0x44 +0xc8 0xbf +0x45 0xf3 0x0f 0x44 + + +#------------------------------------------------------------------------------ +# SEL +#------------------------------------------------------------------------------ +# CHECK: sel r5, r9, r2 +# CHECK: it le +# CHECK: selle r5, r9, r2 + +0xa9 0xfa 0x82 0xf5 +0xd8 0xbf +0xa9 0xfa 0x82 0xf5 + + +#------------------------------------------------------------------------------ +# SEV +#------------------------------------------------------------------------------ +# CHECK: sev.w +# CHECK: it eq +# CHECK: seveq.w + +0xaf 0xf3 0x04 0x80 +0x08 0xbf +0xaf 0xf3 0x04 0x80 + + +#------------------------------------------------------------------------------ +# SADD16/SADD8 +#------------------------------------------------------------------------------ +# CHECK: sadd16 r1, r2, r3 +# CHECK: sadd8 r1, r2, r3 +# CHECK: ite gt +# CHECK: sadd16gt r1, r2, r3 +# CHECK: sadd8le r1, r2, r3 + +0x92 0xfa 0x03 0xf1 +0x82 0xfa 0x03 0xf1 +0xcc 0xbf +0x92 0xfa 0x03 0xf1 +0x82 0xfa 0x03 0xf1 + + +#------------------------------------------------------------------------------ +# SHASX +#------------------------------------------------------------------------------ +# CHECK: shasx r4, r8, r2 +# CHECK: it gt +# CHECK: shasxgt r4, r8, r2 + +0xa8 0xfa 0x22 0xf4 +0xc8 0xbf +0xa8 0xfa 0x22 0xf4 + + +#------------------------------------------------------------------------------ +# SHASX +#------------------------------------------------------------------------------ +# CHECK: shsax r4, r8, r2 +# CHECK: it gt +# CHECK: shsaxgt r4, r8, r2 + +0xe8 0xfa 0x22 0xf4 +0xc8 0xbf +0xe8 0xfa 0x22 0xf4 + + +#------------------------------------------------------------------------------ +# SHSUB16/SHSUB8 +#------------------------------------------------------------------------------ +# CHECK: shsub16 r4, r8, r2 +# CHECK: shsub8 r4, r8, r2 +# CHECK: itt gt +# CHECK: shsub16gt r4, r8, r2 +# CHECK: shsub8gt r4, r8, r2 + +0xd8 0xfa 0x22 0xf4 +0xc8 0xfa 0x22 0xf4 +0xc4 0xbf +0xd8 0xfa 0x22 0xf4 +0xc8 0xfa 0x22 0xf4 + + +#------------------------------------------------------------------------------ +# SMLABB/SMLABT/SMLATB/SMLATT +#------------------------------------------------------------------------------ +# CHECK: smlabb r3, r1, r9, r0 +# CHECK: smlabt r5, r6, r4, r1 +# CHECK: smlatb r4, r2, r3, r2 +# CHECK: smlatt r8, r3, r8, r4 +# CHECK: itete gt +# CHECK: smlabbgt r3, r1, r9, r0 +# CHECK: smlabtle r5, r6, r4, r1 +# CHECK: smlatbgt r4, r2, r3, r2 +# CHECK: smlattle r8, r3, r8, r4 + +0x11 0xfb 0x09 0x03 +0x16 0xfb 0x14 0x15 +0x12 0xfb 0x23 0x24 +0x13 0xfb 0x38 0x48 +0xcb 0xbf +0x11 0xfb 0x09 0x03 +0x16 0xfb 0x14 0x15 +0x12 0xfb 0x23 0x24 +0x13 0xfb 0x38 0x48 + + +#------------------------------------------------------------------------------ +# SMLAD/SMLADX +#------------------------------------------------------------------------------ +# CHECK: smlad r2, r3, r5, r8 +# CHECK: smladx r2, r3, r5, r8 +# CHECK: itt hi +# CHECK: smladhi r2, r3, r5, r8 +# CHECK: smladxhi r2, r3, r5, r8 + +0x23 0xfb 0x05 0x82 +0x23 0xfb 0x15 0x82 +0x84 0xbf +0x23 0xfb 0x05 0x82 +0x23 0xfb 0x15 0x82 + + +#------------------------------------------------------------------------------ +# SMLAL +#------------------------------------------------------------------------------ +# CHECK: smlal r2, r3, r5, r8 +# CHECK: it eq +# CHECK: smlaleq r2, r3, r5, r8 + +0xc5 0xfb 0x08 0x23 +0x08 0xbf +0xc5 0xfb 0x08 0x23 + + +#------------------------------------------------------------------------------ +# SMLALBB/SMLALBT/SMLALTB/SMLALTT +#------------------------------------------------------------------------------ +# CHECK: smlalbb r3, r1, r9, r0 +# CHECK: smlalbt r5, r6, r4, r1 +# CHECK: smlaltb r4, r2, r3, r2 +# CHECK: smlaltt r8, r3, r8, r4 +# CHECK: iteet ge +# CHECK: smlalbbge r3, r1, r9, r0 +# CHECK: smlalbtlt r5, r6, r4, r1 +# CHECK: smlaltblt r4, r2, r3, r2 +# CHECK: smlalttge r8, r3, r8, r4 + +0xc9 0xfb 0x80 0x31 +0xc4 0xfb 0x91 0x56 +0xc3 0xfb 0xa2 0x42 +0xc8 0xfb 0xb4 0x83 +0xad 0xbf +0xc9 0xfb 0x80 0x31 +0xc4 0xfb 0x91 0x56 +0xc3 0xfb 0xa2 0x42 +0xc8 0xfb 0xb4 0x83 + +#------------------------------------------------------------------------------ +# SMLALD/SMLALDX +#------------------------------------------------------------------------------ +# CHECK: smlald r2, r3, r5, r8 +# CHECK: smlaldx r2, r3, r5, r8 +# CHECK: ite eq +# CHECK: smlaldeq r2, r3, r5, r8 +# CHECK: smlaldxne r2, r3, r5, r8 + +0xc5 0xfb 0xc8 0x23 +0xc5 0xfb 0xd8 0x23 +0x0c 0xbf +0xc5 0xfb 0xc8 0x23 +0xc5 0xfb 0xd8 0x23 + + +#------------------------------------------------------------------------------ +# SMLAWB/SMLAWT +#------------------------------------------------------------------------------ +# CHECK: smlawb r2, r3, r10, r8 +# CHECK: smlawt r8, r3, r5, r9 +# CHECK: ite eq +# CHECK: smlawbeq r2, r7, r5, r8 +# CHECK: smlawtne r1, r3, r0, r8 + +0x33 0xfb 0x0a 0x82 +0x33 0xfb 0x15 0x98 +0x0c 0xbf +0x37 0xfb 0x05 0x82 +0x33 0xfb 0x10 0x81 + + +#------------------------------------------------------------------------------ +# SMLSD/SMLSDX +#------------------------------------------------------------------------------ +# CHECK: smlsd r2, r3, r5, r8 +# CHECK: smlsdx r2, r3, r5, r8 +# CHECK: ite le +# CHECK: smlsdle r2, r3, r5, r8 +# CHECK: smlsdxgt r2, r3, r5, r8 + +0x43 0xfb 0x05 0x82 +0x43 0xfb 0x15 0x82 +0xd4 0xbf +0x43 0xfb 0x05 0x82 +0x43 0xfb 0x15 0x82 + + +#------------------------------------------------------------------------------ +# SMLSLD/SMLSLDX +#------------------------------------------------------------------------------ +# CHECK: smlsld r2, r9, r5, r1 +# CHECK: smlsldx r4, r11, r2, r8 +# CHECK: ite ge +# CHECK: smlsldge r8, r2, r5, r6 +# CHECK: smlsldxlt r1, r0, r3, r8 + +0xd5 0xfb 0xc1 0x29 +0xd2 0xfb 0xd8 0x4b +0xac 0xbf +0xd5 0xfb 0xc6 0x82 +0xd3 0xfb 0xd8 0x10 + + +#------------------------------------------------------------------------------ +# SMMLA/SMMLAR +#------------------------------------------------------------------------------ +# CHECK: smmla r1, r2, r3, r4 +# CHECK: smmlar r4, r3, r2, r1 +# CHECK: ite lo +# CHECK: smmlalo r1, r2, r3, r4 +# CHECK: smmlarhs r4, r3, r2, r1 + +0x52 0xfb 0x03 0x41 +0x53 0xfb 0x12 0x14 +0x34 0xbf +0x52 0xfb 0x03 0x41 +0x53 0xfb 0x12 0x14 + + +#------------------------------------------------------------------------------ +# SMMLS/SMMLSR +#------------------------------------------------------------------------------ +# CHECK: smmls r1, r2, r3, r4 +# CHECK: smmlsr r4, r3, r2, r1 +# CHECK: ite lo +# CHECK: smmlslo r1, r2, r3, r4 +# CHECK: smmlsrhs r4, r3, r2, r1 + +0x62 0xfb 0x03 0x41 +0x63 0xfb 0x12 0x14 +0x34 0xbf +0x62 0xfb 0x03 0x41 +0x63 0xfb 0x12 0x14 + +#------------------------------------------------------------------------------ +# SSAT +#------------------------------------------------------------------------------ +# CHECK: ssat r9, #30, r0, asr #2 + +0x20 0xf3 0x9d 0x09 + +#------------------------------------------------------------------------------ +# STR (immediate) +#------------------------------------------------------------------------------ +# CHECK: str r10, [r11], #0 + +0x4b 0xf8 0x00 0xab + +#------------------------------------------------------------------------------ +# STRD (immediate) +#------------------------------------------------------------------------------ +# CHECK: strd r6, r3, [r5], #-8 +# CHECK: strd r8, r5, [r5]{{$}} +# CHECK: strd r7, r4, [r5], #-4 + +0x65 0xe8 0x02 0x63 +0x65 0xe8 0x00 0x85 +0x65 0xe8 0x01 0x74 + +#------------------------------------------------------------------------------ +# STREX/STREXB/STREXH/STREXD +#------------------------------------------------------------------------------ +# CHECK: strex r1, r8, [r4] +# CHECK: strex r8, r2, [r4] +# CHECK: strex r2, r12, [sp, #128] +# CHECK: strexb r5, r1, [r7] +# CHECK: strexh r9, r7, [r12] +# CHECK: strexd r9, r3, r6, [r4] + +0x44 0xe8 0x00 0x81 +0x44 0xe8 0x00 0x28 +0x4d 0xe8 0x20 0xc2 +0xc7 0xe8 0x45 0x1f +0xcc 0xe8 0x59 0x7f +0xc4 0xe8 0x79 0x36 + + +#------------------------------------------------------------------------------ +# STRH(immediate) +#------------------------------------------------------------------------------ +# CHECK: strh r5, [r5, #-4] +# CHECK: strh r5, [r6, #32] +# CHECK: strh.w r5, [r6, #33] +# CHECK: strh.w r5, [r6, #257] +# CHECK: strh.w lr, [r7, #257] +# CHECK: strh r5, [r8, #255]! +# CHECK: strh r2, [r5, #4]! +# CHECK: strh r1, [r4, #-4]! +# CHECK: strh lr, [r3], #255 +# CHECK: strh r9, [r2], #4 +# CHECK: strh r3, [sp], #-4 + +0x25 0xf8 0x04 0x5c +0x35 0x84 +0xa6 0xf8 0x21 0x50 +0xa6 0xf8 0x01 0x51 +0xa7 0xf8 0x01 0xe1 +0x28 0xf8 0xff 0x5f +0x25 0xf8 0x04 0x2f +0x24 0xf8 0x04 0x1d +0x23 0xf8 0xff 0xeb +0x22 0xf8 0x04 0x9b +0x2d 0xf8 0x04 0x39 + + +#------------------------------------------------------------------------------ +# STRH(register) +#------------------------------------------------------------------------------ +# CHECK: strh.w r1, [r8, r1] +# CHECK: strh.w r4, [r5, r2] +# CHECK: strh.w r6, [r0, r2, lsl #3] +# CHECK: strh.w r8, [r8, r2, lsl #2] +# CHECK: strh.w r7, [sp, r2, lsl #1] +# CHECK: strh.w r7, [sp, r2] + +0x28 0xf8 0x01 0x10 +0x25 0xf8 0x02 0x40 +0x20 0xf8 0x32 0x60 +0x28 0xf8 0x22 0x80 +0x2d 0xf8 0x12 0x70 +0x2d 0xf8 0x02 0x70 + + +#------------------------------------------------------------------------------ +# STRHT +#------------------------------------------------------------------------------ +# CHECK: strht r1, [r2] +# CHECK: strht r1, [r8] +# CHECK: strht r1, [r8, #3] +# CHECK: strht r1, [r8, #255] + +0x22 0xf8 0x00 0x1e +0x28 0xf8 0x00 0x1e +0x28 0xf8 0x03 0x1e +0x28 0xf8 0xff 0x1e + + +#------------------------------------------------------------------------------ +# STRT +#------------------------------------------------------------------------------ +# CHECK: strt r1, [r2] +# CHECK: strt r1, [r8] +# CHECK: strt r1, [r8, #3] +# CHECK: strt r1, [r8, #255] + +0x42 0xf8 0x00 0x1e +0x48 0xf8 0x00 0x1e +0x48 0xf8 0x03 0x1e +0x48 0xf8 0xff 0x1e + + +#------------------------------------------------------------------------------ +# SUB (immediate) +#------------------------------------------------------------------------------ +# CHECK: itet eq +# CHECK: subeq r1, r2, #4 +# CHECK: subwne r5, r3, #1023 +# CHECK: subweq r4, r5, #293 +# CHECK: sub.w r2, sp, #1024 +# CHECK: sub.w r2, r8, #65280 +# CHECK: subw r2, r3, #257 +# CHECK: sub.w r12, r6, #256 +# CHECK: subw r12, r6, #256 +# CHECK: subs.w r1, r2, #496 + +0x0a 0xbf +0x11 0x1f +0xa3 0xf2 0xff 0x35 +0xa5 0xf2 0x25 0x14 +0xad 0xf5 0x80 0x62 +0xa8 0xf5 0x7f 0x42 +0xa3 0xf2 0x01 0x12 +0xa6 0xf5 0x80 0x7c +0xa6 0xf2 0x00 0x1c +0xb2 0xf5 0xf8 0x71 + + +#------------------------------------------------------------------------------ +# SUB (register) +#------------------------------------------------------------------------------ +# CHECK: sub.w r4, r5, r6 +# CHECK: sub.w r4, r5, r6, lsl #5 +# CHECK: sub.w r4, r5, r6, lsr #5 +# CHECK: sub.w r4, r5, r6, lsr #5 +# CHECK: sub.w r4, r5, r6, asr #5 +# CHECK: sub.w r4, r5, r6, ror #5 +# CHECK: sub.w r5, r2, r12, rrx + +0xa5 0xeb 0x06 0x04 +0xa5 0xeb 0x46 0x14 +0xa5 0xeb 0x56 0x14 +0xa5 0xeb 0x56 0x14 +0xa5 0xeb 0x66 0x14 +0xa5 0xeb 0x76 0x14 +0xa2 0xeb 0x3c 0x05 + + +#------------------------------------------------------------------------------ +# SVC +#------------------------------------------------------------------------------ +# CHECK: svc #0 +# CHECK: ite eq +# CHECK: svceq #255 +# CHECK: svcne #33 + +0x00 0xdf +0x0c 0xbf +0xff 0xdf +0x21 0xdf + +#------------------------------------------------------------------------------ +# SXTAB +#------------------------------------------------------------------------------ +# CHECK: sxtab r2, r3, r4 +# CHECK: sxtab r4, r5, r6 +# CHECK: it lt +# CHECK: sxtablt r6, r2, r9, ror #8 +# CHECK: sxtab r5, r1, r4, ror #16 +# CHECK: sxtab r7, r8, r3, ror #24 + +0x43 0xfa 0x84 0xf2 +0x45 0xfa 0x86 0xf4 +0xb8 0xbf +0x42 0xfa 0x99 0xf6 +0x41 0xfa 0xa4 0xf5 +0x48 0xfa 0xb3 0xf7 + + +#------------------------------------------------------------------------------ +# SXTAB16 +#------------------------------------------------------------------------------ +# CHECK: sxtab16 r6, r2, r7 +# CHECK: sxtab16 r3, r5, r8, ror #8 +# CHECK: sxtab16 r3, r2, r1, ror #16 +# CHECK: ite ne +# CHECK: sxtab16ne r0, r1, r4 +# CHECK: sxtab16eq r1, r2, r3, ror #24 + +0x22 0xfa 0x87 0xf6 +0x25 0xfa 0x98 0xf3 +0x22 0xfa 0xa1 0xf3 +0x14 0xbf +0x21 0xfa 0x84 0xf0 +0x22 0xfa 0xb3 0xf1 + + +#------------------------------------------------------------------------------ +# SXTAH +#------------------------------------------------------------------------------ +# CHECK: sxtah r1, r3, r9 +# CHECK: sxtah r3, r8, r3, ror #8 +# CHECK: sxtah r9, r3, r3, ror #24 +# CHECK: ite hi +# CHECK: sxtahhi r6, r1, r6 +# CHECK: sxtahls r2, r2, r4, ror #16 + +0x03 0xfa 0x89 0xf1 +0x08 0xfa 0x93 0xf3 +0x03 0xfa 0xb3 0xf9 +0x8c 0xbf +0x01 0xfa 0x86 0xf6 +0x02 0xfa 0xa4 0xf2 + + +#------------------------------------------------------------------------------ +# SXTB +#------------------------------------------------------------------------------ +# CHECK: sxtb r5, r6 +# CHECK: sxtb.w r6, r9, ror #8 +# CHECK: sxtb.w r8, r3, ror #24 +# CHECK: ite ge +# CHECK: sxtbge r2, r4 +# CHECK: sxtblt.w r5, r1, ror #16 + +0x75 0xb2 +0x4f 0xfa 0x99 0xf6 +0x4f 0xfa 0xb3 0xf8 +0xac 0xbf +0x62 0xb2 +0x4f 0xfa 0xa1 0xf5 + + +#------------------------------------------------------------------------------ +# SXTB16 +#------------------------------------------------------------------------------ +# CHECK: sxtb16 r1, r4 +# CHECK: sxtb16 r6, r7 +# CHECK: sxtb16 r3, r1, ror #16 +# CHECK: ite hs +# CHECK: sxtb16hs r3, r5, ror #8 +# CHECK: sxtb16lo r2, r3, ror #24 + +0x2f 0xfa 0x84 0xf1 +0x2f 0xfa 0x87 0xf6 +0x2f 0xfa 0xa1 0xf3 +0x2c 0xbf +0x2f 0xfa 0x95 0xf3 +0x2f 0xfa 0xb3 0xf2 + + +#------------------------------------------------------------------------------ +# SXTH +#------------------------------------------------------------------------------ +# CHECK: sxth r1, r6 +# CHECK: sxth.w r3, r8, ror #8 +# CHECK: sxth.w r9, r3, ror #24 +# CHECK: itt ne +# CHECK: sxthne.w r3, r9 +# CHECK: sxthne.w r2, r2, ror #16 + +0x31 0xb2 +0x0f 0xfa 0x98 0xf3 +0x0f 0xfa 0xb3 0xf9 +0x1c 0xbf +0x0f 0xfa 0x89 0xf3 +0x0f 0xfa 0xa2 0xf2 + + +#------------------------------------------------------------------------------ +# SXTB +#------------------------------------------------------------------------------ +# CHECK: sxtb r5, r6 +# CHECK: sxtb.w r6, r9, ror #8 +# CHECK: sxtb.w r8, r3, ror #24 +# CHECK: ite ge +# CHECK: sxtbge r2, r4 +# CHECK: sxtblt.w r5, r1, ror #16 + +0x75 0xb2 +0x4f 0xfa 0x99 0xf6 +0x4f 0xfa 0xb3 0xf8 +0xac 0xbf +0x62 0xb2 +0x4f 0xfa 0xa1 0xf5 + + +#------------------------------------------------------------------------------ +# SXTB16 +#------------------------------------------------------------------------------ +# CHECK: sxtb16 r1, r4 +# CHECK: sxtb16 r6, r7 +# CHECK: sxtb16 r3, r1, ror #16 +# CHECK: ite hs +# CHECK: sxtb16hs r3, r5, ror #8 +# CHECK: sxtb16lo r2, r3, ror #24 + +0x2f 0xfa 0x84 0xf1 +0x2f 0xfa 0x87 0xf6 +0x2f 0xfa 0xa1 0xf3 +0x2c 0xbf +0x2f 0xfa 0x95 0xf3 +0x2f 0xfa 0xb3 0xf2 + + +#------------------------------------------------------------------------------ +# SXTH +#------------------------------------------------------------------------------ +# CHECK: sxth r1, r6 +# CHECK: sxth.w r3, r8, ror #8 +# CHECK: sxth.w r9, r3, ror #24 +# CHECK: itt ne +# CHECK: sxthne.w r3, r9 +# CHECK: sxthne.w r2, r2, ror #16 + +0x31 0xb2 +0x0f 0xfa 0x98 0xf3 +0x0f 0xfa 0xb3 0xf9 +0x1c 0xbf +0x0f 0xfa 0x89 0xf3 +0x0f 0xfa 0xa2 0xf2 + + +#------------------------------------------------------------------------------ +# TBB/TBH +#------------------------------------------------------------------------------ +# CHECK: tbb [r3, r8] +# CHECK: tbh [r3, r8, lsl #1] +# CHECK: it eq +# CHECK: tbbeq [r3, r8] +# CHECK: it hs +# CHECK: tbhhs [r3, r8, lsl #1] + +0xd3 0xe8 0x08 0xf0 +0xd3 0xe8 0x18 0xf0 +0x08 0xbf +0xd3 0xe8 0x08 0xf0 +0x28 0xbf +0xd3 0xe8 0x18 0xf0 + + +#------------------------------------------------------------------------------ +# TEQ +#------------------------------------------------------------------------------ +# CHECK: teq.w r5, #61440 +# CHECK: teq.w r4, r5 +# CHECK: teq.w r4, r5, lsl #5 +# CHECK: teq.w r4, r5, lsr #5 +# CHECK: teq.w r4, r5, lsr #5 +# CHECK: teq.w r4, r5, asr #5 +# CHECK: teq.w r4, r5, ror #5 + +0x95 0xf4 0x70 0x4f +0x94 0xea 0x05 0x0f +0x94 0xea 0x45 0x1f +0x94 0xea 0x55 0x1f +0x94 0xea 0x55 0x1f +0x94 0xea 0x65 0x1f +0x94 0xea 0x75 0x1f + + +#------------------------------------------------------------------------------ +# TST +#------------------------------------------------------------------------------ +# CHECK: tst.w r5, #61440 +# CHECK: tst r2, r5 +# CHECK: tst.w r3, r12, lsl #5 +# CHECK: tst.w r4, r11, lsr #4 +# CHECK: tst.w r5, r10, lsr #12 +# CHECK: tst.w r6, r9, asr #30 +# CHECK: tst.w r7, r8, ror #2 + +0x15 0xf4 0x70 0x4f +0x2a 0x42 +0x13 0xea 0x4c 0x1f +0x14 0xea 0x1b 0x1f +0x15 0xea 0x1a 0x3f +0x16 0xea 0xa9 0x7f +0x17 0xea 0xb8 0x0f + + +#------------------------------------------------------------------------------ +# UADD16/UADD8 +#------------------------------------------------------------------------------ +# CHECK: uadd16 r1, r2, r3 +# CHECK: uadd8 r1, r2, r3 +# CHECK: ite gt +# CHECK: uadd16gt r1, r2, r3 +# CHECK: uadd8le r1, r2, r3 + +0x92 0xfa 0x43 0xf1 +0x82 0xfa 0x43 0xf1 +0xcc 0xbf +0x92 0xfa 0x43 0xf1 +0x82 0xfa 0x43 0xf1 + + +#------------------------------------------------------------------------------ +# UASX +#------------------------------------------------------------------------------ +# CHECK: uasx r9, r12, r0 +# CHECK: it eq +# CHECK: uasxeq r9, r12, r0 +# CHECK: uasx r9, r12, r0 +# CHECK: it eq +# CHECK: uasxeq r9, r12, r0 + +0xac 0xfa 0x40 0xf9 +0x08 0xbf +0xac 0xfa 0x40 0xf9 +0xac 0xfa 0x40 0xf9 +0x08 0xbf +0xac 0xfa 0x40 0xf9 + + +#------------------------------------------------------------------------------ +# UBFX +#------------------------------------------------------------------------------ +# CHECK: ubfx r4, r5, #16, #1 +# CHECK: it gt +# CHECK: ubfxgt r4, r5, #16, #16 + +0xc5 0xf3 0x00 0x44 +0xc8 0xbf +0xc5 0xf3 0x0f 0x44 + + +#------------------------------------------------------------------------------ +# UHADD16/UHADD8 +#------------------------------------------------------------------------------ +# CHECK: uhadd16 r4, r8, r2 +# CHECK: uhadd8 r4, r8, r2 +# CHECK: itt gt +# CHECK: uhadd16gt r4, r8, r2 +# CHECK: uhadd8gt r4, r8, r2 + +0x98 0xfa 0x62 0xf4 +0x88 0xfa 0x62 0xf4 +0xc4 0xbf +0x98 0xfa 0x62 0xf4 +0x88 0xfa 0x62 0xf4 + + +#------------------------------------------------------------------------------ +# UHASX/UHSAX +#------------------------------------------------------------------------------ +# CHECK: uhasx r4, r1, r5 +# CHECK: uhsax r5, r6, r6 +# CHECK: itt gt +# CHECK: uhasxgt r6, r9, r8 +# CHECK: uhsaxgt r7, r8, r12 + +0xa1 0xfa 0x65 0xf4 +0xe6 0xfa 0x66 0xf5 +0xc4 0xbf +0xa9 0xfa 0x68 0xf6 +0xe8 0xfa 0x6c 0xf7 + +#------------------------------------------------------------------------------ +# UHSUB16/UHSUB8 +#------------------------------------------------------------------------------ +# CHECK: uhsub16 r5, r8, r3 +# CHECK: uhsub8 r1, r7, r6 +# CHECK: itt lt +# CHECK: uhsub16lt r4, r9, r12 +# CHECK: uhsub8lt r3, r1, r5 + +0xd8 0xfa 0x63 0xf5 +0xc7 0xfa 0x66 0xf1 +0xbc 0xbf +0xd9 0xfa 0x6c 0xf4 +0xc1 0xfa 0x65 0xf3 + + +#------------------------------------------------------------------------------ +# UMAAL +#------------------------------------------------------------------------------ +# CHECK: umaal r3, r4, r5, r6 +# CHECK: it lt +# CHECK: umaallt r3, r4, r5, r6 + +0xe5 0xfb 0x66 0x34 +0xb8 0xbf +0xe5 0xfb 0x66 0x34 + + +#------------------------------------------------------------------------------ +# UMLAL +#------------------------------------------------------------------------------ +# CHECK: umlal r2, r4, r6, r8 +# CHECK: it gt +# CHECK: umlalgt r6, r1, r2, r6 + +0xe6 0xfb 0x08 0x24 +0xc8 0xbf +0xe2 0xfb 0x06 0x61 + + +#------------------------------------------------------------------------------ +# UMULL +#------------------------------------------------------------------------------ +# CHECK: umull r2, r4, r6, r8 +# CHECK: it gt +# CHECK: umullgt r6, r1, r2, r6 + +0xa6 0xfb 0x08 0x24 +0xc8 0xbf +0xa2 0xfb 0x06 0x61 + + +#------------------------------------------------------------------------------ +# UQADD16/UQADD8 +#------------------------------------------------------------------------------ +# CHECK: uqadd16 r1, r2, r3 +# CHECK: uqadd8 r3, r4, r8 +# CHECK: ite gt +# CHECK: uqadd16gt r4, r7, r9 +# CHECK: uqadd8le r8, r1, r2 + +0x92 0xfa 0x53 0xf1 +0x84 0xfa 0x58 0xf3 +0xcc 0xbf +0x97 0xfa 0x59 0xf4 +0x81 0xfa 0x52 0xf8 + + +#------------------------------------------------------------------------------ +# UQASX/UQSAX +#------------------------------------------------------------------------------ +# CHECK: uqasx r1, r2, r3 +# CHECK: uqsax r3, r4, r8 +# CHECK: ite gt +# CHECK: uqasxgt r4, r7, r9 +# CHECK: uqsaxle r8, r1, r2 + +0xa2 0xfa 0x53 0xf1 +0xe4 0xfa 0x58 0xf3 +0xcc 0xbf +0xa7 0xfa 0x59 0xf4 +0xe1 0xfa 0x52 0xf8 + + +#------------------------------------------------------------------------------ +# UQSUB16/UQSUB8 +#------------------------------------------------------------------------------ +# CHECK: uqsub8 r8, r2, r9 +# CHECK: uqsub16 r1, r9, r7 +# CHECK: ite gt +# CHECK: uqsub8gt r3, r1, r6 +# CHECK: uqsub16le r4, r6, r4 + +0xc2 0xfa 0x59 0xf8 +0xd9 0xfa 0x57 0xf1 +0xcc 0xbf +0xc1 0xfa 0x56 0xf3 +0xd6 0xfa 0x54 0xf4 + + +#------------------------------------------------------------------------------ +# UQSUB16/UQSUB8 +#------------------------------------------------------------------------------ +# CHECK: usad8 r1, r9, r7 +# CHECK: usada8 r8, r2, r9, r12 +# CHECK: ite gt +# CHECK: usada8gt r3, r1, r6, r9 +# CHECK: usad8le r4, r6, r4 + +0x79 0xfb 0x07 0xf1 +0x72 0xfb 0x09 0xc8 +0xcc 0xbf +0x71 0xfb 0x06 0x93 +0x76 0xfb 0x04 0xf4 + + +#------------------------------------------------------------------------------ +# USAT +#------------------------------------------------------------------------------ +# CHECK: usat r8, #1, r10 +# CHECK: usat r8, #4, r10 +# CHECK: usat r8, #5, r10, lsl #31 +# CHECK: usat r8, #16, r10, asr #1 + +0x8a 0xf3 0x01 0x08 +0x8a 0xf3 0x04 0x08 +0x8a 0xf3 0xc5 0x78 +0xaa 0xf3 0x50 0x08 + + +#------------------------------------------------------------------------------ +# USAT16 +#------------------------------------------------------------------------------ +# CHECK: usat16 r2, #2, r7 +# CHECK: usat16 r3, #15, r5 + +0xa7 0xf3 0x02 0x02 +0xa5 0xf3 0x0f 0x03 + + +#------------------------------------------------------------------------------ +# USAX +#------------------------------------------------------------------------------ +# CHECK: usax r2, r3, r4 +# CHECK: it ne +# CHECK: usaxne r6, r1, r9 +# CHECK: usax r2, r3, r4 +# CHECK: it ne +# CHECK: usaxne r6, r1, r9 + +0xe3 0xfa 0x44 0xf2 +0x18 0xbf +0xe1 0xfa 0x49 0xf6 +0xe3 0xfa 0x44 0xf2 +0x18 0xbf +0xe1 0xfa 0x49 0xf6 + + +#------------------------------------------------------------------------------ +# USUB16/USUB8 +#------------------------------------------------------------------------------ +# CHECK: usub16 r4, r2, r7 +# CHECK: usub8 r1, r8, r5 +# CHECK: ite hi +# CHECK: usub16hi r1, r1, r3 +# CHECK: usub8ls r9, r2, r3 + +0xd2 0xfa 0x47 0xf4 +0xc8 0xfa 0x45 0xf1 +0x8c 0xbf +0xd1 0xfa 0x43 0xf1 +0xc2 0xfa 0x43 0xf9 + + +#------------------------------------------------------------------------------ +# UXTAB +#------------------------------------------------------------------------------ +# CHECK: uxtab r2, r3, r4 +# CHECK: uxtab r4, r5, r6 +# CHECK: it lt +# CHECK: uxtablt r6, r2, r9, ror #8 +# CHECK: uxtab r5, r1, r4, ror #16 +# CHECK: uxtab r7, r8, r3, ror #24 + +0x53 0xfa 0x84 0xf2 +0x55 0xfa 0x86 0xf4 +0xb8 0xbf +0x52 0xfa 0x99 0xf6 +0x51 0xfa 0xa4 0xf5 +0x58 0xfa 0xb3 0xf7 + + +#------------------------------------------------------------------------------ +# UXTAB16 +#------------------------------------------------------------------------------ +# CHECK: it ge +# CHECK: uxtab16ge r0, r1, r4 +# CHECK: uxtab16 r6, r2, r7 +# CHECK: uxtab16 r3, r5, r8, ror #8 +# CHECK: uxtab16 r3, r2, r1, ror #16 +# CHECK: it eq +# CHECK: uxtab16eq r1, r2, r3, ror #24 + +0xa8 0xbf +0x31 0xfa 0x84 0xf0 +0x32 0xfa 0x87 0xf6 +0x35 0xfa 0x98 0xf3 +0x32 0xfa 0xa1 0xf3 +0x08 0xbf +0x32 0xfa 0xb3 0xf1 + + +#------------------------------------------------------------------------------ +# UXTAH +#------------------------------------------------------------------------------ +# CHECK: uxtah r1, r3, r9 +# CHECK: it hi +# CHECK: uxtahhi r6, r1, r6 +# CHECK: uxtah r3, r8, r3, ror #8 +# CHECK: it lo +# CHECK: uxtahlo r2, r2, r4, ror #16 +# CHECK: uxtah r9, r3, r3, ror #24 + +0x13 0xfa 0x89 0xf1 +0x88 0xbf +0x11 0xfa 0x86 0xf6 +0x18 0xfa 0x93 0xf3 +0x38 0xbf +0x12 0xfa 0xa4 0xf2 +0x13 0xfa 0xb3 0xf9 + + +#------------------------------------------------------------------------------ +# UXTB +#------------------------------------------------------------------------------ +# CHECK: it ge +# CHECK: uxtbge r2, r4 +# CHECK: uxtb r5, r6 +# CHECK: uxtb.w r6, r9, ror #8 +# CHECK: it lo +# CHECK: uxtblo.w r5, r1, ror #16 +# CHECK: uxtb.w r8, r3, ror #24 + +0xa8 0xbf +0xe2 0xb2 +0xf5 0xb2 +0x5f 0xfa 0x99 0xf6 +0x38 0xbf +0x5f 0xfa 0xa1 0xf5 +0x5f 0xfa 0xb3 0xf8 + + +#------------------------------------------------------------------------------ +# UXTB16 +#------------------------------------------------------------------------------ +# CHECK: uxtb16 r1, r4 +# CHECK: uxtb16 r6, r7 +# CHECK: it hs +# CHECK: uxtb16hs r3, r5, ror #8 +# CHECK: uxtb16 r3, r1, ror #16 +# CHECK: it ge +# CHECK: uxtb16ge r2, r3, ror #24 + +0x3f 0xfa 0x84 0xf1 +0x3f 0xfa 0x87 0xf6 +0x28 0xbf +0x3f 0xfa 0x95 0xf3 +0x3f 0xfa 0xa1 0xf3 +0xa8 0xbf +0x3f 0xfa 0xb3 0xf2 + + +#------------------------------------------------------------------------------ +# UXTH +#------------------------------------------------------------------------------ +# CHECK: it ne +# CHECK: uxthne.w r3, r9 +# CHECK: uxth r1, r6 +# CHECK: uxth.w r3, r8, ror #8 +# CHECK: it le +# CHECK: uxthle.w r2, r2, ror #16 +# CHECK: uxth.w r9, r3, ror #24 + +0x18 0xbf +0x1f 0xfa 0x89 0xf3 +0xb1 0xb2 +0x1f 0xfa 0x98 0xf3 +0xd8 0xbf +0x1f 0xfa 0xa2 0xf2 +0x1f 0xfa 0xb3 0xf9 + + +#------------------------------------------------------------------------------ +# WFE/WFI/YIELD +#------------------------------------------------------------------------------ +# CHECK: wfe +# CHECK: wfi +# CHECK: yield +# CHECK: itet lt +# CHECK: wfelt +# CHECK: wfige +# CHECK: yieldlt + +0x20 0xbf +0x30 0xbf +0x10 0xbf +0xb6 0xbf +0x20 0xbf +0x30 0xbf +0x10 0xbf + diff --git a/test/MC/Disassembler/X86/enhanced.txt b/test/MC/Disassembler/X86/enhanced.txt index fc69499..752ab17 100644 --- a/test/MC/Disassembler/X86/enhanced.txt +++ b/test/MC/Disassembler/X86/enhanced.txt @@ -4,3 +4,7 @@ 0x0f 0x85 0xf6 0xff 0xff 0xff # CHECK: [o:movq][w: ][1-r:%gs=r63][1-p::][1-l:8=8][p:,][w: ][0-r:%rcx=r108] <mov> 0:[RCX/108]=0 1:[GS/63]=8 0x65 0x48 0x8b 0x0c 0x25 0x08 0x00 0x00 0x00 +# CHECK: [o:xorps][w: ][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0 +0x0f 0x57 0xd1 +# CHECK: [o:andps][w: ][2-r:%xmm1=r129][p:,][w: ][0-r:%xmm2=r130] 0:[XMM2/130]=0 1:[XMM2/130]=0 2:[XMM1/129]=0 +0x0f 0x54 0xd1 diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt new file mode 100644 index 0000000..54b242d --- /dev/null +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -0,0 +1,79 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 -x86-asm-syntax=intel | FileCheck %s + +# CHECK: movsb +0xa4 + +# CHECK: movsw +0x66 0xa5 + +# CHECK: movsd +0xa5 + +# CHECK: movsq +0x48 0xa5 + +# CHECK: pop FS +0x0f 0xa1 + +# CHECK: pop GS +0x0f 0xa9 + +# CHECK: in AL, DX +0xec + +# CHECK: nop +0x90 + +# CHECK: xchg EAX, R8D +0x41 0x90 + +# CHECK: xchg RAX, R8 +0x49 0x90 + +# CHECK: add AL, 0 +0x04 0x00 + +# CHECK: add AX, 0 +0x66 0x05 0x00 0x00 + +# CHECK: add EAX, 0 +0x05 0x00 0x00 0x00 0x00 + +# CHECK: add RAX, 0 +0x48 0x05 0x00 0x00 0x00 0x00 + +# CHECK: adc AL, 0 +0x14 0x00 + +# CHECK: adc AX, 0 +0x66 0x15 0x00 0x00 + +# CHECK: adc EAX, 0 +0x15 0x00 0x00 0x00 0x00 + +# CHECK: adc RAX, 0 +0x48 0x15 0x00 0x00 0x00 0x00 + +# CHECK: cmp AL, 0 +0x3c 0x00 + +# CHECK: cmp AX, 0 +0x66 0x3d 0x00 0x00 + +# CHECK: cmp EAX, 0 +0x3d 0x00 0x00 0x00 0x00 + +# CHECK: cmp RAX, 0 +0x48 0x3d 0x00 0x00 0x00 0x00 + +# CHECK: test AL, 0 +0xa8 0x00 + +# CHECK: test AX, 0 +0x66 0xa9 0x00 0x00 + +# CHECK: test EAX, 0 +0xa9 0x00 0x00 0x00 0x00 + +# CHECK: test RAX, 0 +0x48 0xa9 0x00 0x00 0x00 0x00 diff --git a/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt b/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt new file mode 100644 index 0000000..9feb54c --- /dev/null +++ b/test/MC/Disassembler/X86/invalid-VEX-vvvv.txt @@ -0,0 +1,4 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64-apple-darwin9 |& grep {invalid instruction encoding} + +# This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s. +0xc5 0xf0 0x50 0xc0 diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 08fb4c5..37cde91 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -72,3 +72,518 @@ # CHECK: vaddps %ymm3, %ymm1, %ymm0 0xc5 0xf4 0x58 0xc3 + +# CHECK: vandpd %ymm13, %ymm1, %ymm0 +0xc4 0xc1 0x75 0x54 0xc5 + +# CHECK: vandps %ymm3, %ymm1, %ymm0 +0xc5 0xf4 0x54 0xc3 + +# CHECK: vzeroall +0xc5 0xfc 0x77 + +# CHECK: vcvtps2pd %xmm0, %ymm0 +0xc5 0xfc 0x5a 0xc0 + +# CHECK: vandps (%rdx), %xmm1, %xmm7 +0xc5 0xf0 0x54 0x3a + +# CHECK: vcvtss2sil %xmm0, %eax +0xc5 0xfa 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %eax +0xc5 0xfb 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %rax +0xc4 0xe1 0xfb 0x2d 0xc0 + +# CHECK: vmaskmovpd %xmm0, %xmm1, (%rax) +0xc4 0xe2 0x71 0x2f 0x00 + +# CHECK: vmovapd %xmm0, %xmm2 +0xc5 0xf9 0x28 0xd0 + +# Check X86 immediates print as signed values by default. radr://8795217 +# CHECK: andq $-16, %rsp +0x48 0x83 0xe4 0xf0 + +# Check these special case instructions that the immediate is not sign-extend. +# CHECK: blendps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0c 0xca 0x81 + +# CHECK: blendpd $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0d 0xca 0x81 + +# CHECK: pblendw $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0e 0xca 0x81 + +# CHECK: mpsadbw $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x42 0xca 0x81 + +# CHECK: dpps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x40 0xca 0x81 + +# CHECK: dppd $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x41 0xca 0x81 + +# CHECK: insertps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x21 0xca 0x81 + +# CHECK: vblendps $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0c 0xca 0x81 + +# CHECK: vblendps $129, (%rax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0c 0x08 0x81 + +# CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0d 0xca 0x81 + +# CHECK: vblendpd $129, (%rax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0d 0x08 0x81 + +# CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x0e 0xca 0x81 + +# CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x42 0xca 0x81 + +# CHECK: vdpps $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x40 0xca 0x81 + +# CHECK: vdpps $129, (%rax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x40 0x08 0x81 + +# CHECK: vdppd $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x41 0xca 0x81 + +# CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1 +0xc4 0xe3 0x69 0x21 0xcb 0x81 + +# CHECK: pause +0xf3 0x90 + +# CHECK: addl %eax, %edi +0x01 0xc7 + +# CHECK: addl %edi, %eax +0x03 0xc7 + +# CHECK: movl %eax, %edi +0x89 0xc7 + +# CHECK: movl %edi, %eax +0x8b 0xc7 + +# CHECK: movups %xmm1, %xmm0 +0x0f 0x10 0xc1 + +# CHECK: movups %xmm0, %xmm1 +0x0f 0x11 0xc1 + +# CHECK: movaps %xmm1, %xmm0 +0x0f 0x28 0xc1 + +# CHECK: movaps %xmm0, %xmm1 +0x0f 0x29 0xc1 + +# CHECK: movupd %xmm1, %xmm0 +0x66 0x0f 0x10 0xc1 + +# CHECK: movupd %xmm0, %xmm1 +0x66 0x0f 0x11 0xc1 + +# CHECK: movapd %xmm1, %xmm0 +0x66 0x0f 0x28 0xc1 + +# CHECK: movapd %xmm0, %xmm1 +0x66 0x0f 0x29 0xc1 + +# CHECK: vmovups %xmm1, %xmm0 +0xc5 0xf8 0x10 0xc1 + +# CHECK: vmovups %xmm0, %xmm1 +0xc5 0xf8 0x11 0xc1 + +# CHECK: vmovaps %xmm1, %xmm0 +0xc5 0xf8 0x28 0xc1 + +# CHECK: vmovaps %xmm0, %xmm1 +0xc5 0xf8 0x29 0xc1 + +# CHECK: vmovupd %xmm1, %xmm0 +0xc5 0xf9 0x10 0xc1 + +# CHECK: vmovupd %xmm0, %xmm1 +0xc5 0xf9 0x11 0xc1 + +# CHECK: vmovapd %xmm1, %xmm0 +0xc5 0xf9 0x28 0xc1 + +# CHECK: vmovapd %xmm0, %xmm1 +0xc5 0xf9 0x29 0xc1 + +# CHECK: vmovups %ymm1, %ymm0 +0xc5 0xfc 0x10 0xc1 + +# CHECK: vmovups %ymm0, %ymm1 +0xc5 0xfc 0x11 0xc1 + +# CHECK: vmovaps %ymm1, %ymm0 +0xc5 0xfc 0x28 0xc1 + +# CHECK: vmovaps %ymm0, %ymm1 +0xc5 0xfc 0x29 0xc1 + +# CHECK: movdqa %xmm1, %xmm0 +0x66 0x0f 0x6f 0xc1 + +# CHECK: movdqa %xmm0, %xmm1 +0x66 0x0f 0x7f 0xc1 + +# CHECK: movdqu %xmm1, %xmm0 +0xf3 0x0f 0x6f 0xc1 + +# CHECK: movdqu %xmm0, %xmm1 +0xf3 0x0f 0x7f 0xc1 + +# CHECK: vmovdqa %xmm1, %xmm0 +0xc5 0xf9 0x6f 0xc1 + +# CHECK: vmovdqa %xmm0, %xmm1 +0xc5 0xf9 0x7f 0xc1 + +# CHECK: vmovdqa %ymm1, %ymm0 +0xc5 0xfd 0x6f 0xc1 + +# CHECK: vmovdqa %ymm0, %ymm1 +0xc5 0xfd 0x7f 0xc1 + +# CHECK: vmovdqu %xmm1, %xmm0 +0xc5 0xfa 0x6f 0xc1 + +# CHECK: vmovdqu %xmm0, %xmm1 +0xc5 0xfa 0x7f 0xc1 + +# CHECK: vmovdqu %ymm1, %ymm0 +0xc5 0xfe 0x6f 0xc1 + +# CHECK: vmovdqu %ymm0, %ymm1 +0xc5 0xfe 0x7f 0xc1 + +# CHECK: vblendvps %xmm4, %xmm1, %xmm2, %xmm3 +0xc4 0xe3 0x69 0x4a 0xd9 0x41 + +# CHECK: vroundpd $0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x09 0xc0 0x00 + +# CHECK: vroundps $0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x08 0xc0 0x00 + +# CHECK: vroundpd $0, %ymm0, %ymm0 +0xc4 0xe3 0x7d 0x09 0xc0 0x00 + +# CHECK: vroundps $0, %ymm0, %ymm0 +0xc4 0xe3 0x7d 0x08 0xc0 0x00 + +# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x0a 0xc0 0x00 + +# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x0b 0xc0 0x00 + +# CHECK: crc32b %al, %eax +0xf2 0x0f 0x38 0xf0 0xc0 + +# CHECK: crc32w %ax, %eax +0x66 0xf2 0x0f 0x38 0xf1 0xc0 + +# CHECK: crc32l %eax, %eax +0xf2 0x0f 0x38 0xf1 0xc0 + +# CHECK: crc32q %rax, %rax +0xf2 0x48 0x0f 0x38 0xf1 0xc0 + +# CHECK: invept (%rax), %rax +0x66 0x0f 0x38 0x80 0x00 + +# CHECK: invvpid (%rax), %rax +0x66 0x0f 0x38 0x81 0x00 + +# CHECK: invpcid (%rax), %rax +0x66 0x0f 0x38 0x82 0x00 + +# CHECK: nop +0x90 + +# CHECK: xchgl %r8d, %eax +0x41 0x90 + +# CHECK: xchgq %r8, %rax +0x49 0x90 + +# CHECK: addb $0, %al +0x04 0x00 + +# CHECK: addw $0, %ax +0x66 0x05 0x00 0x00 + +# CHECK: addl $0, %eax +0x05 0x00 0x00 0x00 0x00 + +# CHECK: addq $0, %rax +0x48 0x05 0x00 0x00 0x00 0x00 + +# CHECK: adcb $0, %al +0x14 0x00 + +# CHECK: adcw $0, %ax +0x66 0x15 0x00 0x00 + +# CHECK: adcl $0, %eax +0x15 0x00 0x00 0x00 0x00 + +# CHECK: adcq $0, %rax +0x48 0x15 0x00 0x00 0x00 0x00 + +# CHECK: cmpb $0, %al +0x3c 0x00 + +# CHECK: cmpw $0, %ax +0x66 0x3d 0x00 0x00 + +# CHECK: cmpl $0, %eax +0x3d 0x00 0x00 0x00 0x00 + +# CHECK: cmpq $0, %rax +0x48 0x3d 0x00 0x00 0x00 0x00 + +# CHECK: testb $0, %al +0xa8 0x00 + +# CHECK: testw $0, %ax +0x66 0xa9 0x00 0x00 + +# CHECK: testl $0, %eax +0xa9 0x00 0x00 0x00 0x00 + +# CHECK: testq $0, %rax +0x48 0xa9 0x00 0x00 0x00 0x00 + +# CHECK: vaddps %xmm3, %xmm15, %xmm0 +0xc4 0xe1 0x00 0x58 0xc3 + +# CHECK: movbel (%rax), %eax +0x0f 0x38 0xf0 0x00 + +# CHECK: movbel %eax, (%rax) +0x0f 0x38 0xf1 0x00 + +# CHECK: movbew (%rax), %ax +0x66 0x0f 0x38 0xf0 0x00 + +# CHECK: movbew %ax, (%rax) +0x66 0x0f 0x38 0xf1 0x00 + +# CHECK: movbeq (%rax), %rax +0x48 0x0f 0x38 0xf0 0x00 + +# CHECK: movbeq %rax, (%rax) +0x48 0x0f 0x38 0xf1 0x00 + +# CHECK: rdrandw %ax +0x66 0x0f 0xc7 0xf0 + +# CHECK: rdrandl %eax +0x0f 0xc7 0xf0 + +# CHECK: rdrandq %rax +0x48 0x0f 0xc7 0xf0 + +# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x7d 0x0a 0xc0 0x00 + +# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x7d 0x0b 0xc0 0x00 + +# CHECK: vcvtsd2si %xmm0, %eax +0xc4 0xe1 0x7f 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %rax +0xc4 0xe1 0xff 0x2d 0xc0 + +# CHECK: vucomisd %xmm1, %xmm0 +0xc5 0xfd 0x2e 0xc1 + +# CHECK: vucomiss %xmm1, %xmm0 +0xc5 0xfc 0x2e 0xc1 + +# CHECK: vcomisd %xmm1, %xmm0 +0xc5 0xfd 0x2f 0xc1 + +# CHECK: vcomiss %xmm1, %xmm0 +0xc5 0xfc 0x2f 0xc1 + +# CHECK: vaddss %xmm1, %xmm0, %xmm0 +0xc5 0xfe 0x58 0xc1 + +# CHECK: xsave (%rax) +0x0f 0xae 0x20 + +# CHECK: xrstor (%rax) +0x0f 0xae 0x28 + +# CHECK: xsaveopt (%rax) +0x0f 0xae 0x30 + +# CHECK: rdfsbasel %eax +0xf3 0x0f 0xae 0xc0 + +# CHECK: rdgsbasel %eax +0xf3 0x0f 0xae 0xc8 + +# CHECK: wrfsbasel %eax +0xf3 0x0f 0xae 0xd0 + +# CHECK: wrgsbasel %eax +0xf3 0x0f 0xae 0xd8 + +# CHECK: rdfsbaseq %rax +0xf3 0x48 0x0f 0xae 0xc0 + +# CHECK: rdgsbaseq %rax +0xf3 0x48 0x0f 0xae 0xc8 + +# CHECK: wrfsbaseq %rax +0xf3 0x48 0x0f 0xae 0xd0 + +# CHECK: wrgsbaseq %rax +0xf3 0x48 0x0f 0xae 0xd8 + +# CHECK: vcvtph2ps %xmm0, %xmm0 +0xc4 0xe2 0x79 0x13 0xc0 + +# CHECK: vcvtph2ps (%rax), %xmm0 +0xc4 0xe2 0x79 0x13 0x00 + +# CHECK: vcvtph2ps %xmm0, %ymm0 +0xc4 0xe2 0x7d 0x13 0xc0 + +# CHECK: vcvtph2ps (%rax), %ymm0 +0xc4 0xe2 0x7d 0x13 0x00 + +# CHECK: vcvtps2ph $0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x1d 0xc0 0x00 + +# CHECK: vcvtps2ph $0, %xmm0, (%rax) +0xc4 0xe3 0x79 0x1d 0x00 0x00 + +# CHECK: vcvtps2ph $0, %ymm0, %xmm0 +0xc4 0xe3 0x7d 0x1d 0xc0 0x00 + +# CHECK: vcvtps2ph $0, %ymm0, (%rax) +0xc4 0xe3 0x7d 0x1d 0x00 0x00 + +# CHECK: popcntl %eax, %eax +0xf3 0x0f 0xb8 0xc0 + +# CHECK: popcntw %ax, %ax +0x66 0xf3 0x0f 0xb8 0xc0 + +# CHECK: popcntq %rax, %rax +0xf3 0x48 0x0f 0xb8 0xc0 + +# CHECK: lzcntl %eax, %eax +0xf3 0x0f 0xbd 0xc0 + +# CHECK: lzcntw %ax, %ax +0x66 0xf3 0x0f 0xbd 0xc0 + +# CHECK: lzcntq %rax, %rax +0xf3 0x48 0x0f 0xbd 0xc0 + +# CHECK: tzcntl %eax, %eax +0xf3 0x0f 0xbc 0xc0 + +# CHECK: tzcntw %ax, %ax +0x66 0xf3 0x0f 0xbc 0xc0 + +# CHECK: tzcntq %rax, %rax +0xf3 0x48 0x0f 0xbc 0xc0 + +# CHECK: andnl %ecx, %r15d, %eax +0xc4 0xe2 0x00 0xf2 0xc1 + +# CHECK: andnq %rax, %r15, %rax +0xc4 0xe2 0x80 0xf2 0xc0 + +# CHECK: andnl (%rax), %r15d, %eax +0xc4 0xe2 0x00 0xf2 0x00 + +# CHECK: andnq (%rax), %r15, %rax +0xc4 0xe2 0x80 0xf2 0x00 + +# CHECK: blsrl (%rax), %r15d +0xc4 0xe2 0x00 0xf3 0x08 + +# CHECK: blsrq (%rax), %r15 +0xc4 0xe2 0x80 0xf3 0x08 + +# CHECK: blsmskl (%rax), %r15d +0xc4 0xe2 0x00 0xf3 0x10 + +# CHECK: blsmskq (%rax), %r15 +0xc4 0xe2 0x80 0xf3 0x10 + +# CHECK: blsil (%rax), %r15d +0xc4 0xe2 0x00 0xf3 0x18 + +# CHECK: blsiq (%rax), %r15 +0xc4 0xe2 0x80 0xf3 0x18 + +# CHECK: bextrl %r12d, (%rax), %r10d +0xc4 0x62 0x18 0xf7 0x10 + +# CHECK: bextrl %r12d, %r11d, %r10d +0xc4 0x42 0x18 0xf7 0xd3 + +# CHECK: bextrq %r12, (%rax), %r10 +0xc4 0x62 0x98 0xf7 0x10 + +# CHECK: bextrq %r12, %r11, %r10 +0xc4 0x42 0x98 0xf7 0xd3 + +# CHECK: bzhil %r12d, (%rax), %r10d +0xc4 0x62 0x18 0xf5 0x10 + +# CHECK: bzhil %r12d, %r11d, %r10d +0xc4 0x42 0x18 0xf5 0xd3 + +# CHECK: bzhiq %r12, (%rax), %r10 +0xc4 0x62 0x98 0xf5 0x10 + +# CHECK: bzhiq %r12, %r11, %r10 +0xc4 0x42 0x98 0xf5 0xd3 + +# CHECK: pextl %r12d, %r11d, %r10d +0xc4 0x42 0x22 0xf5 0xd4 + +# CHECK: pextl (%rax), %r11d, %r10d +0xc4 0x62 0x22 0xf5 0x10 + +# CHECK: pextq %r12, %r11, %r10 +0xc4 0x42 0xa2 0xf5 0xd4 + +# CHECK: pextq (%rax), %r11, %r10 +0xc4 0x62 0xa2 0xf5 0x10 + +# CHECK: pdepl %r12d, %r11d, %r10d +0xc4 0x42 0x23 0xf5 0xd4 + +# CHECK: pdepl (%rax), %r11d, %r10d +0xc4 0x62 0x23 0xf5 0x10 + +# CHECK: pdepq %r12, %r11, %r10 +0xc4 0x42 0xa3 0xf5 0xd4 + +# CHECK: pdepq (%rax), %r11, %r10 +0xc4 0x62 0xa3 0xf5 0x10 diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index dd313f1..51901a5 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -24,3 +24,510 @@ # CHECK: pshufb 0x0f 0x38 0x00 0xc0 + +# CHECK: crc32b %al, %eax +0xf2 0x0f 0x38 0xf0 0xc0 + +# CHECK: crc32w %ax, %eax +0x66 0xf2 0x0f 0x38 0xf1 0xc0 + +# CHECK: crc32l %eax, %eax +0xf2 0x0f 0x38 0xf1 0xc0 + + +# CHECK: int $33 +0xCD 0x21 + +# CHECK: int $33 +0xCD 0x21 + + +# CHECK: addb %al, (%eax) +0 0 + +# CHECK: calll -1234 +0xe8 0x2e 0xfb 0xff 0xff + +# CHECK: lfence +0x0f 0xae 0xe8 + +# CHECK: mfence +0x0f 0xae 0xf0 + +# CHECK: monitor +0x0f 0x01 0xc8 + +# CHECK: mwait +0x0f 0x01 0xc9 + +# CHECK: vmcall +0x0f 0x01 0xc1 + +# CHECK: vmlaunch +0x0f 0x01 0xc2 + +# CHECK: vmresume +0x0f 0x01 0xc3 + +# CHECK: vmxoff +0x0f 0x01 0xc4 + +# CHECK: swapgs +0x0f 0x01 0xf8 + +# CHECK: rdtscp +0x0f 0x01 0xf9 + +# CHECK: vmxon +0xf3 0x0f 0xc7 0x30 + +# CHECK: vmptrld +0x0f 0xc7 0x30 + +# CHECK: vmptrst +0x0f 0xc7 0x38 + +# CHECK: movl $0, -4(%ebp) +0xc7 0x45 0xfc 0x00 0x00 0x00 0x00 + +# CHECK: movl %cr0, %ecx +0x0f 0x20 0xc1 + +# CHECK: leal 4(%esp), %ecx +0x8d 0x4c 0x24 0x04 + +# CHECK: enter $1, $2 +0xc8 0x01 0x00 0x02 + +# CHECK: movw $47416, -66(%ebp) +0x66 0xc7 0x45 0xbe 0x38 0xb9 + +# CHECK: vaddpd %ymm5, %ymm1, %ymm0 +0xc4 0xc1 0x75 0x58 0xc5 + +# CHECK: vaddps %ymm3, %ymm1, %ymm0 +0xc5 0xf4 0x58 0xc3 + +# CHECK: vandpd %ymm5, %ymm1, %ymm0 +0xc4 0xc1 0x75 0x54 0xc5 + +# CHECK: vandps %ymm3, %ymm1, %ymm0 +0xc5 0xf4 0x54 0xc3 + +# CHECK: vzeroall +0xc5 0xfc 0x77 + +# CHECK: vcvtps2pd %xmm0, %ymm0 +0xc5 0xfc 0x5a 0xc0 + +# CHECK: vandps (%edx), %xmm1, %xmm7 +0xc5 0xf0 0x54 0x3a + +# CHECK: vcvtss2sil %xmm0, %eax +0xc5 0xfa 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %eax +0xc5 0xfb 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %eax +0xc4 0xe1 0x7b 0x2d 0xc0 + +# CHECK: vmaskmovpd %xmm0, %xmm1, (%eax) +0xc4 0xe2 0x71 0x2f 0x00 + +# CHECK: vmovapd %xmm0, %xmm2 +0xc5 0xf9 0x28 0xd0 + +# Check these special case instructions that the immediate is not sign-extend. +# CHECK: blendps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0c 0xca 0x81 + +# CHECK: blendpd $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0d 0xca 0x81 + +# CHECK: pblendw $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x0e 0xca 0x81 + +# CHECK: mpsadbw $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x42 0xca 0x81 + +# CHECK: dpps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x40 0xca 0x81 + +# CHECK: dppd $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x41 0xca 0x81 + +# CHECK: insertps $129, %xmm2, %xmm1 +0x66 0x0f 0x3a 0x21 0xca 0x81 + +# CHECK: vblendps $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0c 0xca 0x81 + +# CHECK: vblendps $129, (%eax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0c 0x08 0x81 + +# CHECK: vblendpd $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0d 0xca 0x81 + +# CHECK: vblendpd $129, (%eax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x0d 0x08 0x81 + +# CHECK: vpblendw $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x0e 0xca 0x81 + +# CHECK: vmpsadbw $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x42 0xca 0x81 + +# CHECK: vdpps $129, %ymm2, %ymm5, %ymm1 +0xc4 0xe3 0x55 0x40 0xca 0x81 + +# CHECK: vdpps $129, (%eax), %ymm5, %ymm1 +0xc4 0xe3 0x55 0x40 0x08 0x81 + +# CHECK: vdppd $129, %xmm2, %xmm5, %xmm1 +0xc4 0xe3 0x51 0x41 0xca 0x81 + +# CHECK: vinsertps $129, %xmm3, %xmm2, %xmm1 +0xc4 0xe3 0x69 0x21 0xcb 0x81 + +# CHECK: pause +0xf3 0x90 + +# CHECK: addl %eax, %edi +0x01 0xc7 + +# CHECK: addl %edi, %eax +0x03 0xc7 + +# CHECK: movl %eax, %edi +0x89 0xc7 + +# CHECK: movl %edi, %eax +0x8b 0xc7 + +# CHECK: movups %xmm1, %xmm0 +0x0f 0x10 0xc1 + +# CHECK: movups %xmm0, %xmm1 +0x0f 0x11 0xc1 + +# CHECK: movaps %xmm1, %xmm0 +0x0f 0x28 0xc1 + +# CHECK: movaps %xmm0, %xmm1 +0x0f 0x29 0xc1 + +# CHECK: movupd %xmm1, %xmm0 +0x66 0x0f 0x10 0xc1 + +# CHECK: movupd %xmm0, %xmm1 +0x66 0x0f 0x11 0xc1 + +# CHECK: movapd %xmm1, %xmm0 +0x66 0x0f 0x28 0xc1 + +# CHECK: movapd %xmm0, %xmm1 +0x66 0x0f 0x29 0xc1 + +# CHECK: vmovups %xmm1, %xmm0 +0xc5 0xf8 0x10 0xc1 + +# CHECK: vmovups %xmm0, %xmm1 +0xc5 0xf8 0x11 0xc1 + +# CHECK: vmovaps %xmm1, %xmm0 +0xc5 0xf8 0x28 0xc1 + +# CHECK: vmovaps %xmm0, %xmm1 +0xc5 0xf8 0x29 0xc1 + +# CHECK: vmovupd %xmm1, %xmm0 +0xc5 0xf9 0x10 0xc1 + +# CHECK: vmovupd %xmm0, %xmm1 +0xc5 0xf9 0x11 0xc1 + +# CHECK: vmovapd %xmm1, %xmm0 +0xc5 0xf9 0x28 0xc1 + +# CHECK: vmovapd %xmm0, %xmm1 +0xc5 0xf9 0x29 0xc1 + +# CHECK: vmovups %ymm1, %ymm0 +0xc5 0xfc 0x10 0xc1 + +# CHECK: vmovups %ymm0, %ymm1 +0xc5 0xfc 0x11 0xc1 + +# CHECK: vmovaps %ymm1, %ymm0 +0xc5 0xfc 0x28 0xc1 + +# CHECK: vmovaps %ymm0, %ymm1 +0xc5 0xfc 0x29 0xc1 + +# CHECK: movdqa %xmm1, %xmm0 +0x66 0x0f 0x6f 0xc1 + +# CHECK: movdqa %xmm0, %xmm1 +0x66 0x0f 0x7f 0xc1 + +# CHECK: movdqu %xmm1, %xmm0 +0xf3 0x0f 0x6f 0xc1 + +# CHECK: movdqu %xmm0, %xmm1 +0xf3 0x0f 0x7f 0xc1 + +# CHECK: vmovdqa %xmm1, %xmm0 +0xc5 0xf9 0x6f 0xc1 + +# CHECK: vmovdqa %xmm0, %xmm1 +0xc5 0xf9 0x7f 0xc1 + +# CHECK: vmovdqa %ymm1, %ymm0 +0xc5 0xfd 0x6f 0xc1 + +# CHECK: vmovdqa %ymm0, %ymm1 +0xc5 0xfd 0x7f 0xc1 + +# CHECK: vmovdqu %xmm1, %xmm0 +0xc5 0xfa 0x6f 0xc1 + +# CHECK: vmovdqu %xmm0, %xmm1 +0xc5 0xfa 0x7f 0xc1 + +# CHECK: vmovdqu %ymm1, %ymm0 +0xc5 0xfe 0x6f 0xc1 + +# CHECK: vmovdqu %ymm0, %ymm1 +0xc5 0xfe 0x7f 0xc1 + +# CHECK: vblendvps %xmm4, %xmm1, %xmm2, %xmm3 +0xc4 0xe3 0x69 0x4a 0xd9 0x41 + +# CHECK: vroundpd $0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x09 0xc0 0x00 + +# CHECK: vroundps $0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x08 0xc0 0x00 + +# CHECK: vroundpd $0, %ymm0, %ymm0 +0xc4 0xe3 0x7d 0x09 0xc0 0x00 + +# CHECK: vroundps $0, %ymm0, %ymm0 +0xc4 0xe3 0x7d 0x08 0xc0 0x00 + +# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x0a 0xc0 0x00 + +# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x0b 0xc0 0x00 + +# CHECK: invept (%eax), %eax +0x66 0x0f 0x38 0x80 0x00 + +# CHECK: invvpid (%eax), %eax +0x66 0x0f 0x38 0x81 0x00 + +# CHECK: invpcid (%eax), %eax +0x66 0x0f 0x38 0x82 0x00 + +# CHECK: nop +0x90 + +# CHECK: addb $0, %al +0x04 0x00 + +# CHECK: addw $0, %ax +0x66 0x05 0x00 0x00 + +# CHECK: addl $0, %eax +0x05 0x00 0x00 0x00 0x00 + +# CHECK: adcb $0, %al +0x14 0x00 + +# CHECK: adcw $0, %ax +0x66 0x15 0x00 0x00 + +# CHECK: adcl $0, %eax +0x15 0x00 0x00 0x00 0x00 + +# CHECK: cmpb $0, %al +0x3c 0x00 + +# CHECK: cmpw $0, %ax +0x66 0x3d 0x00 0x00 + +# CHECK: cmpl $0, %eax +0x3d 0x00 0x00 0x00 0x00 + +# CHECK: testb $0, %al +0xa8 0x00 + +# CHECK: testw $0, %ax +0x66 0xa9 0x00 0x00 + +# CHECK: testl $0, %eax +0xa9 0x00 0x00 0x00 0x00 + +# CHECK: movb 0, %al +0xa0 0x00 0x00 0x00 0x00 + +# CHECK: movw 0, %ax +0x66 0xa1 0x00 0x00 0x00 0x00 + +# CHECK: movl 0, %eax +0xa1 0x00 0x00 0x00 0x00 + +# CHECK: movb %al, 0 +0xa2 0x00 0x00 0x00 0x00 + +# CHECK: movw %ax, 0 +0x66 0xa3 0x00 0x00 0x00 0x00 + +# CHECK: movl %eax, 0 +0xa3 0x00 0x00 0x00 0x00 + +# CHECK: vaddps %xmm3, %xmm7, %xmm0 +0xc4 0xe1 0x00 0x58 0xc3 + +# CHECK: movbel (%eax), %eax +0x0f 0x38 0xf0 0x00 + +# CHECK: movbel %eax, (%eax) +0x0f 0x38 0xf1 0x00 + +# CHECK: movbew (%eax), %ax +0x66 0x0f 0x38 0xf0 0x00 + +# CHECK: movbew %ax, (%eax) +0x66 0x0f 0x38 0xf1 0x00 + +# CHECK: rdrandw %ax +0x66 0x0f 0xc7 0xf0 + +# CHECK: rdrandl %eax +0x0f 0xc7 0xf0 + +# CHECK: vroundss $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x7d 0x0a 0xc0 0x00 + +# CHECK: vroundsd $0, %xmm0, %xmm0, %xmm0 +0xc4 0xe3 0x7d 0x0b 0xc0 0x00 + +# CHECK: vcvtsd2si %xmm0, %eax +0xc4 0xe1 0x7f 0x2d 0xc0 + +# CHECK: vcvtsd2si %xmm0, %eax +0xc4 0xe1 0xff 0x2d 0xc0 + +# CHECK: vucomisd %xmm1, %xmm0 +0xc5 0xfd 0x2e 0xc1 + +# CHECK: vucomiss %xmm1, %xmm0 +0xc5 0xfc 0x2e 0xc1 + +# CHECK: vcomisd %xmm1, %xmm0 +0xc5 0xfd 0x2f 0xc1 + +# CHECK: vcomiss %xmm1, %xmm0 +0xc5 0xfc 0x2f 0xc1 + +# CHECK: vaddss %xmm1, %xmm0, %xmm0 +0xc5 0xfe 0x58 0xc1 + +# CHECK: xsave (%eax) +0x0f 0xae 0x20 + +# CHECK: xrstor (%eax) +0x0f 0xae 0x28 + +# CHECK: xsaveopt (%eax) +0x0f 0xae 0x30 + +# CHECK: vcvtph2ps %xmm0, %xmm0 +0xc4 0xe2 0x79 0x13 0xc0 + +# CHECK: vcvtph2ps (%eax), %xmm0 +0xc4 0xe2 0x79 0x13 0x00 + +# CHECK: vcvtph2ps %xmm0, %ymm0 +0xc4 0xe2 0x7d 0x13 0xc0 + +# CHECK: vcvtph2ps (%eax), %ymm0 +0xc4 0xe2 0x7d 0x13 0x00 + +# CHECK: vcvtps2ph $0, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x1d 0xc0 0x00 + +# CHECK: vcvtps2ph $0, %xmm0, (%eax) +0xc4 0xe3 0x79 0x1d 0x00 0x00 + +# CHECK: vcvtps2ph $0, %ymm0, %xmm0 +0xc4 0xe3 0x7d 0x1d 0xc0 0x00 + +# CHECK: vcvtps2ph $0, %ymm0, (%eax) +0xc4 0xe3 0x7d 0x1d 0x00 0x00 + +# CHECK: popcntl %eax, %eax +0xf3 0x0f 0xb8 0xc0 + +# CHECK: popcntw %ax, %ax +0x66 0xf3 0x0f 0xb8 0xc0 + +# CHECK: lzcntl %eax, %eax +0xf3 0x0f 0xbd 0xc0 + +# CHECK: lzcntw %ax, %ax +0x66 0xf3 0x0f 0xbd 0xc0 + +# CHECK: tzcntl %eax, %eax +0xf3 0x0f 0xbc 0xc0 + +# CHECK: tzcntw %ax, %ax +0x66 0xf3 0x0f 0xbc 0xc0 + +# CHECK: andnl %ecx, %edi, %eax +0xc4 0xe2 0x00 0xf2 0xc1 + +# CHECK: andnl (%eax), %edi, %eax +0xc4 0xe2 0x00 0xf2 0x00 + +# CHECK: andnl %ecx, %edi, %eax +0xc4 0xe2 0x80 0xf2 0xc1 + +# CHECK: andnl (%eax), %edi, %eax +0xc4 0xe2 0x80 0xf2 0x00 + +# CHECK: blsrl (%eax), %edi +0xc4 0xe2 0x40 0xf3 0x08 + +# CHECK: blsmskl (%eax), %edi +0xc4 0xe2 0x40 0xf3 0x10 + +# CHECK: blsil (%eax), %edi +0xc4 0xe2 0x40 0xf3 0x18 + +# CHECK: bextrl %esi, (%eax), %edx +0xc4 0xe2 0x08 0xf7 0x10 + +# CHECK: bextrl %esi, %ebx, %edx +0xc4 0xe2 0x08 0xf7 0xd3 + +# CHECK: bzhil %esi, (%eax), %edx +0xc4 0xe2 0x08 0xf5 0x10 + +# CHECK: bzhil %esi, %ebx, %edx +0xc4 0xe2 0x08 0xf5 0xd3 + +# CHECK: pextl %esp, %ecx, %edx +0xc4 0xe2 0x72 0xf5 0xd4 + +# CHECK: pextl (%eax), %ecx, %edx +0xc4 0xe2 0x72 0xf5 0x10 + +# CHECK: pdepl %esp, %ecx, %edx +0xc4 0xe2 0x73 0xf5 0xd4 + +# CHECK: pdepl (%eax), %ecx, %edx +0xc4 0xe2 0x73 0xf5 0x10 |