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-rw-r--r--test/MC/Disassembler/ARM/armv8.1a.txt36
-rw-r--r--test/MC/Disassembler/ARM/invalid-armv8.1a.txt83
-rw-r--r--test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt72
-rw-r--r--test/MC/Disassembler/ARM/neont2.txt6
-rw-r--r--test/MC/Disassembler/ARM/thumb-v8.1a.txt98
-rw-r--r--test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt22
-rw-r--r--test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt96
-rw-r--r--test/MC/Disassembler/X86/avx-512.txt3
8 files changed, 411 insertions, 5 deletions
diff --git a/test/MC/Disassembler/ARM/armv8.1a.txt b/test/MC/Disassembler/ARM/armv8.1a.txt
new file mode 100644
index 0000000..de0c89e
--- /dev/null
+++ b/test/MC/Disassembler/ARM/armv8.1a.txt
@@ -0,0 +1,36 @@
+# RUN: llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
+# RUN: not llvm-mc -triple armv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
+
+[0x54,0x0b,0x12,0xf3]
+[0x12,0x0b,0x21,0xf3]
+[0x54,0x0c,0x12,0xf3]
+[0x12,0x0c,0x21,0xf3]
+# CHECK-V81a: vqrdmlah.s16 q0, q1, q2
+# CHECK-V81a: vqrdmlah.s32 d0, d1, d2
+# CHECK-V81a: vqrdmlsh.s16 q0, q1, q2
+# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x54,0x0b,0x12,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0x0b,0x21,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x54,0x0c,0x12,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0x0c,0x21,0xf3]
+
+[0x42,0x0e,0x92,0xf3]
+[0x42,0x0e,0xa1,0xf2]
+[0x42,0x0f,0x92,0xf3]
+[0x42,0x0f,0xa1,0xf2]
+# CHECK-V81a: vqrdmlah.s16 q0, q1, d2[0]
+# CHECK-V81a: vqrdmlah.s32 d0, d1, d2[0]
+# CHECK-V81a: vqrdmlsh.s16 q0, q1, d2[0]
+# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0e,0x92,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0e,0xa1,0xf2]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0f,0x92,0xf3]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x42,0x0f,0xa1,0xf2]
diff --git a/test/MC/Disassembler/ARM/invalid-armv8.1a.txt b/test/MC/Disassembler/ARM/invalid-armv8.1a.txt
new file mode 100644
index 0000000..1a9f275
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-armv8.1a.txt
@@ -0,0 +1,83 @@
+# RUN: not llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
+
+# Check, if sizes 00 and 11 are undefined for RDMA
+[0x12,0x0b,0x01,0xf3] # vqrdmlah.s8 d0, d1, d2
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x12,0x0b,0x01,0xf3] # vqrdmlah.s8 d0, d1, d2
+# CHECK-NEXT: ^
+
+[0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2
+# CHECK-NEXT: ^
+
+[0x54,0x0b,0x02,0xf3] # vqrdmlah.s8 q0, q1, q2
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0b,0x02,0xf3] # vqrdmlah.s8 q0, q1, q2
+# CHECK-NEXT: ^
+
+[0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0
+# CHECK-NEXT: ^
+
+[0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8 d0, d1, d2
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8 d0, d1, d2
+# CHECK-NEXT: ^
+
+[0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2
+# CHECK-NEXT: ^
+
+[0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8 q0, q1, q2
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8 q0, q1, q2
+# CHECK-NEXT: ^
+
+[0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2
+# CHECK-NEXT: ^
+
+[0x42,0x0e,0x81,0xf2] # vqrdmlah.s8 d0, d1, d2[0]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0x81,0xf2] # vqrdmlah.s8 d0, d1, d2[0]
+# CHECK-NEXT: ^
+
+[0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0]
+# CHECK-NEXT: ^
+
+[0x42,0x0e,0x82,0xf3] # vqrdmlah.s8 q0, q1, d2[0]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0x82,0xf3] # vqrdmlah.s8 q0, q1, d2[0]
+# CHECK-NEXT: ^
+
+[0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64 q0, q1, d2[0]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64 q0, q1, d2[0]
+# CHECK-NEXT: ^
+
+
+[0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8 d0, d1, d2[0]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8 d0, d1, d2[0]
+# CHECK-NEXT: ^
+
+[0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64 d0, d1, d2[0]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64 d0, d1, d2[0]
+# CHECK-NEXT: ^
+
+[0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8 q0, q1, d2[0]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8 q0, q1, d2[0]
+# CHECK-NEXT: ^
+
+[0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64 q0, q1, d2[0]
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64 q0, q1, d2[0]
+# CHECK-NEXT: ^
diff --git a/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt b/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt
new file mode 100644
index 0000000..555b8c3
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-thumbv8.1a.txt
@@ -0,0 +1,72 @@
+# RUN: not llvm-mc -triple thumbv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s
+
+# Check, if sizes 00 and 11 are undefined for RDMA
+[0x01,0xff,0x12,0x0b] # vqrdmlah.s8 d0, d1, d2
+[0x31,0xff,0x12,0x0b] # vqrdmlah.s64 d0, d1, d2
+[0x02,0xff,0x54,0x0b] # vqrdmlah.s8 q0, q1, q2
+[0x06,0xff,0x50,0x4b] # vqrdmlah.s64 q2, q3, q0
+
+[0x01,0xff,0x12,0x0c] # vqrdmlsh.s8 d0, d1, d2
+[0x31,0xff,0x12,0x0c] # vqrdmlsh.s64 d0, d1, d2
+[0x02,0xff,0x54,0x0c] # vqrdmlsh.s8 q0, q1, q2
+[0x32,0xff,0x54,0x0c] # vqrdmlsh.s64 q0, q1, q2
+
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x01,0xff,0x12,0x0b] # vqrdmlah.s8 d0, d1, d2
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x31,0xff,0x12,0x0b] # vqrdmlah.s64 d0, d1, d2
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x02,0xff,0x54,0x0b] # vqrdmlah.s8 q0, q1, q2
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x06,0xff,0x50,0x4b] # vqrdmlah.s64 q2, q3, q0
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x01,0xff,0x12,0x0c] # vqrdmlsh.s8 d0, d1, d2
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x31,0xff,0x12,0x0c] # vqrdmlsh.s64 d0, d1, d2
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x02,0xff,0x54,0x0c] # vqrdmlsh.s8 q0, q1, q2
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x32,0xff,0x54,0x0c] # vqrdmlsh.s64 q0, q1, q2
+# CHECK-NEXT: ^
+
+[0x81,0xef,0x42,0x0e] # vqrdmlah.s8 d0, d1, d2[0]
+[0xb1,0xef,0x42,0x0e] # vqrdmlah.s64 d0, d1, d2[0]
+[0x82,0xff,0x42,0x0e] # vqrdmlah.s8 q0, q1, d2[0]
+[0xb2,0xff,0x42,0x0e] # vqrdmlah.s64 q0, q1, d2[0]
+
+[0x81,0xef,0x42,0x0f] # vqrdmlsh.s8 d0, d1, d2[0]
+[0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64 d0, d1, d2[0]
+[0x82,0xff,0x42,0x0f] # vqrdmlsh.s8 q0, q1, d2[0]
+[0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64 q0, q1, d2[0]
+
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x81,0xef,0x42,0x0e] # vqrdmlah.s8 d0, d1, d2[0]
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0xb1,0xef,0x42,0x0e] # vqrdmlah.s64 d0, d1, d2[0]
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x82,0xff,0x42,0x0e] # vqrdmlah.s8 q0, q1, d2[0]
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0xb2,0xff,0x42,0x0e] # vqrdmlah.s64 q0, q1, d2[0]
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x81,0xef,0x42,0x0f] # vqrdmlsh.s8 d0, d1, d2[0]
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0xb1,0xef,0x42,0x0f] # vqrdmlsh.s64 d0, d1, d2[0]
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0x82,0xff,0x42,0x0f] # vqrdmlsh.s8 q0, q1, d2[0]
+# CHECK-NEXT: ^
+# CHECK: warning: invalid instruction encoding
+# CHECK-NEXT: [0xb2,0xff,0x42,0x0f] # vqrdmlsh.s64 q0, q1, d2[0]
+# CHECK-NEXT: ^
diff --git a/test/MC/Disassembler/ARM/neont2.txt b/test/MC/Disassembler/ARM/neont2.txt
index e493fba..536095f 100644
--- a/test/MC/Disassembler/ARM/neont2.txt
+++ b/test/MC/Disassembler/ARM/neont2.txt
@@ -1631,11 +1631,11 @@
# rdar://10798451
0xe7 0xf9 0x32 0x1d
-# CHECK vld2.8 {d17[], d19[]}, [r7:16], r2
+# CHECK: vld2.8 {d17[], d19[]}, [r7:16], r2
0xe7 0xf9 0x3d 0x1d
-# CHECK vld2.8 {d17[], d19[]}, [r7:16]!
+# CHECK: vld2.8 {d17[], d19[]}, [r7:16]!
0xe7 0xf9 0x3f 0x1d
-# CHECK vld2.8 {d17[], d19[]}, [r7:16]
+# CHECK: vld2.8 {d17[], d19[]}, [r7:16]
# rdar://11034702
0x04 0xf9 0x0d 0x87
diff --git a/test/MC/Disassembler/ARM/thumb-v8.1a.txt b/test/MC/Disassembler/ARM/thumb-v8.1a.txt
new file mode 100644
index 0000000..10fea46
--- /dev/null
+++ b/test/MC/Disassembler/ARM/thumb-v8.1a.txt
@@ -0,0 +1,98 @@
+# RUN: llvm-mc -triple thumbv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V81a
+# RUN: not llvm-mc -triple thumbv8 -mattr=+v8 --disassemble < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
+
+[0x11,0xff,0x12,0x0b]
+# CHECK-V81a: vqrdmlah.s16 d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x11,0xff,0x12,0x0b]
+# CHECK-V8: ^
+
+[0x21,0xff,0x12,0x0b]
+# CHECK-V81a: vqrdmlah.s32 d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x21,0xff,0x12,0x0b]
+# CHECK-V8: ^
+
+[0x12,0xff,0x54,0x0b]
+# CHECK-V81a: vqrdmlah.s16 q0, q1, q2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0xff,0x54,0x0b]
+# CHECK-V8: ^
+
+[0x26,0xff,0x50,0x4b]
+# CHECK-V81a: vqrdmlah.s32 q2, q3, q0
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x26,0xff,0x50,0x4b]
+# CHECK-V8: ^
+
+[0x16,0xff,0x15,0x7c]
+# CHECK-V81a: vqrdmlsh.s16 d7, d6, d5
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x16,0xff,0x15,0x7c]
+# CHECK-V8: ^
+
+[0x21,0xff,0x12,0x0c]
+# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x21,0xff,0x12,0x0c]
+# CHECK-V8: ^
+
+[0x12,0xff,0x54,0x0c]
+# CHECK-V81a: vqrdmlsh.s16 q0, q1, q2
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x12,0xff,0x54,0x0c]
+# CHECK-V8: ^
+
+[0x28,0xff,0x5a,0x6c]
+# CHECK-V81a: vqrdmlsh.s32 q3, q4, q5
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x28,0xff,0x5a,0x6c]
+# CHECK-V8: ^
+
+[0x91,0xef,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s16 d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x91,0xef,0x42,0x0e]
+# CHECK-V8: ^
+
+[0xa1,0xef,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s32 d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa1,0xef,0x42,0x0e]
+# CHECK-V8: ^
+
+[0x92,0xff,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s16 q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x92,0xff,0x42,0x0e]
+# CHECK-V8: ^
+
+[0xa2,0xff,0x42,0x0e]
+# CHECK-V81a: vqrdmlah.s32 q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa2,0xff,0x42,0x0e]
+# CHECK-V8: ^
+
+[0x91,0xef,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s16 d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x91,0xef,0x42,0x0f]
+# CHECK-V8: ^
+
+[0xa1,0xef,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s32 d0, d1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa1,0xef,0x42,0x0f]
+# CHECK-V8: ^
+
+[0x92,0xff,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s16 q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0x92,0xff,0x42,0x0f]
+# CHECK-V8: ^
+
+[0xa2,0xff,0x42,0x0f]
+# CHECK-V81a: vqrdmlsh.s32 q0, q1, d2[0]
+# CHECK-V8: warning: invalid instruction encoding
+# CHECK-V8: [0xa2,0xff,0x42,0x0f]
+# CHECK-V8: ^
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
index 7a30b5c..9d63bdd 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-bookII.txt
@@ -42,12 +42,30 @@
# CHECK: dcbf 2, 3
0x7c 0x02 0x18 0xac
-# CHECK: lwarx 2, 3, 4
+# CHECK: lbarx 2, 3, 4
+0x7c 0x43 0x20 0x68
+
+# CHECK: lharx 2, 3, 4
+0x7c 0x43 0x20 0xe8
+
+# CHECK: lwarx 2, 3, 4
0x7c 0x43 0x20 0x28
-# CHECK: ldarx 2, 3, 4
+# CHECK: ldarx 2, 3, 4
0x7c 0x43 0x20 0xa8
+# CHECK: lbarx 2, 3, 4, 1
+0x7c 0x43 0x20 0x69
+
+# CHECK: lharx 2, 3, 4, 1
+0x7c 0x43 0x20 0xe9
+
+# CHECK: lwarx 2, 3, 4, 1
+0x7c 0x43 0x20 0x29
+
+# CHECK: ldarx 2, 3, 4, 1
+0x7c 0x43 0x20 0xa9
+
# CHECK: sync 0
0x7c 0x00 0x04 0xac
diff --git a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
index fe62fdf..4424d69 100644
--- a/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
+++ b/test/MC/Disassembler/PowerPC/ppc64-encoding-vmx.txt
@@ -120,6 +120,42 @@
# CHECK: vperm 2, 3, 4, 5
0x10 0x43 0x21 0x6b
+# CHECK: vpermxor 2, 3, 4, 5
+0x10 0x43 0x21 0x6d
+
+# CHECK: vsbox 2, 5
+0x10 0x45 0x05 0xc8
+
+# CHECK: vcipher 2, 5, 17
+0x10 0x45 0x8d 0x08
+
+# CHECK: vcipherlast 2, 5, 17
+0x10 0x45 0x8d 0x09
+
+# CHECK: vncipher 2, 5, 17
+0x10,0x45,0x8d,0x48
+
+# CHECK: vncipherlast 2, 5, 17
+0x10,0x45,0x8d,0x49
+
+# CHECK: vpmsumb 2, 5, 17
+0x10 0x45 0x8c 0x08
+
+# CHECK: vpmsumh 2, 5, 17
+0x10 0x45 0x8c 0x48
+
+# CHECK: vpmsumw 2, 5, 17
+0x10 0x45 0x8c 0x88
+
+# CHECK: vpmsumd 2, 5, 17
+0x10 0x45 0x8c 0xc8
+
+# CHECK: vshasigmaw 2, 3, 0, 11
+0x10 0x43 0x5e 0x82
+
+# CHECK: vshasigmad 2, 3, 1, 15
+0x10 0x43 0xfe 0xc2
+
# CHECK: vsel 2, 3, 4, 5
0x10 0x43 0x21 0x6a
@@ -159,6 +195,9 @@
# CHECK: vadduwm 2, 3, 4
0x10 0x43 0x20 0x80
+# CHECK: vaddudm 2, 3, 4
+0x10 0x43 0x20 0xc0
+
# CHECK: vaddubs 2, 3, 4
0x10 0x43 0x22 0x00
@@ -189,6 +228,9 @@
# CHECK: vsubuwm 2, 3, 4
0x10 0x43 0x24 0x80
+# CHECK: vsubudm 2, 3, 4
+0x10 0x43 0x24 0xc0
+
# CHECK: vsububs 2, 3, 4
0x10 0x43 0x26 0x00
@@ -204,24 +246,39 @@
# CHECK: vmulesh 2, 3, 4
0x10 0x43 0x23 0x48
+# CHECK: vmulesw 2, 3, 4
+0x10 0x43 0x23 0x88
+
# CHECK: vmuleub 2, 3, 4
0x10 0x43 0x22 0x08
# CHECK: vmuleuh 2, 3, 4
0x10 0x43 0x22 0x48
+# CHECK: vmuleuw 2, 3, 4
+0x10 0x43 0x22 0x88
+
# CHECK: vmulosb 2, 3, 4
0x10 0x43 0x21 0x08
# CHECK: vmulosh 2, 3, 4
0x10 0x43 0x21 0x48
+# CHECK: vmulosw 2, 3, 4
+0x10 0x43 0x21 0x88
+
# CHECK: vmuloub 2, 3, 4
0x10 0x43 0x20 0x08
# CHECK: vmulouh 2, 3, 4
0x10 0x43 0x20 0x48
+# CHECK: vmulouw 2, 3, 4
+0x10 0x43 0x20 0x88
+
+# CHECK: vmuluwm 2, 3, 4
+0x10 0x43 0x20 0x89
+
# CHECK: vmhaddshs 2, 3, 4, 5
0x10 0x43 0x21 0x60
@@ -291,6 +348,9 @@
# CHECK: vmaxsw 2, 3, 4
0x10 0x43 0x21 0x82
+# CHECK: vmaxsd 2, 3, 4
+0x10 0x43 0x21 0xc2
+
# CHECK: vmaxub 2, 3, 4
0x10 0x43 0x20 0x02
@@ -300,6 +360,9 @@
# CHECK: vmaxuw 2, 3, 4
0x10 0x43 0x20 0x82
+# CHECK: vmaxud 2, 3, 4
+0x10 0x43 0x20 0xc2
+
# CHECK: vminsb 2, 3, 4
0x10 0x43 0x23 0x02
@@ -309,6 +372,9 @@
# CHECK: vminsw 2, 3, 4
0x10 0x43 0x23 0x82
+# CHECK: vminsd 2, 3, 4
+0x10 0x43 0x23 0xc2
+
# CHECK: vminub 2, 3, 4
0x10 0x43 0x22 0x02
@@ -318,6 +384,9 @@
# CHECK: vminuw 2, 3, 4
0x10 0x43 0x22 0x82
+# CHECK: vminud 2, 3, 4
+0x10 0x43 0x22 0xc2
+
# CHECK: vcmpequb 2, 3, 4
0x10 0x43 0x20 0x06
@@ -336,6 +405,12 @@
# CHECK: vcmpequw. 2, 3, 4
0x10 0x43 0x24 0x86
+# CHECK: vcmpequd 2, 3, 4
+0x10 0x43 0x20 0xc7
+
+# CHECK: vcmpequd. 2, 3, 4
+0x10 0x43 0x24 0xc7
+
# CHECK: vcmpgtsb 2, 3, 4
0x10 0x43 0x23 0x06
@@ -354,6 +429,12 @@
# CHECK: vcmpgtsw. 2, 3, 4
0x10 0x43 0x27 0x86
+# CHECK: vcmpgtsd 2, 3, 4
+0x10 0x43 0x23 0xc7
+
+# CHECK: vcmpgtsd. 2, 3, 4
+0x10 0x43 0x27 0xc7
+
# CHECK: vcmpgtub 2, 3, 4
0x10 0x43 0x22 0x06
@@ -372,6 +453,12 @@
# CHECK: vcmpgtuw. 2, 3, 4
0x10 0x43 0x26 0x86
+# CHECK: vcmpgtud 2, 3, 4
+0x10 0x43 0x22 0xc7
+
+# CHECK: vcmpgtud. 2, 3, 4
+0x10 0x43 0x26 0xc7
+
# CHECK: vand 2, 3, 4
0x10 0x43 0x24 0x04
@@ -414,6 +501,9 @@
# CHECK: vslw 2, 3, 4
0x10 0x43 0x21 0x84
+# CHECK: vrld 2, 3, 4
+0x10 0x43 0x20 0xc4
+
# CHECK: vsrb 2, 3, 4
0x10 0x43 0x22 0x04
@@ -423,6 +513,9 @@
# CHECK: vsrw 2, 3, 4
0x10 0x43 0x22 0x84
+# CHECK: vsrd 2, 3, 4
+0x10 0x43 0x26 0xc4
+
# CHECK: vsrab 2, 3, 4
0x10 0x43 0x23 0x04
@@ -432,6 +525,9 @@
# CHECK: vsraw 2, 3, 4
0x10 0x43 0x23 0x84
+# CHECK: vsrad 2, 3, 4
+0x10 0x43 0x23 0xc4
+
# CHECK: vaddfp 2, 3, 4
0x10 0x43 0x20 0x0a
diff --git a/test/MC/Disassembler/X86/avx-512.txt b/test/MC/Disassembler/X86/avx-512.txt
index d24a68d..cfe5ffd 100644
--- a/test/MC/Disassembler/X86/avx-512.txt
+++ b/test/MC/Disassembler/X86/avx-512.txt
@@ -136,3 +136,6 @@
# CHECK: vpcmpd $8, %zmm10, %zmm25, %k5
0x62 0xd3 0x35 0x40 0x1f 0xea 0x8
+
+# CHECK: vcmppd {sae}, $127, %zmm27, %zmm11, %k4
+0x62 0x91 0xa5 0x58 0xc2 0xe3 0x7f
generated by cgit v1.1 at 2024-12-22 16:05:18 +0000