diff options
Diffstat (limited to 'test/MC/Disassembler')
46 files changed, 4936 insertions, 50 deletions
diff --git a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt index 966530d..799ecdf 100644 --- a/test/MC/Disassembler/AArch64/a64-ignored-fields.txt +++ b/test/MC/Disassembler/AArch64/a64-ignored-fields.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=fp-armv8 -disassemble -show-encoding < %s | FileCheck %s # The "Rm" bits are ignored, but the canonical representation has them filled # with 0s. This is what we should produce even if the input bit-pattern had diff --git a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt index 4fa2d50..40926b1 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-instructions.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-instructions.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble < %s | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s | FileCheck %s #------------------------------------------------------------------------------ # Add/sub (immediate) diff --git a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt index adb8f75..5363863 100644 --- a/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt +++ b/test/MC/Disassembler/AArch64/basic-a64-unpredictable.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s #------------------------------------------------------------------------------ # Load-store exclusive diff --git a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt index 775660b..637ebdb 100644 --- a/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-postind.predictable.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt index 48ea817..f52d37f 100644 --- a/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt +++ b/test/MC/Disassembler/AArch64/ldp-preind.predictable.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s +# RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s # None of these instructions should be classified as unpredictable: diff --git a/test/MC/Disassembler/AArch64/lit.local.cfg b/test/MC/Disassembler/AArch64/lit.local.cfg index f9df30e..9a66a00 100644 --- a/test/MC/Disassembler/AArch64/lit.local.cfg +++ b/test/MC/Disassembler/AArch64/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.txt'] - targets = set(config.root.targets_to_build.split()) if not 'AArch64' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/AArch64/neon-instructions.txt b/test/MC/Disassembler/AArch64/neon-instructions.txt index 40d1f4c..863730a 100644 --- a/test/MC/Disassembler/AArch64/neon-instructions.txt +++ b/test/MC/Disassembler/AArch64/neon-instructions.txt @@ -131,8 +131,11 @@ #------------------------------------------------------------------------------ # Vector Move - register #------------------------------------------------------------------------------ -# CHECK: mov v1.16b, v15.16b -# CHECK: mov v25.8b, v4.8b + +# FIXME: these should print as "mov", but TableGen can't handle it. + +# CHECK: orr v1.16b, v15.16b, v15.16b +# CHECK: orr v25.8b, v4.8b, v4.8b 0xe1 0x1d 0xaf 0x4e 0x99 0x1c 0xa4 0x0e @@ -671,3 +674,1965 @@ 0xf5 0xdd 0x23 0x4e 0xab 0xdc 0x77 0x4e +#---------------------------------------------------------------------- +# Vector Shift Left long +#---------------------------------------------------------------------- +# CHECK: shll2 v2.8h, v4.16b, #8 +# CHECK: shll2 v6.4s, v8.8h, #16 +# CHECK: shll2 v6.2d, v8.4s, #32 +# CHECK: shll v2.8h, v4.8b, #8 +# CHECK: shll v6.4s, v8.4h, #16 +# CHECK: shll v6.2d, v8.2s, #32 + +0x82,0x38,0x21,0x6e +0x06,0x39,0x61,0x6e +0x06,0x39,0xa1,0x6e +0x82,0x38,0x21,0x2e +0x06,0x39,0x61,0x2e +0x06,0x39,0xa1,0x2e + +#---------------------------------------------------------------------- +# Vector Shift Left by Immediate +#---------------------------------------------------------------------- +# CHECK: shl v0.4h, v1.4h, #3 +# CHECK: shl v0.16b, v1.16b, #3 +# CHECK: shl v0.4s, v1.4s, #3 +# CHECK: shl v0.2d, v1.2d, #3 +0x20,0x54,0x13,0x0f +0x20,0x54,0x0b,0x4f +0x20,0x54,0x23,0x4f +0x20,0x54,0x43,0x4f + +#---------------------------------------------------------------------- +# Vector Shift Left Long (Signed, Unsigned) by Immediate +#---------------------------------------------------------------------- +# CHECK: sshll v0.2d, v1.2s, #3 +# CHECK: sshll2 v0.4s, v1.8h, #3 +# CHECK: ushll v0.4s, v1.4h, #3 +# CHECK: ushll2 v0.8h, v1.16b, #3 +0x20 0xa4 0x23 0x0f +0x20 0xa4 0x13 0x4f +0x20 0xa4 0x13 0x2f +0x20 0xa4 0x0b 0x6f + +#----------------------------------------------------------------------------- +#Integer shift right (Signed) +#----------------------------------------------------------------------------- +# CHECK: sshr v0.8b, v1.8b, #3 +# CHECK: sshr v0.4h, v1.4h, #3 +# CHECK: sshr v0.2s, v1.2s, #3 +# CHECK: sshr v0.16b, v1.16b, #3 +# CHECK: sshr v0.8h, v1.8h, #3 +# CHECK: sshr v0.4s, v1.4s, #3 +# CHECK: sshr v0.2d, v1.2d, #3 +0x20,0x04,0x0d,0x0f +0x20,0x04,0x1d,0x0f +0x20,0x04,0x3d,0x0f +0x20,0x04,0x0d,0x4f +0x20,0x04,0x1d,0x4f +0x20,0x04,0x3d,0x4f +0x20,0x04,0x7d,0x4f + +#----------------------------------------------------------------------------- +#Integer shift right (Unsigned) +#----------------------------------------------------------------------------- +# CHECK: ushr v0.8b, v1.8b, #3 +# CHECK: ushr v0.4h, v1.4h, #3 +# CHECK: ushr v0.2s, v1.2s, #3 +# CHECK: ushr v0.16b, v1.16b, #3 +# CHECK: ushr v0.8h, v1.8h, #3 +# CHECK: ushr v0.4s, v1.4s, #3 +# CHECK: ushr v0.2d, v1.2d, #3 +0x20,0x04,0x0d,0x2f +0x20,0x04,0x1d,0x2f +0x20,0x04,0x3d,0x2f +0x20,0x04,0x0d,0x6f +0x20,0x04,0x1d,0x6f +0x20,0x04,0x3d,0x6f +0x20,0x04,0x7d,0x6f + +#----------------------------------------------------------------------------- +#Integer shift right and accumulate (Signed) +#----------------------------------------------------------------------------- +# CHECK: ssra v0.8b, v1.8b, #3 +# CHECK: ssra v0.4h, v1.4h, #3 +# CHECK: ssra v0.2s, v1.2s, #3 +# CHECK: ssra v0.16b, v1.16b, #3 +# CHECK: ssra v0.8h, v1.8h, #3 +# CHECK: ssra v0.4s, v1.4s, #3 +# CHECK: ssra v0.2d, v1.2d, #3 +0x20,0x14,0x0d,0x0f +0x20,0x14,0x1d,0x0f +0x20,0x14,0x3d,0x0f +0x20,0x14,0x0d,0x4f +0x20,0x14,0x1d,0x4f +0x20,0x14,0x3d,0x4f +0x20,0x14,0x7d,0x4f + +#----------------------------------------------------------------------------- +#Integer shift right and accumulate (Unsigned) +#----------------------------------------------------------------------------- +# CHECK: usra v0.8b, v1.8b, #3 +# CHECK: usra v0.4h, v1.4h, #3 +# CHECK: usra v0.2s, v1.2s, #3 +# CHECK: usra v0.16b, v1.16b, #3 +# CHECK: usra v0.8h, v1.8h, #3 +# CHECK: usra v0.4s, v1.4s, #3 +# CHECK: usra v0.2d, v1.2d, #3 +0x20,0x14,0x0d,0x2f +0x20,0x14,0x1d,0x2f +0x20,0x14,0x3d,0x2f +0x20,0x14,0x0d,0x6f +0x20,0x14,0x1d,0x6f +0x20,0x14,0x3d,0x6f +0x20,0x14,0x7d,0x6f + +#----------------------------------------------------------------------------- +#Integer rounding shift right (Signed) +#----------------------------------------------------------------------------- +# CHECK: srshr v0.8b, v1.8b, #3 +# CHECK: srshr v0.4h, v1.4h, #3 +# CHECK: srshr v0.2s, v1.2s, #3 +# CHECK: srshr v0.16b, v1.16b, #3 +# CHECK: srshr v0.8h, v1.8h, #3 +# CHECK: srshr v0.4s, v1.4s, #3 +# CHECK: srshr v0.2d, v1.2d, #3 +0x20,0x24,0x0d,0x0f +0x20,0x24,0x1d,0x0f +0x20,0x24,0x3d,0x0f +0x20,0x24,0x0d,0x4f +0x20,0x24,0x1d,0x4f +0x20,0x24,0x3d,0x4f +0x20,0x24,0x7d,0x4f + +#----------------------------------------------------------------------------- +#Integer rounding shift right (Unsigned) +#----------------------------------------------------------------------------- +# CHECK: urshr v0.8b, v1.8b, #3 +# CHECK: urshr v0.4h, v1.4h, #3 +# CHECK: urshr v0.2s, v1.2s, #3 +# CHECK: urshr v0.16b, v1.16b, #3 +# CHECK: urshr v0.8h, v1.8h, #3 +# CHECK: urshr v0.4s, v1.4s, #3 +# CHECK: urshr v0.2d, v1.2d, #3 +0x20,0x24,0x0d,0x2f +0x20,0x24,0x1d,0x2f +0x20,0x24,0x3d,0x2f +0x20,0x24,0x0d,0x6f +0x20,0x24,0x1d,0x6f +0x20,0x24,0x3d,0x6f +0x20,0x24,0x7d,0x6f + +#----------------------------------------------------------------------------- +#Integer rounding shift right and accumulate (Signed) +#----------------------------------------------------------------------------- +# CHECK: srsra v0.8b, v1.8b, #3 +# CHECK: srsra v0.4h, v1.4h, #3 +# CHECK: srsra v0.2s, v1.2s, #3 +# CHECK: srsra v0.16b, v1.16b, #3 +# CHECK: srsra v0.8h, v1.8h, #3 +# CHECK: srsra v0.4s, v1.4s, #3 +# CHECK: srsra v0.2d, v1.2d, #3 +0x20,0x34,0x0d,0x0f +0x20,0x34,0x1d,0x0f +0x20,0x34,0x3d,0x0f +0x20,0x34,0x0d,0x4f +0x20,0x34,0x1d,0x4f +0x20,0x34,0x3d,0x4f +0x20,0x34,0x7d,0x4f + +#----------------------------------------------------------------------------- +#Integer rounding shift right and accumulate (Unsigned) +#----------------------------------------------------------------------------- +# CHECK: ursra v0.8b, v1.8b, #3 +# CHECK: ursra v0.4h, v1.4h, #3 +# CHECK: ursra v0.2s, v1.2s, #3 +# CHECK: ursra v0.16b, v1.16b, #3 +# CHECK: ursra v0.8h, v1.8h, #3 +# CHECK: ursra v0.4s, v1.4s, #3 +# CHECK: ursra v0.2d, v1.2d, #3 +0x20,0x34,0x0d,0x2f +0x20,0x34,0x1d,0x2f +0x20,0x34,0x3d,0x2f +0x20,0x34,0x0d,0x6f +0x20,0x34,0x1d,0x6f +0x20,0x34,0x3d,0x6f +0x20,0x34,0x7d,0x6f + +#----------------------------------------------------------------------------- +#Integer shift right and insert +#----------------------------------------------------------------------------- +# CHECK: sri v0.8b, v1.8b, #3 +# CHECK: sri v0.4h, v1.4h, #3 +# CHECK: sri v0.2s, v1.2s, #3 +# CHECK: sri v0.16b, v1.16b, #3 +# CHECK: sri v0.8h, v1.8h, #3 +# CHECK: sri v0.4s, v1.4s, #3 +# CHECK: sri v0.2d, v1.2d, #3 +0x20,0x44,0x0d,0x2f +0x20,0x44,0x1d,0x2f +0x20,0x44,0x3d,0x2f +0x20,0x44,0x0d,0x6f +0x20,0x44,0x1d,0x6f +0x20,0x44,0x3d,0x6f +0x20,0x44,0x7d,0x6f + +#----------------------------------------------------------------------------- +#Integer shift left and insert +#----------------------------------------------------------------------------- +# CHECK: sli v0.8b, v1.8b, #3 +# CHECK: sli v0.4h, v1.4h, #3 +# CHECK: sli v0.2s, v1.2s, #3 +# CHECK: sli v0.16b, v1.16b, #3 +# CHECK: sli v0.8h, v1.8h, #3 +# CHECK: sli v0.4s, v1.4s, #3 +# CHECK: sli v0.2d, v1.2d, #3 +0x20,0x54,0x0b,0x2f +0x20,0x54,0x13,0x2f +0x20,0x54,0x23,0x2f +0x20,0x54,0x0b,0x6f +0x20,0x54,0x13,0x6f +0x20,0x54,0x23,0x6f +0x20,0x54,0x43,0x6f + +#----------------------------------------------------------------------------- +#Integer saturating shift left unsigned +#----------------------------------------------------------------------------- +# CHECK: sqshlu v0.8b, v1.8b, #3 +# CHECK: sqshlu v0.4h, v1.4h, #3 +# CHECK: sqshlu v0.2s, v1.2s, #3 +# CHECK: sqshlu v0.16b, v1.16b, #3 +# CHECK: sqshlu v0.8h, v1.8h, #3 +# CHECK: sqshlu v0.4s, v1.4s, #3 +# CHECK: sqshlu v0.2d, v1.2d, #3 +0x20,0x64,0x0b,0x2f +0x20,0x64,0x13,0x2f +0x20,0x64,0x23,0x2f +0x20,0x64,0x0b,0x6f +0x20,0x64,0x13,0x6f +0x20,0x64,0x23,0x6f +0x20,0x64,0x43,0x6f + +#----------------------------------------------------------------------------- +#Integer saturating shift left (Signed) +#----------------------------------------------------------------------------- +# CHECK: sqshl v0.8b, v1.8b, #3 +# CHECK: sqshl v0.4h, v1.4h, #3 +# CHECK: sqshl v0.2s, v1.2s, #3 +# CHECK: sqshl v0.16b, v1.16b, #3 +# CHECK: sqshl v0.8h, v1.8h, #3 +# CHECK: sqshl v0.4s, v1.4s, #3 +# CHECK: sqshl v0.2d, v1.2d, #3 +0x20,0x74,0x0b,0x0f +0x20,0x74,0x13,0x0f +0x20,0x74,0x23,0x0f +0x20,0x74,0x0b,0x4f +0x20,0x74,0x13,0x4f +0x20,0x74,0x23,0x4f +0x20,0x74,0x43,0x4f + +#----------------------------------------------------------------------------- +#Integer saturating shift left (Unsigned) +#----------------------------------------------------------------------------- +# CHECK: uqshl v0.8b, v1.8b, #3 +# CHECK: uqshl v0.4h, v1.4h, #3 +# CHECK: uqshl v0.2s, v1.2s, #3 +# CHECK: uqshl v0.16b, v1.16b, #3 +# CHECK: uqshl v0.8h, v1.8h, #3 +# CHECK: uqshl v0.4s, v1.4s, #3 +# CHECK: uqshl v0.2d, v1.2d, #3 +0x20,0x74,0x0b,0x2f +0x20,0x74,0x13,0x2f +0x20,0x74,0x23,0x2f +0x20,0x74,0x0b,0x6f +0x20,0x74,0x13,0x6f +0x20,0x74,0x23,0x6f +0x20,0x74,0x43,0x6f + +#----------------------------------------------------------------------------- +#Integer shift right narrow +#----------------------------------------------------------------------------- +# CHECK: shrn v0.8b, v1.8h, #3 +# CHECK: shrn v0.4h, v1.4s, #3 +# CHECK: shrn v0.2s, v1.2d, #3 +# CHECK: shrn2 v0.16b, v1.8h, #3 +# CHECK: shrn2 v0.8h, v1.4s, #3 +# CHECK: shrn2 v0.4s, v1.2d, #3 +0x20,0x84,0x0d,0x0f +0x20,0x84,0x1d,0x0f +0x20,0x84,0x3d,0x0f +0x20,0x84,0x0d,0x4f +0x20,0x84,0x1d,0x4f +0x20,0x84,0x3d,0x4f + +#----------------------------------------------------------------------------- +#Integer saturating shift right unsigned narrow (Signed) +#----------------------------------------------------------------------------- +# CHECK: sqshrun v0.8b, v1.8h, #3 +# CHECK: sqshrun v0.4h, v1.4s, #3 +# CHECK: sqshrun v0.2s, v1.2d, #3 +# CHECK: sqshrun2 v0.16b, v1.8h, #3 +# CHECK: sqshrun2 v0.8h, v1.4s, #3 +# CHECK: sqshrun2 v0.4s, v1.2d, #3 +0x20,0x84,0x0d,0x2f +0x20,0x84,0x1d,0x2f +0x20,0x84,0x3d,0x2f +0x20,0x84,0x0d,0x6f +0x20,0x84,0x1d,0x6f +0x20,0x84,0x3d,0x6f + +#----------------------------------------------------------------------------- +#Integer rounding shift right narrow +#----------------------------------------------------------------------------- +# CHECK: rshrn v0.8b, v1.8h, #3 +# CHECK: rshrn v0.4h, v1.4s, #3 +# CHECK: rshrn v0.2s, v1.2d, #3 +# CHECK: rshrn2 v0.16b, v1.8h, #3 +# CHECK: rshrn2 v0.8h, v1.4s, #3 +# CHECK: rshrn2 v0.4s, v1.2d, #3 +0x20,0x8c,0x0d,0x0f +0x20,0x8c,0x1d,0x0f +0x20,0x8c,0x3d,0x0f +0x20,0x8c,0x0d,0x4f +0x20,0x8c,0x1d,0x4f +0x20,0x8c,0x3d,0x4f + +#----------------------------------------------------------------------------- +#Integer saturating shift right rounded unsigned narrow (Signed) +#----------------------------------------------------------------------------- +# CHECK: sqrshrun v0.8b, v1.8h, #3 +# CHECK: sqrshrun v0.4h, v1.4s, #3 +# CHECK: sqrshrun v0.2s, v1.2d, #3 +# CHECK: sqrshrun2 v0.16b, v1.8h, #3 +# CHECK: sqrshrun2 v0.8h, v1.4s, #3 +# CHECK: sqrshrun2 v0.4s, v1.2d, #3 +0x20,0x8c,0x0d,0x2f +0x20,0x8c,0x1d,0x2f +0x20,0x8c,0x3d,0x2f +0x20,0x8c,0x0d,0x6f +0x20,0x8c,0x1d,0x6f +0x20,0x8c,0x3d,0x6f + +#----------------------------------------------------------------------------- +#Integer saturating shift right narrow (Signed) +#----------------------------------------------------------------------------- +# CHECK: sqshrn v0.8b, v1.8h, #3 +# CHECK: sqshrn v0.4h, v1.4s, #3 +# CHECK: sqshrn v0.2s, v1.2d, #3 +# CHECK: sqshrn2 v0.16b, v1.8h, #3 +# CHECK: sqshrn2 v0.8h, v1.4s, #3 +# CHECK: sqshrn2 v0.4s, v1.2d, #3 +0x20,0x94,0x0d,0x0f +0x20,0x94,0x1d,0x0f +0x20,0x94,0x3d,0x0f +0x20,0x94,0x0d,0x4f +0x20,0x94,0x1d,0x4f +0x20,0x94,0x3d,0x4f + +#----------------------------------------------------------------------------- +#Integer saturating shift right narrow (Unsigned) +#----------------------------------------------------------------------------- +# CHECK: uqshrn v0.8b, v1.8h, #3 +# CHECK: uqshrn v0.4h, v1.4s, #3 +# CHECK: uqshrn v0.2s, v1.2d, #3 +# CHECK: uqshrn2 v0.16b, v1.8h, #3 +# CHECK: uqshrn2 v0.8h, v1.4s, #3 +# CHECK: uqshrn2 v0.4s, v1.2d, #3 +0x20,0x94,0x0d,0x2f +0x20,0x94,0x1d,0x2f +0x20,0x94,0x3d,0x2f +0x20,0x94,0x0d,0x6f +0x20,0x94,0x1d,0x6f +0x20,0x94,0x3d,0x6f + +#----------------------------------------------------------------------------- +#Integer saturating shift right rounded narrow (Signed) +#----------------------------------------------------------------------------- +# CHECK: sqrshrn v0.8b, v1.8h, #3 +# CHECK: sqrshrn v0.4h, v1.4s, #3 +# CHECK: sqrshrn v0.2s, v1.2d, #3 +# CHECK: sqrshrn2 v0.16b, v1.8h, #3 +# CHECK: sqrshrn2 v0.8h, v1.4s, #3 +# CHECK: sqrshrn2 v0.4s, v1.2d, #3 +0x20,0x9c,0x0d,0x0f +0x20,0x9c,0x1d,0x0f +0x20,0x9c,0x3d,0x0f +0x20,0x9c,0x0d,0x4f +0x20,0x9c,0x1d,0x4f +0x20,0x9c,0x3d,0x4f + +#----------------------------------------------------------------------------- +#Integer saturating shift right rounded narrow (Unsigned) +#----------------------------------------------------------------------------- +# CHECK: uqrshrn v0.8b, v1.8h, #3 +# CHECK: uqrshrn v0.4h, v1.4s, #3 +# CHECK: uqrshrn v0.2s, v1.2d, #3 +# CHECK: uqrshrn2 v0.16b, v1.8h, #3 +# CHECK: uqrshrn2 v0.8h, v1.4s, #3 +# CHECK: uqrshrn2 v0.4s, v1.2d, #3 +0x20,0x9c,0x0d,0x2f +0x20,0x9c,0x1d,0x2f +0x20,0x9c,0x3d,0x2f +0x20,0x9c,0x0d,0x6f +0x20,0x9c,0x1d,0x6f +0x20,0x9c,0x3d,0x6f + +#----------------------------------------------------------------------------- +#Fixed-point convert to floating-point +#----------------------------------------------------------------------------- +# CHECK: scvtf v0.2s, v1.2s, #3 +# CHECK: scvtf v0.4s, v1.4s, #3 +# CHECK: scvtf v0.2d, v1.2d, #3 +# CHECK: ucvtf v0.2s, v1.2s, #3 +# CHECK: ucvtf v0.4s, v1.4s, #3 +# CHECK: ucvtf v0.2d, v1.2d, #3 + +0x20,0xe4,0x3d,0x0f +0x20,0xe4,0x3d,0x4f +0x20,0xe4,0x7d,0x4f +0x20,0xe4,0x3d,0x2f +0x20,0xe4,0x3d,0x6f +0x20,0xe4,0x7d,0x6f + +#----------------------------------------------------------------------------- +#Floating-point convert to fixed-point +#----------------------------------------------------------------------------- +# CHECK: fcvtzs v0.2s, v1.2s, #3 +# CHECK: fcvtzs v0.4s, v1.4s, #3 +# CHECK: fcvtzs v0.2d, v1.2d, #3 +# CHECK: fcvtzu v0.2s, v1.2s, #3 +# CHECK: fcvtzu v0.4s, v1.4s, #3 +# CHECK: fcvtzu v0.2d, v1.2d, #3 +0x20,0xfc,0x3d,0x0f +0x20,0xfc,0x3d,0x4f +0x20,0xfc,0x7d,0x4f +0x20,0xfc,0x3d,0x2f +0x20,0xfc,0x3d,0x6f +0x20,0xfc,0x7d,0x6f + + +#------------------------------------------------------------------------------ +# Vector with 3 operands having different data types +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# Long +#------------------------------------------------------------------------------ + +#------------------------------------------------------------------------------ +# Long - Variant 1 +#------------------------------------------------------------------------------ + +# CHECK: saddl v0.8h, v1.8b, v2.8b +# CHECK: saddl v0.4s, v1.4h, v2.4h +# CHECK: saddl v0.2d, v1.2s, v2.2s +0x20 0x00 0x22 0x0e +0x20 0x00 0x62 0x0e +0x20 0x00 0xa2 0x0e + +# CHECK: saddl2 v0.4s, v1.8h, v2.8h +# CHECK: saddl2 v0.8h, v1.16b, v2.16b +# CHECK: saddl2 v0.2d, v1.4s, v2.4s +0x20 0x00 0x62 0x4e +0x20 0x00 0x22 0x4e +0x20 0x00 0xa2 0x4e + +# CHECK: uaddl v0.8h, v1.8b, v2.8b +# CHECK: uaddl v0.4s, v1.4h, v2.4h +# CHECK: uaddl v0.2d, v1.2s, v2.2s +0x20 0x00 0x22 0x2e +0x20 0x00 0x62 0x2e +0x20 0x00 0xa2 0x2e + +# CHECK: uaddl2 v0.8h, v1.16b, v2.16b +# CHECK: uaddl2 v0.4s, v1.8h, v2.8h +# CHECK: uaddl2 v0.2d, v1.4s, v2.4s +0x20 0x00 0x22 0x6e +0x20 0x00 0x62 0x6e +0x20 0x00 0xa2 0x6e + +# CHECK: ssubl v0.8h, v1.8b, v2.8b +# CHECK: ssubl v0.4s, v1.4h, v2.4h +# CHECK: ssubl v0.2d, v1.2s, v2.2s +0x20 0x20 0x22 0x0e +0x20 0x20 0x62 0x0e +0x20 0x20 0xa2 0x0e + +# CHECK: ssubl2 v0.8h, v1.16b, v2.16b +# CHECK: ssubl2 v0.4s, v1.8h, v2.8h +# CHECK: ssubl2 v0.2d, v1.4s, v2.4s +0x20 0x20 0x22 0x4e +0x20 0x20 0x62 0x4e +0x20 0x20 0xa2 0x4e + +# CHECK: usubl v0.8h, v1.8b, v2.8b +# CHECK: usubl v0.4s, v1.4h, v2.4h +# CHECK: usubl v0.2d, v1.2s, v2.2s +0x20 0x20 0x22 0x2e +0x20 0x20 0x62 0x2e +0x20 0x20 0xa2 0x2e + +# CHECK: usubl2 v0.8h, v1.16b, v2.16b +# CHECK: usubl2 v0.4s, v1.8h, v2.8h +# CHECK: usubl2 v0.2d, v1.4s, v2.4s +0x20 0x20 0x22 0x6e +0x20 0x20 0x62 0x6e +0x20 0x20 0xa2 0x6e + +# CHECK: sabal v0.8h, v1.8b, v2.8b +# CHECK: sabal v0.4s, v1.4h, v2.4h +# CHECK: sabal v0.2d, v1.2s, v2.2s +0x20 0x50 0x22 0x0e +0x20 0x50 0x62 0x0e +0x20 0x50 0xa2 0x0e + +# CHECK: sabal2 v0.8h, v1.16b, v2.16b +# CHECK: sabal2 v0.4s, v1.8h, v2.8h +# CHECK: sabal2 v0.2d, v1.4s, v2.4s +0x20 0x50 0x22 0x4e +0x20 0x50 0x62 0x4e +0x20 0x50 0xa2 0x4e + +# CHECK: uabal v0.8h, v1.8b, v2.8b +# CHECK: uabal v0.4s, v1.4h, v2.4h +# CHECK: uabal v0.2d, v1.2s, v2.2s +0x20 0x50 0x22 0x2e +0x20 0x50 0x62 0x2e +0x20 0x50 0xa2 0x2e + +# CHECK: uabal2 v0.8h, v1.16b, v2.16b +# CHECK: uabal2 v0.4s, v1.8h, v2.8h +# CHECK: uabal2 v0.2d, v1.4s, v2.4s +0x20 0x50 0x22 0x6e +0x20 0x50 0x62 0x6e +0x20 0x50 0xa2 0x6e + +# CHECK: sabdl v0.8h, v1.8b, v2.8b +# CHECK: sabdl v0.4s, v1.4h, v2.4h +# CHECK: sabdl v0.2d, v1.2s, v2.2s +0x20 0x70 0x22 0x0e +0x20 0x70 0x62 0x0e +0x20 0x70 0xa2 0x0e + +# CHECK: sabdl2 v0.8h, v1.16b, v2.16b +# CHECK: sabdl2 v0.4s, v1.8h, v2.8h +# CHECK: sabdl2 v0.2d, v1.4s, v2.4s +0x20 0x70 0x22 0x4e +0x20 0x70 0x62 0x4e +0x20 0x70 0xa2 0x4e + +# CHECK: uabdl v0.8h, v1.8b, v2.8b +# CHECK: uabdl v0.4s, v1.4h, v2.4h +# CHECK: uabdl v0.2d, v1.2s, v2.2s +0x20 0x70 0x22 0x2e +0x20 0x70 0x62 0x2e +0x20 0x70 0xa2 0x2e + +# CHECK: uabdl2 v0.8h, v1.16b, v2.16b +# CHECK: uabdl2 v0.4s, v1.8h, v2.8h +# CHECK: uabdl2 v0.2d, v1.4s, v2.4s +0x20 0x70 0x22 0x6e +0x20 0x70 0x62 0x6e +0x20 0x70 0xa2 0x6e + +# CHECK: smlal v0.8h, v1.8b, v2.8b +# CHECK: smlal v0.4s, v1.4h, v2.4h +# CHECK: smlal v0.2d, v1.2s, v2.2s +0x20 0x80 0x22 0x0e +0x20 0x80 0x62 0x0e +0x20 0x80 0xa2 0x0e + +# CHECK: smlal2 v0.8h, v1.16b, v2.16b +# CHECK: smlal2 v0.4s, v1.8h, v2.8h +# CHECK: smlal2 v0.2d, v1.4s, v2.4s +0x20 0x80 0x22 0x4e +0x20 0x80 0x62 0x4e +0x20 0x80 0xa2 0x4e + +# CHECK: umlal v0.8h, v1.8b, v2.8b +# CHECK: umlal v0.4s, v1.4h, v2.4h +# CHECK: umlal v0.2d, v1.2s, v2.2s + +0x20 0x80 0x22 0x2e +0x20 0x80 0x62 0x2e +0x20 0x80 0xa2 0x2e + +# CHECK: umlal2 v0.8h, v1.16b, v2.16b +# CHECK: umlal2 v0.4s, v1.8h, v2.8h +# CHECK: umlal2 v0.2d, v1.4s, v2.4s +0x20 0x80 0x22 0x6e +0x20 0x80 0x62 0x6e +0x20 0x80 0xa2 0x6e + +# CHECK: smlsl v0.8h, v1.8b, v2.8b +# CHECK: smlsl v0.4s, v1.4h, v2.4h +# CHECK: smlsl v0.2d, v1.2s, v2.2s +0x20 0xa0 0x22 0x0e +0x20 0xa0 0x62 0x0e +0x20 0xa0 0xa2 0x0e + +# CHECK: smlsl2 v0.8h, v1.16b, v2.16b +# CHECK: smlsl2 v0.4s, v1.8h, v2.8h +# CHECK: smlsl2 v0.2d, v1.4s, v2.4s +0x20 0xa0 0x22 0x4e +0x20 0xa0 0x62 0x4e +0x20 0xa0 0xa2 0x4e + +# CHECK: umlsl v0.8h, v1.8b, v2.8b +# CHECK: umlsl v0.4s, v1.4h, v2.4h +# CHECK: umlsl v0.2d, v1.2s, v2.2s +0x20 0xa0 0x22 0x2e +0x20 0xa0 0x62 0x2e +0x20 0xa0 0xa2 0x2e + +# CHECK: umlsl2 v0.8h, v1.16b, v2.16b +# CHECK: umlsl2 v0.4s, v1.8h, v2.8h +# CHECK: umlsl2 v0.2d, v1.4s, v2.4s +0x20 0xa0 0x22 0x6e +0x20 0xa0 0x62 0x6e +0x20 0xa0 0xa2 0x6e + +# CHECK: smull v0.8h, v1.8b, v2.8b +# CHECK: smull v0.4s, v1.4h, v2.4h +# CHECK: smull v0.2d, v1.2s, v2.2s +0x20 0xc0 0x22 0x0e +0x20 0xc0 0x62 0x0e +0x20 0xc0 0xa2 0x0e + +# CHECK: smull2 v0.8h, v1.16b, v2.16b +# CHECK: smull2 v0.4s, v1.8h, v2.8h +# CHECK: smull2 v0.2d, v1.4s, v2.4s +0x20 0xc0 0x22 0x4e +0x20 0xc0 0x62 0x4e +0x20 0xc0 0xa2 0x4e + +# CHECK: umull v0.8h, v1.8b, v2.8b +# CHECK: umull v0.4s, v1.4h, v2.4h +# CHECK: umull v0.2d, v1.2s, v2.2s +0x20 0xc0 0x22 0x2e +0x20 0xc0 0x62 0x2e +0x20 0xc0 0xa2 0x2e + +# CHECK: umull2 v0.8h, v1.16b, v2.16b +# CHECK: umull2 v0.4s, v1.8h, v2.8h +# CHECK: umull2 v0.2d, v1.4s, v2.4s +0x20 0xc0 0x22 0x6e +0x20 0xc0 0x62 0x6e +0x20 0xc0 0xa2 0x6e + +#------------------------------------------------------------------------------ +# Long - Variant 2 +#------------------------------------------------------------------------------ + +# CHECK: sqdmlal v0.4s, v1.4h, v2.4h +# CHECK: sqdmlal v0.2d, v1.2s, v2.2s +0x20 0x90 0x62 0x0e +0x20 0x90 0xa2 0x0e + +# CHECK: sqdmlal2 v0.4s, v1.8h, v2.8h +# CHECK: sqdmlal2 v0.2d, v1.4s, v2.4s +0x20 0x90 0x62 0x4e +0x20 0x90 0xa2 0x4e + +# CHECK: sqdmlsl v0.4s, v1.4h, v2.4h +# CHECK: sqdmlsl v0.2d, v1.2s, v2.2s +0x20 0xb0 0x62 0x0e +0x20 0xb0 0xa2 0x0e + +# CHECK: sqdmlsl2 v0.4s, v1.8h, v2.8h +# CHECK: sqdmlsl2 v0.2d, v1.4s, v2.4s +0x20 0xb0 0x62 0x4e +0x20 0xb0 0xa2 0x4e + +# CHECK: sqdmull v0.4s, v1.4h, v2.4h +# CHECK: sqdmull v0.2d, v1.2s, v2.2s +0x20 0xd0 0x62 0x0e +0x20 0xd0 0xa2 0x0e + +# CHECK: sqdmull2 v0.4s, v1.8h, v2.8h +# CHECK: sqdmull2 v0.2d, v1.4s, v2.4s +0x20 0xd0 0x62 0x4e +0x20 0xd0 0xa2 0x4e + +#------------------------------------------------------------------------------ +# Long - Variant 3 +#------------------------------------------------------------------------------ + +# CHECK: pmull v0.8h, v1.8b, v2.8b +0x20 0xe0 0x22 0x0e + +# CHECK: pmull2 v0.8h, v1.16b, v2.16b +0x20 0xe0 0x22 0x4e + +#------------------------------------------------------------------------------ +# Widen +#------------------------------------------------------------------------------ + +# CHECK: saddw v0.8h, v1.8h, v2.8b +# CHECK: saddw v0.4s, v1.4s, v2.4h +# CHECK: saddw v0.2d, v1.2d, v2.2s +0x20 0x10 0x22 0x0e +0x20 0x10 0x62 0x0e +0x20 0x10 0xa2 0x0e + +# CHECK: saddw2 v0.8h, v1.8h, v2.16b +# CHECK: saddw2 v0.4s, v1.4s, v2.8h +# CHECK: saddw2 v0.2d, v1.2d, v2.4s +0x20 0x10 0x22 0x4e +0x20 0x10 0x62 0x4e +0x20 0x10 0xa2 0x4e + +# CHECK: uaddw v0.8h, v1.8h, v2.8b +# CHECK: uaddw v0.4s, v1.4s, v2.4h +# CHECK: uaddw v0.2d, v1.2d, v2.2s +0x20 0x10 0x22 0x2e +0x20 0x10 0x62 0x2e +0x20 0x10 0xa2 0x2e + +# CHECK: uaddw2 v0.8h, v1.8h, v2.16b +# CHECK: uaddw2 v0.4s, v1.4s, v2.8h +# CHECK: uaddw2 v0.2d, v1.2d, v2.4s +0x20 0x10 0x22 0x6e +0x20 0x10 0x62 0x6e +0x20 0x10 0xa2 0x6e + +# CHECK: ssubw v0.8h, v1.8h, v2.8b +# CHECK: ssubw v0.4s, v1.4s, v2.4h +# CHECK: ssubw v0.2d, v1.2d, v2.2s +0x20 0x30 0x22 0x0e +0x20 0x30 0x62 0x0e +0x20 0x30 0xa2 0x0e + +# CHECK: ssubw2 v0.8h, v1.8h, v2.16b +# CHECK: ssubw2 v0.4s, v1.4s, v2.8h +# CHECK: ssubw2 v0.2d, v1.2d, v2.4s +0x20 0x30 0x22 0x4e +0x20 0x30 0x62 0x4e +0x20 0x30 0xa2 0x4e + +# CHECK: usubw v0.8h, v1.8h, v2.8b +# CHECK: usubw v0.4s, v1.4s, v2.4h +# CHECK: usubw v0.2d, v1.2d, v2.2s +0x20 0x30 0x22 0x2e +0x20 0x30 0x62 0x2e +0x20 0x30 0xa2 0x2e + +# CHECK: usubw2 v0.8h, v1.8h, v2.16b +# CHECK: usubw2 v0.4s, v1.4s, v2.8h +# CHECK: usubw2 v0.2d, v1.2d, v2.4s +0x20 0x30 0x22 0x6e +0x20 0x30 0x62 0x6e +0x20 0x30 0xa2 0x6e + +#------------------------------------------------------------------------------ +# Narrow +#------------------------------------------------------------------------------ + +# CHECK: addhn v0.8b, v1.8h, v2.8h +# CHECK: addhn v0.4h, v1.4s, v2.4s +# CHECK: addhn v0.2s, v1.2d, v2.2d +0x20 0x40 0x22 0x0e +0x20 0x40 0x62 0x0e +0x20 0x40 0xa2 0x0e + +# CHECK: addhn2 v0.16b, v1.8h, v2.8h +# CHECK: addhn2 v0.8h, v1.4s, v2.4s +# CHECK: addhn2 v0.4s, v1.2d, v2.2d +0x20 0x40 0x22 0x4e +0x20 0x40 0x62 0x4e +0x20 0x40 0xa2 0x4e + +# CHECK: raddhn v0.8b, v1.8h, v2.8h +# CHECK: raddhn v0.4h, v1.4s, v2.4s +# CHECK: raddhn v0.2s, v1.2d, v2.2d +0x20 0x40 0x22 0x2e +0x20 0x40 0x62 0x2e +0x20 0x40 0xa2 0x2e + +# CHECK: raddhn2 v0.16b, v1.8h, v2.8h +# CHECK: raddhn2 v0.8h, v1.4s, v2.4s +# CHECK: raddhn2 v0.4s, v1.2d, v2.2d +0x20 0x40 0x22 0x6e +0x20 0x40 0x62 0x6e +0x20 0x40 0xa2 0x6e + +# CHECK: rsubhn v0.8b, v1.8h, v2.8h +# CHECK: rsubhn v0.4h, v1.4s, v2.4s +# CHECK: rsubhn v0.2s, v1.2d, v2.2d +0x20 0x60 0x22 0x2e +0x20 0x60 0x62 0x2e +0x20 0x60 0xa2 0x2e + +# CHECK: rsubhn2 v0.16b, v1.8h, v2.8h +# CHECK: rsubhn2 v0.8h, v1.4s, v2.4s +# CHECK: rsubhn2 v0.4s, v1.2d, v2.2d +0x20 0x60 0x22 0x6e +0x20 0x60 0x62 0x6e +0x20 0x60 0xa2 0x6e + +#---------------------------------------------------------------------- +# Scalar Integer Saturating Doubling Multiply Half High +#---------------------------------------------------------------------- +# CHECK: sqdmulh h10, h11, h12 +# CHECK: sqdmulh s20, s21, s2 +0x6a,0xb5,0x6c,0x5e +0xb4,0xb6,0xa2,0x5e + +#---------------------------------------------------------------------- +# Scalar Integer Saturating Rounding Doubling Multiply Half High +#---------------------------------------------------------------------- +# CHECK: sqrdmulh h10, h11, h12 +# CHECK: sqrdmulh s20, s21, s2 +0x6a,0xb5,0x6c,0x7e +0xb4,0xb6,0xa2,0x7e + +#---------------------------------------------------------------------- +# Floating-point multiply extended +#---------------------------------------------------------------------- +# CHECK: fmulx s20, s22, s15 +# CHECK: fmulx d23, d11, d1 +0xd4,0xde,0x2f,0x5e +0x77,0xdd,0x61,0x5e + +#---------------------------------------------------------------------- +# Floating-point Reciprocal Step +#---------------------------------------------------------------------- +# CHECK: frecps s21, s16, s13 +# CHECK: frecps d22, d30, d21 +0x15,0xfe,0x2d,0x5e +0xd6,0xff,0x75,0x5e + +#---------------------------------------------------------------------- +# Floating-point Reciprocal Square Root Step +#---------------------------------------------------------------------- +# CHECK: frsqrts s21, s5, s12 +# CHECK: frsqrts d8, d22, d18 +0xb5,0xfc,0xac,0x5e +0xc8,0xfe,0xf2,0x5e + +#---------------------------------------------------------------------- +# Scalar Signed Integer Convert To Floating-point +#---------------------------------------------------------------------- +# CHECK: scvtf s22, s13 +# CHECK: scvtf d21, d12 +0xb6,0xd9,0x21,0x5e +0x95,0xd9,0x61,0x5e + +#---------------------------------------------------------------------- +# Scalar Unsigned Integer Convert To Floating-point +#---------------------------------------------------------------------- +# CHECK: ucvtf s22, s13 +# CHECK: ucvtf d21, d14 +0xb6,0xd9,0x21,0x7e +0xd5,0xd9,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Reciprocal Estimate +#---------------------------------------------------------------------- +# CHECK: frecpe s19, s14 +# CHECK: frecpe d13, d13 +0xd3,0xd9,0xa1,0x5e +0xad,0xd9,0xe1,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Reciprocal Exponent +#---------------------------------------------------------------------- +# CHECK: frecpx s18, s10 +# CHECK: frecpx d16, d19 +0x52,0xf9,0xa1,0x5e +0x70,0xfa,0xe1,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Reciprocal Square Root Estimate +#---------------------------------------------------------------------- +# CHECK: frsqrte s22, s13 +# CHECK: frsqrte d21, d12 +0xb6,0xd9,0xa1,0x7e +0x95,0xd9,0xe1,0x7e + +#---------------------------------------------------------------------- +# Scalar Compare Bitwise Equal +#---------------------------------------------------------------------- +# CHECK: cmeq d20, d21, d22 +0xb4,0x8e,0xf6,0x7e + +#---------------------------------------------------------------------- +# Scalar Compare Bitwise Equal To Zero +#---------------------------------------------------------------------- +# CHECK: cmeq d20, d21, #0x0 +0xb4,0x9a,0xe0,0x5e + +#---------------------------------------------------------------------- +# Scalar Compare Unsigned Higher Or Same +#---------------------------------------------------------------------- +# CHECK: cmhs d20, d21, d22 +0xb4,0x3e,0xf6,0x7e + + +#---------------------------------------------------------------------- +# Scalar Compare Signed Greather Than Or Equal +#---------------------------------------------------------------------- +# CHECK: cmge d20, d21, d22 +0xb4,0x3e,0xf6,0x5e + +#---------------------------------------------------------------------- +# Scalar Compare Signed Greather Than Or Equal To Zero +#---------------------------------------------------------------------- +# CHECK: cmge d20, d21, #0x0 +0xb4,0x8a,0xe0,0x7e + +#---------------------------------------------------------------------- +# Scalar Compare Unsigned Higher +#---------------------------------------------------------------------- +# CHECK: cmhi d20, d21, d22 +0xb4,0x36,0xf6,0x7e + +#---------------------------------------------------------------------- +# Scalar Compare Signed Greater Than +#---------------------------------------------------------------------- +# CHECK: cmgt d20, d21, d22 +0xb4,0x36,0xf6,0x5e + +#---------------------------------------------------------------------- +# Scalar Compare Signed Greater Than Zero +#---------------------------------------------------------------------- +# CHECK: cmgt d20, d21, #0x0 +0xb4,0x8a,0xe0,0x5e + +#---------------------------------------------------------------------- +# Scalar Compare Signed Less Than Or Equal To Zero +#---------------------------------------------------------------------- +# CHECK: cmle d20, d21, #0x0 +0xb4,0x9a,0xe0,0x7e + +#---------------------------------------------------------------------- +# Scalar Compare Less Than Zero +#---------------------------------------------------------------------- +# CHECK: cmlt d20, d21, #0x0 +0xb4,0xaa,0xe0,0x5e + +#---------------------------------------------------------------------- +# Scalar Compare Bitwise Test Bits +#---------------------------------------------------------------------- +# CHECK: cmtst d20, d21, d22 +0xb4,0x8e,0xf6,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Compare Mask Equal +#---------------------------------------------------------------------- +# CHECK: fcmeq s10, s11, s12 +# CHECK: fcmeq d20, d21, d22 +0x6a,0xe5,0x2c,0x5e +0xb4,0xe6,0x76,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Compare Mask Equal To Zero +#---------------------------------------------------------------------- +# CHECK: fcmeq s10, s11, #0.0 +# CHECK: fcmeq d20, d21, #0.0 +0x6a,0xd9,0xa0,0x5e +0xb4,0xda,0xe0,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Compare Mask Greater Than Or Equal +#---------------------------------------------------------------------- +# CHECK: fcmge s10, s11, s12 +# CHECK: fcmge d20, d21, d22 +0x6a,0xe5,0x2c,0x7e +0xb4,0xe6,0x76,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Compare Mask Greater Than Or Equal To Zero +#---------------------------------------------------------------------- +# CHECK: fcmge s10, s11, #0.0 +# CHECK: fcmge d20, d21, #0.0 +0x6a,0xc9,0xa0,0x7e +0xb4,0xca,0xe0,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Compare Mask Greather Than +#---------------------------------------------------------------------- +# CHECK: fcmgt s10, s11, s12 +# CHECK: fcmgt d20, d21, d22 +0x6a,0xe5,0xac,0x7e +0xb4,0xe6,0xf6,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Compare Mask Greather Than Zero +#---------------------------------------------------------------------- +# CHECK: fcmgt s10, s11, #0.0 +# CHECK: fcmgt d20, d21, #0.0 +0x6a,0xc9,0xa0,0x5e +0xb4,0xca,0xe0,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Compare Mask Less Than Or Equal To Zero +#---------------------------------------------------------------------- +# CHECK: fcmle s10, s11, #0.0 +# CHECK: fcmle d20, d21, #0.0 +0x6a,0xd9,0xa0,0x7e +0xb4,0xda,0xe0,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Compare Mask Less Than +#---------------------------------------------------------------------- +# CHECK: fcmlt s10, s11, #0.0 +# CHECK: fcmlt d20, d21, #0.0 +0x6a,0xe9,0xa0,0x5e +0xb4,0xea,0xe0,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Absolute Compare Mask Greater Than Or Equal +#---------------------------------------------------------------------- +# CHECK: facge s10, s11, s12 +# CHECK: facge d20, d21, d22 +0x6a,0xed,0x2c,0x7e +0xb4,0xee,0x76,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Absolute Compare Mask Greater Than +#---------------------------------------------------------------------- +# CHECK: facgt s10, s11, s12 +# CHECK: facgt d20, d21, d22 +0x6a,0xed,0xac,0x7e +0xb4,0xee,0xf6,0x7e + +#---------------------------------------------------------------------- +# Scalar Absolute Value +#---------------------------------------------------------------------- +# CHECK: abs d29, d24 +0x1d,0xbb,0xe0,0x5e + +#---------------------------------------------------------------------- +# Scalar Signed Saturating Absolute Value +#---------------------------------------------------------------------- +# CHECK: sqabs b19, b14 +# CHECK: sqabs h21, h15 +# CHECK: sqabs s20, s12 +# CHECK: sqabs d18, d12 +0xd3,0x79,0x20,0x5e +0xf5,0x79,0x60,0x5e +0x94,0x79,0xa0,0x5e +0x92,0x79,0xe0,0x5e + +#---------------------------------------------------------------------- +# Scalar Negate +#---------------------------------------------------------------------- +# CHECK: neg d29, d24 +0x1d,0xbb,0xe0,0x7e + +#---------------------------------------------------------------------- +# Scalar Signed Saturating Negate +#---------------------------------------------------------------------- +# CHECK: sqneg b19, b14 +# CHECK: sqneg h21, h15 +# CHECK: sqneg s20, s12 +# CHECK: sqneg d18, d12 +0xd3,0x79,0x20,0x7e +0xf5,0x79,0x60,0x7e +0x94,0x79,0xa0,0x7e +0x92,0x79,0xe0,0x7e + +#---------------------------------------------------------------------- +# Signed Saturating Accumulated of Unsigned Value +#---------------------------------------------------------------------- +# CHECK: suqadd b19, b14 +# CHECK: suqadd h20, h15 +# CHECK: suqadd s21, s12 +# CHECK: suqadd d18, d22 +0xd3,0x39,0x20,0x5e +0xf4,0x39,0x60,0x5e +0x95,0x39,0xa0,0x5e +0xd2,0x3a,0xe0,0x5e + +#---------------------------------------------------------------------- +# Unsigned Saturating Accumulated of Signed Value +#---------------------------------------------------------------------- +# CHECK: usqadd b19, b14 +# CHECK: usqadd h20, h15 +# CHECK: usqadd s21, s12 +# CHECK: usqadd d18, d22 +0xd3,0x39,0x20,0x7e +0xf4,0x39,0x60,0x7e +0x95,0x39,0xa0,0x7e +0xd2,0x3a,0xe0,0x7e + +#---------------------------------------------------------------------- +# Signed Saturating Doubling Multiply-Add Long +#---------------------------------------------------------------------- +# CHECK: sqdmlal s17, h27, h12 +# CHECK: sqdmlal d19, s24, s12 +0x71,0x93,0x6c,0x5e +0x13,0x93,0xac,0x5e + +#---------------------------------------------------------------------- +# Signed Saturating Doubling Multiply-Subtract Long +#---------------------------------------------------------------------- +# CHECK: sqdmlsl s14, h12, h25 +# CHECK: sqdmlsl d12, s23, s13 +0x8e,0xb1,0x79,0x5e +0xec,0xb2,0xad,0x5e + +#---------------------------------------------------------------------- +# Signed Saturating Doubling Multiply Long +#---------------------------------------------------------------------- +# CHECK: sqdmull s12, h22, h12 +# CHECK: sqdmull d15, s22, s12 +0xcc,0xd2,0x6c,0x5e +0xcf,0xd2,0xac,0x5e + +#---------------------------------------------------------------------- +# Scalar Signed Saturating Extract Unsigned Narrow +#---------------------------------------------------------------------- +# CHECK: sqxtun b19, h14 +# CHECK: sqxtun h21, s15 +# CHECK: sqxtun s20, d12 +0xd3,0x29,0x21,0x7e +0xf5,0x29,0x61,0x7e +0x94,0x29,0xa1,0x7e + +#---------------------------------------------------------------------- +# Scalar Signed Saturating Extract Signed Narrow +#---------------------------------------------------------------------- +# CHECK: sqxtn b18, h18 +# CHECK: sqxtn h20, s17 +# CHECK: sqxtn s19, d14 +0x52,0x4a,0x21,0x5e +0x34,0x4a,0x61,0x5e +0xd3,0x49,0xa1,0x5e + +#---------------------------------------------------------------------- +# Scalar Unsigned Saturating Extract Narrow +#---------------------------------------------------------------------- +# CHECK: uqxtn b18, h18 +# CHECK: uqxtn h20, s17 +# CHECK: uqxtn s19, d14 +0x52,0x4a,0x21,0x7e +0x34,0x4a,0x61,0x7e +0xd3,0x49,0xa1,0x7e + +#---------------------------------------------------------------------- +# Scalar Signed Shift Right (Immediate) +#---------------------------------------------------------------------- +# CHECK: sshr d15, d16, #12 +0x0f,0x06,0x74,0x5f + +#---------------------------------------------------------------------- +# Scalar Unsigned Shift Right (Immediate) +#---------------------------------------------------------------------- +# CHECK: ushr d10, d17, #18 +0x2a,0x06,0x6e,0x7f + +#---------------------------------------------------------------------- +# Scalar Signed Rounding Shift Right (Immediate) +#---------------------------------------------------------------------- +# CHECK: srshr d19, d18, #7 +0x53,0x26,0x79,0x5f + +#---------------------------------------------------------------------- +# Scalar Unigned Rounding Shift Right (Immediate) +#---------------------------------------------------------------------- +# CHECK: urshr d20, d23, #31 +0xf4,0x26,0x61,0x7f + +#---------------------------------------------------------------------- +# Scalar Signed Shift Right and Accumulate (Immediate) +#---------------------------------------------------------------------- +# CHECK: ssra d18, d12, #21 +0x92,0x15,0x6b,0x5f + +#---------------------------------------------------------------------- +# Scalar Unsigned Shift Right and Accumulate (Immediate) +#---------------------------------------------------------------------- +# CHECK: usra d20, d13, #61 +0xb4,0x15,0x43,0x7f + +#---------------------------------------------------------------------- +# Scalar Signed Rounding Shift Right and Accumulate (Immediate) +#---------------------------------------------------------------------- +# CHECK: srsra d15, d11, #19 +0x6f,0x35,0x6d,0x5f + +#---------------------------------------------------------------------- +# Scalar Unsigned Rounding Shift Right and Accumulate (Immediate) +#---------------------------------------------------------------------- +# CHECK: ursra d18, d10, #13 +0x52,0x35,0x73,0x7f + +#---------------------------------------------------------------------- +# Scalar Shift Left (Immediate) +#---------------------------------------------------------------------- +# CHECK: shl d7, d10, #12 +0x47,0x55,0x4c,0x5f + +#---------------------------------------------------------------------- +# Signed Saturating Shift Left (Immediate) +#---------------------------------------------------------------------- +# CHECK: sqshl b11, b19, #7 +# CHECK: sqshl h13, h18, #11 +# CHECK: sqshl s14, s17, #22 +# CHECK: sqshl d15, d16, #51 +0x6b,0x76,0x0f,0x5f +0x4d,0x76,0x1b,0x5f +0x2e,0x76,0x36,0x5f +0x0f,0x76,0x73,0x5f + +#---------------------------------------------------------------------- +# Unsigned Saturating Shift Left (Immediate) +#---------------------------------------------------------------------- +# CHECK: uqshl b18, b15, #6 +# CHECK: uqshl h11, h18, #7 +# CHECK: uqshl s14, s19, #18 +# CHECK: uqshl d15, d12, #19 +0xf2,0x75,0x0e,0x7f +0x4b,0x76,0x17,0x7f +0x6e,0x76,0x32,0x7f +0x8f,0x75,0x53,0x7f + +#---------------------------------------------------------------------- +# Signed Saturating Shift Left Unsigned (Immediate) +#---------------------------------------------------------------------- +# CHECK: sqshlu b15, b18, #6 +# CHECK: sqshlu h19, h17, #6 +# CHECK: sqshlu s16, s14, #25 +# CHECK: sqshlu d11, d13, #32 +0x4f,0x66,0x0e,0x7f +0x33,0x66,0x16,0x7f +0xd0,0x65,0x39,0x7f +0xab,0x65,0x60,0x7f + +#---------------------------------------------------------------------- +# Shift Right And Insert (Immediate) +#---------------------------------------------------------------------- +# CHECK: sri d10, d12, #14 +0x8a,0x45,0x72,0x7f + +#---------------------------------------------------------------------- +# Shift Left And Insert (Immediate) +#---------------------------------------------------------------------- +# CHECK: sli d10, d14, #12 +0xca,0x55,0x4c,0x7f + +#---------------------------------------------------------------------- +# Signed Saturating Shift Right Narrow (Immediate) +#---------------------------------------------------------------------- +# CHECK: sqshrn b10, h15, #5 +# CHECK: sqshrn h17, s10, #4 +# CHECK: sqshrn s18, d10, #31 +0xea,0x95,0x0b,0x5f +0x51,0x95,0x1c,0x5f +0x52,0x95,0x21,0x5f + +#---------------------------------------------------------------------- +# Unsigned Saturating Shift Right Narrow (Immediate) +#---------------------------------------------------------------------- +# CHECK: uqshrn b12, h10, #7 +# CHECK: uqshrn h10, s14, #5 +# CHECK: uqshrn s10, d12, #13 +0x4c,0x95,0x09,0x7f +0xca,0x95,0x1b,0x7f +0x8a,0x95,0x33,0x7f + +#---------------------------------------------------------------------- +# Signed Saturating Rounded Shift Right Narrow (Immediate) +#---------------------------------------------------------------------- +# CHECK: sqrshrn b10, h13, #2 +# CHECK: sqrshrn h15, s10, #6 +# CHECK: sqrshrn s15, d12, #9 +0xaa,0x9d,0x0e,0x5f +0x4f,0x9d,0x1a,0x5f +0x8f,0x9d,0x37,0x5f + +#---------------------------------------------------------------------- +# Unsigned Saturating Rounded Shift Right Narrow (Immediate) +#---------------------------------------------------------------------- +# CHECK: uqrshrn b10, h12, #5 +# CHECK: uqrshrn h12, s10, #14 +# CHECK: uqrshrn s10, d10, #25 +0x8a,0x9d,0x0b,0x7f +0x4c,0x9d,0x12,0x7f +0x4a,0x9d,0x27,0x7f + +#---------------------------------------------------------------------- +# Signed Saturating Shift Right Unsigned Narrow (Immediate) +#---------------------------------------------------------------------- +# CHECK: sqshrun b15, h10, #7 +# CHECK: sqshrun h20, s14, #3 +# CHECK: sqshrun s10, d15, #15 +0x4f,0x85,0x09,0x7f +0xd4,0x85,0x1d,0x7f +0xea,0x85,0x31,0x7f + +#---------------------------------------------------------------------- +# Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) +#---------------------------------------------------------------------- +# CHECK: sqrshrun b17, h10, #6 +# CHECK: sqrshrun h10, s13, #15 +# CHECK: sqrshrun s22, d16, #31 +0x51,0x8d,0x0a,0x7f +0xaa,0x8d,0x11,0x7f +0x16,0x8e,0x21,0x7f + +#---------------------------------------------------------------------- +# Scalar Signed Fixed-point Convert To Floating-Point (Immediate) +#---------------------------------------------------------------------- +# CHECK: scvtf s22, s13, #32 +# CHECK: scvtf d21, d12, #64 +0xb6,0xe5,0x20,0x5f +0x95,0xe5,0x40,0x5f + +#---------------------------------------------------------------------- +# Scalar Unsigned Fixed-point Convert To Floating-Point (Immediate) +#---------------------------------------------------------------------- +# CHECK: ucvtf s22, s13, #32 +# CHECK: ucvtf d21, d14, #64 +0xb6,0xe5,0x20,0x7f +0xd5,0xe5,0x40,0x7f + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Fixed-point (Immediate) +#---------------------------------------------------------------------- +# CHECK: fcvtzs s21, s12, #1 +# CHECK: fcvtzs d21, d12, #1 +0x95,0xfd,0x3f,0x5f +0x95,0xfd,0x7f,0x5f + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Fixed-point (Immediate) +#---------------------------------------------------------------------- +# CHECK: fcvtzu s21, s12, #1 +# CHECK: fcvtzu d21, d12, #1 +0x95,0xfd,0x3f,0x7f +0x95,0xfd,0x7f,0x7f + +#---------------------------------------------------------------------- +# Vector load/store multiple N-element structure +#---------------------------------------------------------------------- +# CHECK: ld1 {v0.16b}, [x0] +# CHECK: ld1 {v15.8h, v16.8h}, [x15] +# CHECK: ld1 {v31.4s, v0.4s, v1.4s}, [sp] +# CHECK: ld1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x70,0x40,0x4c +0xef,0xa5,0x40,0x4c +0xff,0x6b,0x40,0x4c +0x00,0x2c,0x40,0x4c + +# CHECK: ld2 {v0.8b, v1.8b}, [x0] +# CHECK: ld3 {v15.4h, v16.4h, v17.4h}, [x15] +# CHECK: ld4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x80,0x40,0x0c +0xef,0x45,0x40,0x0c +0xff,0x0b,0x40,0x0c + +# CHECK: st1 {v0.16b}, [x0] +# CHECK: st1 {v15.8h, v16.8h}, [x15] +# CHECK: st1 {v31.4s, v0.4s, v1.4s}, [sp] +# CHECK: st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [x0] +0x00,0x70,0x00,0x4c +0xef,0xa5,0x00,0x4c +0xff,0x6b,0x00,0x4c +0x00,0x2c,0x00,0x4c + +# CHECK: st2 {v0.8b, v1.8b}, [x0] +# CHECK: st3 {v15.4h, v16.4h, v17.4h}, [x15] +# CHECK: st4 {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +0x00,0x80,0x00,0x0c +0xef,0x45,0x00,0x0c +0xff,0x0b,0x00,0x0c + +#---------------------------------------------------------------------- +# Vector load/store multiple N-element structure (post-index) +#---------------------------------------------------------------------- +# CHECK: ld1 {v15.8h}, [x15], x2 +# CHECK: ld1 {v31.4s, v0.4s}, [sp], #32 +# CHECK: ld1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +# CHECK: ld1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +0xef,0x75,0xc2,0x4c +0xff,0xab,0xdf,0x4c +0x00,0x6c,0xdf,0x4c +0x00,0x20,0xc3,0x0c + +# CHECK: ld2 {v0.16b, v1.16b}, [x0], x1 +# CHECK: ld3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +# CHECK: ld4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +0x00,0x80,0xc1,0x4c +0xef,0x45,0xc2,0x4c +0xff,0x0b,0xdf,0x4c + + +# CHECK: st1 {v15.8h}, [x15], x2 +# CHECK: st1 {v31.4s, v0.4s}, [sp], #32 +# CHECK: st1 {v0.2d, v1.2d, v2.2d}, [x0], #48 +# CHECK: st1 {v0.8b, v1.8b, v2.8b, v3.8b}, [x0], x3 +0xef,0x75,0x82,0x4c +0xff,0xab,0x9f,0x4c +0x00,0x6c,0x9f,0x4c +0x00,0x20,0x83,0x0c + +# CHECK: st2 {v0.16b, v1.16b}, [x0], x1 +# CHECK: st3 {v15.8h, v16.8h, v17.8h}, [x15], x2 +# CHECK: st4 {v31.4s, v0.4s, v1.4s, v2.4s}, [sp], #64 +0x00,0x80,0x81,0x4c +0xef,0x45,0x82,0x4c +0xff,0x0b,0x9f,0x4c + +#---------------------------------------------------------------------- +# Vector load single N-element structure to all lane of N +# consecutive registers (N = 1,2,3,4) +#---------------------------------------------------------------------- +# CHECK: ld1r {v0.16b}, [x0] +# CHECK: ld1r {v15.8h}, [x15] +# CHECK: ld2r {v31.4s, v0.4s}, [sp] +# CHECK: ld2r {v0.2d, v1.2d}, [x0] +# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0] +# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15] +# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp] +# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp] +0x00,0xc0,0x40,0x4d +0xef,0xc5,0x40,0x4d +0xff,0xcb,0x60,0x4d +0x00,0xcc,0x60,0x4d +0x00,0xe0,0x40,0x0d +0xef,0xe5,0x40,0x0d +0xff,0xeb,0x60,0x0d +0xff,0xef,0x60,0x0d + +#---------------------------------------------------------------------- +# Vector load/store single N-element structure to/from one lane of N +# consecutive registers (N = 1,2,3,4) +#---------------------------------------------------------------------- +# CHECK: ld1 {v0.b}[9], [x0] +# CHECK: ld2 {v15.h, v16.h}[7], [x15] +# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp] +# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0] +# CHECK: st1 {v0.d}[1], [x0] +# CHECK: st2 {v31.s, v0.s}[3], [sp] +# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15] +# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0] +0x00,0x04,0x40,0x4d +0xef,0x59,0x60,0x4d +0xff,0xb3,0x40,0x4d +0x00,0xa4,0x60,0x4d +0x00,0x84,0x00,0x4d +0xff,0x93,0x20,0x4d +0xef,0x79,0x00,0x4d +0x00,0x24,0x20,0x4d + +#---------------------------------------------------------------------- +# Post-index of vector load single N-element structure to all lane of N +# consecutive registers (N = 1,2,3,4) +#---------------------------------------------------------------------- +# CHECK: ld1r {v0.16b}, [x0], #1 +# CHECK: ld1r {v15.8h}, [x15], #2 +# CHECK: ld2r {v31.4s, v0.4s}, [sp], #8 +# CHECK: ld2r {v0.2d, v1.2d}, [x0], #16 +# CHECK: ld3r {v0.8b, v1.8b, v2.8b}, [x0], #3 +# CHECK: ld3r {v15.4h, v16.4h, v17.4h}, [x15], #6 +# CHECK: ld4r {v31.2s, v0.2s, v1.2s, v2.2s}, [sp], x30 +# CHECK: ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [sp], x7 +0x00,0xc0,0xdf,0x4d +0xef,0xc5,0xdf,0x4d +0xff,0xcb,0xff,0x4d +0x00,0xcc,0xff,0x4d +0x00,0xe0,0xdf,0x0d +0xef,0xe5,0xdf,0x0d +0xff,0xeb,0xfe,0x0d +0xff,0xef,0xe7,0x0d + +#---------------------------------------------------------------------- +# Post-index of vector load/store single N-element structure to/from +# one lane of N consecutive registers (N = 1,2,3,4) +#---------------------------------------------------------------------- +# CHECK: ld1 {v0.b}[9], [x0], #1 +# CHECK: ld2 {v15.h, v16.h}[7], [x15], #4 +# CHECK: ld3 {v31.s, v0.s, v1.s}[3], [sp], x3 +# CHECK: ld4 {v0.d, v1.d, v2.d, v3.d}[1], [x0], #32 +# CHECK: ld4 {v0.h, v1.h, v2.h, v3.h}[7], [x0], x0 +# CHECK: st1 {v0.d}[1], [x0], #8 +# CHECK: st2 {v31.s, v0.s}[3], [sp], #8 +# CHECK: st3 {v15.h, v16.h, v17.h}[7], [x15], #6 +# CHECK: st4 {v0.b, v1.b, v2.b, v3.b}[9], [x0], x5 +0x00,0x04,0xdf,0x4d +0xef,0x59,0xff,0x4d +0xff,0xb3,0xc3,0x4d +0x00,0xa4,0xff,0x4d +0x00,0x78,0xe0,0x4d +0x00,0x84,0x9f,0x4d +0xff,0x93,0xbf,0x4d +0xef,0x79,0x9f,0x4d +0x00,0x24,0xa5,0x4d + +#---------------------------------------------------------------------- +# Bitwise extract +#---------------------------------------------------------------------- +0x20,0x18,0x02,0x2e +0x20,0x18,0x02,0x6e +# CHECK: ext v0.8b, v1.8b, v2.8b, #0x3 +# CHECK: ext v0.16b, v1.16b, v2.16b, #0x3 + +#---------------------------------------------------------------------- +# unzip with 3 same vectors to get primary result +#---------------------------------------------------------------------- +# CHECK: uzp1 v1.8b, v1.8b, v2.8b +# CHECK: uzp1 v2.16b, v1.16b, v2.16b +# CHECK: uzp1 v3.4h, v1.4h, v2.4h +# CHECK: uzp1 v4.8h, v1.8h, v2.8h +# CHECK: uzp1 v5.2s, v1.2s, v2.2s +# CHECK: uzp1 v6.4s, v1.4s, v2.4s +# CHECK: uzp1 v7.2d, v1.2d, v2.2d +0x21,0x18,0x02,0x0e +0x22,0x18,0x02,0x4e +0x23,0x18,0x42,0x0e +0x24,0x18,0x42,0x4e +0x25,0x18,0x82,0x0e +0x26,0x18,0x82,0x4e +0x27,0x18,0xc2,0x4e + +#---------------------------------------------------------------------- +# transpose with 3 same vectors to get primary result +#---------------------------------------------------------------------- +# CHECK: trn1 v8.8b, v1.8b, v2.8b +# CHECK: trn1 v9.16b, v1.16b, v2.16b +# CHECK: trn1 v10.4h, v1.4h, v2.4h +# CHECK: trn1 v27.8h, v7.8h, v2.8h +# CHECK: trn1 v12.2s, v7.2s, v2.2s +# CHECK: trn1 v29.4s, v6.4s, v2.4s +# CHECK: trn1 v14.2d, v6.2d, v2.2d +0x28,0x28,0x02,0x0e +0x29,0x28,0x02,0x4e +0x2a,0x28,0x42,0x0e +0xfb,0x28,0x42,0x4e +0xec,0x28,0x82,0x0e +0xdd,0x28,0x82,0x4e +0xce,0x28,0xc2,0x4e + +#---------------------------------------------------------------------- +# zip with 3 same vectors to get primary result +#---------------------------------------------------------------------- +# CHECK: zip1 v31.8b, v5.8b, v2.8b +# CHECK: zip1 v0.16b, v5.16b, v2.16b +# CHECK: zip1 v17.4h, v4.4h, v2.4h +# CHECK: zip1 v2.8h, v4.8h, v2.8h +# CHECK: zip1 v19.2s, v3.2s, v2.2s +# CHECK: zip1 v4.4s, v3.4s, v2.4s +# CHECK: zip1 v21.2d, v2.2d, v2.2d +0xbf,0x38,0x02,0x0e +0xa0,0x38,0x02,0x4e +0x91,0x38,0x42,0x0e +0x82,0x38,0x42,0x4e +0x73,0x38,0x82,0x0e +0x64,0x38,0x82,0x4e +0x55,0x38,0xc2,0x4e + +#---------------------------------------------------------------------- +# unzip with 3 same vectors to get secondary result +#---------------------------------------------------------------------- +# CHECK: uzp2 v6.8b, v2.8b, v2.8b +# CHECK: uzp2 v23.16b, v1.16b, v2.16b +# CHECK: uzp2 v8.4h, v1.4h, v2.4h +# CHECK: uzp2 v25.8h, v0.8h, v2.8h +# CHECK: uzp2 v10.2s, v0.2s, v2.2s +# CHECK: uzp2 v27.4s, v7.4s, v2.4s +# CHECK: uzp2 v12.2d, v7.2d, v2.2d +0x46,0x58,0x02,0x0e +0x37,0x58,0x02,0x4e +0x28,0x58,0x42,0x0e +0x19,0x58,0x42,0x4e +0x0a,0x58,0x82,0x0e +0xfb,0x58,0x82,0x4e +0xec,0x58,0xc2,0x4e + +#---------------------------------------------------------------------- +# transpose with 3 same vectors to get secondary result +#---------------------------------------------------------------------- +# CHECK: trn2 v29.8b, v6.8b, v2.8b +# CHECK: trn2 v14.16b, v6.16b, v2.16b +# CHECK: trn2 v31.4h, v5.4h, v2.4h +# CHECK: trn2 v0.8h, v5.8h, v2.8h +# CHECK: trn2 v17.2s, v4.2s, v2.2s +# CHECK: trn2 v2.4s, v4.4s, v2.4s +# CHECK: trn2 v19.2d, v3.2d, v2.2d +0xdd,0x68,0x02,0x0e +0xce,0x68,0x02,0x4e +0xbf,0x68,0x42,0x0e +0xa0,0x68,0x42,0x4e +0x91,0x68,0x82,0x0e +0x82,0x68,0x82,0x4e +0x73,0x68,0xc2,0x4e + +#---------------------------------------------------------------------- +# zip with 3 same vectors to get secondary result +#---------------------------------------------------------------------- +# CHECK: zip2 v4.8b, v3.8b, v2.8b +# CHECK: zip2 v21.16b, v2.16b, v2.16b +# CHECK: zip2 v6.4h, v2.4h, v2.4h +# CHECK: zip2 v23.8h, v1.8h, v2.8h +# CHECK: zip2 v8.2s, v1.2s, v2.2s +# CHECK: zip2 v25.4s, v0.4s, v2.4s +# CHECK: zip2 v10.2d, v0.2d, v2.2d +0x64,0x78,0x02,0x0e +0x55,0x78,0x02,0x4e +0x46,0x78,0x42,0x0e +0x37,0x78,0x42,0x4e +0x28,0x78,0x82,0x0e +0x19,0x78,0x82,0x4e +0x0a,0x78,0xc2,0x4e + +#---------------------------------------------------------------------- +# Scalar Floating Point multiply (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: fmul s0, s1, v1.s[0] +# CHECK: fmul s0, s1, v1.s[3] +# CHECK: fmul d0, d1, v1.d[0] +# CHECK: fmul d0, d1, v1.d[1] +# CHECK: fmul d15, d15, v15.d[1] +0x20 0x90 0x81 0x5f +0x20 0x98 0xa1 0x5f +0x20 0x90 0xc1 0x5f +0x20 0x98 0xc1 0x5f +0xef 0x99 0xcf 0x5f + +#---------------------------------------------------------------------- +# Scalar Floating Point multiply extended (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: fmulx s3, s5, v7.s[0] +# CHECK: fmulx s3, s5, v7.s[3] +# CHECK: fmulx s3, s5, v15.s[3] +# CHECK: fmulx d0, d4, v8.d[0] +# CHECK: fmulx d0, d4, v8.d[1] +0xa3 0x90 0x87 0x7f +0xa3 0x98 0xa7 0x7f +0xa3 0x98 0xaf 0x7f +0x80 0x90 0xc8 0x7f +0x80 0x98 0xc8 0x7f + +#---------------------------------------------------------------------- +# Scalar Floating Point fused multiply-add (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: fmla s0, s1, v1.s[0] +# CHECK: fmla s0, s1, v1.s[3] +# CHECK: fmla d0, d1, v1.d[0] +# CHECK: fmla d0, d1, v1.d[1] +# CHECK: fmla d15, d15, v15.d[1] +0x20 0x10 0x81 0x5f +0x20 0x18 0xa1 0x5f +0x20 0x10 0xc1 0x5f +0x20 0x18 0xc1 0x5f +0xef 0x19 0xcf 0x5f + +#---------------------------------------------------------------------- +# Scalar Floating Point fused multiply-sub (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: fmls s3, s5, v7.s[0] +# CHECK: fmls s3, s5, v7.s[3] +# CHECK: fmls s3, s5, v15.s[3] +# CHECK: fmls d0, d4, v8.d[0] +# CHECK: fmls d0, d4, v8.d[1] +0xa3 0x50 0x87 0x5f +0xa3 0x58 0xa7 0x5f +0xa3 0x58 0xaf 0x5f +0x80 0x50 0xc8 0x5f +0x80 0x58 0xc8 0x5f + +#---------------------------------------------------------------------- +# Scalar Signed saturating doubling +# multiply-add long (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: sqdmlal s0, h0, v0.h[0] +# CHECK: sqdmlal s0, h0, v0.h[1] +# CHECK: sqdmlal s0, h0, v0.h[2] +# CHECK: sqdmlal s0, h0, v0.h[3] +# CHECK: sqdmlal s0, h0, v0.h[4] +# CHECK: sqdmlal s0, h0, v0.h[5] +# CHECK: sqdmlal s0, h0, v0.h[6] +# CHECK: sqdmlal s0, h0, v0.h[7] +# CHECK: sqdmlal d8, s9, v15.s[0] +# CHECK: sqdmlal d8, s9, v15.s[1] +# CHECK: sqdmlal d8, s9, v15.s[2] +# CHECK: sqdmlal d8, s9, v15.s[3] +0x00 0x30 0x40 0x5f +0x00 0x30 0x50 0x5f +0x00 0x30 0x60 0x5f +0x00 0x30 0x70 0x5f +0x00 0x38 0x40 0x5f +0x00 0x38 0x50 0x5f +0x00 0x38 0x60 0x5f +0x00 0x38 0x70 0x5f +0x28 0x31 0x8f 0x5f +0x28 0x31 0xaf 0x5f +0x28 0x39 0x8f 0x5f +0x28 0x39 0xaf 0x5f + +#---------------------------------------------------------------------- +# Scalar Signed saturating doubling +# multiply-sub long (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: sqdmlsl s0, h0, v0.h[0] +# CHECK: sqdmlsl s0, h0, v0.h[1] +# CHECK: sqdmlsl s0, h0, v0.h[2] +# CHECK: sqdmlsl s0, h0, v0.h[3] +# CHECK: sqdmlsl s0, h0, v0.h[4] +# CHECK: sqdmlsl s0, h0, v0.h[5] +# CHECK: sqdmlsl s0, h0, v0.h[6] +# CHECK: sqdmlsl s0, h0, v0.h[7] +# CHECK: sqdmlsl d8, s9, v15.s[0] +# CHECK: sqdmlsl d8, s9, v15.s[1] +# CHECK: sqdmlsl d8, s9, v15.s[2] +# CHECK: sqdmlsl d8, s9, v15.s[3] +0x00 0x70 0x40 0x5f +0x00 0x70 0x50 0x5f +0x00 0x70 0x60 0x5f +0x00 0x70 0x70 0x5f +0x00 0x78 0x40 0x5f +0x00 0x78 0x50 0x5f +0x00 0x78 0x60 0x5f +0x00 0x78 0x70 0x5f +0x28 0x71 0x8f 0x5f +0x28 0x71 0xaf 0x5f +0x28 0x79 0x8f 0x5f +0x28 0x79 0xaf 0x5f + +#---------------------------------------------------------------------- +# Scalar Signed saturating doubling multiply long (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: sqdmull s1, h1, v1.h[0] +# CHECK: sqdmull s1, h1, v1.h[1] +# CHECK: sqdmull s1, h1, v1.h[2] +# CHECK: sqdmull s1, h1, v1.h[3] +# CHECK: sqdmull s1, h1, v1.h[4] +# CHECK: sqdmull s1, h1, v1.h[5] +# CHECK: sqdmull s1, h1, v1.h[6] +# CHECK: sqdmull s1, h1, v1.h[7] +# CHECK: sqdmull d1, s1, v4.s[0] +# CHECK: sqdmull d1, s1, v4.s[1] +# CHECK: sqdmull d1, s1, v4.s[2] +# CHECK: sqdmull d1, s1, v4.s[3] +0x21 0xb0 0x41 0x5f +0x21 0xb0 0x51 0x5f +0x21 0xb0 0x61 0x5f +0x21 0xb0 0x71 0x5f +0x21 0xb8 0x41 0x5f +0x21 0xb8 0x51 0x5f +0x21 0xb8 0x61 0x5f +0x21 0xb8 0x71 0x5f +0x21 0xb0 0x84 0x5f +0x21 0xb0 0xa4 0x5f +0x21 0xb8 0x84 0x5f +0x21 0xb8 0xa4 0x5f + +#---------------------------------------------------------------------- +# Scalar Signed saturating doubling multiply returning +# high half (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: sqdmulh h7, h1, v14.h[0] +# CHECK: sqdmulh h7, h15, v8.h[1] +# CHECK: sqdmulh h7, h15, v8.h[2] +# CHECK: sqdmulh h7, h15, v8.h[3] +# CHECK: sqdmulh h7, h15, v8.h[4] +# CHECK: sqdmulh h7, h15, v8.h[5] +# CHECK: sqdmulh h7, h15, v8.h[6] +# CHECK: sqdmulh h7, h15, v8.h[7] +# CHECK: sqdmulh s15, s3, v4.s[0] +# CHECK: sqdmulh s15, s14, v16.s[1] +# CHECK: sqdmulh s15, s15, v16.s[2] +# CHECK: sqdmulh s15, s16, v17.s[3] +0x27 0xc0 0x4e 0x5f +0xe7 0xc1 0x58 0x5f +0xe7 0xc1 0x68 0x5f +0xe7 0xc1 0x78 0x5f +0xe7 0xc9 0x48 0x5f +0xe7 0xc9 0x58 0x5f +0xe7 0xc9 0x68 0x5f +0xe7 0xc9 0x78 0x5f +0x6f 0xc0 0x84 0x5f +0xcf 0xc1 0xb0 0x5f +0xef 0xc9 0x90 0x5f +0x0f 0xca 0xb1 0x5f + +#---------------------------------------------------------------------- +# Scalar Signed saturating rounding doubling multiply +# returning high half (scalar, by element) +#---------------------------------------------------------------------- +# CHECK: sqrdmulh h7, h1, v14.h[0] +# CHECK: sqrdmulh h7, h15, v8.h[1] +# CHECK: sqrdmulh h7, h15, v8.h[2] +# CHECK: sqrdmulh h7, h15, v8.h[3] +# CHECK: sqrdmulh h7, h15, v8.h[4] +# CHECK: sqrdmulh h7, h15, v8.h[5] +# CHECK: sqrdmulh h7, h15, v8.h[6] +# CHECK: sqrdmulh h7, h15, v8.h[7] +# CHECK: sqrdmulh s15, s3, v4.s[0] +# CHECK: sqrdmulh s15, s14, v16.s[1] +# CHECK: sqrdmulh s15, s15, v16.s[2] +# CHECK: sqrdmulh s15, s16, v17.s[3] +0x27 0xd0 0x4e 0x5f +0xe7 0xd1 0x58 0x5f +0xe7 0xd1 0x68 0x5f +0xe7 0xd1 0x78 0x5f +0xe7 0xd9 0x48 0x5f +0xe7 0xd9 0x58 0x5f +0xe7 0xd9 0x68 0x5f +0xe7 0xd9 0x78 0x5f +0x6f 0xd0 0x84 0x5f +0xcf 0xd1 0xb0 0x5f +0xef 0xd9 0x90 0x5f +0x0f 0xda 0xb1 0x5f + +#---------------------------------------------------------------------- +#Duplicate element (scalar) +#---------------------------------------------------------------------- +# CHECK: dup b0, v0.b[15] +# CHECK: dup h2, v31.h[5] +# CHECK: dup s17, v2.s[2] +# CHECK: dup d6, v12.d[1] +0x00 0x04 0x1f 0x5e +0xe2 0x07 0x16 0x5e +0x51 0x04 0x14 0x5e +0x86 0x05 0x18 0x5e + +#---------------------------------------------------------------------- +# Table look up +#---------------------------------------------------------------------- +0x20,0x00,0x02,0x0e +0xf0,0x23,0x02,0x0e +0x20,0x40,0x02,0x0e +0xf0,0x62,0x02,0x0e +# CHECK: tbl v0.8b, {v1.16b}, v2.8b +# CHECK: tbl v16.8b, {v31.16b, v0.16b}, v2.8b +# CHECK: tbl v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b +# CHECK: tbl v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b + +0x20,0x00,0x02,0x4e +0xf0,0x23,0x02,0x4e +0x20,0x40,0x02,0x4e +0xe0,0x63,0x02,0x4e +# CHECK: tbl v0.16b, {v1.16b}, v2.16b +# CHECK: tbl v16.16b, {v31.16b, v0.16b}, v2.16b +# CHECK: tbl v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b +# CHECK: tbl v0.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b + +0x20,0x10,0x02,0x0e +0xf0,0x33,0x02,0x0e +0x20,0x50,0x02,0x0e +0xf0,0x72,0x02,0x0e +# CHECK: tbx v0.8b, {v1.16b}, v2.8b +# CHECK: tbx v16.8b, {v31.16b, v0.16b}, v2.8b +# CHECK: tbx v0.8b, {v1.16b, v2.16b, v3.16b}, v2.8b +# CHECK: tbx v16.8b, {v23.16b, v24.16b, v25.16b, v26.16b}, v2.8b + +0x20,0x10,0x02,0x4e +0xf0,0x33,0x02,0x4e +0x20,0x50,0x02,0x4e +0xf0,0x73,0x02,0x4e +# CHECK: tbx v0.16b, {v1.16b}, v2.16b +# CHECK: tbx v16.16b, {v31.16b, v0.16b}, v2.16b +# CHECK: tbx v0.16b, {v1.16b, v2.16b, v3.16b}, v2.16b +# CHECK: tbx v16.16b, {v31.16b, v0.16b, v1.16b, v2.16b}, v2.16b + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Lower Precision Narrow, Rounding To +# Odd +#---------------------------------------------------------------------- +# CHECK: fcvtxn s22, d13 +0xb6,0x69,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +# With Ties To Away +#---------------------------------------------------------------------- +# CHECK: fcvtas s12, s13 +# CHECK: fcvtas d21, d14 + +0xac,0xc9,0x21,0x5e +0xd5,0xc9,0x61,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding To +# Nearest With Ties To Away +#---------------------------------------------------------------------- +# CHECK: fcvtau s12, s13 +# CHECK: fcvtau d21, d14 +0xac,0xc9,0x21,0x7e +0xd5,0xc9,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding Toward +# Minus Infinity +#---------------------------------------------------------------------- +# CHECK: fcvtms s22, s13 +# CHECK: fcvtms d21, d14 +0xb6,0xb9,0x21,0x5e +0xd5,0xb9,0x61,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +# Minus Infinity +#---------------------------------------------------------------------- +# CHECK: fcvtmu s12, s13 +# CHECK: fcvtmu d21, d14 +0xac,0xb9,0x21,0x7e +0xd5,0xb9,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding To Nearest +# With Ties To Even +#---------------------------------------------------------------------- + +# CHECK: fcvtns s22, s13 +# CHECK: fcvtns d21, d14 + +0xb6,0xa9,0x21,0x5e +0xd5,0xa9,0x61,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding To +# Nearest With Ties To Even +#---------------------------------------------------------------------- + +# CHECK: fcvtnu s12, s13 +# CHECK: fcvtnu d21, d14 +0xac,0xa9,0x21,0x7e +0xd5,0xa9,0x61,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding Toward +# Positive Infinity +#---------------------------------------------------------------------- +# CHECK: fcvtps s22, s13 +# CHECK: fcvtps d21, d14 +0xb6,0xa9,0xa1,0x5e +0xd5,0xa9,0xe1,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +# Positive Infinity +#---------------------------------------------------------------------- +# CHECK: fcvtpu s12, s13 +# CHECK: fcvtpu d21, d14 +0xac,0xa9,0xa1,0x7e +0xd5,0xa9,0xe1,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Signed Integer, Rounding Toward Zero +#---------------------------------------------------------------------- +# CHECK: fcvtzs s12, s13 +# CHECK: fcvtzs d21, d14 +0xac,0xb9,0xa1,0x5e +0xd5,0xb9,0xe1,0x5e + +#---------------------------------------------------------------------- +# Scalar Floating-point Convert To Unsigned Integer, Rounding Toward +# Zero +#---------------------------------------------------------------------- +# CHECK: fcvtzu s12, s13 +# CHECK: fcvtzu d21, d14 +0xac,0xb9,0xa1,0x7e +0xd5,0xb9,0xe1,0x7e + +#---------------------------------------------------------------------- +# Scalar Floating-point Absolute Difference +#---------------------------------------------------------------------- +# CHECK: fabd s29, s24, s20 +# CHECK: fabd d29, d24, d20 +0x1d,0xd7,0xb4,0x7e +0x1d,0xd7,0xf4,0x7e diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt b/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt new file mode 100644 index 0000000..d9286bf --- /dev/null +++ b/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt @@ -0,0 +1,58 @@ +# RUN: llvm-mc -disassemble -triple armv8 -mattr=+db -show-encoding < %s | FileCheck %s + +# New v8 ARM instructions + +# HLT + +0x70 0x00 0x00 0xe1 +# CHECK: hlt #0 + +0x7f 0xff 0x0f 0xe1 +# CHECK: hlt #65535 + +0x59 0xf0 0x7f 0xf5 +0x51 0xf0 0x7f 0xf5 +0x55 0xf0 0x7f 0xf5 +0x5d 0xf0 0x7f 0xf5 +# CHECK: dmb ishld +# CHECK: dmb oshld +# CHECK: dmb nshld +# CHECK: dmb ld + +0x05 0xf0 0x20 0xe3 +# CHECK: sevl + + +# These are the only coprocessor instructions that remain defined in ARMv8 +# (The operations on p10/p11 disassemble into FP/NEON instructions) + +0x10 0x0e 0x00 0xee +# CHECK: mcr p14 + +0x10 0x0f 0x00 0xee +# CHECK: mcr p15 + +0x10 0x0e 0x10 0xee +# CHECK: mrc p14 + +0x10 0x0f 0x10 0xee +# CHECK: mrc p15 + +0x00 0x0e 0x40 0xec +# CHECK: mcrr p14 + +0x00 0x0f 0x40 0xec +# CHECK: mcrr p15 + +0x00 0x0e 0x50 0xec +# CHECK: mrrc p14 + +0x00 0x0f 0x50 0xec +# CHECK: mrrc p15 + +0x00 0x0e 0x80 0xec +# CHECK: stc p14 + +0x00 0x0e 0x90 0xec +# CHECK: ldc p14 + diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt index fd36268..8bcf4e6 100644 --- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt +++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt @@ -2420,6 +2420,7 @@ # CHECK: wfilt # CHECK: yield # CHECK: yieldne +# CHECK: hint #5 0x02 0xf0 0x20 0xe3 0x02 0xf0 0x20 0x83 @@ -2427,3 +2428,4 @@ 0x03 0xf0 0x20 0xb3 0x01 0xf0 0x20 0xe3 0x01 0xf0 0x20 0x13 +0x05 0xf0 0x20 0xe3 diff --git a/test/MC/Disassembler/ARM/crc32-thumb.txt b/test/MC/Disassembler/ARM/crc32-thumb.txt new file mode 100644 index 0000000..2f83b58 --- /dev/null +++ b/test/MC/Disassembler/ARM/crc32-thumb.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=thumbv8 2>&1 | FileCheck %s + +# CHECK: crc32b r0, r1, r2 +# CHECK: crc32h r0, r1, r2 +# CHECK: crc32w r0, r1, r2 +# CHECK: crc32cb r0, r1, r2 +# CHECK: crc32ch r0, r1, r2 +# CHECK: crc32cw r0, r1, r2 + +0xc1 0xfa 0x82 0xf0 +0xc1 0xfa 0x92 0xf0 +0xc1 0xfa 0xa2 0xf0 +0xd1 0xfa 0x82 0xf0 +0xd1 0xfa 0x92 0xf0 +0xd1 0xfa 0xa2 0xf0 diff --git a/test/MC/Disassembler/ARM/crc32.txt b/test/MC/Disassembler/ARM/crc32.txt new file mode 100644 index 0000000..17bb032 --- /dev/null +++ b/test/MC/Disassembler/ARM/crc32.txt @@ -0,0 +1,15 @@ +# RUN: llvm-mc --disassemble %s -triple=armv8 2>&1 | FileCheck %s + +# CHECK: crc32b r0, r1, r2 +# CHECK: crc32h r0, r1, r2 +# CHECK: crc32w r0, r1, r2 +# CHECK: crc32cb r0, r1, r2 +# CHECK: crc32ch r0, r1, r2 +# CHECK: crc32cw r0, r1, r2 + +0x42 0x00 0x01 0xe1 +0x42 0x00 0x21 0xe1 +0x42 0x00 0x41 0xe1 +0x42 0x02 0x01 0xe1 +0x42 0x02 0x21 0xe1 +0x42 0x02 0x41 0xe1 diff --git a/test/MC/Disassembler/ARM/v8fp.txt b/test/MC/Disassembler/ARM/fp-armv8.txt index a6e88b6..46a26f5 100644 --- a/test/MC/Disassembler/ARM/v8fp.txt +++ b/test/MC/Disassembler/ARM/fp-armv8.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -disassemble -triple armv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -disassemble -triple armv8 -mattr=+fp-armv8 -show-encoding < %s | FileCheck %s 0xe0 0x3b 0xb2 0xee # CHECK: vcvtt.f64.f16 d3, s1 @@ -153,3 +153,8 @@ 0x60 0x6a 0xbb 0xfe # CHECK: vrintm.f32 s12, s1 + + +0x10 0xa 0xf5 0xee +# CHECK: vmrs r0, mvfr2 + diff --git a/test/MC/Disassembler/ARM/invalid-armv7.txt b/test/MC/Disassembler/ARM/invalid-armv7.txt index be79326..550173f 100644 --- a/test/MC/Disassembler/ARM/invalid-armv7.txt +++ b/test/MC/Disassembler/ARM/invalid-armv7.txt @@ -69,14 +69,6 @@ # Undefined encoding space for hint instructions #------------------------------------------------------------------------------ -[0x05 0xf0 0x20 0xe3] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x05 0xf0 0x20 0xe3] - -[0x41 0xf0 0x20 0xe3] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x41 0xf0 0x20 0xe3] - # FIXME: is it "dbg #14" or not???? [0xfe 0xf0 0x20 0xe3] # CHCK: invalid instruction encoding @@ -183,7 +175,7 @@ # | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 1| 0: 0: 0: 0| 0: 0: 1: 0| # ------------------------------------------------------------------------------------------------- # To qualify as an LSL (immediate) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. -# The instruction is UNPREDICTABLE, and is not a valid intruction. +# The instruction is UNPREDICTABLE, and is not a valid instruction. # # See also # A8.6.88 LSL (immediate) @@ -201,7 +193,7 @@ # | 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 1| 1: 1: 0: 0| 1: 1: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 1: 0| # ------------------------------------------------------------------------------------------------- # To qualify as a MOV (register) instruction, Inst{19-16} "should" be 0b0000, instead it is = 0b1100. -# The instruction is UNPREDICTABLE, and is not a valid intruction. +# The instruction is UNPREDICTABLE, and is not a valid instruction. # # See also # A8.6.97 MOV (register) diff --git a/test/MC/Disassembler/ARM/invalid-armv8.txt b/test/MC/Disassembler/ARM/invalid-armv8.txt new file mode 100644 index 0000000..772ff1d --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-armv8.txt @@ -0,0 +1,167 @@ +# RUN: not llvm-mc -triple armv8 -show-encoding -disassemble %s 2>&1 | FileCheck %s + +# Coprocessors other than CP10, CP11, CP14 and CP15 are undefined in ARMv8; +# but in ARMv7, all these instructions are valid + +# RUN: llvm-mc -triple armv7 -show-encoding -disassemble %s | FileCheck %s --check-prefix=CHECK-V7 + +[0x00 0x01 0x00 0xee] +# CHECK-V7: cdp +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x00 0xee] + +[0x00 0x0e 0x00 0xee] +# CHECK-V7: cdp +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0e 0x00 0xee] + +[0x00 0x0f 0x00 0xee] +# CHECK-V7: cdp +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0f 0x00 0xee] + +[0x00 0x01 0x00 0xfe] +# CHECK-V7: cdp2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x00 0xfe] + +[0x00 0x0e 0x00 0xfe] +# CHECK-V7: cdp2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0e 0x00 0xfe] + +[0x00 0x0f 0x00 0xfe] +# CHECK-V7: cdp2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0f 0x00 0xfe] + +[0x10 0x01 0x00 0xee] +# CHECK-V7: mcr +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0x01 0x00 0xee] + +[0x10 0x01 0x00 0xfe] +# CHECK-V7: mcr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0x01 0x00 0xfe] + +[0x10 0x0e 0x00 0xfe] +# CHECK-V7: mcr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0x0e 0x00 0xfe] + +[0x10 0x0f 0x00 0xfe] +# CHECK-V7: mcr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0x0f 0x00 0xfe] + +[0x10 0x01 0x10 0xee] +# CHECK-V7: mrc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0x01 0x10 0xee] + +[0x10 0x01 0x10 0xfe] +# CHECK-V7: mrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0x01 0x10 0xfe] + +[0x10 0x0e 0x10 0xfe] +# CHECK-V7: mrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0x0e 0x10 0xfe] + +[0x10 0x0f 0x10 0xfe] +# CHECK-V7: mrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0x0f 0x10 0xfe] + +[0x00 0x01 0x40 0xec] +# CHECK-V7: mcrr +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x40 0xec] + +[0x00 0x01 0x40 0xfc] +# CHECK-V7: mcrr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x40 0xfc] + +[0x00 0x0e 0x40 0xfc] +# CHECK-V7: mcrr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0e 0x40 0xfc] + +[0x00 0x0f 0x40 0xfc] +# CHECK-V7: mcrr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0f 0x40 0xfc] + +[0x00 0x01 0x50 0xec] +# CHECK-V7: mrrc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x50 0xec] + +[0x00 0x0e 0x50 0xfc] +# CHECK-V7: mrrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0e 0x50 0xfc] + +[0x00 0x0f 0x50 0xfc] +# CHECK-V7: mrrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0f 0x50 0xfc] + +[0x00 0x01 0x50 0xfc] +# CHECK-V7: mrrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x50 0xfc] + +[0x00 0x01 0x80 0xec] +# CHECK-V7: stc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x80 0xec] + +[0x00 0x0f 0x80 0xec] +# CHECK-V7: stc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0f 0x80 0xec] + +[0x00 0x01 0x80 0xfc] +# CHECK-V7: stc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x80 0xfc] + +[0x00 0x0e 0x80 0xfc] +# CHECK-V7: stc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0e 0x80 0xfc] + +[0x00 0x0f 0x80 0xfc] +# CHECK-V7: stc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0f 0x80 0xfc] + +[0x00 0x01 0x90 0xec] +# CHECK-V7: ldc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x90 0xec] + +[0x00 0x0f 0x90 0xec] +# CHECK-V7: ldc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0f 0x90 0xec] + +[0x00 0x01 0x90 0xfc] +# CHECK-V7: ldc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x01 0x90 0xfc] + +[0x00 0x0e 0x90 0xfc] +# CHECK-V7: ldc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0e 0x90 0xfc] + +[0x00 0x0f 0x90 0xfc] +# CHECK-V7: ldc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0x0f 0x90 0xfc] + diff --git a/test/MC/Disassembler/ARM/invalid-because-armv7.txt b/test/MC/Disassembler/ARM/invalid-because-armv7.txt index 4bf4833..beed8e4 100644 --- a/test/MC/Disassembler/ARM/invalid-because-armv7.txt +++ b/test/MC/Disassembler/ARM/invalid-because-armv7.txt @@ -18,3 +18,9 @@ [0x41 0x2b 0xb3 0xbe] # CHECK: invalid instruction encoding # CHECK-NEXT: [0x41 0x2b 0xb3 0xbe] + +# Would be vmrs r0, mvfr2 +[0x10 0xa 0xf5 0xee] +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0xa 0xf5 0xee] + diff --git a/test/MC/Disassembler/ARM/invalid-thumbv7.txt b/test/MC/Disassembler/ARM/invalid-thumbv7.txt index f465b3c..2c84b8a 100644 --- a/test/MC/Disassembler/ARM/invalid-thumbv7.txt +++ b/test/MC/Disassembler/ARM/invalid-thumbv7.txt @@ -32,16 +32,6 @@ # CHECK: invalid instruction encoding # CHECK-NEXT: [0x6f 0xde] - -#------------------------------------------------------------------------------ -# Undefined encoding space for hint instructions -#------------------------------------------------------------------------------ - -[0xaf 0xf3 0x05 0x80] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0xaf 0xf3 0x05 0x80] - - #------------------------------------------------------------------------------ # Undefined encoding for it #------------------------------------------------------------------------------ @@ -50,10 +40,7 @@ # CHECK: potentially undefined instruction encoding # CHECK-NEXT: [0xff 0xbf 0x6b 0x80 0x00 0x75] -# mask = 0 -[0x50 0xbf 0x00 0x00] -# CHECK: invalid instruction encoding -# CHECK-NEXT: [0x50 0xbf 0x00 0x00] +[0x50 0xbf] # hint #5; legal as the third instruction for the iteee above # Two warnings from this block since there are two instructions in there [0xdb 0xbf 0x42 0xbb] @@ -402,3 +389,19 @@ [0x80 0xf9 0x30 0x0b] # CHECK: invalid instruction encoding # CHECK-NEXT: [0x80 0xf9 0x30 0x0b] + + +#------------------------------------------------------------------------------ +# Unpredictable STMs +#------------------------------------------------------------------------------ + +# 32-bit Thumb STM instructions cannot have a writeback register which appears +# in the list. + +[0xa1,0xe8,0x07,0x04] +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: [0xa1,0xe8,0x07,0x04] + +[0x21,0xe9,0x07,0x04] +# CHECK: warning: potentially undefined instruction encoding +# CHECK-NEXT: [0x21,0xe9,0x07,0x04] diff --git a/test/MC/Disassembler/ARM/invalid-thumbv8.txt b/test/MC/Disassembler/ARM/invalid-thumbv8.txt new file mode 100644 index 0000000..4c6b249 --- /dev/null +++ b/test/MC/Disassembler/ARM/invalid-thumbv8.txt @@ -0,0 +1,167 @@ +# RUN: not llvm-mc -disassemble %s -show-encoding -triple thumbv8 2>&1 | FileCheck %s + +# Coprocessors other than CP10, CP11, CP14 and CP15 are undefined in ARMv8; +# but in ARMv7, all these instructions are valid + +# RUN: llvm-mc -triple thumbv7 -show-encoding -disassemble %s | FileCheck %s --check-prefix=CHECK-V7 + +[0x00 0xee 0x00 0x01] +# CHECK-V7: cdp +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xee 0x00 0x01] + +[0x00 0xee 0x00 0x0e] +# CHECK-V7: cdp +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xee 0x00 0x0e] + +[0x00 0xee 0x00 0x0f] +# CHECK-V7: cdp +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xee 0x00 0x0f] + +[0x00 0xfe 0x00 0x01] +# CHECK-V7: cdp2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xfe 0x00 0x01] + +[0x00 0xfe 0x00 0x0e] +# CHECK-V7: cdp2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xfe 0x00 0x0e] + +[0x00 0xfe 0x00 0x0f] +# CHECK-V7: cdp2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xfe 0x00 0x0f] + +[0x00 0xee 0x10 0x01] +# CHECK-V7: mcr +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xee 0x10 0x01] + +[0x00 0xfe 0x10 0x01] +# CHECK-V7: mcr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xfe 0x10 0x01] + +[0x00 0xfe 0x10 0x0e] +# CHECK-V7: mcr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xfe 0x10 0x0e] + +[0x00 0xfe 0x10 0x0f] +# CHECK-V7: mcr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x00 0xfe 0x10 0x0f] + +[0x10 0xee 0x10 0x01] +# CHECK-V7: mrc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0xee 0x10 0x01] + +[0x10 0xfe 0x10 0x01] +# CHECK-V7: mrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0xfe 0x10 0x01] + +[0x10 0xfe 0x10 0x0e] +# CHECK-V7: mrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0xfe 0x10 0x0e] + +[0x10 0xfe 0x10 0x0f] +# CHECK-V7: mrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x10 0xfe 0x10 0x0f] + +[0x40 0xec 0x00 0x01] +# CHECK-V7: mcrr +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x40 0xec 0x00 0x01] + +[0x40 0xfc 0x00 0x01] +# CHECK-V7: mcrr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x40 0xfc 0x00 0x01] + +[0x40 0xfc 0x00 0x0e] +# CHECK-V7: mcrr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x40 0xfc 0x00 0x0e] + +[0x40 0xfc 0x00 0x0f] +# CHECK-V7: mcrr2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x40 0xfc 0x00 0x0f] + +[0x50 0xec 0x00 0x01] +# CHECK-V7: mrrc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x50 0xec 0x00 0x01] + +[0x50 0xfc 0x00 0x0e] +# CHECK-V7: mrrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x50 0xfc 0x00 0x0e] + +[0x50 0xfc 0x00 0x0f] +# CHECK-V7: mrrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x50 0xfc 0x00 0x0f] + +[0x50 0xfc 0x00 0x01] +# CHECK-V7: mrrc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x50 0xfc 0x00 0x01] + +[0x80 0xec 0x00 0x01] +# CHECK-V7: stc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xec 0x00 0x01] + +[0x80 0xec 0x00 0x0f] +# CHECK-V7: stc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xec 0x00 0x0f] + +[0x80 0xfc 0x00 0x01] +# CHECK-V7: stc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xfc 0x00 0x01] + +[0x80 0xfc 0x00 0x0e] +# CHECK-V7: stc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xfc 0x00 0x0e] + +[0x80 0xfc 0x00 0x0f] +# CHECK-V7: stc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x80 0xfc 0x00 0x0f] + +[0x90 0xec 0x00 0x01] +# CHECK-V7: ldc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x90 0xec 0x00 0x01] + +[0x90 0xec 0x00 0x0f] +# CHECK-V7: ldc +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x90 0xec 0x00 0x0f] + +[0x90 0xfc 0x00 0x01] +# CHECK-V7: ldc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x90 0xfc 0x00 0x01] + +[0x90 0xfc 0x00 0x0e] +# CHECK-V7: ldc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x90 0xfc 0x00 0x0e] + +[0x90 0xfc 0x00 0x0f] +# CHECK-V7: ldc2 +# CHECK: invalid instruction encoding +# CHECK-NEXT: [0x90 0xfc 0x00 0x0f] + diff --git a/test/MC/Disassembler/ARM/lit.local.cfg b/test/MC/Disassembler/ARM/lit.local.cfg index 22a76e5..8a3ba96 100644 --- a/test/MC/Disassembler/ARM/lit.local.cfg +++ b/test/MC/Disassembler/ARM/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.txt'] - targets = set(config.root.targets_to_build.split()) if not 'ARM' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/ARM/load-store-acquire-release-v8-thumb.txt b/test/MC/Disassembler/ARM/load-store-acquire-release-v8-thumb.txt new file mode 100644 index 0000000..8a2ba74 --- /dev/null +++ b/test/MC/Disassembler/ARM/load-store-acquire-release-v8-thumb.txt @@ -0,0 +1,33 @@ +# RUN: llvm-mc -triple=thumbv8 -disassemble -show-encoding < %s | FileCheck %s + +0xd4 0xe8 0xcf 0x3f +0xd5 0xe8 0xdf 0x2f +0xd7 0xe8 0xef 0x1f +0xd8 0xe8 0xff 0x67 +# CHECK: ldaexb r3, [r4] @ encoding: [0xd4,0xe8,0xcf,0x3f] +# CHECK: ldaexh r2, [r5] @ encoding: [0xd5,0xe8,0xdf,0x2f] +# CHECK: ldaex r1, [r7] @ encoding: [0xd7,0xe8,0xef,0x1f] +# CHECK: ldaexd r6, r7, [r8] @ encoding: [0xd8,0xe8,0xff,0x67] + +0xc4 0xe8 0xc1 0x3f +0xc5 0xe8 0xd4 0x2f +0xc7 0xe8 0xe2 0x1f +0xc8 0xe8 0xf6 0x23 +# CHECK: stlexb r1, r3, [r4] @ encoding: [0xc4,0xe8,0xc1,0x3f] +# CHECK: stlexh r4, r2, [r5] @ encoding: [0xc5,0xe8,0xd4,0x2f] +# CHECK: stlex r2, r1, [r7] @ encoding: [0xc7,0xe8,0xe2,0x1f] +# CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0xc8,0xe8,0xf6,0x23] + +0xd6 0xe8 0xaf 0x5f +0xd6 0xe8 0x8f 0x5f +0xd9 0xe8 0x9f 0xcf +# CHECK: lda r5, [r6] @ encoding: [0xd6,0xe8,0xaf,0x5f] +# CHECK: ldab r5, [r6] @ encoding: [0xd6,0xe8,0x8f,0x5f] +# CHECK: ldah r12, [r9] @ encoding: [0xd9,0xe8,0x9f,0xcf] + +0xc0 0xe8 0xaf 0x3f +0xc1 0xe8 0x8f 0x2f +0xc3 0xe8 0x9f 0x2f +# CHECK: stl r3, [r0] @ encoding: [0xc0,0xe8,0xaf,0x3f] +# CHECK: stlb r2, [r1] @ encoding: [0xc1,0xe8,0x8f,0x2f] +# CHECK: stlh r2, [r3] @ encoding: [0xc3,0xe8,0x9f,0x2f] diff --git a/test/MC/Disassembler/ARM/load-store-acquire-release-v8.txt b/test/MC/Disassembler/ARM/load-store-acquire-release-v8.txt new file mode 100644 index 0000000..058f9cc --- /dev/null +++ b/test/MC/Disassembler/ARM/load-store-acquire-release-v8.txt @@ -0,0 +1,32 @@ +# RUN: llvm-mc -triple=armv8 -disassemble -show-encoding < %s | FileCheck %s +0x9f 0x0e 0xd8 0xe1 +0x9f 0x1e 0xfc 0xe1 +0x9f 0x1e 0x90 0xe1 +0x9f 0x8e 0xbd 0xe1 +# CHECK: ldaexb r0, [r8] @ encoding: [0x9f,0x0e,0xd8,0xe1] +# CHECK: ldaexh r1, [r12] @ encoding: [0x9f,0x1e,0xfc,0xe1] +# CHECK: ldaex r1, [r0] @ encoding: [0x9f,0x1e,0x90,0xe1] +# CHECK: ldaexd r8, r9, [sp] @ encoding: [0x9f,0x8e,0xbd,0xe1] + +0x93 0x1e 0xc4 0xe1 +0x92 0x4e 0xe5 0xe1 +0x91 0x2e 0x87 0xe1 +0x92 0x6e 0xa8 0xe1 +# CHECK: stlexb r1, r3, [r4] @ encoding: [0x93,0x1e,0xc4,0xe1] +# CHECK: stlexh r4, r2, [r5] @ encoding: [0x92,0x4e,0xe5,0xe1] +# CHECK: stlex r2, r1, [r7] @ encoding: [0x91,0x2e,0x87,0xe1] +# CHECK: stlexd r6, r2, r3, [r8] @ encoding: [0x92,0x6e,0xa8,0xe1] + +0x9f 0x5c 0x96 0xe1 +0x9f 0x5c 0xd6 0xe1 +0x9f 0xcc 0xf9 0xe1 +# CHECK: lda r5, [r6] @ encoding: [0x9f,0x5c,0x96,0xe1] +# CHECK: ldab r5, [r6] @ encoding: [0x9f,0x5c,0xd6,0xe1] +# CHECK: ldah r12, [r9] @ encoding: [0x9f,0xcc,0xf9,0xe1] + +0x93 0xfc 0x80 0xe1 +0x92 0xfc 0xc1 0xe1 +0x92 0xfc 0xe3 0xe1 +# CHECK: stl r3, [r0] @ encoding: [0x93,0xfc,0x80,0xe1] +# CHECK: stlb r2, [r1] @ encoding: [0x92,0xfc,0xc1,0xe1] +# CHECK: stlh r2, [r3] @ encoding: [0x92,0xfc,0xe3,0xe1] diff --git a/test/MC/Disassembler/ARM/neon-crypto.txt b/test/MC/Disassembler/ARM/neon-crypto.txt new file mode 100644 index 0000000..086c781 --- /dev/null +++ b/test/MC/Disassembler/ARM/neon-crypto.txt @@ -0,0 +1,35 @@ +# RUN: llvm-mc -triple armv8-unknown-unknown -mattr=+neon,+crypto -disassemble < %s | FileCheck %s + +0x42,0x03,0xb0,0xf3 +# CHECK: aesd.8 q0, q1 +0x02,0x03,0xb0,0xf3 +# CHECK: aese.8 q0, q1 +0xc2,0x03,0xb0,0xf3 +# CHECK: aesimc.8 q0, q1 +0x82,0x03,0xb0,0xf3 +# CHECK: aesmc.8 q0, q1 + +0xc2,0x02,0xb9,0xf3 +# CHECK: sha1h.32 q0, q1 +0x82,0x03,0xba,0xf3 +# CHECK: sha1su1.32 q0, q1 +0xc2,0x03,0xba,0xf3 +# CHECK: sha256su0.32 q0, q1 + +0x44,0x0c,0x02,0xf2 +# CHECK: sha1c.32 q0, q1, q2 +0x44,0x0c,0x22,0xf2 +# CHECK: sha1m.32 q0, q1, q2 +0x44,0x0c,0x12,0xf2 +# CHECK: sha1p.32 q0, q1, q2 +0x44,0x0c,0x32,0xf2 +# CHECK: sha1su0.32 q0, q1, q2 +0x44,0x0c,0x02,0xf3 +# CHECK: sha256h.32 q0, q1, q2 +0x44,0x0c,0x12,0xf3 +# CHECK: sha256h2.32 q0, q1, q2 +0x44,0x0c,0x22,0xf3 +# CHECK: sha256su1.32 q0, q1, q2 + +0xa1,0x0e,0xe0,0xf2 +# CHECK: vmull.p64 q8, d16, d17 diff --git a/test/MC/Disassembler/ARM/thumb-v8fp.txt b/test/MC/Disassembler/ARM/thumb-fp-armv8.txt index 3457192..c90eed6 100644 --- a/test/MC/Disassembler/ARM/thumb-v8fp.txt +++ b/test/MC/Disassembler/ARM/thumb-fp-armv8.txt @@ -1,4 +1,4 @@ -# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+v8fp -show-encoding < %s | FileCheck %s +# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+fp-armv8 -show-encoding < %s | FileCheck %s 0xb2 0xee 0xe0 0x3b # CHECK: vcvtt.f64.f16 d3, s1 diff --git a/test/MC/Disassembler/ARM/thumb-neon-crypto.txt b/test/MC/Disassembler/ARM/thumb-neon-crypto.txt new file mode 100644 index 0000000..c725c7f --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-neon-crypto.txt @@ -0,0 +1,43 @@ +# RUN: llvm-mc -triple thumbv8-unknown-unknown -mattr=+neon,+crypto -disassemble < %s | FileCheck %s + +0xb0 0xff 0x42 0x03 +# CHECK: aesd.8 q0, q1 +0xb0 0xff 0x02 0x03 +# CHECK: aese.8 q0, q1 +0xb0 0xff 0xc2 0x03 +# CHECK: aesimc.8 q0, q1 +0xb0 0xff 0x82 0x03 +# CHECK: aesmc.8 q0, q1 + +0xb9 0xff 0xc2 0x02 +# CHECK: sha1h.32 q0, q1 +0xba 0xff 0x82 0x03 +# CHECK: sha1su1.32 q0, q1 +0xba 0xff 0xc2 0x03 +# CHECK: sha256su0.32 q0, q1 + +0x02 0xef 0x44 0x0c +# CHECK: sha1c.32 q0, q1, q2 +0x22 0xef 0x44 0x0c +# CHECK: sha1m.32 q0, q1, q2 +0x12 0xef 0x44 0x0c +# CHECK: sha1p.32 q0, q1, q2 +0x32 0xef 0x44 0x0c +# CHECK: sha1su0.32 q0, q1, q2 +0x02 0xff 0x44 0x0c +# CHECK: sha256h.32 q0, q1, q2 +0x12 0xff 0x44 0x0c +# CHECK: sha256h2.32 q0, q1, q2 +0x22 0xff 0x44 0x0c +# CHECK: sha256su1.32 q0, q1, q2 + +0xe0 0xef 0xa1 0x0e +# CHECK: vmull.p64 q8, d16, d17 + +# This used to be incorrectly decoded into an sha256h.32 [0x00,0xff,0x40,0x0c] +# The other similar encodings are stc2 [0x00,0xfd,0x40,0x0c] and cdp2 [0x00,0xfe,0x40,0x0c] +0x00 0xfc 0x40 0x0c +# CHECK-NOT: sha256h.32 +# CHECK-NOT: stc2 +# CHECK-NOT: cdp2 + diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 84dd075..df2bac1 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -125,7 +125,7 @@ # CHECK: cps #15 0xaf 0xf3 0x0f 0x81 -# CHECK: cpsie.w if, #10 +# CHECK: cpsie if, #10 0xaf 0xf3 0x6a 0x85 # CHECK: cpsie aif diff --git a/test/MC/Disassembler/ARM/thumb-v8.txt b/test/MC/Disassembler/ARM/thumb-v8.txt new file mode 100644 index 0000000..eb5ffea --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb-v8.txt @@ -0,0 +1,28 @@ +# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding < %s | FileCheck %s + +0x80 0xba +# CHECK: hlt #0 + +0xbf 0xba +# CHECK: hlt #63 + +# DCPS{1,2,3} + +0x8f 0xf7 0x01 0x80 +# CHECK: dcps1 + +0x8f 0xf7 0x02 0x80 +# CHECK: dcps2 + +0x8f 0xf7 0x03 0x80 +# CHECK: dcps3 + +0xbf 0xf3 0x59 0x8f +0xbf 0xf3 0x51 0x8f +0xbf 0xf3 0x55 0x8f +0xbf 0xf3 0x5d 0x8f + +# CHECK: dmb ishld +# CHECK: dmb oshld +# CHECK: dmb nshld +# CHECK: dmb ld diff --git a/test/MC/Disassembler/ARM/thumb2-v8.txt b/test/MC/Disassembler/ARM/thumb2-v8.txt new file mode 100644 index 0000000..1b2f095 --- /dev/null +++ b/test/MC/Disassembler/ARM/thumb2-v8.txt @@ -0,0 +1,40 @@ +# RUN: llvm-mc -triple=thumbv8 -disassemble < %s | FileCheck %s +# CHECK: sevl +# CHECK: sevl.w +0x50 0xbf +0xaf 0xf3 0x05 0x80 + + +# These are the only coprocessor instructions that remain defined in ARMv8 +# (The operations on p10/p11 disassemble into FP/NEON instructions) + +0x00 0xee 0x10 0x0e +# CHECK: mcr p14 + +0x00 0xee 0x10 0x0f +# CHECK: mcr p15 + +0x10 0xee 0x10 0x0e +# CHECK: mrc p14 + +0x10 0xee 0x10 0x0f +# CHECK: mrc p15 + +0x40 0xec 0x00 0x0e +# CHECK: mcrr p14 + +0x40 0xec 0x00 0x0f +# CHECK: mcrr p15 + +0x50 0xec 0x00 0x0e +# CHECK: mrrc p14 + +0x50 0xec 0x00 0x0f +# CHECK: mrrc p15 + +0x80 0xec 0x00 0x0e +# CHECK: stc p14 + +0x90 0xec 0x00 0x0e +# CHECK: ldc p14 + diff --git a/test/MC/Disassembler/ARM/thumb2.txt b/test/MC/Disassembler/ARM/thumb2.txt index 9fc166f..c8b4080 100644 --- a/test/MC/Disassembler/ARM/thumb2.txt +++ b/test/MC/Disassembler/ARM/thumb2.txt @@ -2707,3 +2707,14 @@ 0x30 0xbf 0x10 0xbf +#------------------------------------------------------------------------------ +# Unallocated hints (They execute as NOPs, but software must not use them.) +#------------------------------------------------------------------------------ +# CHECK: hint #6 +# CHECK: hint.w #6 +# CHECK: hint.w #102 + +0x60 0xbf +0xaf 0xf3 0x06 0x80 +0xaf 0xf3 0x66 0x80 + diff --git a/test/MC/Disassembler/Mips/lit.local.cfg b/test/MC/Disassembler/Mips/lit.local.cfg index 9b698b2..1fa54b4 100644 --- a/test/MC/Disassembler/Mips/lit.local.cfg +++ b/test/MC/Disassembler/Mips/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.txt'] - targets = set(config.root.targets_to_build.split()) if not 'Mips' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/Mips/micromips.txt b/test/MC/Disassembler/Mips/micromips.txt new file mode 100644 index 0000000..b2d0cc0 --- /dev/null +++ b/test/MC/Disassembler/Mips/micromips.txt @@ -0,0 +1,287 @@ +# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mattr=micromips \ +# RUN: | FileCheck %s + +# CHECK: add $9, $6, $7 +0x00 0xe6 0x49 0x10 + +# CHECK: addi $9, $6, 17767 +0x11 0x26 0x45 0x67 + +# CHECK: addiu $9, $6, -15001 +0x31 0x26 0xc5 0x67 + +# CHECK: addi $9, $6, 17767 +0x11 0x26 0x45 0x67 + +# CHECK: addiu $9, $6, -15001 +0x31 0x26 0xc5 0x67 + +# CHECK: addu $9, $6, $7 +0x00 0xe6 0x49 0x50 + +# CHECK: sub $9, $6, $7 +0x00 0xe6 0x49 0x90 + +# CHECK: subu $4, $3, $5 +0x00 0xa3 0x21 0xd0 + +# CHECK: sub $6, $zero, $7 +0x00 0xe0 0x31 0x90 + +# CHECK: subu $6, $zero, $7 +0x00 0xe0 0x31 0xd0 + +# CHECK: addu $7, $8, $zero +0x00 0x08 0x39 0x50 + +# CHECK: slt $3, $3, $5 +0x00 0xa3 0x1b 0x50 + +# CHECK: slti $3, $3, 103 +0x90 0x63 0x00 0x67 + +# CHECK: slti $3, $3, 103 +0x90 0x63 0x00 0x67 + +# CHECK: sltiu $3, $3, 103 +0xb0 0x63 0x00 0x67 + +# CHECK: sltu $3, $3, $5 +0x00 0xa3 0x1b 0x90 + +# CHECK: lui $9, 17767 +0x41 0xa9 0x45 0x67 + +# CHECK: and $9, $6, $7 +0x00 0xe6 0x4a 0x50 + +# CHECK: andi $9, $6, 17767 +0xd1 0x26 0x45 0x67 + +# CHECK: andi $9, $6, 17767 +0xd1 0x26 0x45 0x67 + +# CHECK: or $3, $4, $5 +0x00 0xa4 0x1a 0x90 + +# CHECK: ori $9, $6, 17767 +0x51 0x26 0x45 0x67 + +# CHECK: xor $3, $3, $5 +0x00 0xa3 0x1b 0x10 + +# CHECK: xori $9, $6, 17767 +0x71 0x26 0x45 0x67 + +# CHECK: xori $9, $6, 17767 +0x71 0x26 0x45 0x67 + +# CHECK: nor $9, $6, $7 +0x00 0xe6 0x4a 0xd0 + +# CHECK: not $7, $8 +0x00 0x08 0x3a 0xd0 + +# CHECK: mul $9, $6, $7 +0x00 0xe6 0x4a 0x10 + +# CHECK: mult $9, $7 +0x00 0xe9 0x8b 0x3c + +# CHECK: multu $9, $7 +0x00 0xe9 0x9b 0x3c + +# CHECK-EB: div $zero, $9, $7 +0x00 0xe9 0xab 0x3c + +# CHECK-EB: divu $zero, $9, $7 +0x00 0xe9 0xbb 0x3c + +# CHECK: sll $4, $3, 7 +0x00 0x83 0x38 0x00 + +# CHECK: sllv $2, $3, $5 +0x00 0x65 0x10 0x10 + +# CHECK: sra $4, $3, 7 +0x00 0x83 0x38 0x80 + +# CHECK: srav $2, $3, $5 +0x00 0x65 0x10 0x90 + +# CHECK: srl $4, $3, 7 +0x00 0x83 0x38 0x40 + +# CHECK: srlv $2, $3, $5 +0x00 0x65 0x10 0x50 + +# CHECK: rotr $9, $6, 7 +0x01 0x26 0x38 0xc0 + +# CHECK: rotrv $9, $6, $7 +0x00 0xc7 0x48 0xd0 + +# CHECK: lb $5, 8($4) +0x1c 0xa4 0x00 0x08 + +# CHECK: lbu $6, 8($4) +0x14 0xc4 0x00 0x08 + +# CHECK: lh $2, 8($4) +0x3c 0x44 0x00 0x08 + +# CHECK: lhu $4, 8($2) +0x34 0x82 0x00 0x08 + +# CHECK: lw $6, 4($5) +0xfc 0xc5 0x00 0x04 + +# CHECK: sb $5, 8($4) +0x18 0xa4 0x00 0x08 + +# CHECK: sh $2, 8($4) +0x38 0x44 0x00 0x08 + +# CHECK: sw $5, 4($6) +0xf8 0xa6 0x00 0x04 + +# CHECK: lwl $4, 16($5) +0x60 0x85 0x00 0x10 + +# CHECK: lwr $4, 16($5) +0x60 0x85 0x10 0x10 + +# CHECK: swl $4, 16($5) +0x60 0x85 0x80 0x10 + +# CHECK: swr $4, 16($5) +0x60 0x85 0x90 0x10 + +# CHECK: movz $9, $6, $7 +0x00 0xe6 0x48 0x58 + +# CHECK: movn $9, $6, $7 +0x00 0xe6 0x48 0x18 + +# CHECK: movt $9, $6, $fcc0 +0x55 0x26 0x09 0x7b + +# CHECK: movf $9, $6, $fcc0 +0x55 0x26 0x01 0x7b + +# CHECK: mthi $6 +0x00 0x06 0x2d 0x7c + +# CHECK: mfhi $6 +0x00 0x06 0x0d 0x7c + +# CHECK: mtlo $6 +0x00 0x06 0x3d 0x7c + +# CHECK: mflo $6 +0x00 0x06 0x1d 0x7c + +# CHECK: madd $4, $5 +0x00 0xa4 0xcb 0x3c + +# CHECK: maddu $4, $5 +0x00 0xa4 0xdb 0x3c + +# CHECK: msub $4, $5 +0x00 0xa4 0xeb 0x3c + +# CHECK: msubu $4, $5 +0x00 0xa4 0xfb 0x3c + +# CHECK: clz $9, $6 +0x01 0x26 0x5b 0x3c + +# CHECK: clo $9, $6 +0x01 0x26 0x4b 0x3c + +# CHECK: seb $9, $6 +0x01 0x26 0x2b 0x3c + +# CHECK: seh $9, $6 +0x01 0x26 0x3b 0x3c + +# CHECK: wsbh $9, $6 +0x01 0x26 0x7b 0x3c + +# CHECK: ext $9, $6, 3, 7 +0x01 0x26 0x30 0xec + +# CHECK: ins $9, $6, 3, 7 +0x01 0x26 0x48 0xcc + +# CHECK: j 1328 +0xd4 0x00 0x02 0x98 + +# CHECK: jal 1328 +0xf4 0x00 0x02 0x98 + +# CHECK: jalr $ra, $6 +0x03 0xe6 0x0f 0x3c + +# CHECK: jr $7 +0x00 0x07 0x0f 0x3c + +# CHECK: beq $9, $6, 1332 +0x94 0xc9 0x02 0x9a + +# CHECK: bgez $6, 1332 +0x40 0x46 0x02 0x9a + +# CHECK: bgezal $6, 1332 +0x40 0x66 0x02 0x9a + +# CHECK: bltzal $6, 1332 +0x40 0x26 0x02 0x9a + +# CHECK: bgtz $6, 1332 +0x40 0xc6 0x02 0x9a + +# CHECK: blez $6, 1332 +0x40 0x86 0x02 0x9a + +# CHECK: bne $9, $6, 1332 +0xb4 0xc9 0x02 0x9a + +# CHECK: bltz $6, 1332 +0x40 0x06 0x02 0x9a + +# CHECK: teq $8, $9, 0 +0x01 0x28 0x00 0x3c + +# CHECK: tge $8, $9, 0 +0x01 0x28 0x02 0x3c + +# CHECK: tgeu $8, $9, 0 +0x01 0x28 0x04 0x3c + +# CHECK: tlt $8, $9, 0 +0x01 0x28 0x08 0x3c + +# CHECK: tltu $8, $9, 0 +0x01 0x28 0x0a 0x3c + +# CHECK: tne $8, $9, 0 +0x01 0x28 0x0c 0x3c + +# CHECK: teqi $9, 17767 +0x41,0xc9,0x45,0x67 + +# CHECK: tgei $9, 17767 +0x41 0x29 0x45 0x67 + +# CHECK: tgeiu $9, 17767 +0x41 0x69 0x45 0x67 + +# CHECK: tlti $9, 17767 +0x41 0x09 0x45 0x67 + +# CHECK: tltiu $9, 17767 +0x41 0x49 0x45 0x67 + +# CHECK: tnei $9, 17767 +0x41 0x89 0x45 0x67 diff --git a/test/MC/Disassembler/Mips/micromips_le.txt b/test/MC/Disassembler/Mips/micromips_le.txt new file mode 100644 index 0000000..5b2fe30 --- /dev/null +++ b/test/MC/Disassembler/Mips/micromips_le.txt @@ -0,0 +1,287 @@ +# RUN: llvm-mc --disassemble %s -triple=mipsel-unknown-linux -mattr=micromips \ +# RUN: | FileCheck %s + +# CHECK: add $9, $6, $7 +0xe6 0x00 0x10 0x49 + +# CHECK: addi $9, $6, 17767 +0x26 0x11 0x67 0x45 + +# CHECK: addiu $9, $6, -15001 +0x26 0x31 0x67 0xc5 + +# CHECK: addi $9, $6, 17767 +0x26 0x11 0x67 0x45 + +# CHECK: addiu $9, $6, -15001 +0x26 0x31 0x67 0xc5 + +# CHECK: addu $9, $6, $7 +0xe6 0x00 0x50 0x49 + +# CHECK: sub $9, $6, $7 +0xe6 0x00 0x90 0x49 + +# CHECK: subu $4, $3, $5 +0xa3 0x00 0xd0 0x21 + +# CHECK: sub $6, $zero, $7 +0xe0 0x00 0x90 0x31 + +# CHECK: subu $6, $zero, $7 +0xe0 0x00 0xd0 0x31 + +# CHECK: addu $7, $8, $zero +0x08 0x00 0x50 0x39 + +# CHECK: slt $3, $3, $5 +0xa3 0x00 0x50 0x1b + +# CHECK: slti $3, $3, 103 +0x63 0x90 0x67 0x00 + +# CHECK: slti $3, $3, 103 +0x63 0x90 0x67 0x00 + +# CHECK: sltiu $3, $3, 103 +0x63 0xb0 0x67 0x00 + +# CHECK: sltu $3, $3, $5 +0xa3 0x00 0x90 0x1b + +# CHECK: lui $9, 17767 +0xa9 0x41 0x67 0x45 + +# CHECK: and $9, $6, $7 +0xe6 0x00 0x50 0x4a + +# CHECK: andi $9, $6, 17767 +0x26 0xd1 0x67 0x45 + +# CHECK: andi $9, $6, 17767 +0x26 0xd1 0x67 0x45 + +# CHECK: or $3, $4, $5 +0xa4 0x00 0x90 0x1a + +# CHECK: ori $9, $6, 17767 +0x26 0x51 0x67 0x45 + +# CHECK: xor $3, $3, $5 +0xa3 0x00 0x10 0x1b + +# CHECK: xori $9, $6, 17767 +0x26 0x71 0x67 0x45 + +# CHECK: xori $9, $6, 17767 +0x26 0x71 0x67 0x45 + +# CHECK: nor $9, $6, $7 +0xe6 0x00 0xd0 0x4a + +# CHECK: not $7, $8 +0x08 0x00 0xd0 0x3a + +# CHECK: mul $9, $6, $7 +0xe6 0x00 0x10 0x4a + +# CHECK: mult $9, $7 +0xe9 0x00 0x3c 0x8b + +# CHECK: multu $9, $7 +0xe9 0x00 0x3c 0x9b + +# CHECK: div $zero, $9, $7 +0xe9 0x00 0x3c 0xab + +# CHECK: divu $zero, $9, $7 +0xe9 0x00 0x3c 0xbb + +# CHECK: sll $4, $3, 7 +0x83 0x00 0x00 0x38 + +# CHECK: sllv $2, $3, $5 +0x65 0x00 0x10 0x10 + +# CHECK: sra $4, $3, 7 +0x83 0x00 0x80 0x38 + +# CHECK: srav $2, $3, $5 +0x65 0x00 0x90 0x10 + +# CHECK: srl $4, $3, 7 +0x83 0x00 0x40 0x38 + +# CHECK: srlv $2, $3, $5 +0x65 0x00 0x50 0x10 + +# CHECK: rotr $9, $6, 7 +0x26 0x01 0xc0 0x38 + +# CHECK: rotrv $9, $6, $7 +0xc7 0x00 0xd0 0x48 + +# CHECK: lb $5, 8($4) +0xa4 0x1c 0x08 0x00 + +# CHECK: lbu $6, 8($4) +0xc4 0x14 0x08 0x00 + +# CHECK: lh $2, 8($4) +0x44 0x3c 0x08 0x00 + +# CHECK: lhu $4, 8($2) +0x82 0x34 0x08 0x00 + +# CHECK: lw $6, 4($5) +0xc5 0xfc 0x04 0x00 + +# CHECK: sb $5, 8($4) +0xa4 0x18 0x08 0x00 + +# CHECK: sh $2, 8($4) +0x44 0x38 0x08 0x00 + +# CHECK: sw $5, 4($6) +0xa6 0xf8 0x04 0x00 + +# CHECK: lwl $4, 16($5) +0x85 0x60 0x10 0x00 + +# CHECK: lwr $4, 16($5) +0x85 0x60 0x10 0x10 + +# CHECK: swl $4, 16($5) +0x85 0x60 0x10 0x80 + +# CHECK: swr $4, 16($5) +0x85 0x60 0x10 0x90 + +# CHECK: movz $9, $6, $7 +0xe6 0x00 0x58 0x48 + +# CHECK: movn $9, $6, $7 +0xe6 0x00 0x18 0x48 + +# CHECK: movt $9, $6, $fcc0 +0x26 0x55 0x7b 0x09 + +# CHECK: movf $9, $6, $fcc0 +0x26 0x55 0x7b 0x01 + +# CHECK: mthi $6 +0x06 0x00 0x7c 0x2d + +# CHECK: mfhi $6 +0x06 0x00 0x7c 0x0d + +# CHECK: mtlo $6 +0x06 0x00 0x7c 0x3d + +# CHECK: mflo $6 +0x06 0x00 0x7c 0x1d + +# CHECK: madd $4, $5 +0xa4 0x00 0x3c 0xcb + +# CHECK: maddu $4, $5 +0xa4 0x00 0x3c 0xdb + +# CHECK: msub $4, $5 +0xa4 0x00 0x3c 0xeb + +# CHECK: msubu $4, $5 +0xa4 0x00 0x3c 0xfb + +# CHECK: clz $9, $6 +0x26 0x01 0x3c 0x5b + +# CHECK: clo $9, $6 +0x26 0x01 0x3c 0x4b + +# CHECK: seb $9, $6 +0x26 0x01 0x3c 0x2b + +# CHECK: seh $9, $6 +0x26 0x01 0x3c 0x3b + +# CHECK: wsbh $9, $6 +0x26 0x01 0x3c 0x7b + +# CHECK: ext $9, $6, 3, 7 +0x26 0x01 0xec 0x30 + +# CHECK: ins $9, $6, 3, 7 +0x26 0x01 0xcc 0x48 + +# CHECK: j 1328 +0x00 0xd4 0x98 0x02 + +# CHECK: jal 1328 +0x00 0xf4 0x98 0x02 + +# CHECK: jalr $ra, $6 +0xe6 0x03 0x3c 0x0f + +# CHECK: jr $7 +0x07 0x00 0x3c 0x0f + +# CHECK: beq $9, $6, 1332 +0xc9 0x94 0x9a 0x02 + +# CHECK: bgez $6, 1332 +0x46 0x40 0x9a 0x02 + +# CHECK: bgezal $6, 1332 +0x66 0x40 0x9a 0x02 + +# CHECK: bltzal $6, 1332 +0x26 0x40 0x9a 0x02 + +# CHECK: bgtz $6, 1332 +0xc6 0x40 0x9a 0x02 + +# CHECK: blez $6, 1332 +0x86 0x40 0x9a 0x02 + +# CHECK: bne $9, $6, 1332 +0xc9 0xb4 0x9a 0x02 + +# CHECK: bltz $6, 1332 +0x06 0x40 0x9a 0x02 + +# CHECK: teq $8, $9, 0 +0x28 0x01 0x3c 0x00 + +# CHECK: tge $8, $9, 0 +0x28 0x01 0x3c 0x02 + +# CHECK: tgeu $8, $9, 0 +0x28 0x01 0x3c 0x04 + +# CHECK: tlt $8, $9, 0 +0x28 0x01 0x3c 0x08 + +# CHECK: tltu $8, $9, 0 +0x28 0x01 0x3c 0x0a + +# CHECK: tne $8, $9, 0 +0x28 0x01 0x3c 0x0c + +# CHECK: teqi $9, 17767 +0xc9 0x41 0x67 0x45 + +# CHECK: tgei $9, 17767 +0x29 0x41 0x67 0x45 + +# CHECK: tgeiu $9, 17767 +0x69 0x41 0x67 0x45 + +# CHECK: tlti $9, 17767 +0x09 0x41 0x67 0x45 + +# CHECK: tltiu $9, 17767 +0x49 0x41 0x67 0x45 + +# CHECK: tnei $9, 17767 +0x89 0x41 0x67 0x45 diff --git a/test/MC/Disassembler/Mips/mips-dsp.txt b/test/MC/Disassembler/Mips/mips-dsp.txt index d10e62c..3f60ae1 100644 --- a/test/MC/Disassembler/Mips/mips-dsp.txt +++ b/test/MC/Disassembler/Mips/mips-dsp.txt @@ -11,3 +11,12 @@ # CHECK: mtlo $21, $ac3 0x13 0x18 0xa0 0x02 + +# CHECK: lbux $10, $20($26) +0x8a 0x51 0x54 0x7f + +# CHECK: lhx $11, $21($27) +0x0a 0x59 0x75 0x7f + +# CHECK: lwx $12, $22($gp) +0x0a 0x60 0x96 0x7f diff --git a/test/MC/Disassembler/Mips/mips32r2.txt b/test/MC/Disassembler/Mips/mips32r2.txt index 48b6ad4..11d9058 100644 --- a/test/MC/Disassembler/Mips/mips32r2.txt +++ b/test/MC/Disassembler/Mips/mips32r2.txt @@ -242,6 +242,9 @@ # CHECK: lui $6, 17767 0x3c 0x06 0x45 0x67 +# CHECK: luxc1 $f0, $6($5) +0x4c 0xa6 0x00 0x05 + # CHECK: lw $4, 24($5) 0x8c 0xa4 0x00 0x18 @@ -254,6 +257,9 @@ # CHECK: lwr $3, 16($5) 0x98 0xa3 0x00 0x10 +# CHECK: lwxc1 $f20, $12($14) +0x4d 0xcc 0x05 0x00 + # CHECK: madd $6, $7 0x70 0xc7 0x00 0x00 @@ -404,6 +410,9 @@ # CHECK: subu $4, $3, $5 0x00 0x65 0x20 0x23 +# CHECK: suxc1 $f4, $24($5) +0x4c 0xb8 0x20 0x0d + # CHECK: sw $4, 24($5) 0xac 0xa4 0x00 0x18 @@ -416,6 +425,9 @@ # CHECK: swr $6, 16($7) 0xb8 0xe6 0x00 0x10 +# CHECK: swxc1 $f26, $18($22) +0x4e 0xd2 0xd0 0x08 + # CHECK: sync 7 0x00 0x00 0x01 0xcf diff --git a/test/MC/Disassembler/Mips/mips32r2_le.txt b/test/MC/Disassembler/Mips/mips32r2_le.txt index c62c695..adafcf1 100644 --- a/test/MC/Disassembler/Mips/mips32r2_le.txt +++ b/test/MC/Disassembler/Mips/mips32r2_le.txt @@ -242,6 +242,9 @@ # CHECK: lui $6, 17767 0x67 0x45 0x06 0x3c +# CHECK: luxc1 $f0, $6($5) +0x05 0x00 0xa6 0x4c + # CHECK: lw $4, 24($5) 0x18 0x00 0xa4 0x8c @@ -254,6 +257,9 @@ # CHECK: lwr $3, 16($5) 0x10 0x00 0xa3 0x98 +# CHECK: lwxc1 $f20, $12($14) +0x00 0x05 0xcc 0x4d + # CHECK: madd $6, $7 0x00 0x00 0xc7 0x70 @@ -404,6 +410,9 @@ # CHECK: subu $4, $3, $5 0x23 0x20 0x65 0x00 +# CHECK: suxc1 $f4, $24($5) +0x0d 0x20 0xb8 0x4c + # CHECK: sw $4, 24($5) 0x18 0x00 0xa4 0xac @@ -416,6 +425,9 @@ # CHECK: swr $6, 16($7) 0x10 0x00 0xe6 0xb8 +# CHECK: swxc1 $f26, $18($22) +0x08 0xd0 0xd2 0x4e + # CHECK: sync 7 0xcf 0x01 0x00 0x00 diff --git a/test/MC/Disassembler/Mips/mips64.txt b/test/MC/Disassembler/Mips/mips64.txt index b887473..f3d2d10 100644 --- a/test/MC/Disassembler/Mips/mips64.txt +++ b/test/MC/Disassembler/Mips/mips64.txt @@ -2,6 +2,9 @@ # CHECK: daddiu $11, $26, 31949 0x67 0x4b 0x7c 0xcd +# CHECK: daddiu $sp, $sp, -32 +0x67 0xbd 0xff 0xe0 + # CHECK: daddu $26, $1, $11 0x00 0x2b 0xd0 0x2d @@ -64,3 +67,21 @@ # CHECK: sd $6, 17767($zero) 0xfc 0x06 0x45 0x67 + +# CHECK: luxc1 $f0, $6($5) +0x4c 0xa6 0x00 0x05 + +# CHECK: lwxc1 $f20, $12($14) +0x4d 0xcc 0x05 0x00 + +# CHECK: suxc1 $f4, $24($5) +0x4c 0xb8 0x20 0x0d + +# CHECK: swxc1 $f26, $18($22) +0x4e 0xd2 0xd0 0x08 + +# CHECK: ldxc1 $f2, $2($10) +0x4d 0x42 0x00 0x81 + +# CHECK: sdxc1 $f8, $4($25) +0x4f 0x24 0x40 0x09 diff --git a/test/MC/Disassembler/Mips/mips64_le.txt b/test/MC/Disassembler/Mips/mips64_le.txt index ddc3c2b..0d3d2fa 100644 --- a/test/MC/Disassembler/Mips/mips64_le.txt +++ b/test/MC/Disassembler/Mips/mips64_le.txt @@ -64,3 +64,21 @@ # CHECK: sd $6, 17767($zero) 0x67 0x45 0x06 0xfc + +# CHECK: luxc1 $f0, $6($5) +0x05 0x00 0xa6 0x4c + +# CHECK: lwxc1 $f20, $12($14) +0x00 0x05 0xcc 0x4d + +# CHECK: suxc1 $f4, $24($5) +0x0d 0x20 0xb8 0x4c + +# CHECK: swxc1 $f26, $18($22) +0x08 0xd0 0xd2 0x4e + +# CHECK: ldxc1 $f2, $2($10) +0x81 0x00 0x42 0x4d + +# CHECK: sdxc1 $f8, $4($25) +0x09 0x40 0x24 0x4f diff --git a/test/MC/Disassembler/SystemZ/insns-pcrel.txt b/test/MC/Disassembler/SystemZ/insns-pcrel.txt index c565b6e..b7edab6 100644 --- a/test/MC/Disassembler/SystemZ/insns-pcrel.txt +++ b/test/MC/Disassembler/SystemZ/insns-pcrel.txt @@ -1330,3 +1330,403 @@ # 0x0000077c: # CHECK: brctg %r15, 0x1077a 0xa7 0xf7 0x7f 0xff + +# 0x00000780: +# CHECK: pfdrl 0, 0x780 +0xc6 0x02 0x00 0x00 0x00 0x00 + +# 0x00000786: +# CHECK: pfdrl 15, 0x786 +0xc6 0xf2 0x00 0x00 0x00 0x00 + +# 0x0000078c: +# CHECK: pfdrl 0, 0x78a +0xc6 0x02 0xff 0xff 0xff 0xff + +# 0x00000792: +# CHECK: pfdrl 15, 0x790 +0xc6 0xf2 0xff 0xff 0xff 0xff + +# 0x00000798: +# CHECK: pfdrl 0, 0xffffffff00000798 +0xc6 0x02 0x80 0x00 0x00 0x00 + +# 0x0000079e: +# CHECK: pfdrl 15, 0xffffffff0000079e +0xc6 0xf2 0x80 0x00 0x00 0x00 + +# 0x000007a4: +# CHECK: pfdrl 0, 0x1000007a2 +0xc6 0x02 0x7f 0xff 0xff 0xff + +# 0x000007aa: +# CHECK: pfdrl 15, 0x1000007a8 +0xc6 0xf2 0x7f 0xff 0xff 0xff + +# 0x000007b0: +# CHECK: clgrj %r0, %r0, 0, 0x7b0 +0xec 0x00 0x00 0x00 0x00 0x65 + +# 0x000007b6: +# CHECK: clgrj %r0, %r15, 0, 0x7b6 +0xec 0x0f 0x00 0x00 0x00 0x65 + +# 0x000007bc: +# CHECK: clgrj %r15, %r0, 0, 0x7bc +0xec 0xf0 0x00 0x00 0x00 0x65 + +# 0x000007c2: +# CHECK: clgrj %r7, %r8, 0, 0x7c2 +0xec 0x78 0x00 0x00 0x00 0x65 + +# 0x000007c8: +# CHECK: clgrj %r0, %r0, 0, 0x7c6 +0xec 0x00 0xff 0xff 0x00 0x65 + +# 0x000007ce: +# CHECK: clgrj %r0, %r0, 0, 0xffffffffffff07ce +0xec 0x00 0x80 0x00 0x00 0x65 + +# 0x000007d4: +# CHECK: clgrj %r0, %r0, 0, 0x107d2 +0xec 0x00 0x7f 0xff 0x00 0x65 + +# 0x000007da: +# CHECK: clgrj %r0, %r0, 1, 0x7da +0xec 0x00 0x00 0x00 0x10 0x65 + +# 0x000007e0: +# CHECK: clgrjh %r0, %r0, 0x7e0 +0xec 0x00 0x00 0x00 0x20 0x65 + +# 0x000007e6: +# CHECK: clgrj %r0, %r0, 3, 0x7e6 +0xec 0x00 0x00 0x00 0x30 0x65 + +# 0x000007ec: +# CHECK: clgrjl %r0, %r0, 0x7ec +0xec 0x00 0x00 0x00 0x40 0x65 + +# 0x000007f2: +# CHECK: clgrj %r0, %r0, 5, 0x7f2 +0xec 0x00 0x00 0x00 0x50 0x65 + +# 0x000007f8: +# CHECK: clgrjlh %r0, %r0, 0x7f8 +0xec 0x00 0x00 0x00 0x60 0x65 + +# 0x000007fe: +# CHECK: clgrj %r0, %r0, 7, 0x7fe +0xec 0x00 0x00 0x00 0x70 0x65 + +# 0x00000804: +# CHECK: clgrje %r0, %r0, 0x804 +0xec 0x00 0x00 0x00 0x80 0x65 + +# 0x0000080a: +# CHECK: clgrj %r0, %r0, 9, 0x80a +0xec 0x00 0x00 0x00 0x90 0x65 + +# 0x00000810: +# CHECK: clgrjhe %r0, %r0, 0x810 +0xec 0x00 0x00 0x00 0xa0 0x65 + +# 0x00000816: +# CHECK: clgrj %r0, %r0, 11, 0x816 +0xec 0x00 0x00 0x00 0xb0 0x65 + +# 0x0000081c: +# CHECK: clgrjle %r0, %r0, 0x81c +0xec 0x00 0x00 0x00 0xc0 0x65 + +# 0x00000822: +# CHECK: clgrj %r0, %r0, 13, 0x822 +0xec 0x00 0x00 0x00 0xd0 0x65 + +# 0x00000828: +# CHECK: clgrj %r0, %r0, 14, 0x828 +0xec 0x00 0x00 0x00 0xe0 0x65 + +# 0x0000082e: +# CHECK: clgrj %r0, %r0, 15, 0x82e +0xec 0x00 0x00 0x00 0xf0 0x65 + +# 0x00000834: +# CHECK: clrj %r0, %r0, 0, 0x834 +0xec 0x00 0x00 0x00 0x00 0x77 + +# 0x0000083a: +# CHECK: clrj %r0, %r15, 0, 0x83a +0xec 0x0f 0x00 0x00 0x00 0x77 + +# 0x00000840: +# CHECK: clrj %r15, %r0, 0, 0x840 +0xec 0xf0 0x00 0x00 0x00 0x77 + +# 0x00000846: +# CHECK: clrj %r7, %r8, 0, 0x846 +0xec 0x78 0x00 0x00 0x00 0x77 + +# 0x0000084c: +# CHECK: clrj %r0, %r0, 0, 0x84a +0xec 0x00 0xff 0xff 0x00 0x77 + +# 0x00000852: +# CHECK: clrj %r0, %r0, 0, 0xffffffffffff0852 +0xec 0x00 0x80 0x00 0x00 0x77 + +# 0x00000858: +# CHECK: clrj %r0, %r0, 0, 0x10856 +0xec 0x00 0x7f 0xff 0x00 0x77 + +# 0x0000085e: +# CHECK: clrj %r0, %r0, 1, 0x85e +0xec 0x00 0x00 0x00 0x10 0x77 + +# 0x00000864: +# CHECK: clrjh %r0, %r0, 0x864 +0xec 0x00 0x00 0x00 0x20 0x77 + +# 0x0000086a: +# CHECK: clrj %r0, %r0, 3, 0x86a +0xec 0x00 0x00 0x00 0x30 0x77 + +# 0x00000870: +# CHECK: clrjl %r0, %r0, 0x870 +0xec 0x00 0x00 0x00 0x40 0x77 + +# 0x00000876: +# CHECK: clrj %r0, %r0, 5, 0x876 +0xec 0x00 0x00 0x00 0x50 0x77 + +# 0x0000087c: +# CHECK: clrjlh %r0, %r0, 0x87c +0xec 0x00 0x00 0x00 0x60 0x77 + +# 0x00000882: +# CHECK: clrj %r0, %r0, 7, 0x882 +0xec 0x00 0x00 0x00 0x70 0x77 + +# 0x00000888: +# CHECK: clrje %r0, %r0, 0x888 +0xec 0x00 0x00 0x00 0x80 0x77 + +# 0x0000088e: +# CHECK: clrj %r0, %r0, 9, 0x88e +0xec 0x00 0x00 0x00 0x90 0x77 + +# 0x00000894: +# CHECK: clrjhe %r0, %r0, 0x894 +0xec 0x00 0x00 0x00 0xa0 0x77 + +# 0x0000089a: +# CHECK: clrj %r0, %r0, 11, 0x89a +0xec 0x00 0x00 0x00 0xb0 0x77 + +# 0x000008a0: +# CHECK: clrjle %r0, %r0, 0x8a0 +0xec 0x00 0x00 0x00 0xc0 0x77 + +# 0x000008a6: +# CHECK: clrj %r0, %r0, 13, 0x8a6 +0xec 0x00 0x00 0x00 0xd0 0x77 + +# 0x000008ac: +# CHECK: clrj %r0, %r0, 14, 0x8ac +0xec 0x00 0x00 0x00 0xe0 0x77 + +# 0x000008b2: +# CHECK: clrj %r0, %r0, 15, 0x8b2 +0xec 0x00 0x00 0x00 0xf0 0x77 + +# 0x000008b8: +# CHECK: clgij %r0, 0, 0, 0x8b8 +0xec 0x00 0x00 0x00 0x00 0x7d + +# 0x000008be: +# CHECK: clgij %r0, 127, 0, 0x8be +0xec 0x00 0x00 0x00 0x7f 0x7d + +# 0x000008c4: +# CHECK: clgij %r0, 128, 0, 0x8c4 +0xec 0x00 0x00 0x00 0x80 0x7d + +# 0x000008ca: +# CHECK: clgij %r0, 255, 0, 0x8ca +0xec 0x00 0x00 0x00 0xff 0x7d + +# 0x000008d0: +# CHECK: clgij %r15, 0, 0, 0x8d0 +0xec 0xf0 0x00 0x00 0x00 0x7d + +# 0x000008d6: +# CHECK: clgij %r7, 100, 0, 0x8d6 +0xec 0x70 0x00 0x00 0x64 0x7d + +# 0x000008dc: +# CHECK: clgij %r0, 0, 0, 0x8da +0xec 0x00 0xff 0xff 0x00 0x7d + +# 0x000008e2: +# CHECK: clgij %r0, 0, 0, 0xffffffffffff08e2 +0xec 0x00 0x80 0x00 0x00 0x7d + +# 0x000008e8: +# CHECK: clgij %r0, 0, 0, 0x108e6 +0xec 0x00 0x7f 0xff 0x00 0x7d + +# 0x000008ee: +# CHECK: clgij %r0, 0, 1, 0x8ee +0xec 0x01 0x00 0x00 0x00 0x7d + +# 0x000008f4: +# CHECK: clgijh %r0, 0, 0x8f4 +0xec 0x02 0x00 0x00 0x00 0x7d + +# 0x000008fa: +# CHECK: clgij %r0, 0, 3, 0x8fa +0xec 0x03 0x00 0x00 0x00 0x7d + +# 0x00000900: +# CHECK: clgijl %r0, 0, 0x900 +0xec 0x04 0x00 0x00 0x00 0x7d + +# 0x00000906: +# CHECK: clgij %r0, 0, 5, 0x906 +0xec 0x05 0x00 0x00 0x00 0x7d + +# 0x0000090c: +# CHECK: clgijlh %r0, 0, 0x90c +0xec 0x06 0x00 0x00 0x00 0x7d + +# 0x00000912: +# CHECK: clgij %r0, 0, 7, 0x912 +0xec 0x07 0x00 0x00 0x00 0x7d + +# 0x00000918: +# CHECK: clgije %r0, 0, 0x918 +0xec 0x08 0x00 0x00 0x00 0x7d + +# 0x0000091e: +# CHECK: clgij %r0, 0, 9, 0x91e +0xec 0x09 0x00 0x00 0x00 0x7d + +# 0x00000924: +# CHECK: clgijhe %r0, 0, 0x924 +0xec 0x0a 0x00 0x00 0x00 0x7d + +# 0x0000092a: +# CHECK: clgij %r0, 0, 11, 0x92a +0xec 0x0b 0x00 0x00 0x00 0x7d + +# 0x00000930: +# CHECK: clgijle %r0, 0, 0x930 +0xec 0x0c 0x00 0x00 0x00 0x7d + +# 0x00000936: +# CHECK: clgij %r0, 0, 13, 0x936 +0xec 0x0d 0x00 0x00 0x00 0x7d + +# 0x0000093c: +# CHECK: clgij %r0, 0, 14, 0x93c +0xec 0x0e 0x00 0x00 0x00 0x7d + +# 0x00000942: +# CHECK: clgij %r0, 0, 15, 0x942 +0xec 0x0f 0x00 0x00 0x00 0x7d + +# 0x00000948: +# CHECK: clij %r0, 0, 0, 0x948 +0xec 0x00 0x00 0x00 0x00 0x7f + +# 0x0000094e: +# CHECK: clij %r0, 127, 0, 0x94e +0xec 0x00 0x00 0x00 0x7f 0x7f + +# 0x00000954: +# CHECK: clij %r0, 128, 0, 0x954 +0xec 0x00 0x00 0x00 0x80 0x7f + +# 0x0000095a: +# CHECK: clij %r0, 255, 0, 0x95a +0xec 0x00 0x00 0x00 0xff 0x7f + +# 0x00000960: +# CHECK: clij %r15, 0, 0, 0x960 +0xec 0xf0 0x00 0x00 0x00 0x7f + +# 0x00000966: +# CHECK: clij %r7, 100, 0, 0x966 +0xec 0x70 0x00 0x00 0x64 0x7f + +# 0x0000096c: +# CHECK: clij %r0, 0, 0, 0x96a +0xec 0x00 0xff 0xff 0x00 0x7f + +# 0x00000972: +# CHECK: clij %r0, 0, 0, 0xffffffffffff0972 +0xec 0x00 0x80 0x00 0x00 0x7f + +# 0x00000978: +# CHECK: clij %r0, 0, 0, 0x10976 +0xec 0x00 0x7f 0xff 0x00 0x7f + +# 0x0000097e: +# CHECK: clij %r0, 0, 1, 0x97e +0xec 0x01 0x00 0x00 0x00 0x7f + +# 0x00000984: +# CHECK: clijh %r0, 0, 0x984 +0xec 0x02 0x00 0x00 0x00 0x7f + +# 0x0000098a: +# CHECK: clij %r0, 0, 3, 0x98a +0xec 0x03 0x00 0x00 0x00 0x7f + +# 0x00000990: +# CHECK: clijl %r0, 0, 0x990 +0xec 0x04 0x00 0x00 0x00 0x7f + +# 0x00000996: +# CHECK: clij %r0, 0, 5, 0x996 +0xec 0x05 0x00 0x00 0x00 0x7f + +# 0x0000099c: +# CHECK: clijlh %r0, 0, 0x99c +0xec 0x06 0x00 0x00 0x00 0x7f + +# 0x000009a2: +# CHECK: clij %r0, 0, 7, 0x9a2 +0xec 0x07 0x00 0x00 0x00 0x7f + +# 0x000009a8: +# CHECK: clije %r0, 0, 0x9a8 +0xec 0x08 0x00 0x00 0x00 0x7f + +# 0x000009ae: +# CHECK: clij %r0, 0, 9, 0x9ae +0xec 0x09 0x00 0x00 0x00 0x7f + +# 0x000009b4: +# CHECK: clijhe %r0, 0, 0x9b4 +0xec 0x0a 0x00 0x00 0x00 0x7f + +# 0x000009ba: +# CHECK: clij %r0, 0, 11, 0x9ba +0xec 0x0b 0x00 0x00 0x00 0x7f + +# 0x000009c0: +# CHECK: clijle %r0, 0, 0x9c0 +0xec 0x0c 0x00 0x00 0x00 0x7f + +# 0x000009c6: +# CHECK: clij %r0, 0, 13, 0x9c6 +0xec 0x0d 0x00 0x00 0x00 0x7f + +# 0x000009cc: +# CHECK: clij %r0, 0, 14, 0x9cc +0xec 0x0e 0x00 0x00 0x00 0x7f + +# 0x000009d2: +# CHECK: clij %r0, 0, 15, 0x9d2 +0xec 0x0f 0x00 0x00 0x00 0x7f diff --git a/test/MC/Disassembler/SystemZ/insns.txt b/test/MC/Disassembler/SystemZ/insns.txt index 51860cc..78d348d 100644 --- a/test/MC/Disassembler/SystemZ/insns.txt +++ b/test/MC/Disassembler/SystemZ/insns.txt @@ -349,6 +349,24 @@ # CHECK: ahy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x7a +# CHECK: aih %r0, -2147483648 +0xcc 0x08 0x80 0x00 0x00 0x00 + +# CHECK: aih %r0, -1 +0xcc 0x08 0xff 0xff 0xff 0xff + +# CHECK: aih %r0, 0 +0xcc 0x08 0x00 0x00 0x00 0x00 + +# CHECK: aih %r0, 1 +0xcc 0x08 0x00 0x00 0x00 0x01 + +# CHECK: aih %r0, 2147483647 +0xcc 0x08 0x7f 0xff 0xff 0xff + +# CHECK: aih %r15, 0 +0xcc 0xf8 0x00 0x00 0x00 0x00 + # CHECK: alcgr %r0, %r0 0xb9 0x88 0x00 0x00 @@ -772,6 +790,51 @@ # CHECK: basr %r15, %r1 0x0d 0xf1 +# CHECK: bcr 0, %r14 +0x07 0x0e + +# CHECK: bor %r13 +0x07 0x1d + +# CHECK: bhr %r12 +0x07 0x2c + +# CHECK: bnler %r11 +0x07 0x3b + +# CHECK: blr %r10 +0x07 0x4a + +# CHECK: bnher %r9 +0x07 0x59 + +# CHECK: blhr %r8 +0x07 0x68 + +# CHECK: bner %r7 +0x07 0x77 + +# CHECK: ber %r6 +0x07 0x86 + +# CHECK: bnlhr %r5 +0x07 0x95 + +# CHECK: bher %r4 +0x07 0xa4 + +# CHECK: bnlr %r3 +0x07 0xb3 + +# CHECK: bler %r2 +0x07 0xc2 + +# CHECK: bnhr %r1 +0x07 0xd1 + +# CHECK: bnor %r0 +0x07 0xe0 + # CHECK: br %r1 0x07 0xf1 @@ -1198,6 +1261,36 @@ # CHECK: cgxbr %r15, 0, %f0 0xb3 0xaa 0x00 0xf0 +# CHECK: chf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xcd + +# CHECK: chf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xcd + +# CHECK: chf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xcd + +# CHECK: chf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xcd + +# CHECK: chf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xcd + +# CHECK: chf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xcd + +# CHECK: chf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xcd + +# CHECK: chf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xcd + +# CHECK: chf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xcd + +# CHECK: chf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xcd + # CHECK: chhsi 0, 0 0xe5 0x54 0x00 0x00 0x00 0x00 @@ -1333,6 +1426,60 @@ # CHECK: chy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x79 +# CHECK: cih %r0, -2147483648 +0xcc 0x0d 0x80 0x00 0x00 0x00 + +# CHECK: cih %r0, -1 +0xcc 0x0d 0xff 0xff 0xff 0xff + +# CHECK: cih %r0, 0 +0xcc 0x0d 0x00 0x00 0x00 0x00 + +# CHECK: cih %r0, 1 +0xcc 0x0d 0x00 0x00 0x00 0x01 + +# CHECK: cih %r0, 2147483647 +0xcc 0x0d 0x7f 0xff 0xff 0xff + +# CHECK: cih %r15, 0 +0xcc 0xfd 0x00 0x00 0x00 0x00 + +# CHECK: clc 0(1), 0 +0xd5 0x00 0x00 0x00 0x00 0x00 + +# CHECK: clc 0(1), 0(%r1) +0xd5 0x00 0x00 0x00 0x10 0x00 + +# CHECK: clc 0(1), 0(%r15) +0xd5 0x00 0x00 0x00 0xf0 0x00 + +# CHECK: clc 0(1), 4095 +0xd5 0x00 0x00 0x00 0x0f 0xff + +# CHECK: clc 0(1), 4095(%r1) +0xd5 0x00 0x00 0x00 0x1f 0xff + +# CHECK: clc 0(1), 4095(%r15) +0xd5 0x00 0x00 0x00 0xff 0xff + +# CHECK: clc 0(1,%r1), 0 +0xd5 0x00 0x10 0x00 0x00 0x00 + +# CHECK: clc 0(1,%r15), 0 +0xd5 0x00 0xf0 0x00 0x00 0x00 + +# CHECK: clc 4095(1,%r1), 0 +0xd5 0x00 0x1f 0xff 0x00 0x00 + +# CHECK: clc 4095(1,%r15), 0 +0xd5 0x00 0xff 0xff 0x00 0x00 + +# CHECK: clc 0(256,%r1), 0 +0xd5 0xff 0x10 0x00 0x00 0x00 + +# CHECK: clc 0(256,%r15), 0 +0xd5 0xff 0xf0 0x00 0x00 0x00 + # CHECK: clfhsi 0, 0 0xe5 0x5d 0x00 0x00 0x00 0x00 @@ -1477,6 +1624,36 @@ # CHECK: clg %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x21 +# CHECK: clhf %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xcf + +# CHECK: clhf %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xcf + +# CHECK: clhf %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xcf + +# CHECK: clhf %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xcf + +# CHECK: clhf %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xcf + +# CHECK: clhf %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xcf + +# CHECK: clhf %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xcf + +# CHECK: clhf %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xcf + +# CHECK: clhf %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xcf + +# CHECK: clhf %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xcf + # CHECK: clhhsi 0, 0 0xe5 0x55 0x00 0x00 0x00 0x00 @@ -1519,6 +1696,18 @@ # CHECK: cli 4095(%r15), 42 0x95 0x2a 0xff 0xff +# CHECK: clih %r0, 0 +0xcc 0x0f 0x00 0x00 0x00 0x00 + +# CHECK: clih %r0, 1 +0xcc 0x0f 0x00 0x00 0x00 0x01 + +# CHECK: clih %r0, 4294967295 +0xcc 0x0f 0xff 0xff 0xff 0xff + +# CHECK: clih %r15, 0 +0xcc 0xff 0x00 0x00 0x00 0x00 + # CHECK: cliy -524288, 0 0xeb 0x00 0x00 0x00 0x80 0x55 @@ -1561,6 +1750,18 @@ # CHECK: clr %r7, %r8 0x15 0x78 +# CHECK: clst %r0, %r0 +0xb2 0x5d 0x00 0x00 + +# CHECK: clst %r0, %r15 +0xb2 0x5d 0x00 0x0f + +# CHECK: clst %r15, %r0 +0xb2 0x5d 0x00 0xf0 + +# CHECK: clst %r7, %r8 +0xb2 0x5d 0x00 0x78 + # CHECK: cl %r0, 0 0x55 0x00 0x00 0x00 @@ -2101,6 +2302,24 @@ # CHECK: fidbr %f15, 0, %f0 0xb3 0x5f 0x00 0xf0 +# CHECK: fidbra %f0, 0, %f0, 1 +0xb3 0x5f 0x01 0x00 + +# CHECK: fidbra %f0, 0, %f0, 15 +0xb3 0x5f 0x0f 0x00 + +# CHECK: fidbra %f0, 0, %f15, 1 +0xb3 0x5f 0x01 0x0f + +# CHECK: fidbra %f0, 15, %f0, 1 +0xb3 0x5f 0xf1 0x00 + +# CHECK: fidbra %f4, 5, %f6, 7 +0xb3 0x5f 0x57 0x46 + +# CHECK: fidbra %f15, 0, %f0, 1 +0xb3 0x5f 0x01 0xf0 + # CHECK: fiebr %f0, 0, %f0 0xb3 0x57 0x00 0x00 @@ -2116,6 +2335,24 @@ # CHECK: fiebr %f15, 0, %f0 0xb3 0x57 0x00 0xf0 +# CHECK: fiebra %f0, 0, %f0, 1 +0xb3 0x57 0x01 0x00 + +# CHECK: fiebra %f0, 0, %f0, 15 +0xb3 0x57 0x0f 0x00 + +# CHECK: fiebra %f0, 0, %f15, 1 +0xb3 0x57 0x01 0x0f + +# CHECK: fiebra %f0, 15, %f0, 1 +0xb3 0x57 0xf1 0x00 + +# CHECK: fiebra %f4, 5, %f6, 7 +0xb3 0x57 0x57 0x46 + +# CHECK: fiebra %f15, 0, %f0, 1 +0xb3 0x57 0x01 0xf0 + # CHECK: fixbr %f0, 0, %f0 0xb3 0x47 0x00 0x00 @@ -2131,6 +2368,24 @@ # CHECK: fixbr %f13, 0, %f0 0xb3 0x47 0x00 0xd0 +# CHECK: fixbra %f0, 0, %f0, 1 +0xb3 0x47 0x01 0x00 + +# CHECK: fixbra %f0, 0, %f0, 15 +0xb3 0x47 0x0f 0x00 + +# CHECK: fixbra %f0, 0, %f13, 1 +0xb3 0x47 0x01 0x0d + +# CHECK: fixbra %f0, 15, %f0, 1 +0xb3 0x47 0xf1 0x00 + +# CHECK: fixbra %f4, 5, %f8, 9 +0xb3 0x47 0x59 0x48 + +# CHECK: fixbra %f13, 0, %f0, 1 +0xb3 0x47 0x01 0xd0 + # CHECK: flogr %r0, %r0 0xb9 0x83 0x00 0x00 @@ -2260,6 +2515,15 @@ # CHECK: iill %r15, 0 0xa5 0xf3 0x00 0x00 +# CHECK: ipm %r0 +0xb2 0x22 0x00 0x00 + +# CHECK: ipm %r1 +0xb2 0x22 0x00 0x10 + +# CHECK: ipm %r15 +0xb2 0x22 0x00 0xf0 + # CHECK: la %r0, 0 0x41 0x00 0x00 0x00 @@ -2350,6 +2614,36 @@ # CHECK: lb %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x76 +# CHECK: lbh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xc0 + +# CHECK: lbh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xc0 + +# CHECK: lbh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xc0 + +# CHECK: lbh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xc0 + +# CHECK: lbh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xc0 + +# CHECK: lbh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xc0 + +# CHECK: lbh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xc0 + +# CHECK: lbh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xc0 + +# CHECK: lbh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xc0 + +# CHECK: lbh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xc0 + # CHECK: lcdbr %f0, %f9 0xb3 0x13 0x00 0x09 @@ -2638,6 +2932,36 @@ # CHECK: ley %f15, 0 0xed 0xf0 0x00 0x00 0x00 0x64 +# CHECK: lfh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xca + +# CHECK: lfh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xca + +# CHECK: lfh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xca + +# CHECK: lfh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xca + +# CHECK: lfh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xca + +# CHECK: lfh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xca + +# CHECK: lfh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xca + +# CHECK: lfh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xca + +# CHECK: lfh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xca + +# CHECK: lfh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xca + # CHECK: lgbr %r0, %r15 0xb9 0x06 0x00 0x0f @@ -2866,6 +3190,36 @@ # CHECK: lhi %r15, 0 0xa7 0xf8 0x00 0x00 +# CHECK: lhh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xc4 + +# CHECK: lhh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xc4 + +# CHECK: lhh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xc4 + +# CHECK: lhh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xc4 + +# CHECK: lhh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xc4 + +# CHECK: lhh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xc4 + +# CHECK: lhh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xc4 + +# CHECK: lhh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xc4 + +# CHECK: lhh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xc4 + +# CHECK: lhh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xc4 + # CHECK: lhr %r0, %r15 0xb9 0x27 0x00 0x0f @@ -2965,6 +3319,36 @@ # CHECK: llc %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x94 +# CHECK: llch %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xc2 + +# CHECK: llch %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xc2 + +# CHECK: llch %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xc2 + +# CHECK: llch %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xc2 + +# CHECK: llch %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xc2 + +# CHECK: llch %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xc2 + +# CHECK: llch %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xc2 + +# CHECK: llch %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xc2 + +# CHECK: llch %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xc2 + +# CHECK: llch %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xc2 + # CHECK: llgcr %r0, %r15 0xb9 0x84 0x00 0x0f @@ -3121,6 +3505,36 @@ # CHECK: llh %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x95 +# CHECK: llhh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xc6 + +# CHECK: llhh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xc6 + +# CHECK: llhh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xc6 + +# CHECK: llhh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xc6 + +# CHECK: llhh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xc6 + +# CHECK: llhh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xc6 + +# CHECK: llhh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xc6 + +# CHECK: llhh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xc6 + +# CHECK: llhh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xc6 + +# CHECK: llhh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xc6 + # CHECK: llihf %r0, 0 0xc0 0x0e 0x00 0x00 0x00 0x00 @@ -3250,6 +3664,42 @@ # CHECK: lnebr %f15, %f9 0xb3 0x01 0x00 0xf9 +# CHECK: lngfr %r0, %r0 +0xb9 0x11 0x00 0x00 + +# CHECK: lngfr %r0, %r15 +0xb9 0x11 0x00 0x0f + +# CHECK: lngfr %r15, %r0 +0xb9 0x11 0x00 0xf0 + +# CHECK: lngfr %r7, %r8 +0xb9 0x11 0x00 0x78 + +# CHECK: lngr %r0, %r0 +0xb9 0x01 0x00 0x00 + +# CHECK: lngr %r0, %r15 +0xb9 0x01 0x00 0x0f + +# CHECK: lngr %r15, %r0 +0xb9 0x01 0x00 0xf0 + +# CHECK: lngr %r7, %r8 +0xb9 0x01 0x00 0x78 + +# CHECK: lnr %r0, %r0 +0x11 0x00 + +# CHECK: lnr %r0, %r15 +0x11 0x0f + +# CHECK: lnr %r15, %r0 +0x11 0xf0 + +# CHECK: lnr %r7, %r8 +0x11 0x78 + # CHECK: lnxbr %f0, %f8 0xb3 0x41 0x00 0x08 @@ -3478,6 +3928,42 @@ # CHECK: lpebr %f15, %f9 0xb3 0x00 0x00 0xf9 +# CHECK: lpgfr %r0, %r0 +0xb9 0x10 0x00 0x00 + +# CHECK: lpgfr %r0, %r15 +0xb9 0x10 0x00 0x0f + +# CHECK: lpgfr %r15, %r0 +0xb9 0x10 0x00 0xf0 + +# CHECK: lpgfr %r7, %r8 +0xb9 0x10 0x00 0x78 + +# CHECK: lpgr %r0, %r0 +0xb9 0x00 0x00 0x00 + +# CHECK: lpgr %r0, %r15 +0xb9 0x00 0x00 0x0f + +# CHECK: lpgr %r15, %r0 +0xb9 0x00 0x00 0xf0 + +# CHECK: lpgr %r7, %r8 +0xb9 0x00 0x00 0x78 + +# CHECK: lpr %r0, %r0 +0x10 0x00 + +# CHECK: lpr %r0, %r15 +0x10 0x0f + +# CHECK: lpr %r15, %r0 +0x10 0xf0 + +# CHECK: lpr %r7, %r8 +0x10 0x78 + # CHECK: lpxbr %f0, %f8 0xb3 0x40 0x00 0x08 @@ -4435,6 +4921,42 @@ # CHECK: msy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x51 +# CHECK: mvc 0(1), 0 +0xd2 0x00 0x00 0x00 0x00 0x00 + +# CHECK: mvc 0(1), 0(%r1) +0xd2 0x00 0x00 0x00 0x10 0x00 + +# CHECK: mvc 0(1), 0(%r15) +0xd2 0x00 0x00 0x00 0xf0 0x00 + +# CHECK: mvc 0(1), 4095 +0xd2 0x00 0x00 0x00 0x0f 0xff + +# CHECK: mvc 0(1), 4095(%r1) +0xd2 0x00 0x00 0x00 0x1f 0xff + +# CHECK: mvc 0(1), 4095(%r15) +0xd2 0x00 0x00 0x00 0xff 0xff + +# CHECK: mvc 0(1,%r1), 0 +0xd2 0x00 0x10 0x00 0x00 0x00 + +# CHECK: mvc 0(1,%r15), 0 +0xd2 0x00 0xf0 0x00 0x00 0x00 + +# CHECK: mvc 4095(1,%r1), 0 +0xd2 0x00 0x1f 0xff 0x00 0x00 + +# CHECK: mvc 4095(1,%r15), 0 +0xd2 0x00 0xff 0xff 0x00 0x00 + +# CHECK: mvc 0(256,%r1), 0 +0xd2 0xff 0x10 0x00 0x00 0x00 + +# CHECK: mvc 0(256,%r15), 0 +0xd2 0xff 0xf0 0x00 0x00 0x00 + # CHECK: mvghi 0, 0 0xe5 0x48 0x00 0x00 0x00 0x00 @@ -4585,6 +5107,18 @@ # CHECK: mviy 524287(%r15), 42 0xeb 0x2a 0xff 0xff 0x7f 0x52 +# CHECK: mvst %r0, %r0 +0xb2 0x55 0x00 0x00 + +# CHECK: mvst %r0, %r15 +0xb2 0x55 0x00 0x0f + +# CHECK: mvst %r15, %r0 +0xb2 0x55 0x00 0xf0 + +# CHECK: mvst %r7, %r8 +0xb2 0x55 0x00 0x78 + # CHECK: mxbr %f0, %f0 0xb3 0x4c 0x00 0x00 @@ -4630,6 +5164,42 @@ # CHECK: mxdb %f13, 0 0xed 0xd0 0x00 0x00 0x00 0x07 +# CHECK: nc 0(1), 0 +0xd4 0x00 0x00 0x00 0x00 0x00 + +# CHECK: nc 0(1), 0(%r1) +0xd4 0x00 0x00 0x00 0x10 0x00 + +# CHECK: nc 0(1), 0(%r15) +0xd4 0x00 0x00 0x00 0xf0 0x00 + +# CHECK: nc 0(1), 4095 +0xd4 0x00 0x00 0x00 0x0f 0xff + +# CHECK: nc 0(1), 4095(%r1) +0xd4 0x00 0x00 0x00 0x1f 0xff + +# CHECK: nc 0(1), 4095(%r15) +0xd4 0x00 0x00 0x00 0xff 0xff + +# CHECK: nc 0(1,%r1), 0 +0xd4 0x00 0x10 0x00 0x00 0x00 + +# CHECK: nc 0(1,%r15), 0 +0xd4 0x00 0xf0 0x00 0x00 0x00 + +# CHECK: nc 4095(1,%r1), 0 +0xd4 0x00 0x1f 0xff 0x00 0x00 + +# CHECK: nc 4095(1,%r15), 0 +0xd4 0x00 0xff 0xff 0x00 0x00 + +# CHECK: nc 0(256,%r1), 0 +0xd4 0xff 0x10 0x00 0x00 0x00 + +# CHECK: nc 0(256,%r15), 0 +0xd4 0xff 0xf0 0x00 0x00 0x00 + # CHECK: ngr %r0, %r0 0xb9 0x80 0x00 0x00 @@ -4864,6 +5434,42 @@ # CHECK: ny %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x54 +# CHECK: oc 0(1), 0 +0xd6 0x00 0x00 0x00 0x00 0x00 + +# CHECK: oc 0(1), 0(%r1) +0xd6 0x00 0x00 0x00 0x10 0x00 + +# CHECK: oc 0(1), 0(%r15) +0xd6 0x00 0x00 0x00 0xf0 0x00 + +# CHECK: oc 0(1), 4095 +0xd6 0x00 0x00 0x00 0x0f 0xff + +# CHECK: oc 0(1), 4095(%r1) +0xd6 0x00 0x00 0x00 0x1f 0xff + +# CHECK: oc 0(1), 4095(%r15) +0xd6 0x00 0x00 0x00 0xff 0xff + +# CHECK: oc 0(1,%r1), 0 +0xd6 0x00 0x10 0x00 0x00 0x00 + +# CHECK: oc 0(1,%r15), 0 +0xd6 0x00 0xf0 0x00 0x00 0x00 + +# CHECK: oc 4095(1,%r1), 0 +0xd6 0x00 0x1f 0xff 0x00 0x00 + +# CHECK: oc 4095(1,%r15), 0 +0xd6 0x00 0xff 0xff 0x00 0x00 + +# CHECK: oc 0(256,%r1), 0 +0xd6 0xff 0x10 0x00 0x00 0x00 + +# CHECK: oc 0(256,%r15), 0 +0xd6 0xff 0xf0 0x00 0x00 0x00 + # CHECK: ogr %r0, %r0 0xb9 0x81 0x00 0x00 @@ -5098,6 +5704,36 @@ # CHECK: oy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x56 +# CHECK: pfd 0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x36 + +# CHECK: pfd 0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x36 + +# CHECK: pfd 0, 0 +0xe3 0x00 0x00 0x00 0x00 0x36 + +# CHECK: pfd 0, 1 +0xe3 0x00 0x00 0x01 0x00 0x36 + +# CHECK: pfd 0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x36 + +# CHECK: pfd 0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x36 + +# CHECK: pfd 0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x36 + +# CHECK: pfd 0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x36 + +# CHECK: pfd 0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x36 + +# CHECK: pfd 15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x36 + # CHECK: risbg %r0, %r0, 0, 0, 0 0xec 0x00 0x00 0x00 0x00 0x55 @@ -6148,6 +6784,18 @@ # CHECK: srk %r2, %r3, %r4 0xb9 0xf9 0x40 0x23 +# CHECK: srst %r0, %r0 +0xb2 0x5e 0x00 0x00 + +# CHECK: srst %r0, %r15 +0xb2 0x5e 0x00 0x0f + +# CHECK: srst %r15, %r0 +0xb2 0x5e 0x00 0xf0 + +# CHECK: srst %r7, %r8 +0xb2 0x5e 0x00 0x78 + # CHECK: stc %r0, 0 0x42 0x00 0x00 0x00 @@ -6169,6 +6817,36 @@ # CHECK: stc %r15, 0 0x42 0xf0 0x00 0x00 +# CHECK: stch %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xc3 + +# CHECK: stch %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xc3 + +# CHECK: stch %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xc3 + +# CHECK: stch %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xc3 + +# CHECK: stch %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xc3 + +# CHECK: stch %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xc3 + +# CHECK: stch %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xc3 + +# CHECK: stch %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xc3 + +# CHECK: stch %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xc3 + +# CHECK: stch %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xc3 + # CHECK: stcy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x72 @@ -6352,6 +7030,66 @@ # CHECK: sth %r15, 0 0x40 0xf0 0x00 0x00 +# CHECK: sthh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xc7 + +# CHECK: sthh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xc7 + +# CHECK: sthh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xc7 + +# CHECK: sthh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xc7 + +# CHECK: sthh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xc7 + +# CHECK: sthh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xc7 + +# CHECK: sthh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xc7 + +# CHECK: sthh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xc7 + +# CHECK: sthh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xc7 + +# CHECK: sthh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xc7 + +# CHECK: stfh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0xcb + +# CHECK: stfh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0xcb + +# CHECK: stfh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0xcb + +# CHECK: stfh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0xcb + +# CHECK: stfh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0xcb + +# CHECK: stfh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0xcb + +# CHECK: stfh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0xcb + +# CHECK: stfh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0xcb + +# CHECK: stfh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0xcb + +# CHECK: stfh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0xcb + # CHECK: sthy %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x70 @@ -6691,6 +7429,141 @@ # CHECK: sy %r15, 0 0xe3 0xf0 0x00 0x00 0x00 0x5b +# CHECK: tm 0, 0 +0x91 0x00 0x00 0x00 + +# CHECK: tm 4095, 0 +0x91 0x00 0x0f 0xff + +# CHECK: tm 0, 255 +0x91 0xff 0x00 0x00 + +# CHECK: tm 0(%r1), 42 +0x91 0x2a 0x10 0x00 + +# CHECK: tm 0(%r15), 42 +0x91 0x2a 0xf0 0x00 + +# CHECK: tm 4095(%r1), 42 +0x91 0x2a 0x1f 0xff + +# CHECK: tm 4095(%r15), 42 +0x91 0x2a 0xff 0xff + +# CHECK: tmhh %r0, 0 +0xa7 0x02 0x00 0x00 + +# CHECK: tmhh %r0, 32768 +0xa7 0x02 0x80 0x00 + +# CHECK: tmhh %r0, 65535 +0xa7 0x02 0xff 0xff + +# CHECK: tmhh %r15, 0 +0xa7 0xf2 0x00 0x00 + +# CHECK: tmhl %r0, 0 +0xa7 0x03 0x00 0x00 + +# CHECK: tmhl %r0, 32768 +0xa7 0x03 0x80 0x00 + +# CHECK: tmhl %r0, 65535 +0xa7 0x03 0xff 0xff + +# CHECK: tmhl %r15, 0 +0xa7 0xf3 0x00 0x00 + +# CHECK: tmlh %r0, 0 +0xa7 0x00 0x00 0x00 + +# CHECK: tmlh %r0, 32768 +0xa7 0x00 0x80 0x00 + +# CHECK: tmlh %r0, 65535 +0xa7 0x00 0xff 0xff + +# CHECK: tmlh %r15, 0 +0xa7 0xf0 0x00 0x00 + +# CHECK: tmll %r0, 0 +0xa7 0x01 0x00 0x00 + +# CHECK: tmll %r0, 32768 +0xa7 0x01 0x80 0x00 + +# CHECK: tmll %r0, 65535 +0xa7 0x01 0xff 0xff + +# CHECK: tmll %r15, 0 +0xa7 0xf1 0x00 0x00 + +# CHECK: tmy -524288, 0 +0xeb 0x00 0x00 0x00 0x80 0x51 + +# CHECK: tmy -1, 0 +0xeb 0x00 0x0f 0xff 0xff 0x51 + +# CHECK: tmy 0, 0 +0xeb 0x00 0x00 0x00 0x00 0x51 + +# CHECK: tmy 1, 0 +0xeb 0x00 0x00 0x01 0x00 0x51 + +# CHECK: tmy 524287, 0 +0xeb 0x00 0x0f 0xff 0x7f 0x51 + +# CHECK: tmy 0, 255 +0xeb 0xff 0x00 0x00 0x00 0x51 + +# CHECK: tmy 0(%r1), 42 +0xeb 0x2a 0x10 0x00 0x00 0x51 + +# CHECK: tmy 0(%r15), 42 +0xeb 0x2a 0xf0 0x00 0x00 0x51 + +# CHECK: tmy 524287(%r1), 42 +0xeb 0x2a 0x1f 0xff 0x7f 0x51 + +# CHECK: tmy 524287(%r15), 42 +0xeb 0x2a 0xff 0xff 0x7f 0x51 + +# CHECK: xc 0(1), 0 +0xd7 0x00 0x00 0x00 0x00 0x00 + +# CHECK: xc 0(1), 0(%r1) +0xd7 0x00 0x00 0x00 0x10 0x00 + +# CHECK: xc 0(1), 0(%r15) +0xd7 0x00 0x00 0x00 0xf0 0x00 + +# CHECK: xc 0(1), 4095 +0xd7 0x00 0x00 0x00 0x0f 0xff + +# CHECK: xc 0(1), 4095(%r1) +0xd7 0x00 0x00 0x00 0x1f 0xff + +# CHECK: xc 0(1), 4095(%r15) +0xd7 0x00 0x00 0x00 0xff 0xff + +# CHECK: xc 0(1,%r1), 0 +0xd7 0x00 0x10 0x00 0x00 0x00 + +# CHECK: xc 0(1,%r15), 0 +0xd7 0x00 0xf0 0x00 0x00 0x00 + +# CHECK: xc 4095(1,%r1), 0 +0xd7 0x00 0x1f 0xff 0x00 0x00 + +# CHECK: xc 4095(1,%r15), 0 +0xd7 0x00 0xff 0xff 0x00 0x00 + +# CHECK: xc 0(256,%r1), 0 +0xd7 0xff 0x10 0x00 0x00 0x00 + +# CHECK: xc 0(256,%r15), 0 +0xd7 0xff 0xf0 0x00 0x00 0x00 + # CHECK: xgr %r0, %r0 0xb9 0x82 0x00 0x00 diff --git a/test/MC/Disassembler/SystemZ/lit.local.cfg b/test/MC/Disassembler/SystemZ/lit.local.cfg index 1da00ea..b12af09 100644 --- a/test/MC/Disassembler/SystemZ/lit.local.cfg +++ b/test/MC/Disassembler/SystemZ/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.txt'] - targets = set(config.root.targets_to_build.split()) if not 'SystemZ' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/X86/intel-syntax-32.txt b/test/MC/Disassembler/X86/intel-syntax-32.txt index 08bae6e..2298823 100644 --- a/test/MC/Disassembler/X86/intel-syntax-32.txt +++ b/test/MC/Disassembler/X86/intel-syntax-32.txt @@ -1,13 +1,31 @@ # RUN: llvm-mc --disassemble %s -triple=i386 --output-asm-variant=1 | FileCheck %s -# CHECK: sgdt +# CHECK: sgdt opaque ptr [eax] 0x0f 0x01 0x00 -# CHECK: sidt +# CHECK: sidt opaque ptr [eax] 0x0f 0x01 0x08 -# CHECK: lgdt +# CHECK: lgdt opaque ptr [eax] 0x0f 0x01 0x10 -# CHECK: lidt +# CHECK: lidt opaque ptr [eax] 0x0f 0x01 0x18 + +# CHECK: mov al, byte ptr [878082192] +0xa0 0x90 0x78 0x56 0x34 + +# CHECK: mov ax, word ptr [878082192] +0x66 0xa1 0x90 0x78 0x56 0x34 + +# CHECK: mov eax, dword ptr [878082192] +0xa1 0x90 0x78 0x56 0x34 + +# CHECK: mov byte ptr [878082192], al +0xa2 0x90 0x78 0x56 0x34 + +# CHECK: mov word ptr [878082192], ax +0x66 0xa3 0x90 0x78 0x56 0x34 + +# CHECK: mov dword ptr [878082192], eax +0xa3 0x90 0x78 0x56 0x34 diff --git a/test/MC/Disassembler/X86/intel-syntax.txt b/test/MC/Disassembler/X86/intel-syntax.txt index 6c0c239..3689525 100644 --- a/test/MC/Disassembler/X86/intel-syntax.txt +++ b/test/MC/Disassembler/X86/intel-syntax.txt @@ -105,6 +105,9 @@ # CHECK: retf 0x66 0xcb +# CHECK: vshufpd xmm0, xmm1, xmm2, 1 +0xc5 0xf1 0xc6 0xc2 0x01 + # CHECK: vpgatherqq ymm2, qword ptr [rdi + 2*ymm1], ymm0 0xc4 0xe2 0xfd 0x91 0x14 0x4f @@ -119,3 +122,33 @@ # CHECK: xsaveopt64 opaque ptr [rax] 0x48 0x0f 0xae 0x30 + +# CHECK: movabs al, byte ptr [-6066930261531658096] +0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs al, byte ptr [-6066930261531658096] +0x48 0xa0 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs ax, word ptr [-6066930261531658096] +0x66 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs eax, dword ptr [-6066930261531658096] +0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs rax, qword ptr [-6066930261531658096] +0x48 0xa1 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs byte ptr [-6066930261531658096], al +0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs byte ptr [-6066930261531658096], al +0x48 0xa2 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs word ptr [-6066930261531658096], ax +0x66 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs dword ptr [-6066930261531658096], eax +0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: movabs qword ptr [-6066930261531658096], rax +0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab diff --git a/test/MC/Disassembler/X86/lit.local.cfg b/test/MC/Disassembler/X86/lit.local.cfg index 6211b3e..ba763cf 100644 --- a/test/MC/Disassembler/X86/lit.local.cfg +++ b/test/MC/Disassembler/X86/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.txt'] - targets = set(config.root.targets_to_build.split()) if not 'X86' in targets: config.unsupported = True diff --git a/test/MC/Disassembler/X86/prefixes.txt b/test/MC/Disassembler/X86/prefixes.txt new file mode 100644 index 0000000..56596e3 --- /dev/null +++ b/test/MC/Disassembler/X86/prefixes.txt @@ -0,0 +1,59 @@ +# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s + +# CHECK: lock +# CHECK-NEXT: orl $16, %fs:776 +0xf0 0x64 0x83 0x0c 0x25 0x08 0x03 0x00 0x00 0x10 + +# CHECK: movq %fs:768, %rdi +0x64 0x48 0x8b 0x3c 0x25 0x00 0x03 0x00 0x00 + +# CHECK: rep +# CHECK-NEXT: stosq +0xf3 0x48 0xab + +# CHECK: rep +# CHECK-NEXT: stosl +0xf3 0x67 0x48 0xab + +# CHECK: movl 32(%rbp), %eax +0x8b 0x45 0x20 + +# CHECK: movl %es:32(%rbp), %eax +0x26 0x8b 0x45 0x20 + +# CHECK: movl %es:32(%rbp), %eax +0x2e 0x26 0x8b 0x45 0x20 + +# Test that multiple prefixes stack. +# (todo- the correct disassembly is actually more like "es movl %cs:32(%rbp), %eax" +# but we don't support that) +# CHECK: movl %cs:32(%rbp), %eax +0x26 0x2e 0x8b 0x45 0x20 + +# Test that 0xf3 as part of the opcode works. +# CHECK: cvtdq2pd (%rax), %xmm0 +0xf3 0x0f 0xe6 0x00 + +# CHECK: pause +0xf3 0x90 + +# CHECK: nop +0x90 + +# CHECK: lock +# CHECK-NEXT: nop +0xf0 0x90 + +# Test that multiple redundant prefixes work (redundant, but valid x86). +# CHECK: rep +# CHECK-NEXT: rep +# CHECK-NEXT: stosq +0xf3 0xf3 0x48 0xab + +# Test that a prefix on it's own works. It's debatable as to if this is +# something that is considered valid, but however as LLVM's own disassembler +# has decided to disassemble prefixes as being separate opcodes, it therefore +# should be capable of re-consuming it's own output. +# CHECK: rep +0xf3 +# ***IMPORTANT ^-- this must be at the end of the file to be a valid test *** diff --git a/test/MC/Disassembler/X86/simple-tests.txt b/test/MC/Disassembler/X86/simple-tests.txt index 940b1f7..7ca0874 100644 --- a/test/MC/Disassembler/X86/simple-tests.txt +++ b/test/MC/Disassembler/X86/simple-tests.txt @@ -129,6 +129,9 @@ # CHECK: vcvtsd2si %xmm0, %rax 0xc4 0xe1 0xfb 0x2d 0xc0 +# CHECK: vcvtsd2si %xmm0, %rax +0xc4 0xe1 0xff 0x2d 0xc0 + # CHECK: vmaskmovpd %xmm0, %xmm1, (%rax) 0xc4 0xe2 0x71 0x2f 0x00 @@ -260,6 +263,9 @@ # CHECK: vmovups %ymm0, %ymm1 0xc5 0xfc 0x11 0xc1 +# CHECK: vmovups %ymm0, %ymm1 +0xc4 0xe1 0xfc 0x11 0xc1 + # CHECK: vmovaps %ymm1, %ymm0 0xc5 0xfc 0x28 0xc1 @@ -722,9 +728,66 @@ # CHECK: vfmaddss %xmm1, (%rcx), %xmm0, %xmm0 0xc4 0xe3 0x79 0x6a 0x01 0x10 +# CHECK: vfmaddss (%rcx), %xmm1, %xmm0, %xmm0 +0xc4 0xe3 0xfd 0x6a 0x01 0x10 + +# CHECK: vfmaddss %xmm1, (%rcx), %xmm0, %xmm0 +0xc4 0xe3 0x7d 0x6a 0x01 0x10 + +# CHECK: vfmaddss %xmm2, %xmm1, %xmm0, %xmm0 +0xc4 0xe3 0xf9 0x6a 0xc2 0x10 + +# CHECK: vfmaddss %xmm1, %xmm2, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x6a 0xc2 0x10 + +# CHECK: vfmaddss %xmm2, %xmm1, %xmm0, %xmm0 +0xc4 0xe3 0xfd 0x6a 0xc2 0x10 + +# CHECK: vfmaddss %xmm1, %xmm2, %xmm0, %xmm0 +0xc4 0xe3 0x7d 0x6a 0xc2 0x10 + +# CHECK: vfmaddps (%rcx), %xmm1, %xmm0, %xmm0 +0xc4 0xe3 0xf9 0x68 0x01 0x10 + +# CHECK: vfmaddps %xmm1, (%rcx), %xmm0, %xmm0 +0xc4 0xe3 0x79 0x68 0x01 0x10 + +# CHECK: vfmaddps %xmm1, %xmm2, %xmm0, %xmm0 +0xc4 0xe3 0x79 0x68 0xc2 0x10 + +# CHECK: vfmaddps %xmm2, %xmm1, %xmm0, %xmm0 +0xc4 0xe3 0xf9 0x68 0xc2 0x10 + +# CHECK: vfmaddps (%rcx), %ymm1, %ymm0, %ymm0 +0xc4 0xe3 0xfd 0x68 0x01 0x10 + +# CHECK: vfmaddps %ymm1, (%rcx), %ymm0, %ymm0 +0xc4 0xe3 0x7d 0x68 0x01 0x10 + +# CHECK: vfmaddps %ymm1, %ymm2, %ymm0, %ymm0 +0xc4 0xe3 0x7d 0x68 0xc2 0x10 + +# CHECK: vfmaddps %ymm2, %ymm1, %ymm0, %ymm0 +0xc4 0xe3 0xfd 0x68 0xc2 0x10 + +# CHECK: vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1 +0xc4 0xe3 0x69 0x48 0xcb 0x40 + # CHECK: vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0 0xc4 0xe3 0xe1 0x48 0x40 0x04 0x21 +# CHECK: vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6 +0xc4 0xe3 0xd5 0x48 0x30 0x12 + +# CHECK: vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4 +0xc4 0xe3 0x61 0x48 0x20 0x13 + +# CHECK: vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2 +0xc4 0xe3 0x6d 0x48 0xd4 0x40 + +# CHECK: vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0 +0xc4 0xe3 0x75 0x49 0x40 0x04 0x11 + # CHECK: vgatherdpd %xmm0, (%rdi,%xmm1,2), %xmm2 0xc4 0xe2 0xf9 0x92 0x14 0x4f @@ -796,3 +859,60 @@ # CHECK: xacquire # CHECK-NEXT: xchgl %ebx, (%rax) 0xf2 0x87 0x18 + +# CHECK: bextr $2814, %edi, %eax +0x8f 0xea 0x78 0x10 0xc7 0xfe 0x0a 0x00 0x00 + +# CHECK: blci %rdi, %rax +0x8f 0xe9 0xf8 0x02 0xf7 + +# CHECK: vpcmov %xmm1, %xmm2, %xmm3, %xmm4 +0x8f 0xe8 0x60 0xa2 0xe2 0x10 + +# CHECK: vpcmov (%rax), %xmm2, %xmm3, %xmm4 +0x8f 0xe8 0xe0 0xa2 0x20 0x20 + +# CHECK: vpcmov %xmm1, (%rax), %xmm3, %xmm4 +0x8f 0xe8 0x60 0xa2 0x20 0x10 + +# CHECK: vpcmov %ymm1, %ymm2, %ymm3, %ymm4 +0x8f 0xe8 0x64 0xa2 0xe2 0x10 + +# CHECK: vpcmov (%rax), %ymm2, %ymm3, %ymm4 +0x8f 0xe8 0xe4 0xa2 0x20 0x20 + +# CHECK: vpcmov %ymm1, (%rax), %ymm3, %ymm4 +0x8f 0xe8 0x64 0xa2 0x20 0x10 + +# CHECK: vpcomb $55, %xmm6, %xmm4, %xmm2 +0x8f 0xe8 0x58 0xcc 0xd6 0x37 + +# CHECK: vpcomb $56, 8(%rax), %xmm3, %xmm2 +0x8f 0xe8 0x60 0xcc 0x50 0x08 0x38 + +# CHECK: vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2 +0x8f 0xe8 0x58 0x9e 0xd6 0x40 +# CHECK: vpmacsdd %xmm4, (%rax,%rcx), %xmm4, %xmm3 +0x8f 0xe8 0x58 0x9e 0x1c 0x08 0x40 + +# CHECK: vprotd (%rax), %xmm0, %xmm3 +0x8f 0xe9 0xf8 0x92 0x18 +# CHECK: vprotd %xmm2, (%rax,%rcx), %xmm4 +0x8f 0xe9 0x68 0x92 0x24 0x08 +# CHECK: vprotd %xmm5, %xmm3, %xmm2 +0x8f 0xe9 0x50 0x92 0xd3 +# CHECK: vprotd $43, (%rcx), %xmm6 +0x8f 0xe8 0x78 0xc2 0x31 0x2b +# CHECK: vprotd $44, (%rax,%rcx), %xmm7 +0x8f 0xe8 0x78 0xc2 0x3c 0x08 0x2c +# CHECK: vprotd $45, %xmm4, %xmm4 +0x8f 0xe8 0x78 0xc2 0xe4 0x2d + +# CHECK: vfrczps 4(%rax), %xmm3 +0x8f 0xe9 0x78 0x80 0x58 0x04 +# CHECK: vfrczps %xmm6, %xmm5 +0x8f 0xe9 0x78 0x80 0xee +# CHECK: vfrczps (%rcx), %xmm1 +0x8f 0xe9 0x78 0x80 0x09 +# CHECK: vfrczps %ymm2, %ymm4 +0x8f 0xe9 0x7c 0x80 0xe2 diff --git a/test/MC/Disassembler/X86/x86-32.txt b/test/MC/Disassembler/X86/x86-32.txt index 76d67d3..b6a62c4 100644 --- a/test/MC/Disassembler/X86/x86-32.txt +++ b/test/MC/Disassembler/X86/x86-32.txt @@ -648,3 +648,51 @@ # CHECK: adoxl (%eax), %eax 0xf3 0x0f 0x38 0xf6 0x00 + +# CHECK: movb 878082192, %al +0xa0 0x90 0x78 0x56 0x34 + +# CHECK: movw 878082192, %ax +0x66 0xa1 0x90 0x78 0x56 0x34 + +# CHECK: movl 878082192, %eax +0xa1 0x90 0x78 0x56 0x34 + +# CHECK: movb %al, 878082192 +0xa2 0x90 0x78 0x56 0x34 + +# CHECK: movw %ax, 878082192 +0x66 0xa3 0x90 0x78 0x56 0x34 + +# CHECK: movl %eax, 878082192 +0xa3 0x90 0x78 0x56 0x34 + +# CHECK: incl %ecx +0xff 0xc1 + +# CHECK: decl %ecx +0xff 0xc9 + +# CHECK: incw %cx +0x66 0xff 0xc1 + +# CHECK: decw %cx +0x66 0xff 0xc9 + +# CHECK: incb %cl +0xfe 0xc1 + +# CHECK: decb %cl +0xfe 0xc9 + +# CHECK: incl %ecx +0x41 + +# CHECK: decl %ecx +0x49 + +# CHECK: movq %xmm0, %xmm0 +0xf3 0x0f 0x7e 0xc0 + +# CHECK: vmovq %xmm0, %xmm0 +0xc5 0xfa 0x7e 0xc0 diff --git a/test/MC/Disassembler/X86/x86-64.txt b/test/MC/Disassembler/X86/x86-64.txt index bf1fa21..8c6bc0e 100644 --- a/test/MC/Disassembler/X86/x86-64.txt +++ b/test/MC/Disassembler/X86/x86-64.txt @@ -157,3 +157,87 @@ # CHECK: movabsq %rax, -6066930261531658096 0x48 0xa3 0x90 0x78 0x56 0x34 0x12 0xef 0xcd 0xab + +# CHECK: sha1rnds4 $1, %xmm1, %xmm2 +0x0f 0x3a 0xcc 0xd1 0x01 + +# CHECK: sha1rnds4 $1, (%rax), %xmm2 +0x0f 0x3a 0xcc 0x10 0x01 + +# CHECK: sha1nexte %xmm1, %xmm2 +0x0f 0x38 0xc8 0xd1 + +# CHECK: sha1nexte (%rax), %xmm2 +0x0f 0x38 0xc8 0x10 + +# CHECK: sha1msg1 %xmm1, %xmm2 +0x0f 0x38 0xc9 0xd1 + +# CHECK: sha1msg1 (%rax), %xmm2 +0x0f 0x38 0xc9 0x10 + +# CHECK: sha1msg2 %xmm1, %xmm2 +0x0f 0x38 0xca 0xd1 + +# CHECK: sha1msg2 (%rax), %xmm2 +0x0f 0x38 0xca 0x10 + +# CHECK: sha256rnds2 (%rax), %xmm2 +0x0f 0x38 0xcb 0x10 + +# CHECK: sha256rnds2 %xmm1, %xmm2 +0x0f 0x38 0xcb 0xd1 + +# CHECK: sha256msg1 %xmm1, %xmm2 +0x0f 0x38 0xcc 0xd1 + +# CHECK: sha256msg1 (%rax), %xmm2 +0x0f 0x38 0xcc 0x10 + +# CHECK: sha256msg2 %xmm1, %xmm2 +0x0f 0x38 0xcd 0xd1 + +# CHECK: sha256msg2 (%rax), %xmm2 +0x0f 0x38 0xcd 0x10 + +# CHECK: incl %ecx +0xff 0xc1 + +# CHECK: decl %ecx +0xff 0xc9 + +# CHECK: incw %cx +0x66 0xff 0xc1 + +# CHECK: decw %cx +0x66 0xff 0xc9 + +# CHECK: incb %cl +0xfe 0xc1 + +# CHECK: decb %cl +0xfe 0xc9 + +# CHECK: incq %rcx +0x48 0xff 0xc1 + +# CHECK: decq %rcx +0x48 0xff 0xc9 + +# CHECK: movq %xmm0, %xmm0 +0xf3 0x0f 0x7e 0xc0 + +# CHECK: vmovq %xmm0, %xmm0 +0xc5 0xfa 0x7e 0xc0 + +# CHECK: vmovq %xmm0, %rax +0xc4 0xe1 0xf9 0x7e 0xc0 + +# CHECK: movd %xmm0, %rax +0x66 0x48 0x0f 0x7e 0xc0 + +# CHECK: pextrw $3, %xmm3, %ecx +0x66 0x0f 0x3a 0x15 0xd9 0x03 + +# CHECK: pextrw $3, %xmm3, (%rax) +0x66 0x0f 0x3a 0x15 0x18 0x03 diff --git a/test/MC/Disassembler/XCore/lit.local.cfg b/test/MC/Disassembler/XCore/lit.local.cfg index 15b6583..4d17d46 100644 --- a/test/MC/Disassembler/XCore/lit.local.cfg +++ b/test/MC/Disassembler/XCore/lit.local.cfg @@ -1,5 +1,3 @@ -config.suffixes = ['.txt'] - targets = set(config.root.targets_to_build.split()) if not 'XCore' in targets: config.unsupported = True |