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-rw-r--r--test/MC/Mips/mips-fpu-instructions.s25
1 files changed, 22 insertions, 3 deletions
diff --git a/test/MC/Mips/mips-fpu-instructions.s b/test/MC/Mips/mips-fpu-instructions.s
index dc52676..bfaef9e 100644
--- a/test/MC/Mips/mips-fpu-instructions.s
+++ b/test/MC/Mips/mips-fpu-instructions.s
@@ -1,4 +1,5 @@
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | FileCheck %s
+# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | FileCheck %s
# Check that the assembler can handle the documented syntax
# for FPU instructions.
#------------------------------------------------------------------------------
@@ -137,6 +138,8 @@
#------------------------------------------------------------------------------
# FP move instructions
#------------------------------------------------------------------------------
+# CHECK: bc1f $BB_1 # encoding: [A,A,0x00,0x45]
+# CHECK: # fixup A - offset: 0, value: ($BB_1), kind: fixup_Mips_PC16
# CHECK: cfc1 $6, $0 # encoding: [0x00,0x00,0x46,0x44]
# CHECK: ctc1 $10, $31 # encoding: [0x00,0xf8,0xca,0x44]
@@ -164,7 +167,15 @@
# CHECK: movf.s $f4, $f6, $fcc5 # encoding: [0x11,0x31,0x14,0x46]
# CHECK: luxc1 $f0, $6($5) # encoding: [0x05,0x00,0xa6,0x4c]
# CHECK: suxc1 $f4, $24($5) # encoding: [0x0d,0x20,0xb8,0x4c]
-
+# CHECK: lwxc1 $f20, $12($14) # encoding: [0x00,0x05,0xcc,0x4d]
+# CHECK: swxc1 $f26, $18($22) # encoding: [0x08,0xd0,0xd2,0x4e]
+# CHECK: mfhc1 $17, $f4 # encoding: [0x00,0x20,0x71,0x44]
+# CHECK: mthc1 $17, $f6 # encoding: [0x00,0x30,0xf1,0x44]
+# CHECK: swc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xeb]
+# CHECK: sdc2 $4, 16($sp) # encoding: [0x10,0x00,0xa4,0xfb]
+# CHECK: lwc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xcb]
+# CHECK: ldc2 $11, 12($ra) # encoding: [0x0c,0x00,0xeb,0xdb]
+ bc1f $fcc0, $BB_1
cfc1 $a2,$0
ctc1 $10,$31
mfc1 $a2,$f7
@@ -189,5 +200,13 @@
movt $4, $5, $fcc4
movf.d $f4, $f6, $fcc2
movf.s $f4, $f6, $fcc5
- luxc1 $f0, $a2($a1)
- suxc1 $f4, $t8($a1) \ No newline at end of file
+ luxc1 $f0, $a2($a1)
+ suxc1 $f4, $t8($a1)
+ lwxc1 $f20, $12($14)
+ swxc1 $f26, $s2($s6)
+ mfhc1 $17, $f4
+ mthc1 $17, $f6
+ swc2 $4, 16($sp)
+ sdc2 $4, 16($sp)
+ lwc2 $11, 12($ra)
+ ldc2 $11, 12($ra)