aboutsummaryrefslogtreecommitdiffstats
path: root/test/MC/Mips/mips32r6/invalid-mips1.s
diff options
context:
space:
mode:
Diffstat (limited to 'test/MC/Mips/mips32r6/invalid-mips1.s')
-rw-r--r--test/MC/Mips/mips32r6/invalid-mips1.s4
1 files changed, 4 insertions, 0 deletions
diff --git a/test/MC/Mips/mips32r6/invalid-mips1.s b/test/MC/Mips/mips32r6/invalid-mips1.s
index 44d4fbb..94810f4 100644
--- a/test/MC/Mips/mips32r6/invalid-mips1.s
+++ b/test/MC/Mips/mips32r6/invalid-mips1.s
@@ -5,6 +5,8 @@
# RUN: FileCheck %s < %t1
.set noat
+ add $9,$14,15176 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ add $24,-7193 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
addi $13,$9,26322 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.ngl.d $f29,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
c.ngle.d $f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
@@ -22,3 +24,5 @@
multu $gp,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
# div has been re-encoded. See valid.s
# divu has been re-encoded. See valid.s
+ sub $22,$17,-3126 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+ sub $13,6512 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled