diff options
Diffstat (limited to 'test/MC/Mips')
67 files changed, 3076 insertions, 119 deletions
diff --git a/test/MC/Mips/cpload.s b/test/MC/Mips/cpload.s index 46b3ee4..842e0c7 100644 --- a/test/MC/Mips/cpload.s +++ b/test/MC/Mips/cpload.s @@ -4,7 +4,7 @@ # RUN: llvm-objdump -d -r -arch=mips - | \ # RUN: FileCheck %s -check-prefix=OBJ-O32 -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=-n64,+n32 -filetype=obj -o -| \ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -target-abi n32 -filetype=obj -o -| \ # RUN: llvm-objdump -d -r -arch=mips - | \ # RUN: FileCheck %s -check-prefix=OBJ-N32 diff --git a/test/MC/Mips/cpsetup-bad.s b/test/MC/Mips/cpsetup-bad.s index 09252a1..ec6525a 100644 --- a/test/MC/Mips/cpsetup-bad.s +++ b/test/MC/Mips/cpsetup-bad.s @@ -12,3 +12,11 @@ t1: # ASM: :[[@LINE-1]]:23: error: expected save register or stack offset .cpsetup $31, $32, __cerror # ASM: :[[@LINE-1]]:23: error: invalid register + .cpsetup $25, $2, $3 +# ASM: :[[@LINE-1]]:28: error: expected expression + .cpsetup $25, $2, 4 +# ASM: :[[@LINE-1]]:28: error: expected symbol + .cpsetup $25, $2, 4+65 +# ASM: :[[@LINE-1]]:31: error: expected symbol + .cpsetup $25, $2, foo+4 +# ASM: :[[@LINE-1]]:32: error: expected symbol diff --git a/test/MC/Mips/cpsetup.s b/test/MC/Mips/cpsetup.s index a21a1e3..a3ffae6 100644 --- a/test/MC/Mips/cpsetup.s +++ b/test/MC/Mips/cpsetup.s @@ -1,19 +1,19 @@ -# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 -filetype=obj -o - %s | \ +# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi o32 -filetype=obj -o - %s | \ # RUN: llvm-objdump -d -r -arch=mips64 - | \ # RUN: FileCheck -check-prefix=O32 %s -# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+o32 %s | \ +# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi o32 %s | \ # RUN: FileCheck -check-prefix=ASM %s -# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 -filetype=obj -o - %s | \ -# RUN: llvm-objdump -d -r -arch=mips64 - | \ +# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi n32 -filetype=obj -o - %s | \ +# RUN: llvm-objdump -d -r -t -arch=mips64 - | \ # RUN: FileCheck -check-prefix=NXX -check-prefix=N32 %s -# RUN: llvm-mc -triple mips64-unknown-unknown -mattr=-n64,+n32 %s | \ +# RUN: llvm-mc -triple mips64-unknown-unknown -target-abi n32 %s | \ # RUN: FileCheck -check-prefix=ASM %s # RUN: llvm-mc -triple mips64-unknown-unknown %s -filetype=obj -o - | \ -# RUN: llvm-objdump -d -r -arch=mips64 - | \ +# RUN: llvm-objdump -d -r -t -arch=mips64 - | \ # RUN: FileCheck -check-prefix=NXX -check-prefix=N64 %s # RUN: llvm-mc -triple mips64-unknown-unknown %s | \ @@ -61,6 +61,35 @@ t2: # ASM: .cpsetup $25, $2, __cerror +# .cpsetup with local labels (PR22518): +1: + .cpsetup $25, $2, 1b + nop + sub $3, $3, $2 + nop + +# O32: t2: +# O32: nop +# O32: sub $3, $3, $2 +# O32: nop + +# FIXME: Direct object emission for N32 is still under development. +# N32 doesn't allow 3 operations to be specified in the same relocation +# record like N64 does. + +# NXX: move $2, $gp +# NXX: lui $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_HI16 $tmp0 +# NXX: addiu $gp, $gp, 0 +# NXX: R_MIPS_GPREL16/R_MIPS_SUB/R_MIPS_LO16 $tmp0 +# N32: addu $gp, $gp, $25 +# N64: daddu $gp, $gp, $25 +# NXX: nop +# NXX: sub $3, $3, $2 +# NXX: nop + +# ASM: .cpsetup $25, $2, $tmp0 + t3: .option pic0 nop @@ -76,3 +105,7 @@ t3: # ASM: nop # ASM: .cpsetup $25, 8, __cerror # ASM: nop + +# For .cpsetup with local labels, we need to check if $tmp0 is in the symbol +# table: +# NXX: .text 00000000 $tmp0 diff --git a/test/MC/Mips/do_switch3.s b/test/MC/Mips/do_switch3.s index 02ad087..c0d9dc6 100644 --- a/test/MC/Mips/do_switch3.s +++ b/test/MC/Mips/do_switch3.s @@ -2,7 +2,7 @@ // produced. This was not handled for direct object and an assertion // to occur. This is a variation on test case test/CodeGen/Mips/do_switch.ll -// RUN: llvm-mc < %s -filetype=obj -triple=mips64-pc-linux -relocation-model=pic -mcpu=mips64 -mattr=n64 +// RUN: llvm-mc < %s -filetype=obj -triple=mips64-pc-linux -relocation-model=pic -mcpu=mips64 -target-abi=n64 .text .abicalls diff --git a/test/MC/Mips/elf_eflags.s b/test/MC/Mips/elf_eflags.s index 1f28ee0..708894f 100644 --- a/test/MC/Mips/elf_eflags.s +++ b/test/MC/Mips/elf_eflags.s @@ -8,9 +8,13 @@ # MIPSEL-MIPS64R6-NAN2008: Flags [ (0xA0000406) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r3 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2 %s # MIPSEL-MIPS64R2: Flags [ (0x80000006) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r3 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r5 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64R2-NAN2008 %s # MIPSEL-MIPS64R2-NAN2008: Flags [ (0x80000406) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS64 %s @@ -26,9 +30,13 @@ # MIPSEL-MIPS32R6-NAN2008: Flags [ (0x90001404) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r3 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2 %s # MIPSEL-MIPS32R2: Flags [ (0x70001004) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r2 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r3 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32r5 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32R2-NAN2008 %s # MIPSEL-MIPS32R2-NAN2008: Flags [ (0x70001404) # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32 %s @@ -37,35 +45,35 @@ # RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPSEL-MIPS32-NAN2008 %s # MIPSEL-MIPS32-NAN2008: Flags [ (0x50001404) -# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s +# RUN: llvm-mc -filetype=obj -triple mipsel-unknown-linux -mcpu=mips64r2 -target-abi n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32 %s # MIPS64EL-MIPS64R2-N32: Flags [ (0x80000024) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi n32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N32-NAN2008 %s # MIPS64EL-MIPS64R2-N32-NAN2008: Flags [ (0x80000424) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -target-abi n32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32 %s # MIPS64EL-MIPS64-N32: Flags [ (0x60000024) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -mattr=-n64,n32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 -target-abi n32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N32-NAN2008 %s # MIPS64EL-MIPS64-N32-NAN2008: Flags [ (0x60000424) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi n64 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64 %s # MIPS64EL-MIPS64R2-N64: Flags [ (0x80000006) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=n64,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi n64 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-N64-NAN2008 %s # MIPS64EL-MIPS64R2-N64-NAN2008: Flags [ (0x80000406) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -target-abi n64 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64 %s # MIPS64EL-MIPS64-N64: Flags [ (0x60000006) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=n64,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -target-abi n64 -mattr=+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-N64-NAN2008 %s # MIPS64EL-MIPS64-N64-NAN2008: Flags [ (0x60000406) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi o32 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32 %s # MIPS64EL-MIPS64R2-O32: Flags [ (0x80001104) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -mattr=-n64,o32,+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64r2 -target-abi o32 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64R2-O32-NAN2008 %s # MIPS64EL-MIPS64R2-O32-NAN2008: Flags [ (0x80001504) # RUN: llvm-mc -filetype=obj -triple mips64-unknown-linux -mcpu=mips5 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS5 %s @@ -98,10 +106,10 @@ # RUN: llvm-mc -filetype=obj -triple mips-unknown-linux -mcpu=mips1 -mattr=+nan2008 %s -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS1-NAN2008 %s # MIPS1-NAN2008: Flags [ (0x1404) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -target-abi o32 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32 %s # MIPS64EL-MIPS64-O32: Flags [ (0x60001104) -# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -mattr=-n64,o32,+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32-NAN2008 %s +# RUN: llvm-mc -filetype=obj -triple mips64el-unknown-linux -mcpu=mips64 %s -target-abi o32 -mattr=+nan2008 -o -| llvm-readobj -h | FileCheck --check-prefix=MIPS64EL-MIPS64-O32-NAN2008 %s # MIPS64EL-MIPS64-O32-NAN2008: Flags [ (0x60001504) # Default ABI for MIPS64 is N64 as opposed to GCC/GAS (N32) diff --git a/test/MC/Mips/elf_reginfo.s b/test/MC/Mips/elf_reginfo.s index ba4788a..8a4ed3b 100644 --- a/test/MC/Mips/elf_reginfo.s +++ b/test/MC/Mips/elf_reginfo.s @@ -1,9 +1,9 @@ # These *MUST* match the output of gas compiled with the same triple and # corresponding options (-mabi=64 -> -mattr=+n64 for example). -# RUN: llvm-mc -filetype=obj -triple=mips64el-linux -mattr=-n64,+n64 %s -o - \ +# RUN: llvm-mc -filetype=obj -triple=mips64el-linux -target-abi n64 %s -o - \ # RUN: | llvm-readobj -s | FileCheck --check-prefix=CHECK_64 %s -# RUN: llvm-mc -filetype=obj -triple=mipsel %s -mattr=-o32,+n32 -o - \ +# RUN: llvm-mc -filetype=obj -triple=mipsel %s -target-abi n32 -o - \ # RUN: | llvm-readobj -s | FileCheck --check-prefix=CHECK_32 %s # Check for register information sections. diff --git a/test/MC/Mips/micromips-16-bit-instructions.s b/test/MC/Mips/micromips-16-bit-instructions.s index 35855e1..25fbfdb 100644 --- a/test/MC/Mips/micromips-16-bit-instructions.s +++ b/test/MC/Mips/micromips-16-bit-instructions.s @@ -18,24 +18,49 @@ # CHECK-EL: xor16 $17, $5 # encoding: [0x4d,0x44] # CHECK-EL: sll16 $3, $16, 5 # encoding: [0x8a,0x25] # CHECK-EL: srl16 $4, $17, 6 # encoding: [0x1d,0x26] +# CHECK-EL: lbu16 $3, 4($17) # encoding: [0x94,0x09] +# CHECK-EL: lbu16 $3, -1($16) # encoding: [0x8f,0x09] +# CHECK-EL: lhu16 $3, 4($16) # encoding: [0x82,0x29] +# CHECK-EL: lw16 $4, 8($17) # encoding: [0x12,0x6a] +# CHECK-EL: sb16 $3, 4($16) # encoding: [0x84,0x89] +# CHECK-EL: sh16 $4, 8($17) # encoding: [0x14,0xaa] +# CHECK-EL: sw16 $4, 4($17) # encoding: [0x11,0xea] +# CHECK-EL: sw16 $zero, 4($17) # encoding: [0x11,0xe8] +# CHECK-EL: lw $3, 32($gp) # encoding: [0x88,0x65] +# CHECK-EL: lw $3, 32($sp) # encoding: [0x68,0x48] +# CHECK-EL: sw $4, 124($sp) # encoding: [0x9f,0xc8] # CHECK-EL: li16 $3, -1 # encoding: [0xff,0xed] # CHECK-EL: li16 $3, 126 # encoding: [0xfe,0xed] # CHECK-EL: addiur1sp $7, 4 # encoding: [0x83,0x6f] # CHECK-EL: addiur2 $6, $7, -1 # encoding: [0x7e,0x6f] # CHECK-EL: addiur2 $6, $7, 12 # encoding: [0x76,0x6f] # CHECK-EL: addius5 $7, -2 # encoding: [0xfc,0x4c] +# CHECK-EL: addiusp -1028 # encoding: [0xff,0x4f] +# CHECK-EL: addiusp -1032 # encoding: [0xfd,0x4f] +# CHECK-EL: addiusp 1024 # encoding: [0x01,0x4c] +# CHECK-EL: addiusp 1028 # encoding: [0x03,0x4c] # CHECK-EL: addiusp -16 # encoding: [0xf9,0x4f] # CHECK-EL: mfhi $9 # encoding: [0x09,0x46] # CHECK-EL: mflo $9 # encoding: [0x49,0x46] # CHECK-EL: move $25, $1 # encoding: [0x21,0x0f] +# CHECK-EL: movep $5, $6, $2, $3 # encoding: [0x34,0x84] # CHECK-EL: jrc $9 # encoding: [0xa9,0x45] # CHECK-NEXT: jalr $9 # encoding: [0xc9,0x45] # CHECK-EL: jraddiusp 20 # encoding: [0x05,0x47] -# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK-EL: jalrs16 $9 # encoding: [0xe9,0x45] -# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-NEXT: jalrs16 $9 # encoding: [0xe9,0x45] +# CHECK-EL: nop # encoding: [0x00,0x0c] # CHECK-EL: jr16 $9 # encoding: [0x89,0x45] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: beqz16 $6, 20 # encoding: [0x0a,0x8f] +# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: bnez16 $6, 20 # encoding: [0x0a,0xaf] +# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: b16 132 # encoding: [0x42,0xcc] +# CHECK-EL: nop +# CHECK-EL: b16 132 # encoding: [0x42,0xcc] +# CHECK-EL: nop +# CHECK-EL: break16 8 # encoding: [0x88,0x46] +# CHECK-EL: sdbbp16 14 # encoding: [0xce,0x46] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -48,24 +73,49 @@ # CHECK-EB: xor16 $17, $5 # encoding: [0x44,0x4d] # CHECK-EB: sll16 $3, $16, 5 # encoding: [0x25,0x8a] # CHECK-EB: srl16 $4, $17, 6 # encoding: [0x26,0x1d] +# CHECK-EB: lbu16 $3, 4($17) # encoding: [0x09,0x94] +# CHECK-EB: lbu16 $3, -1($16) # encoding: [0x09,0x8f] +# CHECK-EB: lhu16 $3, 4($16) # encoding: [0x29,0x82] +# CHECK-EB: lw16 $4, 8($17) # encoding: [0x6a,0x12] +# CHECK-EB: sb16 $3, 4($16) # encoding: [0x89,0x84] +# CHECK-EB: sh16 $4, 8($17) # encoding: [0xaa,0x14] +# CHECK-EB: sw16 $4, 4($17) # encoding: [0xea,0x11] +# CHECK-EB: sw16 $zero, 4($17) # encoding: [0xe8,0x11] +# CHECK-EB: lw $3, 32($gp) # encoding: [0x65,0x88] +# CHECK-EB: lw $3, 32($sp) # encoding: [0x48,0x68] +# CHECK-EB: sw $4, 124($sp) # encoding: [0xc8,0x9f] # CHECK-EB: li16 $3, -1 # encoding: [0xed,0xff] # CHECK-EB: li16 $3, 126 # encoding: [0xed,0xfe] # CHECK-EB: addiur1sp $7, 4 # encoding: [0x6f,0x83] # CHECK-EB: addiur2 $6, $7, -1 # encoding: [0x6f,0x7e] # CHECK-EB: addiur2 $6, $7, 12 # encoding: [0x6f,0x76] # CHECK-EB: addius5 $7, -2 # encoding: [0x4c,0xfc] +# CHECK-EB: addiusp -1028 # encoding: [0x4f,0xff] +# CHECK-EB: addiusp -1032 # encoding: [0x4f,0xfd] +# CHECK-EB: addiusp 1024 # encoding: [0x4c,0x01] +# CHECK-EB: addiusp 1028 # encoding: [0x4c,0x03] # CHECK-EB: addiusp -16 # encoding: [0x4f,0xf9] # CHECK-EB: mfhi $9 # encoding: [0x46,0x09] # CHECK-EB: mflo $9 # encoding: [0x46,0x49] # CHECK-EB: move $25, $1 # encoding: [0x0f,0x21] +# CHECK-EB: movep $5, $6, $2, $3 # encoding: [0x84,0x34] # CHECK-EB: jrc $9 # encoding: [0x45,0xa9] # CHECK-NEXT: jalr $9 # encoding: [0x45,0xc9] # CHECK-EB: jraddiusp 20 # encoding: [0x47,0x05] -# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] -# CHECK-EB: jalrs16 $9 # encoding: [0x45,0xe9] -# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-NEXT: jalrs16 $9 # encoding: [0x45,0xe9] +# CHECK-EB: nop # encoding: [0x0c,0x00] # CHECK-EB: jr16 $9 # encoding: [0x45,0x89] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: beqz16 $6, 20 # encoding: [0x8f,0x0a] +# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: bnez16 $6, 20 # encoding: [0xaf,0x0a] +# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: b16 132 # encoding: [0xcc,0x42] +# CHECK-EB: nop +# CHECK-EB: b16 132 # encoding: [0xcc,0x42] +# CHECK-EB: nop +# CHECK-EB: break16 8 # encoding: [0x46,0x88] +# CHECK-EB: sdbbp16 14 # encoding: [0x46,0xce] addu16 $6, $17, $4 subu16 $5, $16, $3 @@ -76,18 +126,40 @@ xor16 $17, $5 sll16 $3, $16, 5 srl16 $4, $17, 6 + lbu16 $3, 4($17) + lbu16 $3, -1($16) + lhu16 $3, 4($16) + lw16 $4, 8($17) + sb16 $3, 4($16) + sh16 $4, 8($17) + sw16 $4, 4($17) + sw16 $0, 4($17) + lw $3, 32($gp) + lw $3, 32($sp) + sw $4, 124($sp) li16 $3, -1 li16 $3, 126 addiur1sp $7, 4 addiur2 $6, $7, -1 addiur2 $6, $7, 12 addius5 $7, -2 + addiusp -1028 + addiusp -1032 + addiusp 1024 + addiusp 1028 addiusp -16 mfhi $9 mflo $9 move $25, $1 + movep $5, $6, $2, $3 jrc $9 jalr $9 jraddiusp 20 jalrs16 $9 jr16 $9 + beqz16 $6, 20 + bnez16 $6, 20 + b 132 + b16 132 + break16 8 + sdbbp16 14 diff --git a/test/MC/Mips/micromips-alu-instructions.s b/test/MC/Mips/micromips-alu-instructions.s index 1131d1f..aeab09e 100644 --- a/test/MC/Mips/micromips-alu-instructions.s +++ b/test/MC/Mips/micromips-alu-instructions.s @@ -38,6 +38,9 @@ # CHECK-EL: multu $9, $7 # encoding: [0xe9,0x00,0x3c,0x9b] # CHECK-EL: div $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xab] # CHECK-EL: divu $zero, $9, $7 # encoding: [0xe9,0x00,0x3c,0xbb] +# CHECK-EL: addiupc $2, 20 # encoding: [0x00,0x79,0x05,0x00] +# CHECK-EL: addiupc $7, 16777212 # encoding: [0xbf,0x7b,0xff,0xff] +# CHECK-EL: addiupc $7, -16777216 # encoding: [0xc0,0x7b,0x00,0x00] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -72,6 +75,9 @@ # CHECK-EB: multu $9, $7 # encoding: [0x00,0xe9,0x9b,0x3c] # CHECK-EB: div $zero, $9, $7 # encoding: [0x00,0xe9,0xab,0x3c] # CHECK-EB: divu $zero, $9, $7 # encoding: [0x00,0xe9,0xbb,0x3c] +# CHECK-EB: addiupc $2, 20 # encoding: [0x79,0x00,0x00,0x05] +# CHECK-EB: addiupc $7, 16777212 # encoding: [0x7b,0xbf,0xff,0xff] +# CHECK-EB: addiupc $7, -16777216 # encoding: [0x7b,0xc0,0x00,0x00] add $9, $6, $7 add $9, $6, 17767 addu $9, $6, -15001 @@ -104,3 +110,6 @@ multu $9, $7 div $0, $9, $7 divu $0, $9, $7 + addiupc $2, 20 + addiupc $7, 16777212 + addiupc $7, -16777216 diff --git a/test/MC/Mips/micromips-bad-branches.s b/test/MC/Mips/micromips-bad-branches.s index 573605e..f64cd9f 100644 --- a/test/MC/Mips/micromips-bad-branches.s +++ b/test/MC/Mips/micromips-bad-branches.s @@ -126,6 +126,11 @@ # CHECK: error: branch target out of range # CHECK: bc1t $fcc0, 65536 +# CHECK: error: branch to misaligned address +# CHECK: beqz16 $6, 31 +# CHECK: error: branch target out of range +# CHECK: beqz16 $6, 130 + b -65535 b -65536 b -65537 @@ -223,3 +228,6 @@ bc1t $fcc0, 65534 bc1t $fcc0, 65535 bc1t $fcc0, 65536 + + beqz16 $6, 31 + beqz16 $6, 130 diff --git a/test/MC/Mips/micromips-branch16.s b/test/MC/Mips/micromips-branch-fixup.s index 321ee86..98b4842 100644 --- a/test/MC/Mips/micromips-branch16.s +++ b/test/MC/Mips/micromips-branch-fixup.s @@ -7,10 +7,22 @@ # Check that the assembler can handle the documented syntax # for relocations. #------------------------------------------------------------------------------ -# CHECK-FIXUP: b bar # encoding: [A,0x94'A',0x00,0x00] +# CHECK-FIXUP: beqz16 $6, bar # encoding: [0b0AAAAAAA,0x8f] # CHECK-FIXUP: # fixup A - offset: 0, -# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1 +# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC7_S1 +# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-FIXUP: bnez16 $6, bar # encoding: [0b0AAAAAAA,0xaf] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC7_S1 # CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-FIXUP: b16 bar # encoding: [A,0b110011AA] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC10_S1 +# CHECK-FIXUP: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-FIXUP: b bar # encoding: [A,0x94'A',0x00,0x00] +# CHECK-FIXUP: # fixup A - offset: 0, +# CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1 +# CHECK-FIXUP: nop # encoding: [0x00,0x0c] # CHECK-FIXUP: beq $3, $4, bar # encoding: [0x83'A',0x94'A',0x00,0x00] # CHECK-FIXUP: # fixup A - offset: 0, # CHECK-FIXUP: value: bar, kind: fixup_MICROMIPS_PC16_S1 @@ -47,6 +59,9 @@ # Check that the appropriate relocations were created. #------------------------------------------------------------------------------ # CHECK-ELF: Relocations [ +# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC7_S1 +# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC7_S1 +# CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC10_S1 # CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1 # CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1 # CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1 @@ -58,6 +73,13 @@ # CHECK-ELF: 0x{{[0-9,A-F]+}} R_MICROMIPS_PC16_S1 # CHECK-ELF: ] + .text + .type main, @function + .set micromips +main: + beqz16 $6, bar + bnez16 $6, bar + b16 bar b bar beq $3, $4, bar bne $3, $4, bar diff --git a/test/MC/Mips/micromips-branch-instructions.s b/test/MC/Mips/micromips-branch-instructions.s index cf0aab7..e85b925 100644 --- a/test/MC/Mips/micromips-branch-instructions.s +++ b/test/MC/Mips/micromips-branch-instructions.s @@ -9,8 +9,8 @@ #------------------------------------------------------------------------------ # Little endian #------------------------------------------------------------------------------ -# CHECK-EL: b 1332 # encoding: [0x00,0x94,0x9a,0x02] -# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: b 1332 # encoding: [0x00,0x94,0x9a,0x02] +# CHECK-EL: nop # encoding: [0x00,0x0c] # CHECK-EL: beq $9, $6, 1332 # encoding: [0xc9,0x94,0x9a,0x02] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: bgez $6, 1332 # encoding: [0x46,0x40,0x9a,0x02] @@ -30,14 +30,14 @@ # CHECK-EL: bltz $6, 1332 # encoding: [0x06,0x40,0x9a,0x02] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: bgezals $6, 1332 # encoding: [0x66,0x42,0x9a,0x02] -# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: nop # encoding: [0x00,0x0c] # CHECK-EL: bltzals $6, 1332 # encoding: [0x26,0x42,0x9a,0x02] -# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: nop # encoding: [0x00,0x0c] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ -# CHECK-EB: b 1332 # encoding: [0x94,0x00,0x02,0x9a] -# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: b 1332 # encoding: [0x94,0x00,0x02,0x9a] +# CHECK-EB: nop # encoding: [0x0c,0x00] # CHECK-EB: beq $9, $6, 1332 # encoding: [0x94,0xc9,0x02,0x9a] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: bgez $6, 1332 # encoding: [0x40,0x46,0x02,0x9a] @@ -57,10 +57,14 @@ # CHECK-EB: bltz $6, 1332 # encoding: [0x40,0x06,0x02,0x9a] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: bgezals $6, 1332 # encoding: [0x42,0x66,0x02,0x9a] -# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: nop # encoding: [0x0c,0x00] # CHECK-EB: bltzals $6, 1332 # encoding: [0x42,0x26,0x02,0x9a] -# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: nop # encoding: [0x0c,0x00] + .text + .type main, @function + .set micromips +main: b 1332 beq $9,$6,1332 bgez $6,1332 diff --git a/test/MC/Mips/micromips-control-instructions.s b/test/MC/Mips/micromips-control-instructions.s index e79896d..76c953f 100644 --- a/test/MC/Mips/micromips-control-instructions.s +++ b/test/MC/Mips/micromips-control-instructions.s @@ -15,6 +15,11 @@ # CHECK-EL: .set mips32r2 # CHECK-EL: rdhwr $5, $29 # CHECK-EL: .set pop # encoding: [0xbd,0x00,0x3c,0x6b] +# CHECK-EL: cache 1, 8($5) # encoding: [0x25,0x20,0x08,0x60] +# CHECK-EL: pref 1, 8($5) # encoding: [0x25,0x60,0x08,0x20] +# CHECK-EL: ssnop # encoding: [0x00,0x00,0x00,0x08] +# CHECK-EL: ehb # encoding: [0x00,0x00,0x00,0x18] +# CHECK-EL: pause # encoding: [0x00,0x00,0x00,0x28] # CHECK-EL: break # encoding: [0x00,0x00,0x07,0x00] # CHECK-EL: break 7 # encoding: [0x07,0x00,0x07,0x00] # CHECK-EL: break 7, 5 # encoding: [0x07,0x00,0x47,0x01] @@ -43,6 +48,11 @@ # CHECK-EB: .set mips32r2 # CHECK-EB: rdhwr $5, $29 # CHECK-EB: .set pop # encoding: [0x00,0xbd,0x6b,0x3c] +# CHECK-EB: cache 1, 8($5) # encoding: [0x20,0x25,0x60,0x08] +# CHECK-EB: pref 1, 8($5) # encoding: [0x60,0x25,0x20,0x08] +# CHECK-EB: ssnop # encoding: [0x00,0x00,0x08,0x00] +# CHECK-EB: ehb # encoding: [0x00,0x00,0x18,0x00] +# CHECK-EB: pause # encoding: [0x00,0x00,0x28,0x00] # CHECK-EB: break # encoding: [0x00,0x00,0x00,0x07] # CHECK-EB: break 7 # encoding: [0x00,0x07,0x00,0x07] # CHECK-EB: break 7, 5 # encoding: [0x00,0x07,0x01,0x47] @@ -66,6 +76,11 @@ sdbbp sdbbp 34 rdhwr $5, $29 + cache 1, 8($5) + pref 1, 8($5) + ssnop + ehb + pause break break 7 break 7,5 diff --git a/test/MC/Mips/micromips-diagnostic-fixup.s b/test/MC/Mips/micromips-diagnostic-fixup.s index f8fe447..041338a 100644 --- a/test/MC/Mips/micromips-diagnostic-fixup.s +++ b/test/MC/Mips/micromips-diagnostic-fixup.s @@ -4,7 +4,7 @@ .text b foo - .space 65536 - 8, 1 # -8 = size of b instr plus size of automatically inserted nop + .space 65536 - 6, 1 # -6 = size of b instr plus size of automatically inserted nop nop # This instr makes the branch too long to fit into a 17-bit offset foo: add $0,$0,$0 diff --git a/test/MC/Mips/micromips-func-addr.s b/test/MC/Mips/micromips-func-addr.s new file mode 100644 index 0000000..e2a4d23 --- /dev/null +++ b/test/MC/Mips/micromips-func-addr.s @@ -0,0 +1,16 @@ +# RUN: llvm-mc %s -filetype=obj -triple=mipsel-unknown-linux \ +# RUN: -mattr=micromips | llvm-readobj -r \ +# RUN: | FileCheck %s -check-prefix=CHECK +# CHECK: Relocations [ +# CHECK: 0x0 R_MIPS_32 bar 0x0 +# CHECK: 0x4 R_MIPS_32 L1 0x0 + + .set micromips + .type bar,@function +bar: +L1: + nop + .data + .4byte bar + .4byte L1 + diff --git a/test/MC/Mips/micromips-invalid.s b/test/MC/Mips/micromips-invalid.s index 779e66e..4321574 100644 --- a/test/MC/Mips/micromips-invalid.s +++ b/test/MC/Mips/micromips-invalid.s @@ -22,6 +22,15 @@ li16 $4, -2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range addiur2 $9, $7, -1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction addiur2 $6, $7, 10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + lwm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + lwm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + lwm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + lwm16 $16, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwm16 $16, $17, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lwm16 $16-$20, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + swm16 $5, $6, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected + swm16 $16, $19, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected + swm16 $16-$25, $ra, 8($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand lwm32 $5, $6, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: $16 or $31 expected lwm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected lwm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand @@ -29,3 +38,38 @@ swm32 $16, $19, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: consecutive register numbers expected swm32 $16-$25, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $24, 8($4) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid register operand + addiupc $7, 16777216 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + addiupc $6, -16777220 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + addiupc $3, 3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + lbu16 $9, 8($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhu16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lw16 $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sb16 $9, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sh16 $9, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sw16 $9, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + sb16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + sh16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + sw16 $4, 64($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + lbu16 $3, -2($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + lhu16 $3, 64($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + lw16 $4, 68($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + sb16 $16, 4($16) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sh16 $16, 8($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sw16 $16, 4($17) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lbu16 $16, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lhu16 $16, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + lw16 $17, 8($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sb16 $7, 4($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sh16 $7, 8($9) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + sw16 $7, 4($10) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + cache 256, 8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + pref 256, 8($5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range + beqz16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bnez16 $9, 20 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $5, $21, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/test/MC/Mips/micromips-jump-instructions.s b/test/MC/Mips/micromips-jump-instructions.s index aed18dc..3147a3f 100644 --- a/test/MC/Mips/micromips-jump-instructions.s +++ b/test/MC/Mips/micromips-jump-instructions.s @@ -19,10 +19,16 @@ # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: jr $7 # encoding: [0x07,0x00,0x3c,0x0f] # CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: jalx 1328 # encoding: [0x00,0xf0,0x4c,0x01] +# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EL: jals 1328 # encoding: [0x00,0x74,0x98,0x02] -# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: nop # encoding: [0x00,0x0c] # CHECK-EL: jalrs $ra, $6 # encoding: [0xe6,0x03,0x3c,0x4f] -# CHECK-EL: move $zero, $zero # encoding: [0x00,0x0c] +# CHECK-EL: nop # encoding: [0x00,0x0c] +# CHECK-EL: jalr $25 # encoding: [0xd9,0x45] +# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EL: jalr $4, $25 # encoding: [0x99,0x00,0x3c,0x0f] +# CHECK-EL: nop # encoding: [0x00,0x00,0x00,0x00] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -36,15 +42,24 @@ # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: jr $7 # encoding: [0x00,0x07,0x0f,0x3c] # CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: jalx 1328 # encoding: [0xf0,0x00,0x01,0x4c] +# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] # CHECK-EB: jals 1328 # encoding: [0x74,0x00,0x02,0x98] -# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: nop # encoding: [0x0c,0x00] # CHECK-EB: jalrs $ra, $6 # encoding: [0x03,0xe6,0x4f,0x3c] -# CHECK-EB: move $zero, $zero # encoding: [0x0c,0x00] +# CHECK-EB: nop # encoding: [0x0c,0x00] +# CHECK-EB: jalr $25 # encoding: [0x45,0xd9] +# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] +# CHECK-EB: jalr $4, $25 # encoding: [0x00,0x99,0x0f,0x3c] +# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00] j 1328 jal 1328 jalr $ra, $6 jr $7 j $7 + jalx 1328 jals 1328 jalrs $ra, $6 + jal $25 + jal $4, $25 diff --git a/test/MC/Mips/micromips-loadstore-instructions.s b/test/MC/Mips/micromips-loadstore-instructions.s index 62fa101..f22719d 100644 --- a/test/MC/Mips/micromips-loadstore-instructions.s +++ b/test/MC/Mips/micromips-loadstore-instructions.s @@ -14,9 +14,12 @@ # CHECK-EL: lh $2, 8($4) # encoding: [0x44,0x3c,0x08,0x00] # CHECK-EL: lhu $4, 8($2) # encoding: [0x82,0x34,0x08,0x00] # CHECK-EL: lw $6, 4($5) # encoding: [0xc5,0xfc,0x04,0x00] +# CHECK-EL: lw $6, 123($sp) # encoding: [0xdd,0xfc,0x7b,0x00] # CHECK-EL: sb $5, 8($4) # encoding: [0xa4,0x18,0x08,0x00] # CHECK-EL: sh $2, 8($4) # encoding: [0x44,0x38,0x08,0x00] # CHECK-EL: sw $5, 4($6) # encoding: [0xa6,0xf8,0x04,0x00] +# CHECK-EL: sw $5, 123($sp) # encoding: [0xbd,0xf8,0x7b,0x00] +# CHECK-EL: sw $3, 32($gp) # encoding: [0x7c,0xf8,0x20,0x00] # CHECK-EL: ll $2, 8($4) # encoding: [0x44,0x60,0x08,0x30] # CHECK-EL: sc $2, 8($4) # encoding: [0x44,0x60,0x08,0xb0] # CHECK-EL: lwu $2, 8($4) # encoding: [0x44,0x60,0x08,0xe0] @@ -29,6 +32,18 @@ # CHECK-EL: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x24,0x23,0x08,0x50] # CHECK-EL: swm32 $16, $17, 8($4) # encoding: [0x44,0x20,0x08,0xd0] # CHECK-EL: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x84,0x20,0x08,0xd0] +# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45] +# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45] +# CHECK-EL: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x12,0x45] +# CHECK-EL: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x5d,0x22,0x40,0x50] +# CHECK-EL: lwm32 $16, $17, $ra, 8($4) # encoding: [0x44,0x22,0x08,0x50] +# CHECK-EL: lwm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0x50] +# CHECK-EL: swm16 $16, $17, $ra, 8($sp) # encoding: [0x52,0x45] +# CHECK-EL: swm32 $16, $17, $ra, 64($sp) # encoding: [0x5d,0x22,0x40,0xd0] +# CHECK-EL: swm32 $16, $17, $ra, 8($4) # encoding: [0x44,0x22,0x08,0xd0] +# CHECK-EL: swm32 $16, $17, 8($sp) # encoding: [0x5d,0x20,0x08,0xd0] +# CHECK-EL: swp $16, 8($4) # encoding: [0x04,0x22,0x08,0x90] +# CHECK-EL: lwp $16, 8($4) # encoding: [0x04,0x22,0x08,0x10] #------------------------------------------------------------------------------ # Big endian #------------------------------------------------------------------------------ @@ -37,9 +52,12 @@ # CHECK-EB: lh $2, 8($4) # encoding: [0x3c,0x44,0x00,0x08] # CHECK-EB: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08] # CHECK-EB: lw $6, 4($5) # encoding: [0xfc,0xc5,0x00,0x04] +# CHECK-EB: lw $6, 123($sp) # encoding: [0xfc,0xdd,0x00,0x7b] # CHECK-EB: sb $5, 8($4) # encoding: [0x18,0xa4,0x00,0x08] # CHECK-EB: sh $2, 8($4) # encoding: [0x38,0x44,0x00,0x08] # CHECK-EB: sw $5, 4($6) # encoding: [0xf8,0xa6,0x00,0x04] +# CHECK-EB: sw $5, 123($sp) # encoding: [0xf8,0xbd,0x00,0x7b] +# CHECK-EB: sw $3, 32($gp) # encoding: [0xf8,0x7c,0x00,0x20] # CHECK-EB: ll $2, 8($4) # encoding: [0x60,0x44,0x30,0x08] # CHECK-EB: sc $2, 8($4) # encoding: [0x60,0x44,0xb0,0x08] # CHECK-EB: lwu $2, 8($4) # encoding: [0x60,0x44,0xe0,0x08] @@ -52,14 +70,29 @@ # CHECK-EB: lwm32 $16, $17, $18, $19, $20, $21, $22, $23, $fp, $ra, 8($4) # encoding: [0x23,0x24,0x50,0x08] # CHECK-EB: swm32 $16, $17, 8($4) # encoding: [0x20,0x44,0xd0,0x08] # CHECK-EB: swm32 $16, $17, $18, $19, 8($4) # encoding: [0x20,0x84,0xd0,0x08] +# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12] +# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52] +# CHECK-EB: lwm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x12] +# CHECK-EB: lwm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0x50,0x40] +# CHECK-EB: lwm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0x50,0x08] +# CHECK-EB: lwm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0x50,0x08] +# CHECK-EB: swm16 $16, $17, $ra, 8($sp) # encoding: [0x45,0x52] +# CHECK-EB: swm32 $16, $17, $ra, 64($sp) # encoding: [0x22,0x5d,0xd0,0x40] +# CHECK-EB: swm32 $16, $17, $ra, 8($4) # encoding: [0x22,0x44,0xd0,0x08] +# CHECK-EB: swm32 $16, $17, 8($sp) # encoding: [0x20,0x5d,0xd0,0x08] +# CHECK-EB: swp $16, 8($4) # encoding: [0x22,0x04,0x90,0x08] +# CHECK-EB: lwp $16, 8($4) # encoding: [0x22,0x04,0x10,0x08] lb $5, 8($4) lbu $6, 8($4) lh $2, 8($4) lhu $4, 8($2) lw $6, 4($5) + lw $6, 123($sp) sb $5, 8($4) sh $2, 8($4) sw $5, 4($6) + sw $5, 123($sp) + sw $3, 32($gp) ll $2, 8($4) sc $2, 8($4) lwu $2, 8($4) @@ -72,3 +105,15 @@ lwm32 $16-$23, $30 - $31, 8($4) swm32 $16, $17, 8($4) swm32 $16 - $19, 8($4) + lwm16 $16, $17, $ra, 8($sp) + swm16 $16, $17, $ra, 8($sp) + lwm $16, $17, $ra, 8($sp) + lwm $16, $17, $ra, 64($sp) + lwm $16, $17, $ra, 8($4) + lwm $16, $17, 8($sp) + swm $16, $17, $ra, 8($sp) + swm $16, $17, $ra, 64($sp) + swm $16, $17, $ra, 8($4) + swm $16, $17, 8($sp) + swp $16, 8($4) + lwp $16, 8($4) diff --git a/test/MC/Mips/mips-abi-bad.s b/test/MC/Mips/mips-abi-bad.s index c4653cf..ba6564f 100644 --- a/test/MC/Mips/mips-abi-bad.s +++ b/test/MC/Mips/mips-abi-bad.s @@ -1,20 +1,30 @@ -# Error checking for malformed abi related directives # RUN: not llvm-mc -triple mips-unknown-unknown %s 2>&1 | FileCheck %s -# CHECK: .text + +# Error checking for malformed .module directives (and .set fp=...). + .module fp=3 -# CHECK : mips-abi-bad.s:4:16: error: unsupported option -# CHECK-NEXT : .module fp=3 -# CHECK-NEXT : ^ +# CHECK: :[[@LINE-1]]:17: error: unsupported value, expected 'xx', '32' or '64' +# CHECK-NEXT: .module fp=3 +# CHECK-NEXT: ^ +# FIXME: Add separate test for .set fp=xx/32/64. .set fp=xx,6 -# CHECK :mips-abi-bad.s:5:15: error: unexpected token in statement -# CHECK-NEXT : .set fp=xx,6 -# CHECK-NEXT : ^ +# CHECK: :[[@LINE-1]]:15: error: unexpected token, expected end of statement +# CHECK-NEXT: .set fp=xx,6 +# CHECK-NEXT: ^ + + .module +# CHECK: :[[@LINE-1]]:12: error: expected .module option identifier +# CHECK-NEXT: .module +# CHECK-NEXT: ^ + + .module 34 +# CHECK: :[[@LINE-1]]:13: error: expected .module option identifier +# CHECK-NEXT: .module 34 +# CHECK-NEXT: ^ -# CHECK :.set mips16 .set mips16 .module fp=32 - -# CHECK :mips-abi-bad.s:14:13: error: .module directive must come before any code -# CHECK-NEXT : .module fp=32 -# CHECK-NEXT : ^ +# CHECK: :[[@LINE-1]]:13: error: .module directive must appear before any code +# CHECK-NEXT: .module fp=32 +# CHECK-NEXT: ^ diff --git a/test/MC/Mips/mips-noat.s b/test/MC/Mips/mips-noat.s index f9d4efd..3a937c7 100644 --- a/test/MC/Mips/mips-noat.s +++ b/test/MC/Mips/mips-noat.s @@ -7,6 +7,8 @@ # CHECK: lui $1, 1 # CHECK: addu $1, $1, $2 # CHECK: lw $2, 0($1) +# CHECK-LABEL: test2: +# CHECK: .set noat test1: lw $2, 65536($2) @@ -20,6 +22,8 @@ test2: # CHECK: lui $1, 1 # CHECK: addu $1, $1, $2 # CHECK: lw $2, 0($1) +# CHECK-LABEL: test4: +# CHECK: .set at=$0 test3: .set at lw $2, 65536($2) diff --git a/test/MC/Mips/mips-reginfo-fp64.s b/test/MC/Mips/mips-reginfo-fp64.s index b60e54e..ba2bf79 100644 --- a/test/MC/Mips/mips-reginfo-fp64.s +++ b/test/MC/Mips/mips-reginfo-fp64.s @@ -2,11 +2,11 @@ # RUN: llvm-readobj -s -section-data | \ # RUN: FileCheck %s -check-prefix=ELF32 -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64,-n64,+n32 -filetype=obj -o - | \ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n32 -filetype=obj -o - | \ # RUN: llvm-readobj -s -section-data | \ # RUN: FileCheck %s -check-prefix=ELF32 -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64,+n64 -filetype=obj -o - | \ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 -mattr=+msa,+fp64 -target-abi n64 -filetype=obj -o - | \ # RUN: llvm-readobj -s -section-data | \ # RUN: FileCheck %s -check-prefix=ELF64 diff --git a/test/MC/Mips/mips32r2/valid-xfail.s b/test/MC/Mips/mips32r2/valid-xfail.s index ef02d51..13385d0 100644 --- a/test/MC/Mips/mips32r2/valid-xfail.s +++ b/test/MC/Mips/mips32r2/valid-xfail.s @@ -293,7 +293,6 @@ swe $24,94($k0) swle $v1,-209($gp) swre $k0,-202($s2) - synci 20023($s0) tlbginv tlbginvf tlbgp diff --git a/test/MC/Mips/mips32r2/valid.s b/test/MC/Mips/mips32r2/valid.s index 4ef5aab..97cfa36 100644 --- a/test/MC/Mips/mips32r2/valid.s +++ b/test/MC/Mips/mips32r2/valid.s @@ -233,3 +233,4 @@ trunc.w.s $f28,$f30 wsbh $k1,$9 xor $s2,$a0,$s8 + synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] diff --git a/test/MC/Mips/mips32r3/abiflags.s b/test/MC/Mips/mips32r3/abiflags.s new file mode 100644 index 0000000..a6c7057 --- /dev/null +++ b/test/MC/Mips/mips32r3/abiflags.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r3 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r3 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=32 +# CHECK-ASM: .set fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002003 01010001 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } + + .module fp=32 + .set fp=64 +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips32r3/invalid-mips64r2.s b/test/MC/Mips/mips32r3/invalid-mips64r2.s new file mode 100644 index 0000000..0f007e2 --- /dev/null +++ b/test/MC/Mips/mips32r3/invalid-mips64r2.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \ +# RUN: -mcpu=mips32r3 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + diff --git a/test/MC/Mips/mips32r3/invalid.s b/test/MC/Mips/mips32r3/invalid.s new file mode 100644 index 0000000..f67f4c5 --- /dev/null +++ b/test/MC/Mips/mips32r3/invalid.s @@ -0,0 +1,10 @@ +# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. +# invalid set of operands or operand's restrictions not met). + +# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r3 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .set noreorder + jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different diff --git a/test/MC/Mips/mips32r3/valid-xfail.s b/test/MC/Mips/mips32r3/valid-xfail.s new file mode 100644 index 0000000..b0fc3a1 --- /dev/null +++ b/test/MC/Mips/mips32r3/valid-xfail.s @@ -0,0 +1,308 @@ +# Instructions that should be valid but currently fail for known reasons (e.g. +# they aren't implemented yet). +# This test is set up to XPASS if any instruction generates an encoding. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | not FileCheck %s +# CHECK-NOT: encoding +# XFAIL: * + + .set noat + abs.ps $f22,$f8 + absq_s.ph $8,$a0 + absq_s.qb $15,$s1 + absq_s.w $s3,$ra + add.ps $f25,$f27,$f13 + addq.ph $s1,$15,$at + addq_s.ph $s3,$s6,$s2 + addq_s.w $a2,$8,$at + addqh.ph $s4,$14,$s1 + addqh.w $s7,$s7,$k1 + addqh_r.ph $sp,$25,$s8 + addqh_r.w $8,$v1,$zero + addsc $s8,$15,$12 + addu.ph $a2,$14,$s3 + addu.qb $s6,$v1,$v1 + addu_s.ph $a3,$s3,$gp + addu_s.qb $s4,$s8,$s1 + adduh.qb $a1,$a1,$at + adduh_r.qb $a0,$9,$12 + addwc $k0,$s6,$s7 + alnv.ps $f12,$f18,$f30,$12 + and.v $w10,$w25,$w29 + bitrev $14,$at + bmnz.v $w15,$w2,$w28 + bmz.v $w13,$w11,$w21 + bsel.v $w28,$w7,$w0 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + cfcmsa $s6,$19 + cmp.eq.ph $s7,$14 + cmp.le.ph $8,$14 + cmp.lt.ph $k0,$sp + cmpgdu.eq.qb $s3,$zero,$k0 + cmpgdu.le.qb $v1,$15,$s2 + cmpgdu.lt.qb $s0,$gp,$sp + cmpgu.eq.qb $14,$s6,$s8 + cmpgu.le.qb $9,$a3,$s4 + cmpgu.lt.qb $sp,$at,$8 + cmpu.eq.qb $v0,$24 + cmpu.le.qb $s1,$a1 + cmpu.lt.qb $at,$a3 + ctcmsa $31,$s7 + cvt.d.l $f4,$f16 + cvt.ps.s $f3,$f18,$f19 + cvt.s.l $f15,$f30 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmt $k0 + dpa.w.ph $ac1,$s7,$k0 + dpaq_s.w.ph $ac2,$a0,$13 + dpaq_sa.l.w $ac0,$a2,$14 + dpaqx_s.w.ph $ac3,$a0,$24 + dpaqx_sa.w.ph $ac1,$zero,$s5 + dpau.h.qbl $ac1,$10,$24 + dpau.h.qbr $ac1,$s7,$s6 + dpax.w.ph $ac3,$a0,$k0 + dps.w.ph $ac1,$a3,$a1 + dpsq_s.w.ph $ac0,$gp,$k0 + dpsq_sa.l.w $ac0,$a3,$15 + dpsqx_s.w.ph $ac3,$13,$a3 + dpsqx_sa.w.ph $ac3,$sp,$s2 + dpsu.h.qbl $ac2,$14,$10 + dpsu.h.qbr $ac2,$a1,$s6 + dpsx.w.ph $ac0,$s7,$gp + dvpe $s6 + emt $8 + evpe $v0 + extpdpv $s6,$ac0,$s8 + extpv $13,$ac0,$14 + extrv.w $8,$ac3,$at + extrv_r.w $8,$ac1,$s6 + extrv_rs.w $gp,$ac1,$s6 + extrv_s.h $s2,$ac1,$14 + fclass.d $w14,$w27 + fclass.w $w19,$w28 + fexupl.d $w10,$w29 + fexupl.w $w12,$w27 + fexupr.d $w31,$w15 + fexupr.w $w29,$w12 + ffint_s.d $w1,$w30 + ffint_s.w $w16,$w14 + ffint_u.d $w23,$w18 + ffint_u.w $w19,$w12 + ffql.d $w2,$w3 + ffql.w $w9,$w0 + ffqr.d $w25,$w24 + ffqr.w $w10,$w6 + fill.b $w9,$v1 + fill.h $w9,$8 + fill.w $w31,$15 + flog2.d $w12,$w16 + flog2.w $w19,$w23 + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + fork $s2,$8,$a0 + frcp.d $w12,$w4 + frcp.w $w30,$w8 + frint.d $w20,$w8 + frint.w $w11,$w29 + frsqrt.d $w29,$w2 + frsqrt.w $w9,$w8 + fsqrt.d $w3,$w1 + fsqrt.w $w5,$w15 + ftint_s.d $w31,$w26 + ftint_s.w $w27,$w14 + ftint_u.d $w5,$w31 + ftint_u.w $w12,$w29 + ftrunc_s.d $w4,$w22 + ftrunc_s.w $w24,$w7 + ftrunc_u.d $w20,$w25 + ftrunc_u.w $w7,$w26 + insv $s2,$at + iret + lbe $14,122($9) + lbue $11,-108($10) + lbux $9,$14($v0) + lhe $s6,219($v1) + lhue $gp,118($11) + lhx $sp,$k0($15) + lle $gp,-237($ra) + lwe $ra,-145($14) + lwle $11,-42($11) + lwre $sp,-152($24) + lwx $12,$12($s4) + madd.ps $f22,$f3,$f14,$f3 + maq_s.w.phl $ac2,$25,$11 + maq_s.w.phr $ac0,$10,$25 + maq_sa.w.phl $ac3,$a1,$v1 + maq_sa.w.phr $ac1,$at,$10 + mfgc0 $s6,c0_datahi1 + mflo $9,$ac2 + modsub $a3,$12,$a3 + mov.ps $f22,$f17 + move.v $w8,$w17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msub $ac2,$sp,$14 + msub.ps $f12,$f14,$f29,$f17 + msubu $ac2,$a1,$24 + mtc0 $9,c0_datahi1 + mtgc0 $s4,$21,7 + mthi $v0,$ac1 + mthlip $a3,$ac0 + mul.ph $s4,$24,$s0 + mul.ps $f14,$f0,$f16 + mul_s.ph $10,$14,$15 + muleq_s.w.phl $11,$s4,$s4 + muleq_s.w.phr $s6,$a0,$s8 + muleu_s.ph.qbl $a2,$14,$8 + muleu_s.ph.qbr $a1,$ra,$9 + mulq_rs.ph $s2,$14,$15 + mulq_rs.w $at,$s4,$25 + mulq_s.ph $s0,$k1,$15 + mulq_s.w $9,$a3,$s0 + mulsa.w.ph $ac1,$s4,$s6 + mulsaq_s.w.ph $ac0,$ra,$s2 + neg.ps $f19,$f13 + nloc.b $w12,$w30 + nloc.d $w16,$w7 + nloc.h $w21,$w17 + nloc.w $w17,$w16 + nlzc.b $w12,$w7 + nlzc.d $w14,$w14 + nlzc.h $w24,$w24 + nlzc.w $w10,$w4 + nmadd.ps $f27,$f4,$f9,$f25 + nmsub.ps $f6,$f12,$f14,$f17 + nor.v $w20,$w20,$w15 + or.v $w13,$w23,$w12 + packrl.ph $ra,$24,$14 + pcnt.b $w30,$w15 + pcnt.d $w5,$w16 + pcnt.h $w20,$w24 + pcnt.w $w22,$w20 + pick.ph $ra,$a2,$gp + pick.qb $11,$a0,$gp + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + preceq.w.phl $s8,$gp + preceq.w.phr $s5,$15 + precequ.ph.qbl $s7,$ra + precequ.ph.qbla $a0,$9 + precequ.ph.qbr $ra,$s3 + precequ.ph.qbra $24,$8 + preceu.ph.qbl $sp,$8 + preceu.ph.qbla $s6,$11 + preceu.ph.qbr $gp,$s1 + preceu.ph.qbra $k1,$s0 + precr.qb.ph $v0,$12,$s8 + precrq.ph.w $14,$s8,$24 + precrq.qb.ph $a2,$12,$12 + precrq_rs.ph.w $a1,$k0,$a3 + precrqu_s.qb.ph $zero,$gp,$s5 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + raddu.w.qb $25,$s3 + rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 + repl.ph $at,-307 + replv.ph $v1,$s7 + replv.qb $25,$12 + rorv $13,$a3,$s5 + round.l.d $f12,$f1 + round.l.s $f25,$f5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sbe $s7,33($s1) + sce $sp,189($10) + she $24,105($v0) + shilo $ac1,26 + shilov $ac2,$10 + shllv.ph $10,$s0,$s0 + shllv.qb $gp,$v1,$zero + shllv_s.ph $k1,$at,$13 + shllv_s.w $s1,$ra,$k0 + shrav.ph $25,$s2,$s1 + shrav.qb $zero,$24,$11 + shrav_r.ph $s3,$11,$25 + shrav_r.qb $a0,$sp,$s5 + shrav_r.w $s7,$s4,$s6 + shrlv.ph $14,$10,$9 + shrlv.qb $a2,$s2,$11 + sub.ps $f5,$f14,$f26 + subq.ph $ra,$9,$s8 + subq_s.ph $13,$s8,$s5 + subq_s.w $k1,$a2,$a3 + subqh.ph $10,$at,$9 + subqh.w $v0,$a2,$zero + subqh_r.ph $a0,$12,$s6 + subqh_r.w $10,$a2,$gp + subu.ph $9,$s6,$s4 + subu.qb $s6,$a2,$s6 + subu_s.ph $v1,$a1,$s3 + subu_s.qb $s1,$at,$ra + subuh.qb $zero,$gp,$gp + subuh_r.qb $s4,$s8,$s6 + swe $24,94($k0) + swle $v1,-209($gp) + swre $k0,-202($s2) + tlbginv + tlbginvf + tlbgp + tlbgr + tlbgwi + tlbgwr + tlbinv + tlbinvf + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + wrpgpr $zero,$13 + xor.v $w20,$w21,$w30 + yield $v1,$s0 diff --git a/test/MC/Mips/mips32r3/valid.s b/test/MC/Mips/mips32r3/valid.s new file mode 100644 index 0000000..4280de5 --- /dev/null +++ b/test/MC/Mips/mips32r3/valid.s @@ -0,0 +1,236 @@ +# Instructions that are valid +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r3 | FileCheck %s + + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] + addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] + and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + deret + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] + eret + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] + jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] + jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] + lb $24,-14515($10) + lbu $8,30195($v1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + madd.d $f18,$f19,$f26,$f20 + madd.s $f1,$f31,$f19,$f25 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhc1 $s8,$f24 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msub.d $f10,$f1,$f31,$f18 + msub.s $f12,$f19,$f10,$f16 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthc1 $zero,$f16 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.s $f1,$f24,$f19,$f4 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] + pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] + rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] + rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] + rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] + sdxc1 $f11,$10($14) + seb $25,$15 + seh $v1,$12 + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] + teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] + tgei $s1,5025 + tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] + tlti $14,-21059 + tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] + tnei $12,-29647 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + wsbh $k1,$9 + xor $s2,$a0,$s8 + synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] diff --git a/test/MC/Mips/mips32r5/abiflags.s b/test/MC/Mips/mips32r5/abiflags.s new file mode 100644 index 0000000..fa5befe --- /dev/null +++ b/test/MC/Mips/mips32r5/abiflags.s @@ -0,0 +1,37 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips32r5 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=32 +# CHECK-ASM: .set fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags (12) +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00002005 01010001 00000000 00000000 |.. .............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } + + .module fp=32 + .set fp=64 +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips32r5/invalid-mips64r2.s b/test/MC/Mips/mips32r5/invalid-mips64r2.s new file mode 100644 index 0000000..ed8f5c7 --- /dev/null +++ b/test/MC/Mips/mips32r5/invalid-mips64r2.s @@ -0,0 +1,10 @@ +# Instructions that are invalid +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \ +# RUN: -mcpu=mips32r5 2>%t1 +# RUN: FileCheck %s < %t1 + + .set noat + dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + diff --git a/test/MC/Mips/mips32r5/invalid.s b/test/MC/Mips/mips32r5/invalid.s new file mode 100644 index 0000000..fec30e1 --- /dev/null +++ b/test/MC/Mips/mips32r5/invalid.s @@ -0,0 +1,10 @@ +# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. +# invalid set of operands or operand's restrictions not met). + +# RUN: not llvm-mc %s -triple=mips-unknown-linux -mcpu=mips32r5 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .set noreorder + jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different diff --git a/test/MC/Mips/mips32r5/valid-xfail.s b/test/MC/Mips/mips32r5/valid-xfail.s new file mode 100644 index 0000000..a821ddd --- /dev/null +++ b/test/MC/Mips/mips32r5/valid-xfail.s @@ -0,0 +1,308 @@ +# Instructions that should be valid but currently fail for known reasons (e.g. +# they aren't implemented yet). +# This test is set up to XPASS if any instruction generates an encoding. +# +# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | not FileCheck %s +# CHECK-NOT: encoding +# XFAIL: * + + .set noat + abs.ps $f22,$f8 + absq_s.ph $8,$a0 + absq_s.qb $15,$s1 + absq_s.w $s3,$ra + add.ps $f25,$f27,$f13 + addq.ph $s1,$15,$at + addq_s.ph $s3,$s6,$s2 + addq_s.w $a2,$8,$at + addqh.ph $s4,$14,$s1 + addqh.w $s7,$s7,$k1 + addqh_r.ph $sp,$25,$s8 + addqh_r.w $8,$v1,$zero + addsc $s8,$15,$12 + addu.ph $a2,$14,$s3 + addu.qb $s6,$v1,$v1 + addu_s.ph $a3,$s3,$gp + addu_s.qb $s4,$s8,$s1 + adduh.qb $a1,$a1,$at + adduh_r.qb $a0,$9,$12 + addwc $k0,$s6,$s7 + alnv.ps $f12,$f18,$f30,$12 + and.v $w10,$w25,$w29 + bitrev $14,$at + bmnz.v $w15,$w2,$w28 + bmz.v $w13,$w11,$w21 + bsel.v $w28,$w7,$w0 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + cfcmsa $s6,$19 + cmp.eq.ph $s7,$14 + cmp.le.ph $8,$14 + cmp.lt.ph $k0,$sp + cmpgdu.eq.qb $s3,$zero,$k0 + cmpgdu.le.qb $v1,$15,$s2 + cmpgdu.lt.qb $s0,$gp,$sp + cmpgu.eq.qb $14,$s6,$s8 + cmpgu.le.qb $9,$a3,$s4 + cmpgu.lt.qb $sp,$at,$8 + cmpu.eq.qb $v0,$24 + cmpu.le.qb $s1,$a1 + cmpu.lt.qb $at,$a3 + ctcmsa $31,$s7 + cvt.d.l $f4,$f16 + cvt.ps.s $f3,$f18,$f19 + cvt.s.l $f15,$f30 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmt $k0 + dpa.w.ph $ac1,$s7,$k0 + dpaq_s.w.ph $ac2,$a0,$13 + dpaq_sa.l.w $ac0,$a2,$14 + dpaqx_s.w.ph $ac3,$a0,$24 + dpaqx_sa.w.ph $ac1,$zero,$s5 + dpau.h.qbl $ac1,$10,$24 + dpau.h.qbr $ac1,$s7,$s6 + dpax.w.ph $ac3,$a0,$k0 + dps.w.ph $ac1,$a3,$a1 + dpsq_s.w.ph $ac0,$gp,$k0 + dpsq_sa.l.w $ac0,$a3,$15 + dpsqx_s.w.ph $ac3,$13,$a3 + dpsqx_sa.w.ph $ac3,$sp,$s2 + dpsu.h.qbl $ac2,$14,$10 + dpsu.h.qbr $ac2,$a1,$s6 + dpsx.w.ph $ac0,$s7,$gp + dvpe $s6 + emt $8 + evpe $v0 + extpdpv $s6,$ac0,$s8 + extpv $13,$ac0,$14 + extrv.w $8,$ac3,$at + extrv_r.w $8,$ac1,$s6 + extrv_rs.w $gp,$ac1,$s6 + extrv_s.h $s2,$ac1,$14 + fclass.d $w14,$w27 + fclass.w $w19,$w28 + fexupl.d $w10,$w29 + fexupl.w $w12,$w27 + fexupr.d $w31,$w15 + fexupr.w $w29,$w12 + ffint_s.d $w1,$w30 + ffint_s.w $w16,$w14 + ffint_u.d $w23,$w18 + ffint_u.w $w19,$w12 + ffql.d $w2,$w3 + ffql.w $w9,$w0 + ffqr.d $w25,$w24 + ffqr.w $w10,$w6 + fill.b $w9,$v1 + fill.h $w9,$8 + fill.w $w31,$15 + flog2.d $w12,$w16 + flog2.w $w19,$w23 + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + fork $s2,$8,$a0 + frcp.d $w12,$w4 + frcp.w $w30,$w8 + frint.d $w20,$w8 + frint.w $w11,$w29 + frsqrt.d $w29,$w2 + frsqrt.w $w9,$w8 + fsqrt.d $w3,$w1 + fsqrt.w $w5,$w15 + ftint_s.d $w31,$w26 + ftint_s.w $w27,$w14 + ftint_u.d $w5,$w31 + ftint_u.w $w12,$w29 + ftrunc_s.d $w4,$w22 + ftrunc_s.w $w24,$w7 + ftrunc_u.d $w20,$w25 + ftrunc_u.w $w7,$w26 + insv $s2,$at + iret + lbe $14,122($9) + lbue $11,-108($10) + lbux $9,$14($v0) + lhe $s6,219($v1) + lhue $gp,118($11) + lhx $sp,$k0($15) + lle $gp,-237($ra) + lwe $ra,-145($14) + lwle $11,-42($11) + lwre $sp,-152($24) + lwx $12,$12($s4) + madd.ps $f22,$f3,$f14,$f3 + maq_s.w.phl $ac2,$25,$11 + maq_s.w.phr $ac0,$10,$25 + maq_sa.w.phl $ac3,$a1,$v1 + maq_sa.w.phr $ac1,$at,$10 + mfgc0 $s6,c0_datahi1 + mflo $9,$ac2 + modsub $a3,$12,$a3 + mov.ps $f22,$f17 + move.v $w8,$w17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msub $ac2,$sp,$14 + msub.ps $f12,$f14,$f29,$f17 + msubu $ac2,$a1,$24 + mtc0 $9,c0_datahi1 + mtgc0 $s4,$21,7 + mthi $v0,$ac1 + mthlip $a3,$ac0 + mul.ph $s4,$24,$s0 + mul.ps $f14,$f0,$f16 + mul_s.ph $10,$14,$15 + muleq_s.w.phl $11,$s4,$s4 + muleq_s.w.phr $s6,$a0,$s8 + muleu_s.ph.qbl $a2,$14,$8 + muleu_s.ph.qbr $a1,$ra,$9 + mulq_rs.ph $s2,$14,$15 + mulq_rs.w $at,$s4,$25 + mulq_s.ph $s0,$k1,$15 + mulq_s.w $9,$a3,$s0 + mulsa.w.ph $ac1,$s4,$s6 + mulsaq_s.w.ph $ac0,$ra,$s2 + neg.ps $f19,$f13 + nloc.b $w12,$w30 + nloc.d $w16,$w7 + nloc.h $w21,$w17 + nloc.w $w17,$w16 + nlzc.b $w12,$w7 + nlzc.d $w14,$w14 + nlzc.h $w24,$w24 + nlzc.w $w10,$w4 + nmadd.ps $f27,$f4,$f9,$f25 + nmsub.ps $f6,$f12,$f14,$f17 + nor.v $w20,$w20,$w15 + or.v $w13,$w23,$w12 + packrl.ph $ra,$24,$14 + pcnt.b $w30,$w15 + pcnt.d $w5,$w16 + pcnt.h $w20,$w24 + pcnt.w $w22,$w20 + pick.ph $ra,$a2,$gp + pick.qb $11,$a0,$gp + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + preceq.w.phl $s8,$gp + preceq.w.phr $s5,$15 + precequ.ph.qbl $s7,$ra + precequ.ph.qbla $a0,$9 + precequ.ph.qbr $ra,$s3 + precequ.ph.qbra $24,$8 + preceu.ph.qbl $sp,$8 + preceu.ph.qbla $s6,$11 + preceu.ph.qbr $gp,$s1 + preceu.ph.qbra $k1,$s0 + precr.qb.ph $v0,$12,$s8 + precrq.ph.w $14,$s8,$24 + precrq.qb.ph $a2,$12,$12 + precrq_rs.ph.w $a1,$k0,$a3 + precrqu_s.qb.ph $zero,$gp,$s5 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + raddu.w.qb $25,$s3 + rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 + repl.ph $at,-307 + replv.ph $v1,$s7 + replv.qb $25,$12 + rorv $13,$a3,$s5 + round.l.d $f12,$f1 + round.l.s $f25,$f5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sbe $s7,33($s1) + sce $sp,189($10) + she $24,105($v0) + shilo $ac1,26 + shilov $ac2,$10 + shllv.ph $10,$s0,$s0 + shllv.qb $gp,$v1,$zero + shllv_s.ph $k1,$at,$13 + shllv_s.w $s1,$ra,$k0 + shrav.ph $25,$s2,$s1 + shrav.qb $zero,$24,$11 + shrav_r.ph $s3,$11,$25 + shrav_r.qb $a0,$sp,$s5 + shrav_r.w $s7,$s4,$s6 + shrlv.ph $14,$10,$9 + shrlv.qb $a2,$s2,$11 + sub.ps $f5,$f14,$f26 + subq.ph $ra,$9,$s8 + subq_s.ph $13,$s8,$s5 + subq_s.w $k1,$a2,$a3 + subqh.ph $10,$at,$9 + subqh.w $v0,$a2,$zero + subqh_r.ph $a0,$12,$s6 + subqh_r.w $10,$a2,$gp + subu.ph $9,$s6,$s4 + subu.qb $s6,$a2,$s6 + subu_s.ph $v1,$a1,$s3 + subu_s.qb $s1,$at,$ra + subuh.qb $zero,$gp,$gp + subuh_r.qb $s4,$s8,$s6 + swe $24,94($k0) + swle $v1,-209($gp) + swre $k0,-202($s2) + tlbginv + tlbginvf + tlbgp + tlbgr + tlbgwi + tlbgwr + tlbinv + tlbinvf + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + wrpgpr $zero,$13 + xor.v $w20,$w21,$w30 + yield $v1,$s0 diff --git a/test/MC/Mips/mips32r5/valid.s b/test/MC/Mips/mips32r5/valid.s new file mode 100644 index 0000000..13341d5 --- /dev/null +++ b/test/MC/Mips/mips32r5/valid.s @@ -0,0 +1,236 @@ +# Instructions that are valid +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r5 | FileCheck %s + + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] + addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] + and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] + ctc1 $a2,$26 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + deret + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] + eret + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] + jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] + jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] + lb $24,-14515($10) + lbu $8,30195($v1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + madd.d $f18,$f19,$f26,$f20 + madd.s $f1,$f31,$f19,$f25 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhc1 $s8,$f24 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msub.d $f10,$f1,$f31,$f18 + msub.s $f12,$f19,$f10,$f16 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthc1 $zero,$f16 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nmadd.d $f18,$f9,$f14,$f19 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.d $f30,$f8,$f16,$f30 + nmsub.s $f1,$f24,$f19,$f4 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] + pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] + rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] + rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] + rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] + sdxc1 $f11,$10($14) + seb $25,$15 + seh $v1,$12 + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] + teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] + tgei $s1,5025 + tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] + tlti $14,-21059 + tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] + tnei $12,-29647 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + wsbh $k1,$9 + xor $s2,$a0,$s8 + synci -15842($a2) # CHECK: synci -15842($6) # encoding: [0x04,0xdf,0xc2,0x1e] diff --git a/test/MC/Mips/mips4/invalid-mips64r2.s b/test/MC/Mips/mips4/invalid-mips64r2.s index b259706..70a8261 100644 --- a/test/MC/Mips/mips4/invalid-mips64r2.s +++ b/test/MC/Mips/mips4/invalid-mips64r2.s @@ -17,19 +17,15 @@ luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$t5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $t8,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msubu $t7,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mtc0 $t1,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seb $t9,$t7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled seh $v1,$t4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips4/valid-xfail.s b/test/MC/Mips/mips4/valid-xfail.s index ff6f457..9c647d1 100644 --- a/test/MC/Mips/mips4/valid-xfail.s +++ b/test/MC/Mips/mips4/valid-xfail.s @@ -35,14 +35,6 @@ c.ult.s $fcc7,$f24,$f10 c.un.d $fcc6,$f23,$f24 c.un.s $fcc1,$f30,$f4 - madd.d $f18,$f19,$f26,$f20 - madd.s $f1,$f31,$f19,$f25 - msub.d $f10,$f1,$f31,$f18 - msub.s $f12,$f19,$f10,$f16 - nmadd.d $f18,$f9,$f14,$f19 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 - nmsub.s $f1,$f24,$f19,$f4 recip.d $f19,$f6 recip.s $f3,$f30 rsqrt.d $f3,$f28 diff --git a/test/MC/Mips/mips4/valid.s b/test/MC/Mips/mips4/valid.s index c221b76..fc747a5 100644 --- a/test/MC/Mips/mips4/valid.s +++ b/test/MC/Mips/mips4/valid.s @@ -134,6 +134,8 @@ lwr $zero,-19147($gp) lwu $s3,-24086($v1) lwxc1 $f12,$s1($s8) + madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1] + madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0] mfc1 $a3,$f27 mfhi $s3 mfhi $sp @@ -156,6 +158,8 @@ movz $a1,$s6,$9 movz.d $f12,$f29,$9 movz.s $f25,$f7,$v1 + msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9] + msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28] mtc1 $s8,$f9 mthi $s1 mtlo $sp @@ -170,6 +174,10 @@ negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] neg.d $f27,$f18 neg.s $f1,$f15 + nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1] + nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30] + nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] + nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nop nor $a3,$zero,$a3 or $12,$s0,$sp diff --git a/test/MC/Mips/mips5/invalid-mips64r2.s b/test/MC/Mips/mips5/invalid-mips64r2.s index b91e520..a96f4b3 100644 --- a/test/MC/Mips/mips5/invalid-mips64r2.s +++ b/test/MC/Mips/mips5/invalid-mips64r2.s @@ -21,19 +21,15 @@ ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $s6,$13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled madd $zero,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $s3,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msub $s7,$k1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled msubu $15,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips5/valid-xfail.s b/test/MC/Mips/mips5/valid-xfail.s index 8d1d0d7..d761189 100644 --- a/test/MC/Mips/mips5/valid-xfail.s +++ b/test/MC/Mips/mips5/valid-xfail.s @@ -57,25 +57,17 @@ cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 - madd.d $f18,$f19,$f26,$f20 madd.ps $f22,$f3,$f14,$f3 - madd.s $f1,$f31,$f19,$f25 mov.ps $f22,$f17 movf.ps $f10,$f28,$fcc6 movn.ps $f31,$f31,$s3 movt.ps $f20,$f25,$fcc2 movz.ps $f18,$f17,$ra - msub.d $f10,$f1,$f31,$f18 msub.ps $f12,$f14,$f29,$f17 - msub.s $f12,$f19,$f10,$f16 mul.ps $f14,$f0,$f16 neg.ps $f19,$f13 - nmadd.d $f18,$f9,$f14,$f19 nmadd.ps $f27,$f4,$f9,$f25 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 nmsub.ps $f6,$f12,$f14,$f17 - nmsub.s $f1,$f24,$f19,$f4 pll.ps $f25,$f9,$f30 plu.ps $f1,$f26,$f29 pul.ps $f9,$f30,$f26 diff --git a/test/MC/Mips/mips5/valid.s b/test/MC/Mips/mips5/valid.s index b93b22f..995d1a5 100644 --- a/test/MC/Mips/mips5/valid.s +++ b/test/MC/Mips/mips5/valid.s @@ -135,6 +135,8 @@ lwr $zero,-19147($gp) lwu $s3,-24086($v1) lwxc1 $f12,$s1($s8) + madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1] + madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0] mfc1 $a3,$f27 mfhi $s3 mfhi $sp @@ -157,6 +159,8 @@ movz $a1,$s6,$9 movz.d $f12,$f29,$9 movz.s $f25,$f7,$v1 + msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9] + msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28] mtc1 $s8,$f9 mthi $s1 mtlo $sp @@ -171,6 +175,10 @@ negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] neg.d $f27,$f18 neg.s $f1,$f15 + nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1] + nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30] + nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] + nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nop nor $a3,$zero,$a3 or $12,$s0,$sp diff --git a/test/MC/Mips/mips64-register-names-n32-n64.s b/test/MC/Mips/mips64-register-names-n32-n64.s index efe1cdb..fb2c426 100644 --- a/test/MC/Mips/mips64-register-names-n32-n64.s +++ b/test/MC/Mips/mips64-register-names-n32-n64.s @@ -3,7 +3,7 @@ # RUN: FileCheck -check-prefix=WARNING %s < %t0 # # RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding \ -# RUN: -mattr=-n64,+n32 2>%t1 | FileCheck %s +# RUN: -target-abi n32 2>%t1 | FileCheck %s # RUN: FileCheck -check-prefix=WARNING %s < %t1 # # Check that the register names are mapped to their correct numbers for n32/n64 diff --git a/test/MC/Mips/mips64-register-names-o32.s b/test/MC/Mips/mips64-register-names-o32.s index c170578..f5df527 100644 --- a/test/MC/Mips/mips64-register-names-o32.s +++ b/test/MC/Mips/mips64-register-names-o32.s @@ -1,5 +1,5 @@ # RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding \ -# RUN: -mattr=-n64,+o32 | FileCheck %s +# RUN: -target-abi o32 | FileCheck %s # Check that the register names are mapped to their correct numbers for o32 # Second byte of daddiu with $zero at rt contains the number of the source diff --git a/test/MC/Mips/mips64/invalid-mips64r2.s b/test/MC/Mips/mips64/invalid-mips64r2.s index 1a5abb6..1caa2bd 100644 --- a/test/MC/Mips/mips64/invalid-mips64r2.s +++ b/test/MC/Mips/mips64/invalid-mips64r2.s @@ -14,12 +14,8 @@ dsbh $v1,$14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ei $14 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - madd.s $f1,$f31,$f19,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - msub.s $f12,$f19,$f10,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mthc1 $zero,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmadd.s $f0,$f5,$f25,$f12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - nmsub.s $f1,$f24,$f19,$f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pause # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/mips64/valid-xfail.s b/test/MC/Mips/mips64/valid-xfail.s index e5455f5..7d1eb92 100644 --- a/test/MC/Mips/mips64/valid-xfail.s +++ b/test/MC/Mips/mips64/valid-xfail.s @@ -62,9 +62,7 @@ cvt.s.pu $f14,$f25 dmfc0 $10,c0_watchhi,2 dmtc0 $15,c0_datalo - madd.d $f18,$f19,$f26,$f20 madd.ps $f22,$f3,$f14,$f3 - madd.s $f1,$f31,$f19,$f25 mov.ps $f22,$f17 movf.ps $f10,$f28,$fcc6 movn.ps $f31,$f31,$s3 @@ -72,17 +70,11 @@ movz.ps $f18,$f17,$ra msgn.qh $v0,$v24,$v20 msgn.qh $v12,$v21,$v0[1] - msub.d $f10,$f1,$f31,$f18 msub.ps $f12,$f14,$f29,$f17 - msub.s $f12,$f19,$f10,$f16 mul.ps $f14,$f0,$f16 neg.ps $f19,$f13 - nmadd.d $f18,$f9,$f14,$f19 nmadd.ps $f27,$f4,$f9,$f25 - nmadd.s $f0,$f5,$f25,$f12 - nmsub.d $f30,$f8,$f16,$f30 nmsub.ps $f6,$f12,$f14,$f17 - nmsub.s $f1,$f24,$f19,$f4 pll.ps $f25,$f9,$f30 plu.ps $f1,$f26,$f29 pul.ps $f9,$f30,$f26 diff --git a/test/MC/Mips/mips64/valid.s b/test/MC/Mips/mips64/valid.s index 032777e..f481a28 100644 --- a/test/MC/Mips/mips64/valid.s +++ b/test/MC/Mips/mips64/valid.s @@ -144,6 +144,8 @@ madd $zero,$9 maddu $s3,$gp maddu $24,$s2 + madd.d $f18, $f22, $f26, $f20 # encoding: [0x4e,0xd4,0xd4,0xa1] + madd.s $f2, $f30, $f18, $f24 # encoding: [0x4f,0xd8,0x90,0xa0] mfc0 $a2,$14,1 mfc1 $a3,$f27 mfhi $s3 @@ -169,6 +171,8 @@ movz.s $f25,$f7,$v1 msub $s7,$k1 msubu $15,$a1 + msub.d $f10, $f2, $f30, $f18 # encoding: [0x4c,0x52,0xf2,0xa9] + msub.s $f12, $f18, $f10, $f16 # encoding: [0x4e,0x50,0x53,0x28] mtc0 $9,$29,3 mtc1 $s8,$f9 mthi $s1 @@ -185,6 +189,10 @@ negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] neg.d $f27,$f18 neg.s $f1,$f15 + nmadd.d $f18, $f8, $f14, $f20 # encoding: [0x4d,0x14,0x74,0xb1] + nmadd.s $f0, $f4, $f24, $f12 # encoding: [0x4c,0x8c,0xc0,0x30] + nmsub.d $f30, $f8, $f16, $f30 # encoding: [0x4d,0x1e,0x87,0xb9] + nmsub.s $f0, $f24, $f20, $f4 # encoding: [0x4f,0x04,0xa0,0x38] nop nor $a3,$zero,$a3 or $12,$s0,$sp diff --git a/test/MC/Mips/mips64extins.ll b/test/MC/Mips/mips64extins.ll index ebe8f86..093bc87 100644 --- a/test/MC/Mips/mips64extins.ll +++ b/test/MC/Mips/mips64extins.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -mattr=n64 %s -o - \ +; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -target-abi=n64 %s -o - \ ; RUN: | llvm-objdump -disassemble -triple mips64el -mattr +mips64r2 - \ ; RUN: | FileCheck %s diff --git a/test/MC/Mips/mips64r2/abi-bad.s b/test/MC/Mips/mips64r2/abi-bad.s index 31d13ab..7070d45 100644 --- a/test/MC/Mips/mips64r2/abi-bad.s +++ b/test/MC/Mips/mips64r2/abi-bad.s @@ -1,9 +1,5 @@ -# RUN: not llvm-mc %s -triple mips-unknown-unknown -mcpu=mips64r2 2>&1 | FileCheck %s -# CHECK: .text - - - +# RUN: not llvm-mc %s -triple mips-unknown-linux -mcpu=mips64r2 2>&1 | FileCheck %s .set fp=xx -# CHECK : error: 'set fp=xx'option requires O32 ABI -# CHECK : .set fp=xx -# CHECK : ^ +# CHECK: error: '.set fp=xx' requires the O32 ABI +# CHECK: .set fp=xx +# CHECK: ^ diff --git a/test/MC/Mips/mips64r2/valid-xfail.s b/test/MC/Mips/mips64r2/valid-xfail.s index 9ac47f6..148758c 100644 --- a/test/MC/Mips/mips64r2/valid-xfail.s +++ b/test/MC/Mips/mips64r2/valid-xfail.s @@ -176,7 +176,6 @@ lwle $11,-42($11) lwre $sp,-152($24) lwx $12,$12($s4) - madd.d $f18,$f19,$f26,$f20 madd.ps $f22,$f3,$f14,$f3 maq_s.w.phl $ac2,$25,$11 maq_s.w.phr $ac0,$10,$25 @@ -193,7 +192,6 @@ msgn.qh $v0,$v24,$v20 msgn.qh $v12,$v21,$v0[1] msub $ac2,$sp,$14 - msub.d $f10,$f1,$f31,$f18 msub.ps $f12,$f14,$f29,$f17 msubu $ac2,$a1,$24 mtc0 $9,c0_datahi1 @@ -222,9 +220,7 @@ nlzc.d $w14,$w14 nlzc.h $w24,$w24 nlzc.w $w10,$w4 - nmadd.d $f18,$f9,$f14,$f19 nmadd.ps $f27,$f4,$f9,$f25 - nmsub.d $f30,$f8,$f16,$f30 nmsub.ps $f6,$f12,$f14,$f17 nor.v $w20,$w20,$w15 or.v $w13,$w23,$w12 @@ -297,7 +293,6 @@ swe $24,94($k0) swle $v1,-209($gp) swre $k0,-202($s2) - synci 20023($s0) tlbginv tlbginvf tlbgp diff --git a/test/MC/Mips/mips64r3/abi-bad.s b/test/MC/Mips/mips64r3/abi-bad.s new file mode 100644 index 0000000..7691601 --- /dev/null +++ b/test/MC/Mips/mips64r3/abi-bad.s @@ -0,0 +1,5 @@ +# RUN: not llvm-mc %s -triple mips-unknown-linux -mcpu=mips64r3 2>&1 | FileCheck %s + .set fp=xx +# CHECK: error: '.set fp=xx' requires the O32 ABI +# CHECK: .set fp=xx +# CHECK: ^ diff --git a/test/MC/Mips/mips64r3/abiflags.s b/test/MC/Mips/mips64r3/abiflags.s new file mode 100644 index 0000000..e89be29 --- /dev/null +++ b/test/MC/Mips/mips64r3/abiflags.s @@ -0,0 +1,36 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips64r3 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00004003 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } + + .module fp=64 + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips64r3/invalid.s b/test/MC/Mips/mips64r3/invalid.s new file mode 100644 index 0000000..99cd080 --- /dev/null +++ b/test/MC/Mips/mips64r3/invalid.s @@ -0,0 +1,10 @@ +# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. +# invalid set of operands or operand's restrictions not met). + +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r3 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .set noreorder + jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different diff --git a/test/MC/Mips/mips64r3/valid-xfail.s b/test/MC/Mips/mips64r3/valid-xfail.s new file mode 100644 index 0000000..f2949c4 --- /dev/null +++ b/test/MC/Mips/mips64r3/valid-xfail.s @@ -0,0 +1,306 @@ +# Instructions that should be valid but currently fail for known reasons (e.g. +# they aren't implemented yet). +# This test is set up to XPASS if any instruction generates an encoding. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 | not FileCheck %s +# CHECK-NOT: encoding +# XFAIL: * + + .set noat + abs.ps $f22,$f8 + absq_s.ph $8,$a0 + absq_s.qb $15,$s1 + absq_s.w $s3,$ra + add.ps $f25,$f27,$f13 + addq.ph $s1,$15,$at + addq_s.ph $s3,$s6,$s2 + addq_s.w $a2,$8,$at + addqh.ph $s4,$14,$s1 + addqh.w $s7,$s7,$k1 + addqh_r.ph $sp,$25,$s8 + addqh_r.w $8,$v1,$zero + addsc $s8,$15,$12 + addu.ph $a2,$14,$s3 + addu.qb $s6,$v1,$v1 + addu_s.ph $a3,$s3,$gp + addu_s.qb $s4,$s8,$s1 + adduh.qb $a1,$a1,$at + adduh_r.qb $a0,$9,$12 + addwc $k0,$s6,$s7 + alnv.ob $v22,$v19,$v30,$v1 + alnv.ob $v31,$v23,$v30,$at + alnv.ob $v8,$v17,$v30,$a1 + alnv.ps $f12,$f18,$f30,$12 + and.v $w10,$w25,$w29 + bitrev $14,$at + bmnz.v $w15,$w2,$w28 + bmz.v $w13,$w11,$w21 + bsel.v $w28,$w7,$w0 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + cvt.ps.s $f3,$f18,$f19 + cmp.eq.ph $s7,$14 + cmp.le.ph $8,$14 + cmp.lt.ph $k0,$sp + cmpgdu.eq.qb $s3,$zero,$k0 + cmpgdu.le.qb $v1,$15,$s2 + cmpgdu.lt.qb $s0,$gp,$sp + cmpgu.eq.qb $14,$s6,$s8 + cmpgu.le.qb $9,$a3,$s4 + cmpgu.lt.qb $sp,$at,$8 + cmpu.eq.qb $v0,$24 + cmpu.le.qb $s1,$a1 + cmpu.lt.qb $at,$a3 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmfc0 $10,c0_watchhi,2 + dmfgc0 $gp,c0_perfcnt,6 + dmt $k0 + dmtc0 $15,c0_datalo + dmtgc0 $a2,c0_watchlo,2 + dpa.w.ph $ac1,$s7,$k0 + dpaq_s.w.ph $ac2,$a0,$13 + dpaq_sa.l.w $ac0,$a2,$14 + dpaqx_s.w.ph $ac3,$a0,$24 + dpaqx_sa.w.ph $ac1,$zero,$s5 + dpau.h.qbl $ac1,$10,$24 + dpau.h.qbr $ac1,$s7,$s6 + dpax.w.ph $ac3,$a0,$k0 + dps.w.ph $ac1,$a3,$a1 + dpsq_s.w.ph $ac0,$gp,$k0 + dpsq_sa.l.w $ac0,$a3,$15 + dpsqx_s.w.ph $ac3,$13,$a3 + dpsqx_sa.w.ph $ac3,$sp,$s2 + dpsu.h.qbl $ac2,$14,$10 + dpsu.h.qbr $ac2,$a1,$s6 + dpsx.w.ph $ac0,$s7,$gp + drorv $at,$a1,$s7 + dvpe $s6 + emt $8 + evpe $v0 + extpdpv $s6,$ac0,$s8 + extpv $13,$ac0,$14 + extrv.w $8,$ac3,$at + extrv_r.w $8,$ac1,$s6 + extrv_rs.w $gp,$ac1,$s6 + extrv_s.h $s2,$ac1,$14 + fclass.d $w14,$w27 + fclass.w $w19,$w28 + fexupl.d $w10,$w29 + fexupl.w $w12,$w27 + fexupr.d $w31,$w15 + fexupr.w $w29,$w12 + ffint_s.d $w1,$w30 + ffint_s.w $w16,$w14 + ffint_u.d $w23,$w18 + ffint_u.w $w19,$w12 + ffql.d $w2,$w3 + ffql.w $w9,$w0 + ffqr.d $w25,$w24 + ffqr.w $w10,$w6 + fill.b $w9,$v1 + fill.d $w28,$8 + fill.h $w9,$8 + fill.w $w31,$15 + flog2.d $w12,$w16 + flog2.w $w19,$w23 + fork $s2,$8,$a0 + frcp.d $w12,$w4 + frcp.w $w30,$w8 + frint.d $w20,$w8 + frint.w $w11,$w29 + frsqrt.d $w29,$w2 + frsqrt.w $w9,$w8 + fsqrt.d $w3,$w1 + fsqrt.w $w5,$w15 + ftint_s.d $w31,$w26 + ftint_s.w $w27,$w14 + ftint_u.d $w5,$w31 + ftint_u.w $w12,$w29 + ftrunc_s.d $w4,$w22 + ftrunc_s.w $w24,$w7 + ftrunc_u.d $w20,$w25 + ftrunc_u.w $w7,$w26 + insv $s2,$at + iret + lbe $14,122($9) + lbue $11,-108($10) + lbux $9,$14($v0) + lhe $s6,219($v1) + lhue $gp,118($11) + lhx $sp,$k0($15) + lle $gp,-237($ra) + lwe $ra,-145($14) + lwle $11,-42($11) + lwre $sp,-152($24) + lwx $12,$12($s4) + madd.ps $f22,$f3,$f14,$f3 + maq_s.w.phl $ac2,$25,$11 + maq_s.w.phr $ac0,$10,$25 + maq_sa.w.phl $ac3,$a1,$v1 + maq_sa.w.phr $ac1,$at,$10 + mfgc0 $s6,c0_datahi1 + mflo $9,$ac2 + modsub $a3,$12,$a3 + mov.ps $f22,$f17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msgn.qh $v0,$v24,$v20 + msgn.qh $v12,$v21,$v0[1] + msub $ac2,$sp,$14 + msub.ps $f12,$f14,$f29,$f17 + msubu $ac2,$a1,$24 + mtc0 $9,c0_datahi1 + mtgc0 $s4,$21,7 + mthi $v0,$ac1 + mthlip $a3,$ac0 + mul.ph $s4,$24,$s0 + mul.ps $f14,$f0,$f16 + mul_s.ph $10,$14,$15 + muleq_s.w.phl $11,$s4,$s4 + muleq_s.w.phr $s6,$a0,$s8 + muleu_s.ph.qbl $a2,$14,$8 + muleu_s.ph.qbr $a1,$ra,$9 + mulq_rs.ph $s2,$14,$15 + mulq_rs.w $at,$s4,$25 + mulq_s.ph $s0,$k1,$15 + mulq_s.w $9,$a3,$s0 + mulsa.w.ph $ac1,$s4,$s6 + mulsaq_s.w.ph $ac0,$ra,$s2 + neg.ps $f19,$f13 + nloc.b $w12,$w30 + nloc.d $w16,$w7 + nloc.h $w21,$w17 + nloc.w $w17,$w16 + nlzc.b $w12,$w7 + nlzc.d $w14,$w14 + nlzc.h $w24,$w24 + nlzc.w $w10,$w4 + nmadd.ps $f27,$f4,$f9,$f25 + nmsub.ps $f6,$f12,$f14,$f17 + nor.v $w20,$w20,$w15 + or.v $w13,$w23,$w12 + packrl.ph $ra,$24,$14 + pcnt.b $w30,$w15 + pcnt.d $w5,$w16 + pcnt.h $w20,$w24 + pcnt.w $w22,$w20 + pick.ph $ra,$a2,$gp + pick.qb $11,$a0,$gp + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + preceq.w.phl $s8,$gp + preceq.w.phr $s5,$15 + precequ.ph.qbl $s7,$ra + precequ.ph.qbla $a0,$9 + precequ.ph.qbr $ra,$s3 + precequ.ph.qbra $24,$8 + preceu.ph.qbl $sp,$8 + preceu.ph.qbla $s6,$11 + preceu.ph.qbr $gp,$s1 + preceu.ph.qbra $k1,$s0 + precr.qb.ph $v0,$12,$s8 + precrq.ph.w $14,$s8,$24 + precrq.qb.ph $a2,$12,$12 + precrq_rs.ph.w $a1,$k0,$a3 + precrqu_s.qb.ph $zero,$gp,$s5 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + raddu.w.qb $25,$s3 + rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 + repl.ph $at,-307 + replv.ph $v1,$s7 + replv.qb $25,$12 + rorv $13,$a3,$s5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sbe $s7,33($s1) + sce $sp,189($10) + she $24,105($v0) + shilo $ac1,26 + shilov $ac2,$10 + shllv.ph $10,$s0,$s0 + shllv.qb $gp,$v1,$zero + shllv_s.ph $k1,$at,$13 + shllv_s.w $s1,$ra,$k0 + shrav.ph $25,$s2,$s1 + shrav.qb $zero,$24,$11 + shrav_r.ph $s3,$11,$25 + shrav_r.qb $a0,$sp,$s5 + shrav_r.w $s7,$s4,$s6 + shrlv.ph $14,$10,$9 + shrlv.qb $a2,$s2,$11 + sub.ps $f5,$f14,$f26 + subq.ph $ra,$9,$s8 + subq_s.ph $13,$s8,$s5 + subq_s.w $k1,$a2,$a3 + subqh.ph $10,$at,$9 + subqh.w $v0,$a2,$zero + subqh_r.ph $a0,$12,$s6 + subqh_r.w $10,$a2,$gp + subu.ph $9,$s6,$s4 + subu.qb $s6,$a2,$s6 + subu_s.ph $v1,$a1,$s3 + subu_s.qb $s1,$at,$ra + subuh.qb $zero,$gp,$gp + subuh_r.qb $s4,$s8,$s6 + swe $24,94($k0) + swle $v1,-209($gp) + swre $k0,-202($s2) + tlbginv + tlbginvf + tlbgp + tlbgr + tlbgwi + tlbgwr + tlbinv + tlbinvf + wrpgpr $zero,$13 + xor.v $w20,$w21,$w30 + yield $v1,$s0 diff --git a/test/MC/Mips/mips64r3/valid.s b/test/MC/Mips/mips64r3/valid.s new file mode 100644 index 0000000..d8f1721 --- /dev/null +++ b/test/MC/Mips/mips64r3/valid.s @@ -0,0 +1,305 @@ +# Instructions that are valid +# +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r3 | FileCheck %s + + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] + addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] + and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] + daddi $sp,$s4,-27705 + daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24] + deret + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa] + drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa] + drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe] + drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe] + drotrv $1,$14,$15 # CHECK: drotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x56] + dsbh $v1,$14 + dshd $v0,$sp + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsub $a3,$s6,$8 + dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubu $a1,$a1,$k0 + dsubu $a1,$a1,$k0 + dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] + jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] + jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70] + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + madd.s $f1,$f31,$f19,$f25 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhc1 $s8,$f24 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msub.s $f12,$f19,$f10,$f16 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthc1 $zero,$f16 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.s $f1,$f24,$f19,$f4 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] + pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] + rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] + rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] + rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] + sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + seb $25,$15 + seh $v1,$12 + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] + teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] + tgei $s1,5025 + tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] + tlti $14,-21059 + tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 + wsbh $k1,$9 diff --git a/test/MC/Mips/mips64r5/abi-bad.s b/test/MC/Mips/mips64r5/abi-bad.s new file mode 100644 index 0000000..c6bb29a --- /dev/null +++ b/test/MC/Mips/mips64r5/abi-bad.s @@ -0,0 +1,5 @@ +# RUN: not llvm-mc %s -triple mips-unknown-linux -mcpu=mips64r5 2>&1 | FileCheck %s + .set fp=xx +# CHECK: error: '.set fp=xx' requires the O32 ABI +# CHECK: .set fp=xx +# CHECK: ^ diff --git a/test/MC/Mips/mips64r5/abiflags.s b/test/MC/Mips/mips64r5/abiflags.s new file mode 100644 index 0000000..43a5fe6 --- /dev/null +++ b/test/MC/Mips/mips64r5/abiflags.s @@ -0,0 +1,36 @@ +# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 | \ +# RUN: FileCheck %s -check-prefix=CHECK-ASM +# +# RUN: llvm-mc %s -arch=mips -mcpu=mips64r5 -filetype=obj -o - | \ +# RUN: llvm-readobj -sections -section-data -section-relocations - | \ +# RUN: FileCheck %s -check-prefix=CHECK-OBJ + +# CHECK-ASM: .module fp=64 + +# Checking if the Mips.abiflags were correctly emitted. +# CHECK-OBJ: Section { +# CHECK-OBJ: Index: 5 +# CHECK-OBJ-LABEL: Name: .MIPS.abiflags +# CHECK-OBJ: Type: SHT_MIPS_ABIFLAGS (0x7000002A) +# CHECK-OBJ: Flags [ (0x2) +# CHECK-OBJ: SHF_ALLOC (0x2) +# CHECK-OBJ: ] +# CHECK-OBJ: Address: 0x0 +# CHECK-OBJ: Size: 24 +# CHECK-OBJ: Link: 0 +# CHECK-OBJ: Info: 0 +# CHECK-OBJ: AddressAlignment: 8 +# CHECK-OBJ: EntrySize: 24 +# CHECK-OBJ: Relocations [ +# CHECK-OBJ: ] +# CHECK-OBJ: SectionData ( +# CHECK-OBJ: 0000: 00004005 02020001 00000000 00000000 |..@.............| +# CHECK-OBJ: 0010: 00000001 00000000 |........| +# CHECK-OBJ: ) +# CHECK-OBJ-LABEL: } + + .module fp=64 + +# FIXME: Test should include gnu_attributes directive when implemented. +# An explicit .gnu_attribute must be checked against the effective +# command line options and any inconsistencies reported via a warning. diff --git a/test/MC/Mips/mips64r5/invalid.s b/test/MC/Mips/mips64r5/invalid.s new file mode 100644 index 0000000..8319deb --- /dev/null +++ b/test/MC/Mips/mips64r5/invalid.s @@ -0,0 +1,10 @@ +# Instructions that are valid for the current ISA but should be rejected by the assembler (e.g. +# invalid set of operands or operand's restrictions not met). + +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -mcpu=mips64r5 2>%t1 +# RUN: FileCheck %s < %t1 -check-prefix=ASM + + .text + .set noreorder + jalr.hb $31 # ASM: :[[@LINE]]:9: error: source and destination must be different + jalr.hb $31, $31 # ASM: :[[@LINE]]:9: error: source and destination must be different diff --git a/test/MC/Mips/mips64r5/valid-xfail.s b/test/MC/Mips/mips64r5/valid-xfail.s new file mode 100644 index 0000000..04221dd --- /dev/null +++ b/test/MC/Mips/mips64r5/valid-xfail.s @@ -0,0 +1,306 @@ +# Instructions that should be valid but currently fail for known reasons (e.g. +# they aren't implemented yet). +# This test is set up to XPASS if any instruction generates an encoding. +# +# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 | not FileCheck %s +# CHECK-NOT: encoding +# XFAIL: * + + .set noat + abs.ps $f22,$f8 + absq_s.ph $8,$a0 + absq_s.qb $15,$s1 + absq_s.w $s3,$ra + add.ps $f25,$f27,$f13 + addq.ph $s1,$15,$at + addq_s.ph $s3,$s6,$s2 + addq_s.w $a2,$8,$at + addqh.ph $s4,$14,$s1 + addqh.w $s7,$s7,$k1 + addqh_r.ph $sp,$25,$s8 + addqh_r.w $8,$v1,$zero + addsc $s8,$15,$12 + addu.ph $a2,$14,$s3 + addu.qb $s6,$v1,$v1 + addu_s.ph $a3,$s3,$gp + addu_s.qb $s4,$s8,$s1 + adduh.qb $a1,$a1,$at + adduh_r.qb $a0,$9,$12 + addwc $k0,$s6,$s7 + alnv.ob $v22,$v19,$v30,$v1 + alnv.ob $v31,$v23,$v30,$at + alnv.ob $v8,$v17,$v30,$a1 + alnv.ps $f12,$f18,$f30,$12 + and.v $w10,$w25,$w29 + bitrev $14,$at + bmnz.v $w15,$w2,$w28 + bmz.v $w13,$w11,$w21 + bsel.v $w28,$w7,$w0 + c.eq.d $fcc1,$f15,$f15 + c.eq.ps $fcc5,$f0,$f9 + c.eq.s $fcc5,$f24,$f17 + c.f.d $fcc4,$f11,$f21 + c.f.ps $fcc6,$f11,$f11 + c.f.s $fcc4,$f30,$f7 + c.le.d $fcc4,$f18,$f1 + c.le.ps $fcc1,$f7,$f20 + c.le.s $fcc6,$f24,$f4 + c.lt.d $fcc3,$f9,$f3 + c.lt.ps $f19,$f5 + c.lt.s $fcc2,$f17,$f14 + c.nge.d $fcc5,$f21,$f16 + c.nge.ps $f1,$f26 + c.nge.s $fcc3,$f11,$f8 + c.ngl.ps $f21,$f30 + c.ngl.s $fcc2,$f31,$f23 + c.ngle.ps $fcc7,$f12,$f20 + c.ngle.s $fcc2,$f18,$f23 + c.ngt.d $fcc4,$f24,$f7 + c.ngt.ps $fcc5,$f30,$f6 + c.ngt.s $fcc5,$f8,$f13 + c.ole.d $fcc2,$f16,$f31 + c.ole.ps $fcc7,$f21,$f8 + c.ole.s $fcc3,$f7,$f20 + c.olt.d $fcc4,$f19,$f28 + c.olt.ps $fcc3,$f7,$f16 + c.olt.s $fcc6,$f20,$f7 + c.seq.d $fcc4,$f31,$f7 + c.seq.ps $fcc6,$f31,$f14 + c.seq.s $fcc7,$f1,$f25 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.d $fcc4,$f13,$f25 + c.ueq.ps $fcc1,$f5,$f29 + c.ueq.s $fcc6,$f3,$f30 + c.ule.d $fcc7,$f25,$f18 + c.ule.ps $fcc6,$f17,$f3 + c.ule.s $fcc7,$f21,$f30 + c.ult.d $fcc6,$f6,$f17 + c.ult.ps $fcc7,$f14,$f0 + c.ult.s $fcc7,$f24,$f10 + c.un.d $fcc6,$f23,$f24 + c.un.ps $fcc4,$f2,$f26 + c.un.s $fcc1,$f30,$f4 + cvt.ps.s $f3,$f18,$f19 + cmp.eq.ph $s7,$14 + cmp.le.ph $8,$14 + cmp.lt.ph $k0,$sp + cmpgdu.eq.qb $s3,$zero,$k0 + cmpgdu.le.qb $v1,$15,$s2 + cmpgdu.lt.qb $s0,$gp,$sp + cmpgu.eq.qb $14,$s6,$s8 + cmpgu.le.qb $9,$a3,$s4 + cmpgu.lt.qb $sp,$at,$8 + cmpu.eq.qb $v0,$24 + cmpu.le.qb $s1,$a1 + cmpu.lt.qb $at,$a3 + cvt.s.pl $f30,$f1 + cvt.s.pu $f14,$f25 + dmfc0 $10,c0_watchhi,2 + dmfgc0 $gp,c0_perfcnt,6 + dmt $k0 + dmtc0 $15,c0_datalo + dmtgc0 $a2,c0_watchlo,2 + dpa.w.ph $ac1,$s7,$k0 + dpaq_s.w.ph $ac2,$a0,$13 + dpaq_sa.l.w $ac0,$a2,$14 + dpaqx_s.w.ph $ac3,$a0,$24 + dpaqx_sa.w.ph $ac1,$zero,$s5 + dpau.h.qbl $ac1,$10,$24 + dpau.h.qbr $ac1,$s7,$s6 + dpax.w.ph $ac3,$a0,$k0 + dps.w.ph $ac1,$a3,$a1 + dpsq_s.w.ph $ac0,$gp,$k0 + dpsq_sa.l.w $ac0,$a3,$15 + dpsqx_s.w.ph $ac3,$13,$a3 + dpsqx_sa.w.ph $ac3,$sp,$s2 + dpsu.h.qbl $ac2,$14,$10 + dpsu.h.qbr $ac2,$a1,$s6 + dpsx.w.ph $ac0,$s7,$gp + drorv $at,$a1,$s7 + dvpe $s6 + emt $8 + evpe $v0 + extpdpv $s6,$ac0,$s8 + extpv $13,$ac0,$14 + extrv.w $8,$ac3,$at + extrv_r.w $8,$ac1,$s6 + extrv_rs.w $gp,$ac1,$s6 + extrv_s.h $s2,$ac1,$14 + fclass.d $w14,$w27 + fclass.w $w19,$w28 + fexupl.d $w10,$w29 + fexupl.w $w12,$w27 + fexupr.d $w31,$w15 + fexupr.w $w29,$w12 + ffint_s.d $w1,$w30 + ffint_s.w $w16,$w14 + ffint_u.d $w23,$w18 + ffint_u.w $w19,$w12 + ffql.d $w2,$w3 + ffql.w $w9,$w0 + ffqr.d $w25,$w24 + ffqr.w $w10,$w6 + fill.b $w9,$v1 + fill.d $w28,$8 + fill.h $w9,$8 + fill.w $w31,$15 + flog2.d $w12,$w16 + flog2.w $w19,$w23 + fork $s2,$8,$a0 + frcp.d $w12,$w4 + frcp.w $w30,$w8 + frint.d $w20,$w8 + frint.w $w11,$w29 + frsqrt.d $w29,$w2 + frsqrt.w $w9,$w8 + fsqrt.d $w3,$w1 + fsqrt.w $w5,$w15 + ftint_s.d $w31,$w26 + ftint_s.w $w27,$w14 + ftint_u.d $w5,$w31 + ftint_u.w $w12,$w29 + ftrunc_s.d $w4,$w22 + ftrunc_s.w $w24,$w7 + ftrunc_u.d $w20,$w25 + ftrunc_u.w $w7,$w26 + insv $s2,$at + iret + lbe $14,122($9) + lbue $11,-108($10) + lbux $9,$14($v0) + lhe $s6,219($v1) + lhue $gp,118($11) + lhx $sp,$k0($15) + lle $gp,-237($ra) + lwe $ra,-145($14) + lwle $11,-42($11) + lwre $sp,-152($24) + lwx $12,$12($s4) + madd.ps $f22,$f3,$f14,$f3 + maq_s.w.phl $ac2,$25,$11 + maq_s.w.phr $ac0,$10,$25 + maq_sa.w.phl $ac3,$a1,$v1 + maq_sa.w.phr $ac1,$at,$10 + mfgc0 $s6,c0_datahi1 + mflo $9,$ac2 + modsub $a3,$12,$a3 + mov.ps $f22,$f17 + movf.ps $f10,$f28,$fcc6 + movn.ps $f31,$f31,$s3 + movt.ps $f20,$f25,$fcc2 + movz.ps $f18,$f17,$ra + msgn.qh $v0,$v24,$v20 + msgn.qh $v12,$v21,$v0[1] + msub $ac2,$sp,$14 + msub.ps $f12,$f14,$f29,$f17 + msubu $ac2,$a1,$24 + mtc0 $9,c0_datahi1 + mtgc0 $s4,$21,7 + mthi $v0,$ac1 + mthlip $a3,$ac0 + mul.ph $s4,$24,$s0 + mul.ps $f14,$f0,$f16 + mul_s.ph $10,$14,$15 + muleq_s.w.phl $11,$s4,$s4 + muleq_s.w.phr $s6,$a0,$s8 + muleu_s.ph.qbl $a2,$14,$8 + muleu_s.ph.qbr $a1,$ra,$9 + mulq_rs.ph $s2,$14,$15 + mulq_rs.w $at,$s4,$25 + mulq_s.ph $s0,$k1,$15 + mulq_s.w $9,$a3,$s0 + mulsa.w.ph $ac1,$s4,$s6 + mulsaq_s.w.ph $ac0,$ra,$s2 + neg.ps $f19,$f13 + nloc.b $w12,$w30 + nloc.d $w16,$w7 + nloc.h $w21,$w17 + nloc.w $w17,$w16 + nlzc.b $w12,$w7 + nlzc.d $w14,$w14 + nlzc.h $w24,$w24 + nlzc.w $w10,$w4 + nmadd.ps $f27,$f4,$f9,$f25 + nmsub.ps $f6,$f12,$f14,$f17 + nor.v $w20,$w20,$w15 + or.v $w13,$w23,$w12 + packrl.ph $ra,$24,$14 + pcnt.b $w30,$w15 + pcnt.d $w5,$w16 + pcnt.h $w20,$w24 + pcnt.w $w22,$w20 + pick.ph $ra,$a2,$gp + pick.qb $11,$a0,$gp + pll.ps $f25,$f9,$f30 + plu.ps $f1,$f26,$f29 + preceq.w.phl $s8,$gp + preceq.w.phr $s5,$15 + precequ.ph.qbl $s7,$ra + precequ.ph.qbla $a0,$9 + precequ.ph.qbr $ra,$s3 + precequ.ph.qbra $24,$8 + preceu.ph.qbl $sp,$8 + preceu.ph.qbla $s6,$11 + preceu.ph.qbr $gp,$s1 + preceu.ph.qbra $k1,$s0 + precr.qb.ph $v0,$12,$s8 + precrq.ph.w $14,$s8,$24 + precrq.qb.ph $a2,$12,$12 + precrq_rs.ph.w $a1,$k0,$a3 + precrqu_s.qb.ph $zero,$gp,$s5 + pul.ps $f9,$f30,$f26 + puu.ps $f24,$f9,$f2 + raddu.w.qb $25,$s3 + rdpgpr $s3,$9 + recip.d $f19,$f6 + recip.s $f3,$f30 + repl.ph $at,-307 + replv.ph $v1,$s7 + replv.qb $25,$12 + rorv $13,$a3,$s5 + rsqrt.d $f3,$f28 + rsqrt.s $f4,$f8 + sbe $s7,33($s1) + sce $sp,189($10) + she $24,105($v0) + shilo $ac1,26 + shilov $ac2,$10 + shllv.ph $10,$s0,$s0 + shllv.qb $gp,$v1,$zero + shllv_s.ph $k1,$at,$13 + shllv_s.w $s1,$ra,$k0 + shrav.ph $25,$s2,$s1 + shrav.qb $zero,$24,$11 + shrav_r.ph $s3,$11,$25 + shrav_r.qb $a0,$sp,$s5 + shrav_r.w $s7,$s4,$s6 + shrlv.ph $14,$10,$9 + shrlv.qb $a2,$s2,$11 + sub.ps $f5,$f14,$f26 + subq.ph $ra,$9,$s8 + subq_s.ph $13,$s8,$s5 + subq_s.w $k1,$a2,$a3 + subqh.ph $10,$at,$9 + subqh.w $v0,$a2,$zero + subqh_r.ph $a0,$12,$s6 + subqh_r.w $10,$a2,$gp + subu.ph $9,$s6,$s4 + subu.qb $s6,$a2,$s6 + subu_s.ph $v1,$a1,$s3 + subu_s.qb $s1,$at,$ra + subuh.qb $zero,$gp,$gp + subuh_r.qb $s4,$s8,$s6 + swe $24,94($k0) + swle $v1,-209($gp) + swre $k0,-202($s2) + tlbginv + tlbginvf + tlbgp + tlbgr + tlbgwi + tlbgwr + tlbinv + tlbinvf + wrpgpr $zero,$13 + xor.v $w20,$w21,$w30 + yield $v1,$s0 diff --git a/test/MC/Mips/mips64r5/valid.s b/test/MC/Mips/mips64r5/valid.s new file mode 100644 index 0000000..1706852 --- /dev/null +++ b/test/MC/Mips/mips64r5/valid.s @@ -0,0 +1,305 @@ +# Instructions that are valid +# +# RUN: llvm-mc %s -triple=mips64-unknown-linux -show-encoding -mcpu=mips64r5 | FileCheck %s + + .set noat + abs.d $f7,$f25 # CHECK: encoding: + abs.s $f9,$f16 + add $s7,$s2,$a1 + add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] + add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] + add.d $f1,$f7,$f29 + add.s $f8,$f21,$f24 + addi $13,$9,26322 + addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] + addu $9,$a0,$a2 + addu $9,10 # CHECK: addiu $9, $9, 10 # encoding: [0x25,0x29,0x00,0x0a] + and $s7,$v0,$12 + and $2,4 # CHECK: andi $2, $2, 4 # encoding: [0x30,0x42,0x00,0x04] + bc1f $fcc0, 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1f $fcc1, 4 # CHECK: bc1f $fcc1, 4 # encoding: [0x45,0x04,0x00,0x01] + bc1f 4 # CHECK: bc1f 4 # encoding: [0x45,0x00,0x00,0x01] + bc1fl $fcc0,4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl 4688 # CHECK: bc1fl 4688 # encoding: [0x45,0x02,0x04,0x94] + bc1fl $fcc7,27 # CHECK: bc1fl $fcc7, 27 # encoding: [0x45,0x1e,0x00,0x06] + bc1t $fcc0, 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x45,0x05,0x00,0x01] + bc1t 4 # CHECK: bc1t 4 # encoding: [0x45,0x01,0x00,0x01] + bc1tl $fcc0,4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl 4688 # CHECK: bc1tl 4688 # encoding: [0x45,0x03,0x04,0x94] + bc1tl $fcc7,27 # CHECK: bc1tl $fcc7, 27 # encoding: [0x45,0x1f,0x00,0x06] + bal 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $0, 21100 # CHECK: bal 21100 # encoding: [0x04,0x11,0x14,0x9b] + bgezal $6, 21100 # CHECK: bgezal $6, 21100 # encoding: [0x04,0xd1,0x14,0x9b] + bltzal $6, 21100 # CHECK: bltzal $6, 21100 # encoding: [0x04,0xd0,0x14,0x9b] + beql $14,$s3,12544 # CHECK: beql $14, $19, 12544 # encoding: [0x51,0xd3,0x0c,0x40] + bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f] + bgezl $4,-6858 # CHECK: bgezl $4, -6858 # encoding: [0x04,0x83,0xf9,0x4d] + bgtzl $10,-3738 # CHECK: bgtzl $10, -3738 # encoding: [0x5d,0x40,0xfc,0x59] + blezl $6,2974 # CHECK: blezl $6, 2974 # encoding: [0x58,0xc0,0x02,0xe7] + bltzall $6,488 # CHECK: bltzall $6, 488 # encoding: [0x04,0xd2,0x00,0x7a] + bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] + bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] + cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] + c.ngl.d $f29,$f29 + c.ngle.d $f0,$f16 + c.sf.d $f30,$f0 + c.sf.s $f14,$f22 + ceil.l.d $f1,$f3 + ceil.l.s $f18,$f13 + ceil.w.d $f11,$f25 + ceil.w.s $f6,$f20 + cfc1 $s1,$21 + clo $11,$a1 # CHECK: clo $11, $5 # encoding: [0x70,0xab,0x58,0x21] + clz $sp,$gp # CHECK: clz $sp, $gp # encoding: [0x73,0x9d,0xe8,0x20] + ctc1 $a2,$26 + cvt.d.l $f4,$f16 + cvt.d.s $f22,$f28 + cvt.d.w $f26,$f11 + cvt.l.d $f24,$f15 + cvt.l.s $f11,$f29 + cvt.s.d $f26,$f8 + cvt.s.l $f15,$f30 + cvt.s.w $f22,$f15 + cvt.w.d $f20,$f14 + cvt.w.s $f20,$f24 + dadd $s3,$at,$ra + dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] + daddi $sp,$s4,-27705 + daddi $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7] + daddi $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7] + daddiu $k0,$s6,-4586 + daddu $s3,$at,$ra + daddu $24,$2,18079 # CHECK: daddiu $24, $2, 18079 # encoding: [0x64,0x58,0x46,0x9f] + daddu $19,26943 # CHECK: daddiu $19, $19, 26943 # encoding: [0x66,0x73,0x69,0x3f] + dclo $s2,$a2 # CHECK: dclo $18, $6 # encoding: [0x70,0xd2,0x90,0x25] + dclz $s0,$25 # CHECK: dclz $16, $25 # encoding: [0x73,0x30,0x80,0x24] + deret + di $s8 # CHECK: di $fp # encoding: [0x41,0x7e,0x60,0x00] + di # CHECK: di # encoding: [0x41,0x60,0x60,0x00] + ddiv $zero,$k0,$s3 + ddivu $zero,$s0,$s1 + div $zero,$25,$11 + div.d $f29,$f20,$f27 + div.s $f4,$f5,$f15 + divu $zero,$25,$15 + dmfc1 $12,$f13 + dmtc1 $s0,$f14 + dmult $s7,$9 + dmultu $a1,$a2 + drotr $1,15 # CHECK: drotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfa] + drotr $1,$14,15 # CHECK: drotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfa] + drotr32 $1,15 # CHECK: drotr32 $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xfe] + drotr32 $1,$14,15 # CHECK: drotr32 $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xfe] + drotrv $1,$14,$15 # CHECK: drotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x56] + dsbh $v1,$14 + dshd $v0,$sp + dsll $zero,18 # CHECK: dsll $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xb8] + dsll $zero,$s4,18 # CHECK: dsll $zero, $20, 18 # encoding: [0x00,0x14,0x04,0xb8] + dsll $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsll32 $zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsll32 $zero,$zero,18 # CHECK: dsll32 $zero, $zero, 18 # encoding: [0x00,0x00,0x04,0xbc] + dsllv $zero,$s4,$12 # CHECK: dsllv $zero, $20, $12 # encoding: [0x01,0x94,0x00,0x14] + dsra $gp,10 # CHECK: dsra $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbb] + dsra $gp,$s2,10 # CHECK: dsra $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbb] + dsra $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsra32 $gp,10 # CHECK: dsra32 $gp, $gp, 10 # encoding: [0x00,0x1c,0xe2,0xbf] + dsra32 $gp,$s2,10 # CHECK: dsra32 $gp, $18, 10 # encoding: [0x00,0x12,0xe2,0xbf] + dsrav $gp,$s2,$s3 # CHECK: dsrav $gp, $18, $19 # encoding: [0x02,0x72,0xe0,0x17] + dsrl $s3,23 # CHECK: dsrl $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfa] + dsrl $s3,$6,23 # CHECK: dsrl $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfa] + dsrl $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsrl32 $s3,23 # CHECK: dsrl32 $19, $19, 23 # encoding: [0x00,0x13,0x9d,0xfe] + dsrl32 $s3,$6,23 # CHECK: dsrl32 $19, $6, 23 # encoding: [0x00,0x06,0x9d,0xfe] + dsrlv $s3,$6,$s4 # CHECK: dsrlv $19, $6, $20 # encoding: [0x02,0x86,0x98,0x16] + dsub $a3,$s6,$8 + dsub $a3,$s6,$8 + dsub $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsub $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubi $sp,$s4,-27705 # CHECK: daddi $sp, $20, 27705 # encoding: [0x62,0x9d,0x6c,0x39] + dsubi $sp,-27705 # CHECK: daddi $sp, $sp, 27705 # encoding: [0x63,0xbd,0x6c,0x39] + dsubu $a1,$a1,$k0 + dsubu $a1,$a1,$k0 + dsubu $15,$11,5025 # CHECK: daddiu $15, $11, -5025 # encoding: [0x65,0x6f,0xec,0x5f] + dsubu $14,-4586 # CHECK: daddiu $14, $14, 4586 # encoding: [0x65,0xce,0x11,0xea] + ehb # CHECK: ehb # encoding: [0x00,0x00,0x00,0xc0] + ei $14 # CHECK: ei $14 # encoding: [0x41,0x6e,0x60,0x20] + ei # CHECK: ei # encoding: [0x41,0x60,0x60,0x20] + eret + floor.l.d $f26,$f7 + floor.l.s $f12,$f5 + floor.w.d $f14,$f11 + floor.w.s $f8,$f9 + jr.hb $4 # CHECK: jr.hb $4 # encoding: [0x00,0x80,0x04,0x08] + jalr.hb $4 # CHECK: jalr.hb $4 # encoding: [0x00,0x80,0xfc,0x09] + jalr.hb $4, $5 # CHECK: jalr.hb $4, $5 # encoding: [0x00,0xa0,0x24,0x09] + lb $24,-14515($10) + lbu $8,30195($v1) + ld $sp,-28645($s1) + ldc1 $f11,16391($s0) + ldc2 $8,-21181($at) # CHECK: ldc2 $8, -21181($1) # encoding: [0xd8,0x28,0xad,0x43] + ldl $24,-4167($24) + ldr $14,-30358($s4) + ldxc1 $f8,$s7($15) + lh $11,-8556($s5) + lhu $s3,-22851($v0) + li $at,-29773 + li $zero,-29889 + ll $v0,-7321($s2) # CHECK: ll $2, -7321($18) # encoding: [0xc2,0x42,0xe3,0x67] + lld $zero,-14736($ra) # CHECK: lld $zero, -14736($ra) # encoding: [0xd3,0xe0,0xc6,0x70] + luxc1 $f19,$s6($s5) + lw $8,5674($a1) + lwc1 $f16,10225($k0) + lwc2 $18,-841($a2) # CHECK: lwc2 $18, -841($6) # encoding: [0xc8,0xd2,0xfc,0xb7] + lwl $s4,-4231($15) + lwr $zero,-19147($gp) + lwu $s3,-24086($v1) + lwxc1 $f12,$s1($s8) + madd $s6,$13 + madd $zero,$9 + madd.s $f1,$f31,$f19,$f25 + maddu $s3,$gp + maddu $24,$s2 + mfc0 $a2,$14,1 + mfc1 $a3,$f27 + mfhc1 $s8,$f24 + mfhi $s3 + mfhi $sp + mflo $s1 + mov.d $f20,$f14 + mov.s $f2,$f27 + move $a0,$a3 + move $s5,$a0 + move $s8,$a0 + move $25,$a2 + movf $gp,$8,$fcc7 + movf.d $f6,$f11,$fcc5 + movf.s $f23,$f5,$fcc6 + movn $v1,$s1,$s0 + movn.d $f27,$f21,$k0 + movn.s $f12,$f0,$s7 + movt $zero,$s4,$fcc5 + movt.d $f0,$f2,$fcc0 + movt.s $f30,$f2,$fcc1 + movz $a1,$s6,$9 + movz.d $f12,$f29,$9 + movz.s $f25,$f7,$v1 + msub $s7,$k1 + msub.s $f12,$f19,$f10,$f16 + msubu $15,$a1 + mtc0 $9,$29,3 + mtc1 $s8,$f9 + mthc1 $zero,$f16 + mthi $s1 + mtlo $sp + mtlo $25 + mul $s0,$s4,$at + mul.d $f20,$f20,$f16 + mul.s $f30,$f10,$f2 + mult $sp,$s4 + mult $sp,$v0 + multu $gp,$k0 + multu $9,$s2 + negu $2 # CHECK: negu $2, $2 # encoding: [0x00,0x02,0x10,0x23] + negu $2,$3 # CHECK: negu $2, $3 # encoding: [0x00,0x03,0x10,0x23] + neg.d $f27,$f18 + neg.s $f1,$f15 + nmadd.s $f0,$f5,$f25,$f12 + nmsub.s $f1,$f24,$f19,$f4 + nop + nor $a3,$zero,$a3 + or $12,$s0,$sp + or $2, 4 # CHECK: ori $2, $2, 4 # encoding: [0x34,0x42,0x00,0x04] + pause # CHECK: pause # encoding: [0x00,0x00,0x01,0x40] + pref 1, 8($5) # CHECK: pref 1, 8($5) # encoding: [0xcc,0xa1,0x00,0x08] + # FIXME: Use the code generator in order to print the .set directives + # instead of the instruction printer. + rdhwr $sp,$11 # CHECK: .set push + # CHECK-NEXT: .set mips32r2 + # CHECK-NEXT: rdhwr $sp, $11 + # CHECK-NEXT: .set pop # encoding: [0x7c,0x1d,0x58,0x3b] + rotr $1,15 # CHECK: rotr $1, $1, 15 # encoding: [0x00,0x21,0x0b,0xc2] + rotr $1,$14,15 # CHECK: rotr $1, $14, 15 # encoding: [0x00,0x2e,0x0b,0xc2] + rotrv $1,$14,$15 # CHECK: rotrv $1, $14, $15 # encoding: [0x01,0xee,0x08,0x46] + round.l.d $f12,$f1 + round.l.s $f25,$f5 + round.w.d $f6,$f4 + round.w.s $f27,$f28 + sb $s6,-19857($14) + sc $15,18904($s3) # CHECK: sc $15, 18904($19) # encoding: [0xe2,0x6f,0x49,0xd8] + scd $15,-8243($sp) # CHECK: scd $15, -8243($sp) # encoding: [0xf3,0xaf,0xdf,0xcd] + sdbbp # CHECK: sdbbp # encoding: [0x70,0x00,0x00,0x3f] + sdbbp 34 # CHECK: sdbbp 34 # encoding: [0x70,0x00,0x08,0xbf] + sd $12,5835($10) + sdc1 $f31,30574($13) + sdc2 $20,23157($s2) # CHECK: sdc2 $20, 23157($18) # encoding: [0xfa,0x54,0x5a,0x75] + sdl $a3,-20961($s8) + sdr $11,-20423($12) + sdxc1 $f11,$10($14) + seb $25,$15 + seh $v1,$12 + sh $14,-6704($15) + sll $a3,18 # CHECK: sll $7, $7, 18 # encoding: [0x00,0x07,0x3c,0x80] + sll $a3,$zero,18 # CHECK: sll $7, $zero, 18 # encoding: [0x00,0x00,0x3c,0x80] + sll $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + sllv $a3,$zero,$9 # CHECK: sllv $7, $zero, $9 # encoding: [0x01,0x20,0x38,0x04] + slt $s7,$11,$k1 # CHECK: slt $23, $11, $27 # encoding: [0x01,0x7b,0xb8,0x2a] + slti $s1,$10,9489 # CHECK: slti $17, $10, 9489 # encoding: [0x29,0x51,0x25,0x11] + sltiu $25,$25,-15531 # CHECK: sltiu $25, $25, -15531 # encoding: [0x2f,0x39,0xc3,0x55] + sltu $s4,$s5,$11 # CHECK: sltu $20, $21, $11 # encoding: [0x02,0xab,0xa0,0x2b] + sltu $24,$25,-15531 # CHECK: sltiu $24, $25, -15531 # encoding: [0x2f,0x38,0xc3,0x55] + sqrt.d $f17,$f22 + sqrt.s $f0,$f1 + sra $s1,15 # CHECK: sra $17, $17, 15 # encoding: [0x00,0x11,0x8b,0xc3] + sra $s1,$s7,15 # CHECK: sra $17, $23, 15 # encoding: [0x00,0x17,0x8b,0xc3] + sra $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srav $s1,$s7,$sp # CHECK: srav $17, $23, $sp # encoding: [0x03,0xb7,0x88,0x07] + srl $2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $2,$2,7 # CHECK: srl $2, $2, 7 # encoding: [0x00,0x02,0x11,0xc2] + srl $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + srlv $25,$s4,$a0 # CHECK: srlv $25, $20, $4 # encoding: [0x00,0x94,0xc8,0x06] + ssnop # CHECK: ssnop # encoding: [0x00,0x00,0x00,0x40] + sub $s6,$s3,$12 + sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] + sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] + sub.d $f18,$f3,$f17 + sub.s $f23,$f22,$f22 + subu $sp,$s6,$s6 + suxc1 $f12,$k1($13) + sw $ra,-10160($sp) + swc1 $f6,-8465($24) + swc2 $25,24880($s0) # CHECK: swc2 $25, 24880($16) # encoding: [0xea,0x19,0x61,0x30] + swl $15,13694($s3) + swr $s1,-26590($14) + swxc1 $f19,$12($k0) + sync # CHECK: sync # encoding: [0x00,0x00,0x00,0x0f] + sync 1 # CHECK: sync 1 # encoding: [0x00,0x00,0x00,0x4f] + teq $0,$3 # CHECK: teq $zero, $3 # encoding: [0x00,0x03,0x00,0x34] + teq $5,$7,620 # CHECK: teq $5, $7, 620 # encoding: [0x00,0xa7,0x9b,0x34] + teqi $s5,-17504 + tge $7,$10 # CHECK: tge $7, $10 # encoding: [0x00,0xea,0x00,0x30] + tge $5,$19,340 # CHECK: tge $5, $19, 340 # encoding: [0x00,0xb3,0x55,0x30] + tgei $s1,5025 + tgeiu $sp,-28621 + tgeu $22,$28 # CHECK: tgeu $22, $gp # encoding: [0x02,0xdc,0x00,0x31] + tgeu $20,$14,379 # CHECK: tgeu $20, $14, 379 # encoding: [0x02,0x8e,0x5e,0xf1] + tlbp # CHECK: tlbp # encoding: [0x42,0x00,0x00,0x08] + tlbr # CHECK: tlbr # encoding: [0x42,0x00,0x00,0x01] + tlbwi # CHECK: tlbwi # encoding: [0x42,0x00,0x00,0x02] + tlbwr # CHECK: tlbwr # encoding: [0x42,0x00,0x00,0x06] + tlt $15,$13 # CHECK: tlt $15, $13 # encoding: [0x01,0xed,0x00,0x32] + tlt $2,$19,133 # CHECK: tlt $2, $19, 133 # encoding: [0x00,0x53,0x21,0x72] + tlti $14,-21059 + tltiu $ra,-5076 + tltu $11,$16 # CHECK: tltu $11, $16 # encoding: [0x01,0x70,0x00,0x33] + tltu $16,$29,1016 # CHECK: tltu $16, $sp, 1016 # encoding: [0x02,0x1d,0xfe,0x33] + tne $6,$17 # CHECK: tne $6, $17 # encoding: [0x00,0xd1,0x00,0x36] + tne $7,$8,885 # CHECK: tne $7, $8, 885 # encoding: [0x00,0xe8,0xdd,0x76] + tnei $12,-29647 + trunc.l.d $f23,$f23 + trunc.l.s $f28,$f31 + trunc.w.d $f22,$f15 + trunc.w.s $f28,$f30 + xor $s2,$a0,$s8 + wsbh $k1,$9 diff --git a/test/MC/Mips/nabi-regs.s b/test/MC/Mips/nabi-regs.s index d79df4e..c265809 100644 --- a/test/MC/Mips/nabi-regs.s +++ b/test/MC/Mips/nabi-regs.s @@ -7,10 +7,10 @@ # RUN: -mcpu=mips64r2 -arch=mips64 | FileCheck %s # # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \ -# RUN: -mcpu=mips64r2 -arch=mips64 -mattr=-n64,+n32 | FileCheck %s +# RUN: -mcpu=mips64r2 -arch=mips64 -target-abi n32 | FileCheck %s # # RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding \ -# RUN: -mcpu=mips64r2 -arch=mips64 -mattr=-n64,+n64 | FileCheck %s +# RUN: -mcpu=mips64r2 -arch=mips64 -target-abi n64 | FileCheck %s .text foo: diff --git a/test/MC/Mips/nooddspreg-cmdarg.s b/test/MC/Mips/nooddspreg-cmdarg.s index 52b040e..74c9d4d 100644 --- a/test/MC/Mips/nooddspreg-cmdarg.s +++ b/test/MC/Mips/nooddspreg-cmdarg.s @@ -5,7 +5,7 @@ # RUN: llvm-readobj -sections -section-data -section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ -# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=-n64,+n32,+nooddspreg 2> %t0 +# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 -mattr=+nooddspreg 2> %t0 # RUN: FileCheck %s -check-prefix=INVALID < %t0 # # RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=+nooddspreg 2> %t0 diff --git a/test/MC/Mips/nooddspreg.s b/test/MC/Mips/nooddspreg.s index f268ef4..6332b70 100644 --- a/test/MC/Mips/nooddspreg.s +++ b/test/MC/Mips/nooddspreg.s @@ -5,7 +5,7 @@ # RUN: llvm-readobj -sections -section-data -section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ -# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -mattr=-n64,n32 2> %t1 +# RUN: not llvm-mc %s -arch=mips -mcpu=mips64 -target-abi n32 2> %t1 # RUN: FileCheck %s -check-prefix=INVALID < %t1 # # RUN: not llvm-mc %s -arch=mips -mcpu=mips64 2> %t2 diff --git a/test/MC/Mips/octeon-instructions.s b/test/MC/Mips/octeon-instructions.s index 2922744..34830c0 100644 --- a/test/MC/Mips/octeon-instructions.s +++ b/test/MC/Mips/octeon-instructions.s @@ -3,10 +3,18 @@ # CHECK: baddu $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x28] # CHECK: baddu $17, $18, $19 # encoding: [0x72,0x53,0x88,0x28] # CHECK: baddu $2, $2, $3 # encoding: [0x70,0x43,0x10,0x28] +# CHECK: bbit0 $19, 22, foo # encoding: [0xca,0x76,A,A] +# CHECK: bbit032 $fp, 11, foo # encoding: [0xdb,0xcb,A,A] +# CHECK: bbit032 $8, 10, foo # encoding: [0xd9,0x0a,A,A] +# CHECK: bbit1 $3, 31, foo # encoding: [0xe8,0x7f,A,A] +# CHECK: bbit132 $24, 10, foo # encoding: [0xfb,0x0a,A,A] +# CHECK: bbit132 $14, 14, foo # encoding: [0xf9,0xce,A,A] # CHECK: cins $25, $10, 22, 2 # encoding: [0x71,0x59,0x15,0xb2] # CHECK: cins $9, $9, 17, 29 # encoding: [0x71,0x29,0xec,0x72] # CHECK: cins32 $15, $2, 18, 8 # encoding: [0x70,0x4f,0x44,0xb3] # CHECK: cins32 $22, $22, 9, 22 # encoding: [0x72,0xd6,0xb2,0x73] +# CHECK: cins32 $24, $ra, 0, 31 # encoding: [0x73,0xf8,0xf8,0x33] +# CHECK: cins32 $15, $15, 5, 5 # encoding: [0x71,0xef,0x29,0x73] # CHECK: dmul $9, $6, $7 # encoding: [0x70,0xc7,0x48,0x03] # CHECK: dmul $19, $24, $25 # encoding: [0x73,0x19,0x98,0x03] # CHECK: dmul $9, $9, $6 # encoding: [0x71,0x26,0x48,0x03] @@ -18,6 +26,8 @@ # CHECK: exts $15, $15, 17, 6 # encoding: [0x71,0xef,0x34,0x7a] # CHECK: exts32 $4, $13, 10, 8 # encoding: [0x71,0xa4,0x42,0xbb] # CHECK: exts32 $15, $15, 11, 20 # encoding: [0x71,0xef,0xa2,0xfb] +# CHECK: exts32 $7, $4, 22, 9 # encoding: [0x70,0x87,0x4d,0xbb] +# CHECK: exts32 $25, $25, 5, 25 # encoding: [0x73,0x39,0xc9,0x7b] # CHECK: mtm0 $15 # encoding: [0x71,0xe0,0x00,0x08] # CHECK: mtm1 $16 # encoding: [0x72,0x00,0x00,0x0c] # CHECK: mtm2 $17 # encoding: [0x72,0x20,0x00,0x0d] @@ -46,13 +56,22 @@ # CHECK: vmulu $sp, $10, $17 # encoding: [0x71,0x51,0xe8,0x0f] # CHECK: vmulu $27, $27, $6 # encoding: [0x73,0x66,0xd8,0x0f] +foo: baddu $9, $6, $7 baddu $17, $18, $19 baddu $2, $3 + bbit0 $19, 22, foo + bbit032 $30, 11, foo + bbit0 $8, 42, foo + bbit1 $3, 31, foo + bbit132 $24, 10, foo + bbit1 $14, 46, foo cins $25, $10, 22, 2 cins $9, 17, 29 cins32 $15, $2, 18, 8 cins32 $22, 9, 22 + cins $24, $31, 32, 31 + cins $15, 37, 5 dmul $9, $6, $7 dmul $19, $24, $25 dmul $9, $6 @@ -64,6 +83,8 @@ exts $15, 17, 6 exts32 $4, $13, 10, 8 exts32 $15, 11, 20 + exts $7, $4, 54, 9 + exts $25, 37, 25 mtm0 $15 mtm1 $16 mtm2 $17 diff --git a/test/MC/Mips/oddspreg.s b/test/MC/Mips/oddspreg.s index 32ba9e0..a3902f6 100644 --- a/test/MC/Mips/oddspreg.s +++ b/test/MC/Mips/oddspreg.s @@ -5,10 +5,10 @@ # RUN: llvm-readobj -sections -section-data -section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-O32 # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 | \ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 | \ # RUN: FileCheck %s -check-prefix=CHECK-ASM # -# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 -filetype=obj -o - | \ +# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64 -target-abi n32 -filetype=obj -o - | \ # RUN: llvm-readobj -sections -section-data -section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N32 @@ -25,7 +25,7 @@ # RUN: llvm-readobj -sections -section-data -section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-O32 # -# RUN: llvm-mc /dev/null -arch=mips64 -mcpu=mips64 -mattr=-n64,+n32 -filetype=obj -o - | \ +# RUN: llvm-mc /dev/null -arch=mips64 -mcpu=mips64 -target-abi n32 -filetype=obj -o - | \ # RUN: llvm-readobj -sections -section-data -section-relocations - | \ # RUN: FileCheck %s -check-prefix=CHECK-OBJ-ALL -check-prefix=CHECK-OBJ-N32 diff --git a/test/MC/Mips/set-arch.s b/test/MC/Mips/set-arch.s index 6267468..834718c 100644 --- a/test/MC/Mips/set-arch.s +++ b/test/MC/Mips/set-arch.s @@ -16,12 +16,24 @@ clo $2, $2 .set arch=mips32r2 rotr $2, $2, 15 + .set arch=mips32 + .set arch=mips32r3 + rotr $2, $2, 15 + .set arch=mips32 + .set arch=mips32r5 + rotr $2, $2, 15 .set arch=mips32r6 mod $2, $4, $6 .set arch=mips64 daddi $2, $2, 10 .set arch=mips64r2 drotr32 $1, $14, 15 + .set arch=mips64 + .set arch=mips64r3 + drotr32 $1, $14, 15 + .set arch=mips64 + .set arch=mips64r5 + drotr32 $1, $14, 15 .set arch=mips64r6 mod $2, $4, $6 .set arch=cnmips diff --git a/test/MC/Mips/set-at-directive-explicit-at.s b/test/MC/Mips/set-at-directive-explicit-at.s index 797a2b7..28a7091 100644 --- a/test/MC/Mips/set-at-directive-explicit-at.s +++ b/test/MC/Mips/set-at-directive-explicit-at.s @@ -15,6 +15,16 @@ foo: # WARNINGS: :[[@LINE+2]]:11: warning: used $at without ".set noat" .set at=$1 jr $1 + +# CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00] +# WARNINGS: :[[@LINE+2]]:11: warning: used $at without ".set noat" + .set at=$at + jr $at + +# CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00] +# WARNINGS: :[[@LINE+2]]:11: warning: used $at without ".set noat" + .set at=$at + jr $1 # WARNINGS-NOT: warning: used $at without ".set noat" # CHECK: jr $1 # encoding: [0x08,0x00,0x20,0x00] diff --git a/test/MC/Mips/set-at-directive.s b/test/MC/Mips/set-at-directive.s index 7e93f76..1bfc473 100644 --- a/test/MC/Mips/set-at-directive.s +++ b/test/MC/Mips/set-at-directive.s @@ -4,156 +4,187 @@ # for ".set at" and set the correct value. .text foo: +# CHECK: .set at=$1 # CHECK: lui $1, 1 # CHECK: addu $1, $1, $2 # CHECK: lw $2, 0($1) .set at=$1 lw $2, 65536($2) +# CHECK: .set at=$2 # CHECK: lui $2, 1 # CHECK: addu $2, $2, $1 # CHECK: lw $1, 0($2) .set at=$2 lw $1, 65536($1) +# CHECK: .set at=$3 # CHECK: lui $3, 1 # CHECK: addu $3, $3, $1 # CHECK: lw $1, 0($3) .set at=$3 lw $1, 65536($1) +# CHECK: .set at=$4 # CHECK: lui $4, 1 # CHECK: addu $4, $4, $1 # CHECK: lw $1, 0($4) .set at=$a0 lw $1, 65536($1) +# CHECK: .set at=$5 # CHECK: lui $5, 1 # CHECK: addu $5, $5, $1 # CHECK: lw $1, 0($5) .set at=$a1 lw $1, 65536($1) +# CHECK: .set at=$6 # CHECK: lui $6, 1 # CHECK: addu $6, $6, $1 # CHECK: lw $1, 0($6) .set at=$a2 lw $1, 65536($1) +# CHECK: .set at=$7 # CHECK: lui $7, 1 # CHECK: addu $7, $7, $1 # CHECK: lw $1, 0($7) .set at=$a3 lw $1, 65536($1) +# CHECK: .set at=$8 # CHECK: lui $8, 1 # CHECK: addu $8, $8, $1 # CHECK: lw $1, 0($8) .set at=$8 lw $1, 65536($1) +# CHECK: .set at=$9 # CHECK: lui $9, 1 # CHECK: addu $9, $9, $1 # CHECK: lw $1, 0($9) .set at=$9 lw $1, 65536($1) +# CHECK: .set at=$10 # CHECK: lui $10, 1 # CHECK: addu $10, $10, $1 # CHECK: lw $1, 0($10) .set at=$10 lw $1, 65536($1) +# CHECK: .set at=$11 # CHECK: lui $11, 1 # CHECK: addu $11, $11, $1 # CHECK: lw $1, 0($11) .set at=$11 lw $1, 65536($1) +# CHECK: .set at=$12 # CHECK: lui $12, 1 # CHECK: addu $12, $12, $1 # CHECK: lw $1, 0($12) .set at=$12 lw $1, 65536($1) +# CHECK: .set at=$13 # CHECK: lui $13, 1 # CHECK: addu $13, $13, $1 # CHECK: lw $1, 0($13) .set at=$13 lw $1, 65536($1) +# CHECK: .set at=$14 # CHECK: lui $14, 1 # CHECK: addu $14, $14, $1 # CHECK: lw $1, 0($14) .set at=$14 lw $1, 65536($1) +# CHECK: .set at=$15 # CHECK: lui $15, 1 # CHECK: addu $15, $15, $1 # CHECK: lw $1, 0($15) .set at=$15 lw $1, 65536($1) +# CHECK: .set at=$16 # CHECK: lui $16, 1 # CHECK: addu $16, $16, $1 # CHECK: lw $1, 0($16) .set at=$s0 lw $1, 65536($1) +# CHECK: .set at=$17 # CHECK: lui $17, 1 # CHECK: addu $17, $17, $1 # CHECK: lw $1, 0($17) .set at=$s1 lw $1, 65536($1) +# CHECK: .set at=$18 # CHECK: lui $18, 1 # CHECK: addu $18, $18, $1 # CHECK: lw $1, 0($18) .set at=$s2 lw $1, 65536($1) +# CHECK: .set at=$19 # CHECK: lui $19, 1 # CHECK: addu $19, $19, $1 # CHECK: lw $1, 0($19) .set at=$s3 lw $1, 65536($1) +# CHECK: .set at=$20 # CHECK: lui $20, 1 # CHECK: addu $20, $20, $1 # CHECK: lw $1, 0($20) .set at=$s4 lw $1, 65536($1) +# CHECK: .set at=$21 # CHECK: lui $21, 1 # CHECK: addu $21, $21, $1 # CHECK: lw $1, 0($21) .set at=$s5 lw $1, 65536($1) +# CHECK: .set at=$22 # CHECK: lui $22, 1 # CHECK: addu $22, $22, $1 # CHECK: lw $1, 0($22) .set at=$s6 lw $1, 65536($1) +# CHECK: .set at=$23 # CHECK: lui $23, 1 # CHECK: addu $23, $23, $1 # CHECK: lw $1, 0($23) .set at=$s7 lw $1, 65536($1) +# CHECK: .set at=$24 # CHECK: lui $24, 1 # CHECK: addu $24, $24, $1 # CHECK: lw $1, 0($24) .set at=$24 lw $1, 65536($1) +# CHECK: .set at=$25 # CHECK: lui $25, 1 # CHECK: addu $25, $25, $1 # CHECK: lw $1, 0($25) .set at=$25 lw $1, 65536($1) +# CHECK: .set at=$26 # CHECK: lui $26, 1 # CHECK: addu $26, $26, $1 # CHECK: lw $1, 0($26) .set at=$26 lw $1, 65536($1) +# CHECK: .set at=$27 # CHECK: lui $27, 1 # CHECK: addu $27, $27, $1 # CHECK: lw $1, 0($27) .set at=$27 lw $1, 65536($1) +# CHECK: .set at=$28 # CHECK: lui $gp, 1 # CHECK: addu $gp, $gp, $1 # CHECK: lw $1, 0($gp) .set at=$gp lw $1, 65536($1) +# CHECK: .set at=$30 # CHECK: lui $fp, 1 # CHECK: addu $fp, $fp, $1 # CHECK: lw $1, 0($fp) .set at=$fp lw $1, 65536($1) +# CHECK: .set at=$29 # CHECK: lui $sp, 1 # CHECK: addu $sp, $sp, $1 # CHECK: lw $1, 0($sp) .set at=$sp lw $1, 65536($1) +# CHECK: .set at=$31 # CHECK: lui $ra, 1 # CHECK: addu $ra, $ra, $1 # CHECK: lw $1, 0($ra) diff --git a/test/MC/Mips/set-at-noat-bad-syntax.s b/test/MC/Mips/set-at-noat-bad-syntax.s new file mode 100644 index 0000000..47f5be7 --- /dev/null +++ b/test/MC/Mips/set-at-noat-bad-syntax.s @@ -0,0 +1,29 @@ +# RUN: not llvm-mc %s -triple=mips-unknown-unknown -mcpu=mips32 2>%t1 +# RUN: FileCheck %s < %t1 + +.set at~ +# CHECK: error: unexpected token, expected equals sign + +.set at= +# CHECK: error: no register specified + +.set at=~ +# CHECK: error: unexpected token, expected dollar sign '$' + +.set at=$ +# CHECK: error: unexpected token, expected identifier or integer + +.set at=$-4 +# CHECK: error: unexpected token, expected identifier or integer + +.set at=$1000 +# CHECK: error: invalid register + +.set at=$foo +# CHECK: error: invalid register + +.set at=$2bar +# CHECK: error: unexpected token, expected end of statement + +.set noat bar +# CHECK: error: unexpected token, expected end of statement diff --git a/test/MC/Mips/set-mips-directives-bad.s b/test/MC/Mips/set-mips-directives-bad.s index 6726987..68a0da8 100644 --- a/test/MC/Mips/set-mips-directives-bad.s +++ b/test/MC/Mips/set-mips-directives-bad.s @@ -21,10 +21,22 @@ rotr $2,15 # CHECK: error: instruction requires a CPU feature not currently enabled .set mips32r2 mod $2, $4, $6 # CHECK: error:instruction requires a CPU feature not currently enabled + .set mips64r3 + .set mips32r3 + daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips64r3 + .set mips32r5 + daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled .set mips32r6 daddi $2, $2, 10 # CHECK: error: instruction requires a CPU feature not currently enabled .set mips64 drotr32 $1,$14,15 # CHECK: error: instruction requires a CPU feature not currently enabled .set mips64r2 mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips64r6 + .set mips64r3 + mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled + .set mips64r6 + .set mips64r5 + mod $2, $4, $6 # CHECK: error: instruction requires a CPU feature not currently enabled diff --git a/test/MC/Mips/set-mips-directives.s b/test/MC/Mips/set-mips-directives.s index 96c2308..5225968 100644 --- a/test/MC/Mips/set-mips-directives.s +++ b/test/MC/Mips/set-mips-directives.s @@ -17,12 +17,24 @@ clo $2,$2 .set mips32r2 rotr $2,15 + .set mips32 + .set mips32r3 + rotr $2,15 + .set mips32 + .set mips32r5 + rotr $2,15 .set mips32r6 mod $2, $4, $6 .set mips64 daddi $2, $2, 10 .set mips64r2 drotr32 $1,$14,15 + .set mips64 + .set mips64r3 + drotr32 $1,$14,15 + .set mips64 + .set mips64r5 + drotr32 $1,$14,15 .set mips64r6 mod $2, $4, $6 @@ -41,11 +53,23 @@ # CHECK: clo $2, $2 # CHECK: .set mips32r2 # CHECK: rotr $2, $2, 15 +# CHECK: .set mips32 +# CHECK: .set mips32r3 +# CHECK: rotr $2, $2, 15 +# CHECK: .set mips32 +# CHECK: .set mips32r5 +# CHECK: rotr $2, $2, 15 # CHECK: .set mips32r6 # CHECK: mod $2, $4, $6 # CHECK: .set mips64 # CHECK: daddi $2, $2, 10 # CHECK: .set mips64r2 # CHECK: drotr32 $1, $14, 15 +# CHECK: .set mips64 +# CHECK: .set mips64r3 +# CHECK: drotr32 $1, $14, 15 +# CHECK: .set mips64 +# CHECK: .set mips64r5 +# CHECK: drotr32 $1, $14, 15 # CHECK: .set mips64r6 # CHECK: mod $2, $4, $6 |