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-rw-r--r--test/TableGen/Slice.td8
1 files changed, 4 insertions, 4 deletions
diff --git a/test/TableGen/Slice.td b/test/TableGen/Slice.td
index 22bf7fb..13d9da2 100644
--- a/test/TableGen/Slice.td
+++ b/test/TableGen/Slice.td
@@ -66,19 +66,19 @@ def not : SDNode;
multiclass scalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
def SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
!strconcat(asmstr, "\t$dst, $src"),
- !if(!null(patterns),[]<dag>,patterns[0])>;
+ !if(!empty(patterns),[]<dag>,patterns[0])>;
def SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
!strconcat(asmstr, "\t$dst, $src"),
- !if(!null(patterns),[]<dag>,!if(!null(!cdr(patterns)),patterns[0],patterns[1]))>;
+ !if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>;
}
multiclass vscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> {
def V#NAME#SSrr : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
!strconcat(asmstr, "\t$dst, $src"),
- !if(!null(patterns),[]<dag>,patterns[0])>;
+ !if(!empty(patterns),[]<dag>,patterns[0])>;
def V#NAME#SSrm : Inst<opcode, (outs FR32:$dst), (ins FR32:$src),
!strconcat(asmstr, "\t$dst, $src"),
- !if(!null(patterns),[]<dag>,!if(!null(!cdr(patterns)),patterns[0],patterns[1]))>;
+ !if(!empty(patterns),[]<dag>,!if(!empty(!tail(patterns)),patterns[0],patterns[1]))>;
}
multiclass myscalar<bits<8> opcode, string asmstr = "", list<list<dag>> patterns = []> :