diff options
Diffstat (limited to 'test')
-rw-r--r-- | test/CodeGen/X86/2009-02-26-MachineLICMBug.ll | 6 | ||||
-rw-r--r-- | test/CodeGen/X86/2011-09-14-valcoalesce.ll | 37 | ||||
-rw-r--r-- | test/CodeGen/X86/fast-isel-divrem-x86-64.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/fast-isel-divrem.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/X86/hoist-common.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/licm-dominance.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/licm-nested.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/lsr-interesting-step.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/lsr-static-addr.ll | 3 | ||||
-rw-r--r-- | test/CodeGen/X86/sibcall.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/X86/tail-opts.ll | 4 | ||||
-rw-r--r-- | test/CodeGen/X86/zext-extract_subreg.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/X86/zext-sext.ll | 5 |
13 files changed, 51 insertions, 24 deletions
diff --git a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll index 68a9faf..8174fbd 100644 --- a/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll +++ b/test/CodeGen/X86/2009-02-26-MachineLICMBug.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn -stats 2>&1 | grep "5 machine-licm" +; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn -stats 2>&1 | grep "4 machine-licm" ; RUN: llc < %s -march=x86-64 -mattr=+sse3,+sse41 -mcpu=penryn | FileCheck %s ; rdar://6627786 ; rdar://7792037 @@ -15,11 +15,11 @@ entry: bb4: ; preds = %bb.i, %bb26, %bb4, %entry ; CHECK: %bb4 -; CHECK: xorb +; CHECK: xorl ; CHECK: callq ; CHECK: movq ; CHECK: xorl -; CHECK: xorb +; CHECK: xorl %0 = call i32 (...)* @xxGetOffsetForCode(i32 undef) nounwind ; <i32> [#uses=0] %ins = or i64 %p, 2097152 ; <i64> [#uses=1] diff --git a/test/CodeGen/X86/2011-09-14-valcoalesce.ll b/test/CodeGen/X86/2011-09-14-valcoalesce.ll index 6d91109..4e84e84 100644 --- a/test/CodeGen/X86/2011-09-14-valcoalesce.ll +++ b/test/CodeGen/X86/2011-09-14-valcoalesce.ll @@ -14,22 +14,47 @@ ; Prior to fixing PR10920 401.bzip miscompile, the coalescer would ; consider vreg1 and vreg27 to be copies of the same value. It would ; then remove one of the critical edge copes, which cannot safely be removed. -; + +; There are two obvious ways the register-allocator could go here, either +; reusing the pre-addition register later, or the post-addition one. Currently, +; it does the latter, so we check: + ; CHECK: # %while.body85.i ; CHECK-NOT: # % ; CHECK-NOT: add ; CHECK: movl %[[POSTR:e[abcdxi]+]], %[[PRER:e[abcdxi]+]] ; CHECK: addl %{{.*}}, %[[POSTR]] ; CHECK: # %while.end.i -; CHECK: movl %[[POSTR]], %[[USER:e[abcdxi]+]] +; CHECK-NOT: movl %[[POSTR]] ; CHECK: # %land.lhs.true.i -; CHECK: movl %[[POSTR]], %[[USER]] +; CHECK-NOT: movl %[[POSTR]] ; CHECK: # %land.lhs.true103.i -; CHECK: movl %[[POSTR]], %[[USER]] +; CHECK-NOT: movl %[[POSTR]] ; CHECK: # %if.then108.i -; [[PRER] live out, so nothing on this path should define it. -; CHECK-NOT: , %[[PRER]] +; CHECK: movl %[[PRER]], %[[POSTR]] ; CHECK: # %if.end117.i +; and use it for fprintf: +; CHECK: movl %[[POSTR]], 12(%esp) + + +; If it ever reverts to reusing the pre-addition register then we should +; *probably* check this instead (it certainly worked last time): + +; CHECKALT: # %while.body85.i +; CHECKALT-NOT: # % +; CHECKALT-NOT: add +; CHECKALT: movl %[[POSTR:e[abcdxi]+]], %[[PRER:e[abcdxi]+]] +; CHECKALT: addl %{{.*}}, %[[POSTR]] +; CHECKALT: # %while.end.i +; CHECKALT: movl %[[POSTR]], %[[USER:e[abcdxi]+]] +; CHECKALT: # %land.lhs.true.i +; CHECKALT: movl %[[POSTR]], %[[USER]] +; CHECKALT: # %land.lhs.true103.i +; CHECKALT: movl %[[POSTR]], %[[USER]] +; CHECKALT: # %if.then108.i +; [[PRER] live out, so nothing on this path should define it. +; CHECKALT-NOT: , %[[PRER]] +; CHECKALT: # %if.end117.i target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" diff --git a/test/CodeGen/X86/fast-isel-divrem-x86-64.ll b/test/CodeGen/X86/fast-isel-divrem-x86-64.ll index 45494f1..f2afaa0 100644 --- a/test/CodeGen/X86/fast-isel-divrem-x86-64.ll +++ b/test/CodeGen/X86/fast-isel-divrem-x86-64.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s define i64 @test_sdiv64(i64 %dividend, i64 %divisor) nounwind { entry: diff --git a/test/CodeGen/X86/fast-isel-divrem.ll b/test/CodeGen/X86/fast-isel-divrem.ll index 7aba7f7..1a309a1 100644 --- a/test/CodeGen/X86/fast-isel-divrem.ll +++ b/test/CodeGen/X86/fast-isel-divrem.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s -; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort < %s | FileCheck %s +; RUN: llc -mtriple=x86_64-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -mtriple=i686-none-linux -fast-isel -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s define i8 @test_sdiv8(i8 %dividend, i8 %divisor) nounwind { entry: diff --git a/test/CodeGen/X86/hoist-common.ll b/test/CodeGen/X86/hoist-common.ll index 72e17c0..cdfdea3 100644 --- a/test/CodeGen/X86/hoist-common.ll +++ b/test/CodeGen/X86/hoist-common.ll @@ -8,7 +8,7 @@ define zeroext i1 @t(i32 %c) nounwind ssp { entry: ; CHECK: t: -; CHECK: xorb %al, %al +; CHECK: xorl %eax, %eax ; CHECK: test ; CHECK: je %tobool = icmp eq i32 %c, 0 diff --git a/test/CodeGen/X86/licm-dominance.ll b/test/CodeGen/X86/licm-dominance.ll index 019f8a3..7e3c6fd 100644 --- a/test/CodeGen/X86/licm-dominance.ll +++ b/test/CodeGen/X86/licm-dominance.ll @@ -2,7 +2,7 @@ ; MachineLICM should check dominance before hoisting instructions. ; CHECK: ## in Loop: -; CHECK-NEXT: xorb %al, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: testb %al, %al target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" diff --git a/test/CodeGen/X86/licm-nested.ll b/test/CodeGen/X86/licm-nested.ll index 66074fb..083ae08 100644 --- a/test/CodeGen/X86/licm-nested.ll +++ b/test/CodeGen/X86/licm-nested.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -o /dev/null -stats -info-output-file - | grep "hoisted out of loops" | grep 3 +; RUN: llc -mtriple=x86_64-apple-darwin -march=x86-64 < %s -o /dev/null -stats -info-output-file - | grep "hoisted out of loops" | grep 4 ; MachineLICM should be able to hoist the symbolic addresses out of ; the inner loops. diff --git a/test/CodeGen/X86/lsr-interesting-step.ll b/test/CodeGen/X86/lsr-interesting-step.ll index d1de051..d4a7ac7 100644 --- a/test/CodeGen/X86/lsr-interesting-step.ll +++ b/test/CodeGen/X86/lsr-interesting-step.ll @@ -5,7 +5,7 @@ ; CHECK: BB0_3: ; CHECK-NEXT: movb $0, flags(%rdx) -; CHECK-NEXT: addq %rcx, %rdx +; CHECK-NEXT: addq %rax, %rdx ; CHECK-NEXT: cmpq $8192, %rdx ; CHECK-NEXT: jl diff --git a/test/CodeGen/X86/lsr-static-addr.ll b/test/CodeGen/X86/lsr-static-addr.ll index b2aea90..1bac790 100644 --- a/test/CodeGen/X86/lsr-static-addr.ll +++ b/test/CodeGen/X86/lsr-static-addr.ll @@ -10,8 +10,9 @@ ; CHECK-NEXT: movsd ; CHECK-NEXT: incq %rax -; ATOM: movsd .LCPI0_0(%rip), %xmm0 + ; ATOM: xorl %eax, %eax +; ATOM: movsd .LCPI0_0(%rip), %xmm0 ; ATOM: align ; ATOM-NEXT: BB0_2: ; ATOM-NEXT: movsd A(,%rax,8) diff --git a/test/CodeGen/X86/sibcall.ll b/test/CodeGen/X86/sibcall.ll index ceb79ea..de98cb4 100644 --- a/test/CodeGen/X86/sibcall.ll +++ b/test/CodeGen/X86/sibcall.ll @@ -279,7 +279,7 @@ entry: ; 32: jmp {{_?}}bar5 ; 64: t17: -; 64: xorb %al, %al +; 64: xorl %eax, %eax ; 64: jmp {{_?}}bar5 tail call void (...)* @bar5() nounwind ret void @@ -295,7 +295,7 @@ entry: ; 32: fstp %st(0) ; 64: t18: -; 64: xorb %al, %al +; 64: xorl %eax, %eax ; 64: jmp {{_?}}bar6 %0 = tail call double (...)* @bar6() nounwind ret void diff --git a/test/CodeGen/X86/tail-opts.ll b/test/CodeGen/X86/tail-opts.ll index 6e20af5..75a728c 100644 --- a/test/CodeGen/X86/tail-opts.ll +++ b/test/CodeGen/X86/tail-opts.ll @@ -118,7 +118,7 @@ altret: ; CHECK-NEXT: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}} ; CHECK-NEXT: jbe .LBB2_2 ; CHECK-NEXT: .LBB2_4: -; CHECK-NEXT: xorb %al, %al +; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: ret ; CHECK-NEXT: .LBB2_2: ; CHECK-NEXT: movb $1, %al @@ -161,7 +161,7 @@ bb30: ; CHE: jmp .LBB3_11 ; CHE-NEXT: .LBB3_9: ; CHE-NEXT: movq 8(%rax), %rax -; CHE-NEXT: xorb %dl, %dl +; CHE-NEXT: xorl %edx, %edx ; CHE-NEXT: movb 16(%rax), %al ; CHE-NEXT: cmpb $16, %al ; CHE-NEXT: je .LBB3_11 diff --git a/test/CodeGen/X86/zext-extract_subreg.ll b/test/CodeGen/X86/zext-extract_subreg.ll index 168b898..7fa0574 100644 --- a/test/CodeGen/X86/zext-extract_subreg.ll +++ b/test/CodeGen/X86/zext-extract_subreg.ll @@ -14,7 +14,7 @@ if.end: ; preds = %if.end.i ; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]] ; CHECK-NOT: movl [[REG]], [[REG]] ; CHECK-NEXT: testl [[REG]], [[REG]] -; CHECK-NEXT: xorb +; CHECK-NEXT: xorl %tmp138 = select i1 undef, i32 0, i32 %tmp7.i %tmp867 = zext i32 %tmp138 to i64 br label %while.cond diff --git a/test/CodeGen/X86/zext-sext.ll b/test/CodeGen/X86/zext-sext.ll index 6432ae3..e4264ae 100644 --- a/test/CodeGen/X86/zext-sext.ll +++ b/test/CodeGen/X86/zext-sext.ll @@ -1,8 +1,9 @@ -; XFAIL: * -; ...should pass. See PR12324: misched bringup ; RUN: llc < %s -march=x86-64 | FileCheck %s ; <rdar://problem/8006248> +; This randomly started passing after an unrelated change, if it fails again it +; might be worth looking at PR12324: misched bringup. + @llvm.used = appending global [1 x i8*] [i8* bitcast (void ([40 x i16]*, i32*, i16**, i64*)* @func to i8*)], section "llvm.metadata" define void @func([40 x i16]* %a, i32* %b, i16** %c, i64* %d) nounwind { |