diff options
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/X86/i486-fence-loop.ll | 27 |
2 files changed, 28 insertions, 1 deletions
diff --git a/test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll b/test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll index a883d79..cd8a16f 100644 --- a/test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll +++ b/test/CodeGen/X86/2012-01-16-mfence-nosse-flags.ll @@ -15,7 +15,7 @@ entry: ; CHECK: lock ; CHECK-NEXT: orl {{.*}}, (%esp) -; CHECK-NEXT: cmpl $0 +; CHECK-NEXT: testl [[REG:%e[a-z]+]], [[REG]] if.then: ; preds = %entry tail call void bitcast (void (...)* @foo to void ()*)() nounwind diff --git a/test/CodeGen/X86/i486-fence-loop.ll b/test/CodeGen/X86/i486-fence-loop.ll new file mode 100644 index 0000000..d809619 --- /dev/null +++ b/test/CodeGen/X86/i486-fence-loop.ll @@ -0,0 +1,27 @@ +; RUN: llc -march=x86 -mcpu=i486 -o - %s | FileCheck %s + +; Main test here was that ISelDAG could cope with a MachineNode in the chain +; from the first load to the "X86ISD::SUB". Previously it thought that meant no +; cycle could be formed so it tried to use "sub (%eax), [[RHS]]". + +define void @gst_atomic_queue_push(i32* %addr) { +; CHECK-LABEL: gst_atomic_queue_push: +; CHECK: movl (%eax), [[LHS:%e[a-z]+]] +; CHECK: lock +; CHECK-NEXT: orl +; CHECK: movl (%eax), [[RHS:%e[a-z]+]] +; CHECK: cmpl [[LHS]], [[RHS]] + +entry: + br label %while.body + +while.body: + %0 = load volatile i32* %addr, align 4 + fence seq_cst + %1 = load volatile i32* %addr, align 4 + %cmp = icmp sgt i32 %1, %0 + br i1 %cmp, label %while.body, label %if.then + +if.then: + ret void +}
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