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-rw-r--r--test/MC/Disassembler/ARM/basic-arm-instructions.txt4
-rw-r--r--test/MC/Disassembler/ARM/invalid-CPS-arm.txt9
2 files changed, 13 insertions, 0 deletions
diff --git a/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/test/MC/Disassembler/ARM/basic-arm-instructions.txt
index 92cfe68..ae4172b 100644
--- a/test/MC/Disassembler/ARM/basic-arm-instructions.txt
+++ b/test/MC/Disassembler/ARM/basic-arm-instructions.txt
@@ -454,10 +454,14 @@
# CHECK: cpsie aif
# CHECK: cps #15
# CHECK: cpsid if, #10
+# CHECK: cpsid af, #17
+# CHECK: cpsie f, #26
0xc0 0x01 0x08 0xf1
0x0f 0x00 0x02 0xf1
0xca 0x00 0x0e 0xf1
+0x51 0x01 0x0e 0xf1
+0x5a 0x00 0x0a 0xf1
#------------------------------------------------------------------------------
diff --git a/test/MC/Disassembler/ARM/invalid-CPS-arm.txt b/test/MC/Disassembler/ARM/invalid-CPS-arm.txt
new file mode 100644
index 0000000..e447eb6
--- /dev/null
+++ b/test/MC/Disassembler/ARM/invalid-CPS-arm.txt
@@ -0,0 +1,9 @@
+# CPS: various encodings that are ambiguous with other instructions
+
+# RUN: echo "0x9f 0xff 0x4e 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x80 0x80 0x2c 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0xce 0x3f 0x28 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0x80 0x00 0x20 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+# RUN: echo "0xa0 0x00 0x00 0xf1" | llvm-mc -triple=armv7 -disassemble 2>&1 | FileCheck %s
+
+# CHECK: invalid instruction encoding